JPH10340925A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a semiconductor device by omitting a resin substrate and a through-hole therefrom. SOLUTION: A semiconductor element 21 is mounted on a plated interconnection layer 23 which is formed on the surface of a copper plate, followed by sealing with a first resin 25 and removing the copper plate by melting. Alternatively, the semiconductor element 21 may be mounted on the plated interconnection layer 23 formed on the surface of a transfer plate, which is in less intimate contact with the first resin 25, followed by sealing with the first resin 25 and removing the transfer plate by peeling, thereby exposing the reverse side of the plated interconnection layer 23. After bonding solder balls 26 to the reverse side of the plated interconnection layer 23, a second resin 27 is applied thereto and cured. In this way, a miniaturized semiconductor device eliminating a substrate and a through-hole is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which protects an integrated circuit portion of a semiconductor, secures an electrical connection between an external device and a semiconductor element, and enables the highest density mounting and a method of manufacturing the same. It is about. The semiconductor device of the present invention facilitates miniaturization of information communication equipment, office electronic equipment, and the like.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of electronic devices, the miniaturization, the increase in the number of pins, and the increase in the density have been required of semiconductor devices, and the QFP (Quad Flat Package) type with a narrow lead pitch A semiconductor device or a BGA (ball grid array) type semiconductor device in which electrodes are arranged in an area array has been developed.

Hereinafter, a conventional BGA type semiconductor device and a method of manufacturing the same will be described with reference to the drawings.

FIG. 14 is a sectional view showing a conventional BGA type semiconductor device. In FIG. 14, 1 is a semiconductor element, 2
Reference numeral denotes a semiconductor element electrode formed on the semiconductor element 1, 3 denotes a resin substrate, 4 denotes a substrate surface conductor formed on the surface of the resin substrate 3, and 5 denotes a substrate surface resist for protecting the substrate surface conductor 4. Reference numeral 6 denotes a bonding area formed by providing an opening in a part of the substrate surface resist 5 to expose a part of the substrate surface conductor 4. Reference numeral 7 denotes a substrate back surface conductor formed on the back surface of the resin substrate 3, and reference numeral 8 denotes a substrate back surface resist for protecting the substrate back surface conductor 7. Reference numeral 9 denotes a ball land formed by providing an opening in a part of the substrate back surface resist 8 and exposing a part of the substrate back surface conductor 7. Reference numeral 10 denotes a through hole provided in a peripheral portion of the resin substrate 3 for electrically connecting the substrate front surface conductor 4 and the substrate rear surface conductor 7. Reference numeral 11 denotes a bonding material for bonding the semiconductor element 1, and 12 denotes a gold wire for electrically connecting the semiconductor element electrode 2 and the bonding area 6. Reference numeral 13 denotes a solder ball joined to the ball land 9. Reference numeral 14 denotes a sealing resin.

As described above, in the conventional semiconductor device, the semiconductor element 1 is mounted on the resin substrate 3 having the through hole 10 and the bonding area 6 (substrate surface conductor 4) on the resin substrate 3 is connected to the semiconductor element electrode by the gold wire 12. 2 are electrically connected to each other, and a conductor 7 on the back surface of the resin substrate 3 through the through hole 10 from the bonding area 6.
And a solder ball 13 is provided as an external terminal.

Next, a method of manufacturing a conventional BGA type semiconductor device will be described with reference to FIG.

First, as shown in FIG. 15A, the semiconductor element 1 is bonded to the surface of the resin substrate 3 with the bonding material 11 with the surface on which the semiconductor element electrodes 2 are formed facing upward. Here, a silver (Ag) paste or an insulating resin paste is used as the bonding material 11.

Next, as shown in FIG. 15B, the semiconductor element electrode 2 and the bonding area 6 are electrically connected by wire bonding with a gold wire 12.

Next, as shown in FIG. 15C, the surface of the resin substrate 3 on which the semiconductor element 1 is mounted is sealed with a sealing resin 14.

Next, as shown in FIG. 15D, the solder ball 13 is heated, melted and joined to the ball land 9 of the resin substrate 3.

The semiconductor device is manufactured as described above.

[0012]

However, in the above-mentioned conventional structure, it is necessary to provide a resin substrate, and to provide a through hole for electrically connecting a substrate surface conductor and a substrate rear surface conductor in a peripheral portion of the resin substrate. There was a problem that the area of the device became large.

The present invention solves the above-mentioned conventional problems, and focuses on fundamental miniaturization, and provides a semiconductor device which can be reduced in size and weight by eliminating a resin substrate and through holes, and a method of manufacturing the same. The purpose is to:

[0014]

In order to achieve this object, a semiconductor device according to the present invention comprises a semiconductor element, a plating wiring layer on which the semiconductor element is mounted, and surfaces of the semiconductor element and the plating wiring layer. And a connection conductor for electrically connecting
A first resin for protecting the surface of the mounted semiconductor element and the plating wiring layer and the connection conductor, an external electrode electrically connected to a back surface of the plating wiring layer, and a back surface of the plating wiring layer; From the second resin that protects

According to the manufacturing method of the present invention, the semiconductor element is mounted on a plating wiring layer formed on the surface of a metal plate and sealed with a first resin, and then only the metal plate is selectively melted and removed. After exposing a semiconductor element on a plating wiring layer formed on a transfer plate having a low adhesion to the first resin and sealing with the first resin, or exposing only the transfer plate, A step of exfoliating and removing the back surface of the plating wiring layer.

According to the above configuration, the resin substrate and the through-hole, which are conventionally required, can be omitted, so that a small and lightweight semiconductor device can be provided.

[0017]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In FIG. 1, reference numeral 21 denotes a semiconductor element, and reference numeral 22 denotes a semiconductor element electrode formed on the semiconductor element. 23 is a plated wiring layer, 24 is a solder bump for electrically connecting the semiconductor element electrode 22 and the plated wiring layer 23, and 25 is a first resin for sealing the lower surface of the semiconductor element 21 and the surface of the plated wiring layer 23. . Reference numeral 26 denotes a solder ball connected to the back surface of the plating wiring layer 23, and reference numeral 27 denotes a second resin that seals the back surface of the plating wiring layer 23.

The semiconductor device of the present embodiment has a semiconductor element 2
1, the arrangement of the semiconductor element electrodes 22 provided on the surface of the substrate 1 is arranged in a grid pattern by the plating wiring layer 23, and is arranged.
A solder ball 26 which is a ball electrode serving as an external terminal is provided on the plating wiring layer 23. The gap between the plating wiring layer 23 and the semiconductor element 21 is sealed with a first resin 25, and the back surface of the plating wiring layer 23 is
It is a structure sealed with. That is, the semiconductor device of the present embodiment includes a semiconductor element 21, a plated wiring layer 23 on which the semiconductor element 21 is mounted, and a solder bump 24 for electrically connecting the semiconductor element 21 and the surface of the plated wiring layer 23. A first resin 25 for protecting the surface area of the mounted semiconductor element 21 and the plated wiring layer 23;
This is a semiconductor device including external electrodes such as solder balls 26 electrically connected to the back surface of the plating wiring layer 23 and a second resin 27 for protecting the back surface of the plating wiring layer 23.

Next, FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention (referred to as a metal plate melting method in this embodiment). In FIG. 2, 21 is a semiconductor element, 22 is a semiconductor element electrode, 23 is a plating wiring layer, 24 is a solder bump, 25 is a first resin, 26
Is a solder ball, 27 is a second resin, 31 is a copper plate, and 32 is a plating resist pattern formed on the copper plate 31.

Hereinafter, a method of manufacturing a semiconductor device using the metal plate melting method will be described with reference to FIG.

First, as shown in FIG. 2A, a plating resist is applied on a copper plate 31, exposed and developed to form a plating resist pattern 32. Next, gold (A
u), palladium (Pd), nickel (Ni), and palladium (Pd) are plated in this order to form a plated wiring layer 23. Each plating method may be electrolytic plating,
Electroless plating may be used.

Next, as shown in FIG. 2B, the plating resist pattern 32 is removed with a solvent.

Next, as shown in FIG. 2C, the semiconductor element 21 having the solder bumps 24 formed on the semiconductor element electrodes 22 in advance is bonded to the surface of the plating wiring layer 23 by flip chip bonding.

Then, as shown in FIG. 2D, the first resin 25 is sealed and cured. The first resin 25 can be applied before joining the semiconductor element 21 to the plating wiring layer 23.

Next, as shown in FIG. 2E, the copper plate is melted and removed with an etching solution having a selectivity only for the copper plate 31, for example, a cupric sulfate solution, so that the back surface of the plating wiring layer 23 is exposed. You.

Next, as shown in FIG. 2 (f), after the solder balls 26 are mounted on the back surface of the plating wiring layer 23, the plating wiring layer 23 and the solder balls 26 are joined by heating and melting. Here, the solder paste may be supplied before the solder balls 26 are mounted.

Next, as shown in FIG. 2G, a second resin 27 is applied and cured for the purpose of protecting the plating wiring layer.

As described above, it is possible to manufacture an extremely small semiconductor device having no substrate as in the prior art.

Next, FIG. 3 is a sectional view showing a manufacturing method (hereinafter, referred to as a transfer plate peeling method in the present embodiment) different from the metal plate melting method in the first embodiment of the present invention. . In FIG. 3, reference numeral 21 denotes a semiconductor element, 22 denotes a semiconductor element electrode, 23 denotes a plating wiring layer, 24 denotes a solder bump, 25 denotes a first resin, 26 denotes a solder ball, and 27 denotes a second ball.
These are the same as those in the metal plate melting method. Reference numeral 41 denotes a transfer plate, and reference numeral 32 denotes a plating resist pattern formed on the transfer plate 41.

Hereinafter, in the first embodiment of the present invention,
A manufacturing method using the transfer plate peeling method will be described with reference to FIG.

First, as shown in FIG. 3A, a plating resist is applied on a transfer plate 41 having low adhesion to metal plating, for example, Teflon or glass, and the plating resist pattern 32 is formed by exposing and developing. Form.
Next, electroless plating is performed to form a plating wiring layer 23.

Then, as shown in FIG. 3B, the plating resist pattern 32 is removed with a solvent.

Next, as shown in FIG. 3C, the semiconductor element 21 having the solder bumps 24 formed on the semiconductor element electrodes 22 in advance is bonded to the surface of the plating wiring layer 23 by flip chip bonding.

Then, as shown in FIG. 3D, the first resin 25 is sealed and cured. Next, as shown in FIG. 3E, only the transfer plate 41 is peeled off to expose the back surface of the plating wiring layer 23. When Teflon or glass is used, the transfer plate 41 has low adhesion to the plating wiring layer 23 and the first resin 25, so that the transfer plate 41 can be peeled off and removed in a peel-off manner. Need not be dissolved and removed.

Next, as shown in FIG. 3F, after the solder balls 26 are mounted on the back surface of the plating wiring layer 23, the plating wiring layer 23 and the solder balls 26 are joined by heating and melting.

Next, as shown in FIG. 3G, a second resin 27 for protecting the plating wiring layer 23 is applied and cured.

As described above, according to this embodiment, the copper plate 31 is melted and removed after the plating wiring layer 23 is formed,
Alternatively, since the transfer plate 41 having low adhesion is peeled off after the formation of the plating wiring layer 23 and the solder ball 26 can be directly bonded to the back surface of the plating wiring layer 23, a resin required in the conventional BGA type semiconductor device is used. Since the substrate and the through hole 10 are not required, a small and lightweight semiconductor device can be realized.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a sectional view showing a semiconductor device according to the second embodiment of the present invention. In FIG. 4, 21 is a semiconductor element, and 22 is a semiconductor element electrode formed on the semiconductor element. 23 is a plated wiring layer, 24 is a solder bump for electrically connecting the semiconductor element electrode 22 and the plated wiring layer 23, and 25 is a first resin for sealing the lower surface of the semiconductor element 21 and the surface of the plated wiring layer 23. . Reference numeral 27 denotes a second resin for sealing the back surface of the plating wiring layer 23, and reference numeral 28 denotes a resin opening formed in the second resin 27 for exposing a part of the back surface of the plating wiring layer 23 to be used as an external electrode. is there.

The semiconductor device according to the present embodiment includes a semiconductor element 2
1, the arrangement of the semiconductor element electrodes 22 provided on the surface of the substrate 1 is arranged in a grid pattern by the plating wiring layer 23, and is arranged.
The gap between the plating wiring layer 23 and the semiconductor element 21 is sealed with a first resin 25, and a resin opening 28 is provided in the plating wiring layer 23 and sealed with a second resin 27. Unlike the semiconductor device of the first embodiment, the semiconductor device of the present embodiment does not have a ball electrode such as a solder ball, and has a structure in which a ball electrode can be provided as needed.

FIG. 5 is a sectional view showing a method of manufacturing a semiconductor device by a metal plate melting method according to the second embodiment of the present invention. In FIG. 5, 21 is a semiconductor element, 22 is a semiconductor element electrode, 23 is a plating wiring layer, 24 is a solder bump, 25
Is a first resin, 27 is a second resin, 28 is a resin opening,
Reference numeral 31 denotes a copper plate, and 32 denotes a plating resist pattern formed on the copper plate 31.

Hereinafter, a method of manufacturing a semiconductor device by a metal plate melting method according to the second embodiment will be described with reference to FIG.

First, as shown in FIG. 5A, a plating resist is applied on a copper plate 31, exposed and developed to form a plating resist pattern 32. Next, Au, P
d, Ni, and Pd are plated in this order, and the plating wiring layer 23 is formed.
To form Each plating method may be electrolytic plating or electroless plating.

Then, as shown in FIG. 5B, the plating resist pattern 32 is removed with a solvent.

Next, as shown in FIG. 5C, the semiconductor element 21 having the solder bumps 24 formed on the semiconductor element electrodes 22 in advance is bonded to the surface of the plating wiring layer 23 by flip chip bonding.

Then, as shown in FIG.
The first resin 25 is sealed and cured. The first resin 25 can be applied before joining the semiconductor element 21 to the plating wiring layer 23.

Next, as shown in FIG. 5E, the copper plate is melted and removed with an etching solution having a selectivity only for the copper plate 31, for example, a cupric sulfate solution, so that the back surface of the plating wiring layer 23 is exposed.

Next, as shown in FIG. 5F, a second resin 27 is applied and cured for the purpose of protecting the back surface of the plating wiring layer 23. At this time, when the second resin 27 is applied, a resin opening 28 is formed by, for example, a printing method in order to expose a part of the back surface of the plating wiring layer 23 and use it as an external electrode. The method for forming the resin opening 28 may be a printing method or a photo method.

As described above, according to this embodiment, since the resin opening 28 is provided on the back surface of the plating wiring layer 23 and a part of the back surface of the plating wiring layer is exposed to be used as an external electrode, no solder ball or the like is required. Thus, a low-cost semiconductor device can be realized.

Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a sectional view showing a semiconductor device according to the third embodiment of the present invention. In FIG. 6, 21 is a semiconductor element, and 22 is a semiconductor element electrode formed on the semiconductor element. 23 is a plated wiring layer, 24 is a solder bump for electrically connecting the semiconductor element electrode 22 and the plated wiring layer 23, and 25 is a first resin for sealing the lower surface of the semiconductor element 21 and the surface of the plated wiring layer 23. . Reference numeral 27 denotes a second resin for sealing the back surface of the plating wiring layer 23, and reference numeral 52 denotes a conductive projection formed on a part of the plating wiring layer 23 and used as an external terminal.

The semiconductor device of this embodiment differs from the above-described embodiment in that it does not have solder balls as ball terminals as external terminals, and the arrangement of the semiconductor element electrodes 22 provided on the surface of the semiconductor element 21 is plated. The wiring layer 23 is arranged in a grid pattern by wiring, and the gap between the plating wiring layer 23 and the semiconductor element 21 is sealed with a first resin 25.
Further, a part of the plated wiring layer 23 forms a conductive projection 52 acting as an external electrode. The surface of the plating wiring layer 23 and the space between the conductive protrusions 52 are sealed with the second resin 27.

Next, FIG. 7 is a sectional view showing a method of manufacturing a semiconductor device by a metal plate melting method according to a third embodiment of the present invention. 7, reference numeral 21 denotes a semiconductor element, 22 denotes a semiconductor element electrode, 23 denotes a plating wiring layer, 24 denotes a solder bump, 25 denotes a first resin, 27 denotes a second resin, 31 denotes a copper plate, and 32 denotes a copper plate. The formed plating resist pattern, 51 is a copper plate recess formed on the copper plate 31, and 52 is a conductive projection.

Hereinafter, a method of manufacturing a semiconductor device by a metal plate melting method according to the third embodiment will be described with reference to FIG.

First, as shown in FIG. 7A, the surface of the copper plate 31 is partially etched to form a concave portion 51 of the copper plate. Instead of partially etching the surface of the copper plate 31, the copper plate concave portion 51 may be formed by cutting.

Next, as shown in FIG. 7B, a plating resist is applied on the copper plate 31, exposed and developed to form a plating resist pattern 32. Next, gold (A
u), palladium (Pd), nickel (Ni), and palladium (Pd) are plated in this order to form the plating wiring layer 23 including the copper plate concave portion 51. Each plating method may be electrolytic plating or electroless plating.

Thereafter, as shown in FIG. 7C, the plating resist pattern 32 is removed with a solvent.

Next, as shown in FIG. 7D, the semiconductor element 21 having the solder bumps 24 formed on the semiconductor element electrodes 22 in advance is bonded to the surface of the plating wiring layer 23 by flip chip bonding.

Thereafter, as shown in FIG. 7E, the first resin 25 is sealed and cured. The first resin 25 can be applied before joining the semiconductor element 21 to the plating wiring layer 23.

Next, as shown in FIG. 7 (f), the copper plate is melted and removed with an etching solution having a selectivity only for the copper plate 31, for example, a cupric sulfate solution, so that the back surface of the plating wiring layer 23 is exposed. You. At this time, the back surface of the plating wiring layer 23 formed in the copper plate concave portion 51 of the copper plate 31 forms the conductive protrusion 52.

Next, as shown in FIG. 7G, a second resin 27 is applied and cured for the purpose of protecting the back surface of the plating wiring layer 23. At this time, the conductive projections 52 are exposed to form external electrodes.

As described above, according to the present embodiment, since the conductive projections 52 are formed on the back surface of the plating wiring layer 23, external electrodes such as solder balls are not required, thereby realizing a low-cost semiconductor device. Can be.

Next, a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention. In FIG. 8, 21 is a semiconductor element, and 22 is a semiconductor element electrode formed on the semiconductor element. 23 is a plating wiring layer, 24
Is a solder bump for electrically connecting the semiconductor element electrode 22 and the plating wiring layer 23, and 25 is a first resin for sealing the lower surface of the semiconductor element 21 and the surface of the plating wiring layer 23. 26
Are solder balls connected to the back surface of the plating wiring layer 23;
Reference numeral 7 denotes a second resin that seals the back surface of the plating wiring layer 23.

The semiconductor device according to the present embodiment includes a semiconductor element 2
1 has a structure in which the arrangement of the semiconductor element electrodes 22 provided on the surface of the semiconductor device 21 is drawn out of the semiconductor element 21 by the plating wiring layer 23. The gap between the plating wiring layer 23 and the semiconductor element 21 is the first resin 25. A portion of the plating wiring layer 23 where the solder balls 26 are not provided is sealed with a second resin 27. According to the present embodiment, the structure can easily cope with the increase in the number of pins by drawing out the plating wiring layer 23 outside the semiconductor element 21.

Next, FIG. 9 is a sectional view showing a method for manufacturing a semiconductor device by a metal plate melting method according to the fourth embodiment of the present invention. In FIG. 9, 21 is a semiconductor element, 22 is a semiconductor element electrode, 23 is a plating wiring layer, 24 is a solder bump,
25 is a first resin, 26 is a solder ball, 27 is a second resin, 31 is a copper plate, and 32 is a plating resist pattern formed on the copper plate 31.

Hereinafter, a method for manufacturing a semiconductor device by a metal plate melting method according to the fourth embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 9A, a plating resist is applied on a copper plate 31, exposed and developed to form a plating resist pattern 32. Next, gold (A
u), palladium (Pd), nickel (Ni), and palladium (Pd) are plated in this order to form a plated wiring layer 23. Here, each plating method may be electrolytic plating or electroless plating.

Thereafter, as shown in FIG. 9B, the plating resist pattern 32 is removed with a solvent.

Next, as shown in FIG. 9C, the semiconductor element 21 having the solder bumps 24 formed on the semiconductor element electrodes 22 in advance is bonded to the surface of the plating wiring layer 23 by flip chip bonding.

Thereafter, as shown in FIG. 9D, the first resin 25 is sealed and cured. Here, since the plating wiring layer 23 is formed up to the region outside the semiconductor element 21, the resin sealing region also becomes large.

Next, as shown in FIG. 9E, the copper plate is melted and removed with an etching solution having a selectivity only for the copper plate 31, for example, a cupric sulfate solution, thereby exposing the back surface of the plating wiring layer 23. .

Next, as shown in FIG. 9F, after the solder balls 26 are mounted on the back surface of the plating wiring layer 23, the plating wiring layer 23 and the solder balls 26 are joined by heating and melting. Here, the solder paste may be supplied before the solder balls 26 are mounted.

Next, as shown in FIG. 9G, a second resin 27 is applied and cured for the purpose of protecting the plating wiring layer.

As described above, according to the present embodiment, a semiconductor device which can easily cope with the increase in the number of pins can be manufactured by drawing out the plating wiring layer 23 outside the semiconductor element 21.

Next, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a sectional view showing a semiconductor device according to the fifth embodiment of the present invention. FIG.
In the figure, 21 is a semiconductor element, and 22 is a semiconductor element electrode formed on the semiconductor element. 23 is a plating wiring layer,
61 is a resist formed on the surface of the plating wiring layer 23;
62 is a bonding area in which an opening is formed in a part of the resist 61 to expose the surface of the plating wiring layer 23;
Is a bonding material for bonding the semiconductor element 21 and the resist 61;
Reference numeral 64 denotes a gold wire for electrically connecting the semiconductor element electrode 22 and the plating wiring layer 23, and reference numeral 65 denotes a first resin for sealing the surface of the semiconductor element 21, the surface of the plating wiring layer 23, and the gold wire 64. Reference numeral 26 denotes a solder ball connected to the back surface of the plating wiring layer 23, and reference numeral 27 denotes a second resin that seals the back surface of the plating wiring layer 23.

The semiconductor device according to the present embodiment has the second resin 2
The semiconductor element 21 is bonded to the plating wiring layer 23 supported by the semiconductor element 21 with its surface facing upward via a resist, and the semiconductor element electrode 22 of the semiconductor element 21 and the bonding area 6 are bonded.
2 is electrically connected by a gold wire 64. The area of the semiconductor element 21 and the gold wire 64 is sealed on one side with a first sealing resin 65, and a solder ball 26 is provided on the bottom surface of the plated wiring layer 23 which is opened and exposed in the second resin 25. It is what is being done. That is, wiring is routed from the bonding area 62 to the back surface of the semiconductor element 21 through the plating wiring layer 23, and the semiconductor element 2
1 has a structure in which solder balls 26 are provided as external terminals in the lower surface region.

Next, FIG. 11 is a sectional view showing a method of manufacturing a semiconductor device by a metal plate melting method according to a fifth embodiment of the present invention. In FIG. 11, 21 is a semiconductor element, 22 is a semiconductor element electrode, 23 is a plating wiring layer, 61 is a resist, 62 is a bonding area, 63 is a bonding material, 64
Is a gold wire, 65 is a first resin, 26 is a solder ball,
27 is a second resin. 31 is a copper plate, 32 is a copper plate 31
It is a plating resist pattern formed thereon.

Hereinafter, a method of manufacturing a semiconductor device by a metal plate melting method according to the fifth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

First, as shown in FIG.
A plating resist is applied, exposed, and developed to form a plating resist pattern 32. Next, gold (A
u), palladium (Pd), nickel (Ni), and palladium (Pd) are plated in this order to form a plated wiring layer 23. Each plating method may be electrolytic plating,
Electroless plating may be used.

Thereafter, as shown in FIG. 11B, the plating resist pattern 32 is removed with a solvent.

Next, as shown in FIG. 11C, a resist 61 is applied and cured for the purpose of protecting the surface of the plating wiring layer 23. At this time, a bonding area 62 is formed exposing a part of the surface of the plating wiring layer. The method of applying the resist 61 may be a printing method or a photo method. Then, the semiconductor element 21 is bonded to the surface of the resist 61 with the bonding material 63 with the surface on which the semiconductor element electrode 22 is formed facing upward. A silver (Ag) paste or an insulating resin paste is used as the bonding material 63. Then, the semiconductor element electrode 2 and the bonding area 62 are electrically connected by wire bonding with the gold wire 64.

Next, as shown in FIG.
The surface on which the semiconductor element 21 is mounted is sealed with the first resin 65.

Next, as shown in FIG.
The back surface of the plating wiring layer 23 is exposed by melting and removing the copper plate with an etchant having a selectivity only, for example, a cupric sulfate solution.

Next, as shown in FIG. 11F, after the solder balls 26 are mounted on the back surface of the plating wiring layer 23, the plating wiring layer 23 and the solder balls 26 are joined by heating and melting. Here, the solder paste may be supplied before the solder balls 26 are mounted.

Next, as shown in FIG. 11G, a second resin 27 is applied and cured for the purpose of protecting the plating wiring layer.

As described above, according to the present embodiment, a low-cost, high-yield semiconductor device can be realized by using the existing technology of wire bonding for bonding the semiconductor elements 21.

Next, a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 12 is a sectional view showing a semiconductor device according to the sixth embodiment of the present invention. In FIG. 6, 21 is a semiconductor element, and 22 is a semiconductor element electrode formed on the semiconductor element. 23 is a plating wiring layer, 2
Reference numeral 4 denotes a solder bump for electrically connecting the semiconductor element electrode 22 to the plating wiring layer 23, and reference numeral 25 denotes a first resin for sealing the lower surface of the semiconductor element 21 and the surface of the plating wiring layer 23. 2
6 is a solder ball connected to the back surface of the plating wiring layer 23;
27 is a second resin for sealing the back surface of the plating wiring layer 23. Reference numeral 72 denotes a saw-toothed plating uneven portion formed on a part of the plating wiring layer 23.

The semiconductor device of the present embodiment has the semiconductor element 2
1, the arrangement of the semiconductor element electrodes 22 provided on the surface of the substrate 1 is arranged in a grid pattern by the plating wiring layer 23, and is arranged.
A solder ball 26 which is a ball electrode serving as an external terminal is provided on the plating wiring layer 23. The gap between the plating wiring layer 23 and the semiconductor element 21 is sealed with a first resin 25, and the back surface of the plating wiring layer 23 is
It is a structure sealed with. The semiconductor device has the same configuration as that of the semiconductor device of the first embodiment described above, except that the sawtooth-plated uneven portion 72 is formed on a part of the plating wiring layer 23, and is added to the plating wiring layer 23. It has a structure to absorb stress.

Next, FIG. 13 is a sectional view showing a method of manufacturing a semiconductor device by a metal plate melting method according to the sixth embodiment of the present invention. In FIG. 13, reference numeral 21 denotes a semiconductor element;
Is a semiconductor element electrode, 23 is a plating wiring layer, 24 is a solder bump, 25 is a first resin, 26 is a solder ball, 27 is a second resin, 31 is a copper plate, and 32 is a plating resist formed on the copper plate 31. The pattern 71 is a saw-toothed copper plate uneven portion formed on a part of the copper plate 31, and the reference numeral 72 is a sawtooth plated uneven portion formed on a part of the plating wiring layer 23.

Hereinafter, a method of manufacturing a semiconductor device by a metal plate melting method according to the sixth embodiment will be described with reference to FIG.

First, as shown in FIG.
Is partially etched to form a saw-toothed copper plate uneven portion 71. Instead of partially etching the surface of the copper plate 31, the serrated copper plate uneven portion 71 may be formed by cutting. Further, the shape of the serrated copper plate uneven portion 71 may be a sine wave shape or a triangular wave shape instead of the sawtooth shape.

Next, as shown in FIG.
A plating resist is applied, exposed, and developed to form a plating resist pattern 32. Next, gold (A
u), palladium (Pd), nickel (Ni), and palladium (Pd) are plated in this order, and the serrated copper plate
1 and the plating wiring layer 23 are formed. By this step, the sawtooth-plated uneven portion 72 is formed on the plating wiring layer 23 according to the shape of the sawtooth-shaped copper plate uneven portion 71 of the copper plate 31. Each plating method may be electrolytic plating or electroless plating.

Thereafter, as shown in FIG. 13C, the plating resist pattern 32 is removed with a solvent.

Next, as shown in FIG. 13D, the semiconductor element 21 having the solder bumps 24 formed on the semiconductor element electrodes 22 in advance is bonded to the surface of the plating wiring layer 23 by flip chip bonding.

Thereafter, as shown in FIG.
And curing is performed. The first resin 25
Can be applied before joining the semiconductor element 21 to the plating wiring layer 23.

Next, as shown in FIG.
The back surface of the plating wiring layer 23 is exposed by melting and removing the copper plate with an etchant having a selectivity only, for example, a cupric sulfate solution.

Next, as shown in FIG. 13G, after the solder balls 26 are mounted on the back surface of the plating wiring layer 23, the plating wiring layer 23 and the solder balls 26 are joined by heating and melting. Here, the solder paste may be supplied before the solder balls 26 are mounted.

Next, as shown in FIG. 13H, a second resin 27 is applied and cured for the purpose of protecting the plating wiring layer.

As described above, according to the present embodiment, the serration-shaped plating irregularities 72 are formed on the plating wiring layer 23 to absorb the stress applied to the plating wiring layer 23, thereby achieving high reliability. A semiconductor device can be realized.

Note that the second, third, fourth, fifth,
As a manufacturing method in the sixth embodiment, a transfer plate peeling method may be used instead of the metal plate melting method.

Also, the first, second, third, fourth,
In the fifth and sixth embodiments, the configuration of the plating wiring layer 23 is gold / palladium / nickel / palladium (Au / P
d / Ni / Pd), but gold / nickel / copper / nickel / gold (Au / Ni / Cu / Ni / Au), gold / nickel / gold (Au / Ni / Au), palladium / nickel / A configuration such as palladium (Pd / Ni / Pd), palladium / nickel (Pd / Ni), gold / palladium / nickel (Au / Pd / Ni), or gold / nickel (Au / Ni) may be used.

In the first, second, third, fourth, and sixth embodiments, gold (A) is used instead of the solder bump 24.
u), metal bumps such as nickel (Ni), and metal balls such as copper may be used. The bonding material used for the flip chip bonding may be solder, conductive paste, anisotropic conductive film, or anisotropic conductive paste.

In the first, third, fourth, and sixth embodiments, the solder ball 26 is bonded to the back surface of the plating wiring layer 23, and then the second resin 27 is applied and cured. Only the mounting portion of the solder ball 26 is the plated wiring layer 23
After applying and curing the second resin 27 so that the back surface of the plating wiring layer 23 is exposed, the solder ball 26 may be bonded to the back surface of the plating wiring layer 23.

In the first, third, fourth, and sixth embodiments, instead of bonding the solder balls 26, metal balls such as copper or metal-coated resin balls may be bonded by supplying a solder paste. I do not care.

Further, in the first, third, fourth and sixth embodiments, instead of applying and curing the second resin 27, a solder resist may be formed by a printing method. It may be formed by a photo method.

[0105]

As described above, the semiconductor device of the present invention can be formed by melting and removing a metal plate after forming a plating wiring layer, or by peeling and removing a transfer plate after forming a plating wiring layer. A conventionally required resin substrate and through holes can be omitted, and a small and lightweight semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a manufacturing method by a metal plate melting method according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing method by a transfer plate peeling method according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing method by a metal plate melting method according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a third embodiment of the present invention;

FIG. 7 is a sectional view showing a manufacturing method by a metal plate melting method according to a third embodiment of the present invention.

FIG. 8 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention;

FIG. 9 is a sectional view showing a manufacturing method by a metal plate melting method according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view showing a semiconductor device according to a fifth embodiment of the present invention;

FIG. 11 is a sectional view showing a manufacturing method by a metal plate melting method according to a fifth embodiment of the present invention.

FIG. 12 is a sectional view showing a semiconductor device according to a sixth embodiment of the present invention;

FIG. 13 is a sectional view showing a manufacturing method by a metal plate melting method according to a sixth embodiment of the present invention.

FIG. 14 is a sectional view showing a conventional semiconductor device.

FIG. 15 is a sectional view showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Semiconductor element electrode 3 Resin substrate 4 Substrate surface conductor 5 Substrate surface resist 6 Bonding area 7 Substrate backside conductor 8 Substrate backside resist 9 Ball land 10 Through hole 11 Bonding material 12 Gold wire 13 Solder ball 14 Sealing resin 21 Semiconductor Element 22 Semiconductor element electrode 23 Plating wiring layer 24 Solder bump 25 First resin 26 Solder ball 27 Second resin 28 Resin opening 31 Copper plate 32 Plating resist pattern 41 Transfer plate 51 Copper plate recess 52 Conductive protrusion 61 Resist 62 Bonding area 63 bonding material 64 gold wire 65 first resin 71 serrated copper plate uneven part 72 saw tooth plated uneven part

Continuing from the front page (72) Inventor Nozomu Shimoishizaka 1-1, Yukicho, Takatsuki-shi, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd. (72) Inventor Shinji Murakami 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Corporation (72) Inventor Shigeki Sakaguchi 1-1, Sachimachi, Takatsuki-shi, Osaka Prefecture Inside Matsushita Electronics Corporation (72) Inventor Hiroaki Fujimoto 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation

Claims (6)

[Claims] 1. A semiconductor element, a plated wiring layer on which the semiconductor element is mounted, a connection conductor for electrically connecting the semiconductor element to a surface of the plated wiring layer, and the mounted semiconductor element A first resin that protects the surface of the plating wiring layer and the connection conductor element; an external electrode that is electrically connected to the back surface of the plating wiring layer; and a second resin that protects the back surface of the plating wiring layer. A semiconductor device comprising a resin. 2. The semiconductor device according to claim 1, wherein an opening for partially exposing the back surface of the plating wiring layer is provided in the second resin instead of the external electrode. 3. The semiconductor device according to claim 1, further comprising a conductive protrusion formed of a plated wiring layer partially exposed from the second resin, instead of the external electrode. 4. The semiconductor device according to claim 1, wherein a saw-toothed unevenness is provided on the plated wiring layer. 5. A step of forming a plating wiring layer on a surface of a metal plate, placing a semiconductor element on the surface of the plating wiring layer, and connecting the semiconductor element and the surface of the plating wiring layer via a connection conductor. Electrically connecting the semiconductor element, the bonding conductor, and the plating wiring layer with a first resin, and removing the plating wiring layer from the metal plate on which the plating wiring layer is formed. A step of selectively melting and removing only the remaining metal plate to expose the back surface of the plating wiring layer, a step of heating and melting the solder ball and joining it to the back surface of the plating wiring layer, and A method for manufacturing a semiconductor device, comprising a step of sealing with a second resin. 6. A step of forming a plating wiring layer on a transfer plate having low adhesion to the second resin and the plating wiring layer instead of the step of forming the plating wiring layer on the surface of the metal plate, Leaving the plating wiring layer from the transfer plate on which the plating wiring layer is formed in place of the step of selectively melting and removing only the metal plate while leaving the plating wiring layer from the metal plate on which the layer is formed; 6. The method for manufacturing a semiconductor device according to claim 5, further comprising a step of removing and removing only the transfer plate.