JP2010135828A - Substrate and manufacturing method therefor, and circuit device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate having improved moisture resistance, a method for manufacturing the substrate, a circuit device, and a method for manufacturing the circuit device. <P>SOLUTION: The substrate 20 is composed of a base material 12, wiring 14 formed on the top surface of the base material 12, a covering layer 18 which covers the wiring 14 with the exception of an region acting as a connection part, a rear surface electrode 32 formed on the bottom surface of the base material 12, and a through electrode 30 which penetrates the base material 12 to connect the wiring 14 and the rear surface electrode 32. The width of irregularities of the surface of the wiring 14 positioned at the peripheral part of the base material 12 is made larger than that positioned at the center of the base material 12, and thereby, the reliability of adhesion between the wiring 14 and the covering layer 18 at loading thermal cycling is improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a substrate, a manufacturing method thereof, a circuit device, and a manufacturing method thereof. In particular, the present invention relates to a substrate having a structure in which a wiring formed on a main surface of a base material is covered with a coating layer and a method for manufacturing the same. Furthermore, the present invention relates to a circuit device including such a substrate and a manufacturing method thereof.

  As electronic devices such as mobile phones become smaller and more functional, circuit devices housed therein are mainly equipped with fine wiring. A circuit device having a wiring board 107 will be described with reference to FIG.

  Here, the circuit device 100 is configured by mounting a circuit element (semiconductor element 105) on the first wiring layer 102 </ b> A formed on the upper surface of the wiring substrate 107.

  In the wiring board 107, wiring layers are formed on the front surface and the back surface of the base material 101 made of a resin such as glass epoxy. Here, the first wiring layer 102 </ b> A and the second wiring layer 102 </ b> B are formed on the upper surface of the substrate 101. The first wiring layer 102A and the second wiring layer 102B are stacked with an insulating layer 103 interposed therebetween. A third wiring layer 102 </ b> C and a fourth wiring layer 102 </ b> D are stacked on the lower surface of the substrate 101 with an insulating layer 103 interposed therebetween. Each wiring layer is connected at a predetermined location by a connecting portion 104 provided through the insulating layer 103. Further, the second wiring layer 102 </ b> B and the third wiring layer 102 </ b> C are connected at a predetermined location by a connecting portion 104 provided so as to penetrate the base material 101. Here, the thickness of the wiring board 107 is, for example, about 1 mm.

  In addition, the first wiring layer 102 </ b> A that is the uppermost wiring layer is covered with a covering layer 109. The first wiring layer 102A in the electrical connection region (the portion to which the thin metal wire 108 is connected) is exposed from an opening provided by partially removing the covering layer 109. Here, the covering layer 109 is made of a resin material such as an epoxy resin.

  A semiconductor element 105 is fixed to the upper surface of the covering layer 109. Here, the lower surface of the semiconductor element 105 is fixed using an insulating adhesive or the like. The electrode provided on the upper surface of the semiconductor element 105 is electrically connected to the first wiring layer 102 </ b> A via the fine metal wire 108.

  Further, the upper surface of the wiring substrate 107 is covered with a sealing resin 106 so that the semiconductor element 105 and the fine metal wires 108 are covered.

  The manufacturing method of the wiring board 107 having the above-described configuration is as follows. First, the second wiring layer 102B and the third wiring layer 102C are formed on the upper and lower surfaces of the base material 101 made of a resin-based material such as an epoxy resin. These wiring layers are formed by etching or selectively plating the attached conductive film. Further, a connection portion 104 that penetrates the base material 101 and connects the second wiring layer 102B and the third wiring layer 102C is formed. Next, the second wiring layer 102B and the third wiring layer 102C are covered with an insulating layer 103 made of resin. Further, a first wiring layer 102A and a fourth wiring layer 102D are formed on the surface of the insulating layer 103. The method of forming these wiring layers is the same as that of the second wiring layer 102B and the like described above. Further, a connection portion 104 that penetrates the insulating layer 103 and connects the first wiring layer 102A and the second wiring layer 102B is formed. In addition, the covering layer 109 is formed so as to cover the first wiring layer 102A which is the uppermost wiring layer, and the first wiring layer 102A in the portion serving as an electrical connection region is exposed to the outside. Layer 109 is partially removed to provide an opening.

  However, the circuit device 100 configured as described above has a problem that the adhesion between the uppermost first wiring layer 102A and the covering layer 109 is not sufficient. Specifically, when the scale of a circuit integrated in the semiconductor element 105 increases, the amount of heat generated by the operation of the semiconductor element 105 increases. The first wiring layer 102A made of metal such as copper and the coating layer 109 made of resin have greatly different coefficients of thermal expansion, so that thermal stress is generated at the interface between them. Therefore, there is a possibility that the covering layer 109 may be peeled off from the first wiring layer 102 </ b> A due to many thermal stresses applied to the interface between them.

  A method for solving this problem is described in Patent Document 2 below. This technical matter will be described with reference to FIG. Here, the conductor circuit 111 is formed on the upper surface of the insulating substrate 110. Further, in order to avoid a problem caused by a difference in thermal expansion coefficient between the conductor circuit 111 and the insulating resin portion, unevenness with uniform roughness is formed on the surface of the conductor circuit 111.

  Specifically, in Patent Document 2, in order to realize the above configuration, the conductor circuit 111 is patterned using an etching solution containing hydrogen peroxide, sulfuric acid, tetrazole, and the like. Thereby, the compound 112 adheres to the surface of the conductor circuit 111 in the etching process. As a result, the etching proceeds uniformly from the portion other than the portion where the compound 112 is adhered, and uniform unevenness is formed on the surface of the conductor circuit 111. The following Patent Document 2 describes that the adhesion strength between the conductor circuit 111 and another resin member is improved by this, and the problem of separation between the two is avoided.

JP 2003-324263 A

JP 2002-76610 A

  However, the technical matter described in Patent Document 2 has a problem that the conductor circuit 111 is peeled off from the solder resist. 18A is a cross-sectional view showing the vicinity of the periphery of the conductor circuit 111, and FIG. 18B is a cross-sectional view showing a state where the coating layer 114 (solder resist) is peeled from the conductor circuit 111.

  Referring to FIG. 18A, a conductor circuit 111 is formed on the upper surface of the substrate 110, and an end portion (right end portion on the paper surface) of the conductor circuit 111 is formed by an electrolytic plating method. It is covered with a plating film 112. Furthermore, a covering layer 114 made of a resin material is formed so that the upper surfaces of the conductor circuit 111 and the substrate 110 are covered. The coating layer 114 covers the surface of the conductor circuit 111 and partially covers the surface of the plating film 112.

  With reference to FIG. 18B, a phenomenon in which the coating layer 114 formed as described above is separated will be described. Specifically, as described above, since the thermal expansion coefficient is different between the conductor circuit 111 and the covering layer 114, thermal stress is generated at the boundary between the two due to temperature change. This thermal stress is large at the end of the coating layer 114. Referring to this figure, the magnitude F1 of the thermal stress near the inside of the coating layer 114 (left side on the paper surface) is small, and the magnitude of the thermal stress near the periphery at the end of the coating layer 114. F2 is relatively large. Further, since the roughness of the conductor circuit 111 is substantially the same in all regions, the adhesion strength between the conductor circuit 11 and the covering layer 114 is substantially the same throughout.

  Due to the above, a large thermal stress is applied to the interface between the conductor circuit 111 and the covering layer 114 in the peripheral portion of the substrate 110 whenever the temperature changes. As a result, there arises a problem that the covering layer 114 is peeled off from the conductor circuit 111 in this region. If the covering layer 114 is peeled off, moisture easily enters the interface between the two, and the moisture resistance deteriorates.

  The present invention has been made in view of the above-described problems. A main object of the present invention is to provide a substrate having improved moisture resistance, a manufacturing method thereof, a circuit device, and a manufacturing method thereof.

  The substrate of the present invention comprises a base material, a wiring formed on one main surface of the base material and having a connection portion, and a coating layer that covers the wiring except the connection portion, The connecting portion of the wiring is arranged so as to surround one region defined on the upper surface of the base material, and the width of the unevenness on the surface of the wiring located in the peripheral portion of the one region is set to the central portion of the one region. It is characterized in that it is made larger than the width of the unevenness of the wiring located in the area.

  The present invention is a circuit device having a substrate and a circuit element mounted on the substrate, and the substrate is formed on a base material and one main surface of the base material, and is electrically connected to the circuit element. A wiring having a connecting portion connected to the wiring, and a coating layer covering the wiring except the connecting portion, wherein the connecting portion of the wiring is a region of the one main surface of the base material The width of the unevenness on the surface of the wiring located in the peripheral part of the one region is made larger than the width of the unevenness of the wiring located in the central part of the one region. .

  According to the substrate and the circuit device of the present invention, the width of the unevenness on the wiring surface located in the peripheral portion of the substrate is made larger than that of the wiring surface located in the central portion of the substrate. As a result, in the central portion of the substrate, the adhesion strength between the wiring and the coating layer can be improved, and the separation of both can be suppressed. Further, in the peripheral part of the substrate, since the width of the surface irregularities of the wiring is relatively large, thermal stress (stress) is dispersed, and peeling of the coating layer from the wiring is prevented.

  Moreover, according to the manufacturing method of the present invention, the substrate and circuit device having the above-described configuration can be efficiently manufactured. Specifically, by using etchants having different properties in the step of etching the peripheral portion of the wiring and the step of etching the central portion of the wiring, the width of the unevenness of the wiring located in the peripheral portion is reduced to the central portion. Can be larger. In other words, the width of the unevenness on the surface of the wiring located in the central portion of the substrate can be made finer than that in the peripheral portion.

  Furthermore, an electroless plating film formed so as to cover the entire upper surface of the substrate may be used as a plating wire when performing electrolytic plating. In such a case, the step of removing the unnecessary electroless plating film and the step of etching the surface of the wiring located in the peripheral portion can be performed in the same step. Therefore, an increase in the number of processes due to a change in roughness on the surface of the wiring is suppressed.

It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. (A)-(C) is the image which image | photographed the wiring contained in the circuit apparatus of this invention. (A) And (B) is the image which image | photographed the wiring contained in the circuit apparatus of this invention. It is a figure which shows the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, and is the image which image | photographed the surface of the electrolytic plating film. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is a figure which shows the manufacturing method of the circuit apparatus of this invention, (A) is sectional drawing, (B) is a top view. It is sectional drawing which shows the circuit apparatus of background art. It is sectional drawing which shows the circuit apparatus of background art. (A) And (B) is sectional drawing which shows the circuit apparatus of background art.

<First Embodiment>
First, the structure of the circuit device 10 according to the present embodiment will be described with reference to FIGS. FIG. 1 is a diagram showing the overall structure of the circuit device 10, FIG. 2 is a diagram showing the roughness of the wiring 14, FIG. 3 is an image of the surface state of the wiring 14, and FIG. FIG. 5 is a diagram showing another structure of the wiring 14, which is an image of the state of the wiring surface and the plating surface.

  First, the structure of the circuit device 10 will be described with reference to FIG. FIG. 1A is a cross-sectional view of the circuit device 10, and FIG. 1B is a plan view thereof. Here, FIG. 1A is a typical cross-sectional view of the plan view shown in FIG.

  The circuit device 10 is a resin-encapsulated CSP having a size that is slightly larger in external dimensions than the built-in semiconductor element 16. The external appearance of the circuit device 10 is a rectangular parallelepiped shape or a cubic shape. Further, the circuit device 10 is a BGA (Ball Grid Array) in which connection electrodes 34 electrically connected to the built-in semiconductor element 16 are provided in a grid shape on the back surface of the substrate 20.

  In addition, since it is possible also by SIP etc., the position of a connection electrode may be arrange | positioned in the ring shape around a board | substrate, and may be arrange | positioned at random.

  Referring to FIG. 1A, a circuit device 10 includes a substrate 20 having a wiring 14 provided on an upper surface, a semiconductor element 16 fixed to the substrate 20 and electrically connected to the wiring 14, and a semiconductor element 16 And a sealing resin 22 for covering the upper surface of the substrate 20.

  The substrate 20 is formed on the base 12, the wiring 14 formed on the upper surface of the base 12, the coating layer 18 that covers the wiring 14 excluding the region to be the connection portion, and the lower surface of the base 12. It consists of a back electrode 32 and a through electrode 30 that penetrates the substrate 12 and connects the wiring 14 and the back electrode 32.

  The substrate 12 is glass epoxy or the like in which glass fibers are impregnated with an epoxy resin, and is an interposer mainly composed of a resin material. The base material 12 has a function of mechanically supporting the semiconductor element 16 in the manufacturing process, while wiring layers are formed on the upper surface and the back surface. As the material of the base material 12, materials other than a resin-based material can be used. For example, a substrate made of an inorganic material such as ceramic or Si, a metal substrate made of metal such as copper or aluminum, or the like can be used. It can also be employed as a material. When a metal substrate is adopted as the material of the base material 12, the upper surface and the lower surface of the base material 12 are covered with an insulating layer made of resin or the like, and the wiring 14 and the base material 12 are insulated.

  The wiring 14 is made of a metal such as copper or aluminum, and is formed into a predetermined shape by selectively etching a conductive foil having a thickness of about 20 μm to 50 μm laminated on the upper surface of the base 12. The wiring 14 may be formed by selectively depositing a plating film. The present embodiment is characterized in that the width of the unevenness on the surface of the wiring 14 located in the peripheral portion of the opening 24 of the coating layer 18 is made larger than that in the periphery of the opening 24, but this feature is It will be described later. Further, here, the single layer wiring 14 is formed on the upper surface of the base material 12, but two or more multilayer wiring layers laminated via an insulating layer are formed on the upper surface or the lower surface of the base material 12. May be. Further, the substrate structure may be anything, such as a clad structure in which patterns are laminated from the bottom to the top via an insulating layer.

  Referring to FIG. 1B, the wiring 14 includes a first connecting portion 14A (connecting portion), a second connecting portion 14B, and a wiring portion 14C that is elongated between both connecting portions. The first connection portion 14A is a portion that is electrically connected to the semiconductor element 16 (circuit element). In the drawing, as an example, a plurality of first connection portions 14A are provided so as to surround the semiconductor element 16 along the peripheral portion of the substrate 20. Is formed. The 2nd connection part 14B is a site | part which the penetration electrode 30 connects to a lower surface, and is located inside the circuit board 20 rather than 14 A of 1st connection parts. The first connecting portion 14A and the second connecting portion 14B are connected by a wiring portion 14C that is longer than both connecting portions. By configuring the wiring 14 in such a configuration, the back electrode 32 formed by arranging the electrodes arranged in a dense line on the upper surface of the semiconductor element 16 and spaced apart in a matrix (matrix) on the back surface of the substrate 20. Can be rearranged as

  On the lower surface of the base material 12, a back electrode 32 is provided by etching the conductive foil. Due to the configuration of the wiring 14 described above, the distance at which the back electrodes 32 are separated from each other is longer than the distance at which the first connection portions 14 </ b> A of the wiring 14 are separated from each other.

  The through electrode 30 is formed by embedding a metal such as copper in a through hole provided by penetrating the base material 12 at a predetermined location in the thickness direction by a plating method or the like. Referring to FIG. 1B, a through electrode 30 and a back electrode 32 are provided below the second connection portion 14 </ b> B of each wiring 14. Here, except for the portion where the connection electrode 34 is formed, a coating resin that covers the back electrode 32 and the lower surface of the substrate 12 may be provided. Further, in this case, as in the case of the wiring 14 on the upper surface, the width of the unevenness on the surface of the back electrode 32 located in the peripheral portion of the opening 24 of the coating layer 18 is positioned other than the peripheral portion of the opening of the coating layer 18. It may be larger than the back electrode 32.

  The upper surface of the base material 12 is covered with a covering layer 18 so as to cover the wiring 14 except for a portion to be a connection portion. The covering layer 18 is made of a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyethylene. The thickness of the covering layer 18 covering the upper surface of the wiring 14 is, for example, about 20 μm to 100 μm. Referring to FIG. 1B, a rectangular opening 24 is provided by partially removing the covering layer 18 so that the first connecting portion 14A of each wiring 14 is exposed. The covering layer 18 is also called a solder resist or PSR (Photo solder resist). In addition, you may provide this coating layer in the back surface of a board | substrate.

  The semiconductor element 16 (circuit element) is fixed to the upper surface of the substrate 20 and is electrically connected to the wiring 14. Specifically, the semiconductor element 16 is mounted on the substrate 20 face up, and its lower surface is fixed to the upper surface of the coating layer 18 with an insulating adhesive. In addition, when the back surface of the semiconductor element is fixed to GND, it is fixed to the island through a conductive material such as a brazing material or a conductive paste. Further, the electrode formed on the upper surface of the semiconductor element 16 is connected to the wiring 14 via a fine metal wire 26 made of Au or the like. Here, the semiconductor element 16 mounted face-up is illustrated, but the semiconductor element 16 may be mounted face-down. In this case, the semiconductor element 16 is placed so that the electrode is on the lower surface, and the wiring 14 formed on the upper surface of the substrate 20 and the semiconductor element 16 are electrically connected via the bump-shaped electrode connected to the electrode. Connected to.

  Here, the semiconductor element 16 is employed as the circuit element incorporated in the circuit device 10, but other circuit elements may be employed. Specifically, an active element such as an IC, LSI, discrete transistor, or diode may be employed as the circuit element. Furthermore, passive elements such as a chip resistor, a chip capacitor, and a sensor may be employed as the circuit element. Furthermore, a system in which a plurality of passive elements and active elements are combined and internally connected may be built inside the circuit device 10 (SIP: System in Package). In this case, referring to FIG. 1A, a passive element such as a chip resistor is arranged next to the semiconductor element 16. Further, the wiring 14 having the above-described configuration is formed in the semiconductor element 16 and its peripheral portion (one region).

  This substrate can be applied to a module in which circuit elements are simply mounted and a circuit device in which the entire substrate is sealed. Further, a semiconductor chip or a passive element can be considered as a circuit element mounted on the substrate or the circuit device. Moreover, these circuit elements are provided three-dimensionally or planarly. That is, in three dimensions, a plurality of semiconductor chips may be stacked. Furthermore, a plurality of semiconductor elements may be arranged in a plane. In either case, a system is configured by providing a plurality of circuit elements.

  The sealing resin 22 is made of a thermosetting resin formed by transfer molding or a thermoplastic resin formed by injection molding. Further, the sealing resin 22 is formed so as to cover the semiconductor element 16, the fine metal wire 26, and the upper surface of the substrate 20. Further, the sealing resin 22 is in contact with the upper surface of the substrate 12, the upper surface of the coating layer 18, the wiring 14 and the plating film 28.

  With reference to FIG. 1 (B), the structure of the circuit apparatus 10 is further demonstrated. In this figure, the thin metal wire 26 that connects the semiconductor element 16 and the wiring 14 is omitted.

  First, here, one semiconductor element 16 is mounted near the center of the substrate 20. A plurality of first connection portions 14 </ b> A of the wiring 14 are provided so as to surround the semiconductor element 16. The first connection portion 14 </ b> A is provided corresponding to the electrode provided on the upper surface of the semiconductor element 16.

  The upper surface of the substrate 20 is substantially entirely covered with the coating layer 18. In addition, the opening 24 is provided by partially removing the covering layer 18 in a quadrangular shape so that the first connection portion 14A of the wiring portion 14 is exposed. From the opening 24, the first connecting portion 14A of the wiring 14, the plating film 28 covering the first connecting portion 14A, and the upper surface of the base material 12 in the vicinity of the first connecting portion 14A are exposed.

  A plurality of wirings 14 are provided on the upper surface of the base material 12 and extend radially from below the semiconductor element 16 (near the center of the substrate 20) toward the periphery of the substrate 20. The second connection portion 14B is formed at a position inside the substrate 20 relative to the first connection portion 14A, and the through electrode 30 is connected to the lower side. The multiple second connection portions 14B can be classified into those arranged below the semiconductor element 16 and those arranged in a region outside the semiconductor element 16. Here, all the second connection portions 14 </ b> B may be arranged below the semiconductor element 16.

  The roughness of the surface of the wiring 14 will be described with reference to FIG. 2A is a cross-sectional view of the first connecting portion 14A of the wiring 14 and the vicinity thereof, and FIG. 2B is a plan view thereof. Here, FIG. 2A is a typical cross-sectional view of the plan view shown in FIG.

  In the present embodiment, the width of the unevenness on the surface of the wiring 14 located in the peripheral part of the opening 24 formed in the covering layer 18 is set to be a wiring located outside the peripheral part of the opening 24 formed in the covering layer 18. 14 is larger than the surface. In other words, the surface of the wiring 14 has a width of unevenness other than the periphery of the opening 24 smaller than that of the periphery. This improves the reliability of the wiring 14 and the coating layer 18 that covers the wiring 14 under a heat cycle load. That is, peeling of the coating layer 18 from the wiring 14 is prevented. Here, the surface of the wiring 14 is the upper surface and side surfaces of the wiring 14, and these surfaces are covered with the coating layer 18.

  Referring to FIG. 2A, wiring 14 is formed on the upper surface of the base material 12, and a covering layer 18 is formed so as to cover the wiring 14. Further, the semiconductor element 16 is fixed to the upper surface of the covering layer 18. Here, the first connection portion 14A and the wiring portion 14C of the wiring 14 are shown, the wiring portion 14C is covered with the covering layer 18, and the first connecting portion 14A is not covered with the covering layer 18 and is exposed. ing. The upper surface and side surfaces of the first connection portion 14A are covered with a plating film 28. As the plating film 28, for example, a film in which nickel (Ni) and gold (Au) are sequentially formed is used. Although not shown, one end of a fine metal wire is connected to the upper surface of the plating film 28, and the other end of the fine metal wire is connected to an electrode provided on the upper surface of the semiconductor element 16.

  The wiring 14 can be divided into a first roughened region 36 having a relatively small surface irregularity width and a second region 38 having a larger surface irregularity width than the first roughened region 36. The widths of the surface roughness of the first roughened region 36 and the second roughened region 38 can be adjusted by appropriately selecting an etchant used for etching these surfaces.

  The first roughening region 36 corresponds to the wiring 14 in the region inside the substrate 20 (left side in the drawing) from the middle of the wiring portion 14C, and a part of the wiring portion 14C and the second connection portion 14B (see FIG. 1). Including. Relatively fine irregularities are formed on the surface of the first roughened region 36, and the size of the convex portions on the surface is, for example, a height of 1.2 μm, and the width between the convex portions is about 1.7 μm. . In the first roughened region 36, an anchor effect is generated between the sharp irregularities on the surface and the coating layer 18, so that the adhesion strength between the wiring 14 and the coating layer 18 is improved. Furthermore, since the sharp irregularities are formed on the surface of the first roughened region 36, the surface area of the wiring 14 in this region is increased, and the area where the wiring 14 and the coating layer 18 are in close contact with each other increases. This also improves the adhesion strength between the wiring 14 and the coating layer 18 in the first roughened region 36.

  The second roughening region 38 corresponds to the wiring 14 in the region outside the substrate 20 (on the right side in the drawing) from the middle of the wiring portion 14C, and includes a part of the wiring portion 14C and the first connection portion 14A. The surface of the second roughened region 38 has a shape in which the width of the unevenness on the surface is not smaller than that of the first roughened region 36 as compared with the first roughened region 36 described above. Specifically, the size of the protrusions formed on the surface of the second roughened region 38 is, for example, a height of 0.8 μm and a width of about 2.4 μm. Therefore, as compared with the first roughened region 36, the convex portion on the surface of the second roughened region 38 has a wider shape.

  By configuring the surface of the second roughened region 38 to have the above-described configuration, it is possible to prevent the wiring 14 and the coating layer 18 from peeling off in the second roughened region 38. Specifically, when a temperature change occurs, the thermal expansion coefficient acts on the boundary surface between the coating layer 18 made of resin and the wiring 14 that is a metal material because the coefficients of thermal expansion are different. This thermal stress acts in parallel along the interface between the upper surface of the wiring 14 and the coating layer 18. Furthermore, this thermal stress is relatively small at the center of the substrate 20 and relatively large near the periphery of the opening 24 (see FIG. 1) of the coating layer 18. In other words, in the present embodiment, since the opening 24 is formed in the peripheral portion of the substrate 20, thermal stress is large in the peripheral portion of the substrate 20. Therefore, when peeling due to thermal stress occurs, it often occurs in the vicinity of the opening 24 of the coating layer 18, that is, in the peripheral portion of the substrate 20.

  In the present embodiment, the wiring 14 located in the peripheral portion of the substrate 20 is used as the second roughened region 38 as described above. As a result, in the second roughened region 38, since the width of the unevenness on the surface of the wiring 14 is large, there is no sharp shape where heat stress tends to concentrate. That is, the concentration of heat stress is suppressed. Thereby, peeling of the coating layer 18 from the wiring 14 in the peripheral portion of the substrate 20 is prevented.

  On the other hand, in the central portion of the substrate 20, as described above, the thermal stress is small with respect to the peripheral portion, so that the stress is likely to be concentrated. 14 generates a large anchor effect between the first roughened region 36 and the covering layer 18, and prevents the covering layer 18 from being peeled off from the wiring 14.

  As described above, in the present embodiment, a large thermal stress is applied to the boundary surface between the wiring 14 and the covering layer 18 by making the width of the surface unevenness of the wiring 14 different between the central portion and the peripheral portion of the substrate 20. Even if it acts, peeling of both is prevented.

  There are also the following effects. Because of the tendency to be light and thin, it is necessary to reduce the width of the wiring provided on the substrate and the interval between the wirings to improve the pattern mounting density. That is, the width of the wiring becomes thinner. At that time, if the surface roughness of the entire wiring area is in the roughened region, the stress shown in FIG. 18B is applied due to the mismatch of the thermal expansion coefficient with the coating layer or the sealing resin on the coating layer. Voids are generated at the neck), which may increase the electrical resistance.

  This is because stress concentrates on the base portion, and defects in the wiring concentrate there. However, as can be seen from FIG. 2, the second roughened region 38 is provided and a shape in which stress is not concentrated can suppress the generation of voids, thereby improving the reliability.

  With reference to FIG. 3, the image which image | photographed each area | region of the wiring 14 is demonstrated. 3A is an image of the surface of the wiring 14 in the first roughened region 36, FIG. 3B is an image of the surface of the wiring 14 in the second roughened region 38, and FIG. It is an image obtained by photographing both the first roughened area 36 and the second roughened area 38 of the wiring 14.

  3A and 3B, when the first roughened region 36 and the second roughened region 38 of the wiring 14 are compared, the surface of the first roughened region 36 is second. It can be understood that the degree of unevenness is larger than the surface of the roughened region 38. That is, the convex portion formed in the first roughened region 36 is higher in height and narrower than the convex portion formed in the second roughened region 38. As described above, the above-described effects can be obtained by making the surface roughness of the first roughened region 36 and the second roughened region 38 different. Such a configuration can be obtained by etching the first roughened region 36 and the second roughened region 38 with an etchant having different properties. Details of this matter will be described later.

  Referring to FIG. 3C, the left side of the wiring shown in this image is the first roughened region 36, and the right side is the second roughened region 38. From this image, it can be read that the roughness of the first roughened region 36 and the second roughened region 38 is different as the boundary line clearly appears.

  Further, referring to FIG. 2B, the second roughened region 38 (conductive material) of the wiring 14 is exposed together with the plated film 28 from the opening 24 provided by removing the covering layer 18. And the plating film 28 and the 2nd roughening area | region 38 which are exposed from the opening part 24 are coat | covered with the sealing resin 22 (refer FIG. 1 (A)). In other words, the coating layer 18 covers only the wiring 14, and the plating film 28 is not covered with the coating layer 18. Thereby, the adhesiveness between the sealing resin 22 and the wiring 14 can be improved. Specifically, the surface of the plating film 28 whose outermost surface is made of gold is very smooth. On the other hand, the second roughened region 38 of the wiring 14 is exposed from the opening 24, but the second roughened region 38 is rougher than the surface of the plating film 28.

  FIG. 4A is an image obtained by photographing the surface of the plating film 28, and FIG. 4B is an image obtained by photographing a representative surface of the wiring 14. From these figures, it can be read that the surface of the wiring 14 is rougher than the surface of the plating film 28. Therefore, with the above configuration, the adhesion strength between the sealing resin 22 and another member (here, the wiring 14) is improved.

  With reference to FIG. 5, another related configuration of the wiring 14 and the covering layer 18 will be described. 5A is a cross-sectional view of the first connecting portion 14A of the wiring 14 and the vicinity thereof, and FIG. 5B is a plan view thereof.

  The configuration shown in FIGS. 5A and 5B is basically the same as that described with reference to FIG. 2, and the difference is that the surface of the wiring 14 and the surface of the plating film 28 are the same. Is partially covered by the coating layer 18.

  That is, referring to FIG. 5A, the coating layer 18 covers a part of the second connection part 14B, the wiring part 14C, and the first connection part 14A (not shown) and a part of the plating film 28. It is covered. In other words, the entire surface of the wiring 14 that is not covered with the plating film 28 is covered with the covering layer 18.

  Referring to FIG. 5B, what is exposed from the opening 24 provided by removing the covering layer 18 is the plating film 28 covering the first connecting portion 14A, and the wiring 14 itself is not exposed to the outside.

  With such a configuration, since the wiring 14 is not exposed to the outside, oxidation of the surface of the wiring 14 is suppressed. Furthermore, the second roughened region 38 is formed to be extremely thin as compared with other regions, but since this portion is also covered with the coating layer 18, disconnection of the thin second roughened region 38 can be prevented. Specifically, the width of the second roughened region 38 is, for example, about 35 μm, and the width of the wiring 14 in the other region (first roughened region 36) is about 45 μm. The reason why the width of the second roughened region 38 is narrowed is that this portion is etched a plurality of times, as will be apparent from the description of the manufacturing method later.

  Furthermore, referring to FIG. 5A, the covering layer 18 covers the wiring 14 including the plating film 28, whereby the moisture resistance of the entire apparatus can be improved. Specifically, in addition to the surfaces of the wiring 14 and the plating film 28, the covering layer 18 covers a step portion at the boundary between them. Therefore, this increases the path between different materials of the covering layer 18 and the wiring 14, and the moisture resistance is improved by this amount.

  Further, referring to FIG. 5A, the wiring 14 at the end portion of the plating film 28 is provided with a recess 40 that is recessed inward. Specifically, after the plating film 28 is deposited on the first connection portion 14A of the wiring 14, the wiring 14 is thinly wet etched on the entire surface. Since wet etching proceeds in an isotropic manner, etching proceeds toward the plating film 28 (on the right side in the drawing) at the end portion of the plating film 28 to form a recess 40. And the edge part of the plating film 28 becomes a shape protruding in eaves shape. The recess 40 is filled with a resin material constituting the coating layer 18. The recess 40 is provided along the terminal portion of the plating film 28 on the upper surface and side surface of the wiring 14. With this configuration, the route at the boundary between the surface of the wiring 14 and the coating layer 18 is further lengthened, so that the moisture resistance is further improved.

<Second Embodiment>
In the present embodiment, a method for manufacturing the circuit device 10 having the above configuration will be described with reference to FIGS. In each of these drawings, (A) is a sectional view and (B) is a plan view.

  With reference to FIG. 6, first, a substrate 20 having a wiring or the like formed on the main surface of the base 12 is prepared. 6A is a cross-sectional view showing the substrate 20 in this process, and FIG. 6B is a plan view of the substrate 20 as viewed from above.

  With reference to FIG. 6 (A), the wiring 14 of a predetermined shape is formed on the upper surface of the base material 12, the back electrode 32 is formed on the back surface of the base material 12, and the through electrode 30 connecting the two is the base material. 12 is formed.

  The material of the base material 12 is the same as that of the first embodiment described above, and is made of a resin material, an inorganic material, or a metal material. The substrate 12 has the wiring 14 formed on the upper surface and the back electrode 32 formed on the lower surface, and also has a function of mechanically supporting the semiconductor element 16 in the manufacturing process.

  The wiring 14 is made of a metal such as copper or aluminum, and is formed by selectively etching a conductive foil having a thickness of about 20 μm to 50 μm attached to the upper surface of the substrate 12. Here, the wiring 14 includes a first connection portion 14A, a second connection portion 14B, and a wiring portion 14C that is elongated between the two connection portions. With reference to FIG. 6B, a plurality of wirings 14 are provided on the upper surface of the base material 12 and extend radially from the vicinity of the center of the substrate 20 toward the periphery. In plan view, a plurality of first connection portions 14 </ b> A are arranged in parallel along the side of the substrate 20. The second connection portion 14B is formed at a position inside the substrate 20 relative to the first connection portion 14A, and the through electrode 30 is connected to the lower side.

Similar to the wiring 14, the back electrode 32 is formed in a predetermined shape by etching the conductive foil adhered to the back surface of the substrate 12. Referring to FIG. 6B, the back surface electrodes 32 are arranged on the back surface of the substrate 20 at a regular interval in a grid pattern.

  The through electrode 30 is formed by embedding a metal such as copper by a plating method or the like in a through hole provided through the base material 12 at a predetermined location in the thickness direction.

  Next, referring to FIG. 7, an electroless plating film 42 is deposited on the upper surface of the substrate 12 and the surface of the wiring 14.

  7A and 7B, in this step, a plating film 42 having a thickness of, for example, about 1 μm is electrolessly formed on the upper surface of the base material 12 and the surface of the wiring 14 (upper surface and both side surfaces). Adhere by plating. The electroless plating film 42 is also attached to the surface of the wiring 14 that is a conductive material, and the electroless plating film 42 is also attached to the upper surface of the base material 12 that is an insulating material. The material of the electroless plating film 42 may be the same material (for example, copper) as the wiring 14 or other metal material.

  Due to the electroless plating film 42 formed in this step, all the wirings 14 formed on the upper surface of the substrate 20 are short-circuited. The electroless plating film 42 has an effect like a plated wire for power supply when an electrolytic plating film is formed in a later process.

  FIG. 8 is an image obtained by photographing the electrolytic plating film 42 formed by this process. Referring to this figure, the surface of the plating film 42 is more uneven than the surface of the first roughened region 36 (see FIG. 3A) and the surface of the second roughened region 38 (see FIG. 3B). The details are read. In the second roughened region 38, the surface of the second roughened region 38 is obtained by etching the surface of the electroless plating film 42 shown in FIG. The width of the unevenness becomes larger than that of the electroless plating film 42.

  Next, referring to FIG. 9, the upper surface of the substrate 20 on which the electroless plating film 42 is formed is covered with an etching resist 46. In this step, first, an etching resist 46 made of a resin material is thinly formed on the upper surface of the substrate 12. By doing so, the surface of the electroless plating film 42 covering the base material 12 and the wiring 14 is entirely covered with the etching resist 46.

  Further, after selectively irradiating the photosensitive etching resist 46 with light from above, a strong alkali solution is brought into contact with the etching resist 46. As a result, the etching resist 46 that has not been exposed is partially removed to form the opening 44.

  Referring to FIG. 9B, the first connecting portion 14A of the wiring 14 and the upper surface of the surrounding base material 12 are exposed from the opening 44 formed by the above method. Here, the portion exposed from the opening 44 is entirely covered with the electroless plating film 42.

  Referring to FIG. 10, next, etching is performed from the opening 44 of the etching resist 46 to remove the electroless plating film 42 exposed from the opening 44.

  In this step, wet etching is performed from the opening 44 provided by removing the etching resist 46. As a result, the electroless plating film 42 exposed from the opening 44 is etched. In this step, etching is performed until the electroless plating film 42 covering the upper surface of the substrate 12 is removed inside the opening 44.

  Referring to FIG. 10B, the electroless plating film 42 covering the upper surface of the substrate 12 is removed inside the opening 44 of the etching resist 46. On the other hand, the surface of the first connection portion 14A of the wiring 14 exposed in the opening 44 is also etched by this process.

  The purpose of the etching in this step is to deposit a plating film only on the surface of the first connecting portion 14A and not to deposit a plating film on the upper surface of the base material 12 in the next step of performing the electrolytic plating process. If, for example, a gold plating film is deposited on the upper surface of the substrate 12 in the next step, the electroless plating film 42 where the gold plating film is adhered may remain without being removed. If the electroless plating film 42 which is unnecessary as a product remains, there is a risk that the wires 14 are short-circuited via the electroless plating film 42. In the present embodiment, in order to eliminate such danger, the electroless plating film 42 that covers the upper surface of the base material 12 in the vicinity of the first connection portion 14A is formed by performing etching through the opening 44. It has been removed.

  In this step, when the material of the wiring 14 is copper, an etchant having a high etching rate between the wiring copper (the material of the wiring 14: for example, rolled copper foil or electrolytic copper) and electroless copper (electroless plating film 42). Is used to perform the etching. That is, an etchant that can etch the electroless plating film 42 more easily than the wiring 14 is selected and this process is performed.

  Further, in this step, as described above, the surface of the first connection portion 14A of the wiring 14 exposed from the opening 44 (the electroless plating film 42 covering the surface of the first connection portion 14A) is etched. In other words, the surface of the wiring 14 located in the periphery of the substrate 20 (one region) is wet etched. Therefore, by this step, the surface of the wiring 14 located in the peripheral portion is etched and the surface is flattened. Then, the wiring 14 affected by the etching in this step becomes the second roughened region 38 shown in FIG.

  Further, in this step, etching is performed using an etchant suitable for planarization. Specifically, on the surface of the wiring 14, the surface of the crystal constituting the wiring 14 and the boundary (grain boundary) between the crystals are exposed. In this step, an etchant that uniformly (uniformly) removes the crystal surface and grain boundaries is used. As a result, the surface of the first connection portion 14A of the wiring 14 to be etched in this step becomes smoother.

  After this step is completed, the etching resist 46 is peeled off from the substrate 20 and removed.

  Referring to FIG. 11, next, a plating resist 48 for performing an electrolytic plating process in the next process is formed.

  Referring to FIG. 11A, after a plating resist 48 is formed on the entire top surface of the substrate 20, an exposure development process is performed to remove the plating resist 48 partially. As a result, the upper surface and the side surface of the first connection portion 14A where the plating film is to be formed are exposed to the outside from the opening 50.

  Referring to FIG. 11B, an opening 50 is provided in the plating resist 48 so that the first connection portion 14A of each wiring 14 is exposed. Here, the opening 50 formed in the plating resist 48 is smaller than the opening 44 provided in the etching resist 46 in the previous step. That is, the portion of the wiring 14 that has been flattened by etching in the previous step is partially exposed from the opening 50 of the plating resist 48. A plating film is attached to the portion of the wiring 14 exposed from the opening 50. On the other hand, there is a portion of the wiring 14 that is flattened by the etching in the previous step and is not exposed from the opening 50. With reference to FIG. 2A, this portion becomes a second roughened region 38 that is not covered with the plating film 28. Referring to FIG. 12A, the portion of the wiring 14 that is not covered with the electroless plating film 42 and is not exposed to the opening 50 corresponds to this portion (second roughened region 38).

  Referring to FIG. 12, next, a plating film 28 is attached to the surface of the wiring 14 exposed from the opening 50 of the plating resist 48 by an electrolytic plating method.

  Referring to FIG. 12A, in this step, the plating solution is brought into contact with the wiring 14 (first connecting portion) exposed from the opening 50 provided in the plating resist 48 to apply a voltage to the electroless plating film 42. By applying this, an electrolytic plating film is formed on the surface of the wiring 14. Here, after the electrolytic plating film made of nickel is deposited on the surface of the exposed wiring 14, the electrolytic plating film made of gold is deposited on the upper surface of the electrolytic plating film made of nickel.

  In this step, the electroplating process is performed using the electroless plating film 42 that covers the entire top surface of the base material 12 and the wiring 14 as an electrode, excluding the top surface of the base material 12 inside the opening 50. ing. Therefore, conventionally, a plated wire for electrolytic plating has been formed between the wires 14, but since this plated wire can be made unnecessary, the wires 14 can be brought close to each other.

  Referring to FIG. 12B, a plating film 28 that covers the surface of the wiring 14 is formed inside each opening 50. In addition, regarding the base material 12 exposed inside the opening 50, the electroless plating film 42 covering the upper surface of the base material 12 is removed in the previous step, so that the plating film 28 is deposited on this portion. Not.

  After this step is completed, the plating resist 48 is peeled off from the upper surface of the substrate 20 and removed. Referring to FIG. 13, the state of substrate 20 after the plating resist is removed is shown. Referring particularly to FIG. 13B, the upper surface of the substrate 20 excluding the inside of the opening 50 is covered with an electroless plating film 42 functioning as a plating wire.

  Referring to FIG. 14, next, the electroless plating film used for the electrolytic plating process is completely removed.

  In this step, the etching resist is basically not used, and etching is performed by bringing the etchant into contact with the entire upper surface of the substrate 20. Etching is continuously performed until the electroless plating film covering the upper surface of the substrate 12 is removed. By this step, the electroless plating film covering the upper surface of the substrate 12 is etched and the surface of the entire region of the wiring 14 is etched.

  By removing the electroless plating film functioning as a plating wire by the above process, each wiring 14 is electrically independent.

  The etchant used in this process is more selective than the etchant used in the previous process etching. Specifically, the etchant used in this step removes the grain boundary preferentially over the crystal surface. Here, on the surface of the wiring 14 and the electroless plating film 42 on the wiring 14, the surface of the crystal constituting the wiring 14 and the electroless plating and the boundary (grain boundary) between the crystals are exposed. Therefore, the crystal grains of the electroless plating film 42 are finer than the crystal grains constituting the wiring 14.

  Therefore, the surface of the wiring 14 in the vicinity (peripheral portion) of the first connection portion 14A where the electroless plating film 42 has been removed smoothly in the previous etching process has a larger crystal than the electroless plating film 42. The grains are exposed, and the width of the unevenness is relatively large even after this step. That is, this portion has been etched a plurality of times, forming a second roughened region 38 shown in FIG.

  On the other hand, referring to FIG. 2A, the wiring 14 that is only etched in this step has an electroless plating film 42 with a relatively small crystal grain size on the surface during the etching process in this step. For this reason, the first roughened region 36 has a small surface irregularity width.

  Referring to FIG. 15, next, the upper surface of the substrate 20 is covered with a covering layer 18. FIG. 15A is a cross-sectional view of the substrate 20 in this step, and FIG. 15B is a plan view of the substrate 20 as viewed from above.

  Referring to FIGS. 15A and 15B, first, a coating layer 18 made of a resin is formed so that the upper surface of the base material 12 and the wiring 14 are entirely covered. Next, the covering layer 18 is removed to form the opening 24 so that the first connection portion 14A of each wiring 14 is exposed. The first connecting portion 14A and the plating film 28 are exposed from the opening 24.

  Here, not only the plating film 28 but also the metal material constituting the wiring 14 is exposed to the outside from the opening 24. However, as shown in FIGS. 5A and 5B, the width of the opening 24 may be narrowed so that only the plating film 28 is exposed to the outside from the opening 24. In this case, the metal material constituting the wiring 14 is entirely covered with the coating layer 18.

  The board | substrate 20 is manufactured according to the above process. Further, the following steps are required to manufacture the circuit device 10 shown in FIG. That is, the step of fixing the semiconductor element 16 to the substrate 20 via an insulating adhesive, the step of electrically connecting the electrode of the semiconductor element 16 and the wiring 14 via the fine metal wire 26, the semiconductor element 16 and the fine metal wire For example, a process of forming the sealing resin 22 on the upper surface of the substrate 20 so as to seal 26 and a process of welding the connection electrode 34 made of solder to the back electrode 32 are required.

DESCRIPTION OF SYMBOLS 10 Circuit apparatus 12 Base material 14 Wiring 14A 1st connection part 14B 2nd connection part 14C Wiring part 16 Semiconductor element 18 Covering layer 20 Substrate 22 Sealing resin 24 Opening part 26 Metal fine wire 28 Plating film 30 Through electrode 32 Back surface electrode 34 Connection Electrode 36 1st roughening area | region 38 2nd roughening area | region 40 Concave part 42 Electroless plating film | membrane 44 Opening part 46 Etching resist 48 Plating resist 50 Opening part

Claims (10)

It is a manufacturing method of a substrate for forming a wiring covered with a coating layer on one main surface of a substrate,
A first step of forming a wiring having a connection portion so as to surround one region on the one main surface of the base material;
A second step of attaching an electroless plating film to the one main surface of the substrate and the surface of the wiring;
A third step of opening the one main surface of the base material at the connection portion of the wiring and the peripheral portion thereof as a first opening, and covering the one main surface of the base material and the wiring with an etching resist;
A fourth step of removing the electroless plating film in the region exposed from the first opening by etching;
A fifth step of forming a plating resist covering the wiring on one main surface of the base material by opening the region provided with the connection portion as a second opening portion;
A sixth step of depositing an electrolytic plating film on the connection portion of the wiring exposed from the second opening by an electrolytic plating method using the electroless plating film as an electrode;
A seventh step of removing the electroless plating film covering the first main surface of the base material and electrically separating the wirings;
An eighth step of exposing the connection portion to which the electrolytic plating film is deposited as a third opening and forming a coating layer on the first main surface of the base material so as to cover the wiring; A method for manufacturing a substrate, comprising: In the fourth step, a first etchant is used, and in the seventh step, a second etchant having a different property from the first etchant is used,
The substrate manufacturing method according to claim 1, wherein the first etchant has a property of etching the surface of the wiring more uniformly than the second etchant. In the seventh step, the electroless plating film covering the one main surface of the base material and the surface of the wiring are etched,
2. The method for manufacturing a substrate according to claim 1, wherein the etching is continued until the electroless plating film covering the one main surface of the base material is removed. A circuit device comprising: a step of forming a substrate having a wiring covered with a coating layer on one main surface of a base material; and a step of mounting a circuit element electrically connected to the wiring on the substrate. Is the way
The step of forming the substrate includes:
A first step of making the width of the unevenness of the wiring located in the peripheral part of the region of the base material larger than the width of the unevenness of the wiring located in the center part of the region of the base material;
And a second step of forming a coating layer so that the surface of the wiring and one main surface of the substrate are coated. Manufacturing a circuit device comprising: a step of forming a substrate having a wiring covered with a coating layer on one main surface of a substrate; and a step of mounting a circuit element electrically connected to the wiring on the substrate. Is the way
The step of forming the substrate includes:
A first step of forming a wiring having a connection portion so as to surround one region on the one main surface of the base material;
A second step of attaching an electroless plating film to the one main surface of the substrate and the surface of the wiring;
A third step of opening the one main surface of the base material at the connection portion of the wiring and the peripheral portion thereof as a first opening, and covering the one main surface of the base material and the wiring with an etching resist;
A fourth step of removing the electroless plating film in the region exposed from the first opening by etching;
A fifth step of forming a plating resist covering the wiring on one main surface of the base material by opening the region provided with the connection portion as a second opening portion;
A sixth step of depositing an electrolytic plating film on the connection portion of the wiring exposed from the second opening by an electrolytic plating method using the electroless plating film as an electrode;
A seventh step of removing the electroless plating film covering the first main surface of the base material and electrically separating the wirings;
An eighth step of exposing the connection portion to which the electrolytic plating film is deposited as a third opening and forming a coating layer on the first main surface of the base material so as to cover the wiring; A method of manufacturing a circuit device, comprising: A support substrate made of an insulating layer;
A first terminal provided on at least one surface of the support substrate and electrically connected to an external connection electrode on the other surface of the support substrate;
A wiring provided on one surface of the support substrate and extending integrally with the first terminal;
A substrate having a second terminal provided on one surface of the support base and provided integrally with the wiring;
The surface of the adjacent wiring located in the vicinity of the second terminal surface and the second terminal is formed smaller than the roughness of the adjacent wiring surface,
A coating layer made of resin is provided on the substrate so that a part of the adjacent wiring on the second terminal and the second terminal side is exposed,
A substrate characterized in that the anchoring effect of the covering layer on the adjacent wiring having a small roughness is made smaller than that of other regions. A support substrate made of an insulating layer;
A first terminal provided on at least one surface of the support substrate and electrically connected to an external connection electrode on the other surface of the support substrate;
A wiring provided on one surface of the support substrate and extending integrally with the first terminal;
A substrate having a second terminal provided on one surface of the support base and provided integrally with the wiring;
A circuit device having at least one semiconductor element provided on the support substrate and electrically connected to the second terminal;
The surface of the adjacent wiring located in the vicinity of the second terminal surface and the second terminal is formed smaller than the roughness of the adjacent wiring surface,
A coating layer made of resin is provided on the substrate so that a part of the adjacent wiring on the second terminal and the second terminal side is exposed,
2. A circuit device according to claim 1, wherein an anchor effect is made smaller in the covering layer on the adjacent wiring having a low roughness than in other regions.   The substrate according to claim 6, wherein the second terminal is made of Cu, and Ni or Au is coated thereon. The circuit device according to claim 7, wherein the second terminal is made of Cu, and Ni or Au is coated thereon. A substrate;
A wiring formed on one main surface of the substrate and having an external terminal portion,
A coating layer that covers the wiring except for the external terminal portion, and
The coating layer has an opening through which the external terminal portion of the wiring is exposed,
The width of the unevenness on the surface of the wiring covered with the coating layer located near the periphery of the opening is made larger than the roughness of the wiring covered with the coating layer other than the periphery of the opening. A substrate characterized by that.

Images