JPH1167953A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1167953A JPH1167953A JP22809797A JP22809797A JPH1167953A JP H1167953 A JPH1167953 A JP H1167953A JP 22809797 A JP22809797 A JP 22809797A JP 22809797 A JP22809797 A JP 22809797A JP H1167953 A JPH1167953 A JP H1167953A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor chip
- connection
- electrode
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は回路基板に半導体チ
ップを実装し、その半導体チップを樹脂封止してなる半
導体装置に関するもので、さらに詳しくは、半田バンプ
付き半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip mounted on a circuit board and sealing the semiconductor chip with a resin, and more particularly to a semiconductor device having solder bumps.
【０００２】[0002]
【従来の技術】近年、電子回路の高機能化に伴い、多数
の電極端子を有する半導体装置が開発されている。その
代表的なものとして、表面実装形多端子パッケージであ
るプラスチック・ボールグリッドアレイ（Plastic Ball
Grid Array ：以下ＰＢＧＡと記載する）がある。2. Description of the Related Art In recent years, semiconductor devices having a large number of electrode terminals have been developed as electronic circuits become more sophisticated. A typical example is a plastic ball grid array (Plastic Ball Grid Array), which is a surface mount multi-terminal package.
Grid Array: hereinafter referred to as PBGA).
【０００３】図７は従来技術のＰＢＧＡを示す断面図で
あり、図８は従来技術のＰＢＧＡを示す平面図である。
以下に、図７および図８を用いて、従来技術のＰＢＧＡ
の構造について説明する。FIG. 7 is a sectional view showing a conventional PBGA, and FIG. 8 is a plan view showing a conventional PBGA.
The following describes a conventional PBGA with reference to FIGS.
Will be described.
【０００４】図７および図８に示すように、半導体チッ
プ２９は、回路基板２５上面のダイアタッチパターン１
７の上に、接着剤２７を用いて固定されている。回路基
板２５は、樹脂基板１１の上下両面に厚さ１８μｍの銅
箔をエッチングして形成されたパターンを有し、そのパ
ターンがソルダーレジスト２３によって覆われている。As shown in FIGS. 7 and 8, a semiconductor chip 29 is provided with a die attach pattern 1 on an upper surface of a circuit board 25.
7 is fixed using an adhesive 27. The circuit board 25 has a pattern formed by etching a copper foil having a thickness of 18 μm on both upper and lower surfaces of the resin substrate 11, and the pattern is covered with the solder resist 23.
【０００５】このダイアタッチパターン１７は、回路基
板２５の中央に位置し、半導体チップ２９の電源グラン
ドと、半導体チップ２９の発熱を放散させる役割を兼ね
ている。[0005] The die attach pattern 17 is located at the center of the circuit board 25, and also serves as a power supply ground for the semiconductor chip 29 and for dissipating heat generated by the semiconductor chip 29.
【０００６】ダイアタッチパターン１７の領域内には、
サーマルビアホール１５が複数個設けられている。サー
マルビアホール１５は、ダイアタッチパターン１７で受
けた半導体チップ２９の熱を回路基板２５の下面側へ逃
がす役割と、ダイアタッチパターン１７と回路基板２５
の下面側のパッド電極２１とを電気的に接続する役割と
を兼ねている。In the area of the die attach pattern 17,
A plurality of thermal via holes 15 are provided. The thermal via hole 15 serves to release the heat of the semiconductor chip 29 received by the die attach pattern 17 to the lower surface of the circuit board 25, and
And also serves to electrically connect the pad electrode 21 on the lower surface side.
【０００７】半導体チップ２９の電極と回路基板２５上
の接続電極１９は、ボンディングワイヤ３１で電気的に
接続されている。このときボンディングワイヤ３１は、
電気特性が良好で、かつ接続電極１９との密着性が良好
な、直径０．０３ｍｍ前後の金線が、用いられる。The electrodes of the semiconductor chip 29 and the connection electrodes 19 on the circuit board 25 are electrically connected by bonding wires 31. At this time, the bonding wire 31
A gold wire having a good electrical property and good adhesion to the connection electrode 19 and having a diameter of about 0.03 mm is used.
【０００８】接続電極１９とパッド電極２１は、スルー
ホール１３を介して、電気的に接続されている。The connection electrode 19 and the pad electrode 21 are electrically connected via the through hole 13.
【０００９】半導体チップ２９およびボンディングワイ
ヤ３１は、遮蔽と保護のため、封止樹脂３３で樹脂封止
される。封止樹脂３３は、熱硬化性樹脂のエポキシ系樹
脂が用いられている。The semiconductor chip 29 and the bonding wires 31 are sealed with a sealing resin 33 for shielding and protection. As the sealing resin 33, a thermosetting epoxy resin is used.
【００１０】さらに、回路基板２５の下面側のパッド電
極２１には、半田バンプ３５を有する。半田バンプ３５
には、すずと鉛の比率が約６：４の組成の半田を用い
る。なお半田バンプ３５は、図示しないＰＢＧＡ４１を
実装するマザーボード基板の電極パターン上に実装され
る。よってＰＢＧＡ４１とマザーボード基板が電気的に
接続される。Further, the pad electrodes 21 on the lower surface side of the circuit board 25 have solder bumps 35. Solder bump 35
In this case, a solder having a composition of tin and lead having a ratio of about 6: 4 is used. The solder bump 35 is mounted on an electrode pattern of a motherboard substrate on which a PBGA 41 (not shown) is mounted. Therefore, the PBGA 41 and the motherboard substrate are electrically connected.
【００１１】つぎに回路基板２５の製造方法を説明す
る。図９〜図１２は、従来技術の回路基板２５の製造工
程を示す図である。図９から図１１は、従来技術の回路
基板２５の製造工程を示す要部断面図であり、図１２
は、従来技術の回路基板２５の製造工程を示す平面図で
ある。Next, a method of manufacturing the circuit board 25 will be described. 9 to 12 are views showing a manufacturing process of the circuit board 25 according to the related art. 9 to 11 are main-portion cross-sectional views showing a manufacturing process of the conventional circuit board 25.
FIG. 9 is a plan view showing a manufacturing process of the circuit board 25 of the related art.
【００１２】図９に記すように、樹脂基板１１は四角形
で板厚が０．２ｍｍ程度のビスマレミイミド―トリアジ
ン系樹脂からなり、その上下両面に厚さ１８μｍ程度の
銅箔が設けられている。その樹脂基板１１には、複数の
スルーホール１３と半導体チップ２９の放熱のためのサ
ーマルビアホール１５が、切削ドリル加工によって設け
られる。スルーホール１３とサーマルビアホール１５と
の壁面を含む基板面を洗浄した後、樹脂基板１１の全表
面には、無電解銅メッキおよび電解銅メッキにより銅メ
ッキ層４５が設けられる。その銅メッキ層４５はスルー
ホール１３とサーマルビアホール１５の内まで施され
る。As shown in FIG. 9, the resin substrate 11 is made of a bismalemiimide-triazine resin having a rectangular shape and a plate thickness of about 0.2 mm, and a copper foil having a thickness of about 18 μm is provided on both upper and lower surfaces thereof. The resin substrate 11 is provided with a plurality of through holes 13 and thermal via holes 15 for heat radiation of the semiconductor chip 29 by cutting drilling. After cleaning the substrate surface including the wall surfaces of the through hole 13 and the thermal via hole 15, a copper plating layer 45 is provided on the entire surface of the resin substrate 11 by electroless copper plating and electrolytic copper plating. The copper plating layer 45 is provided up to the inside of the through hole 13 and the thermal via hole 15.
【００１３】つぎに樹脂基板１１の上下両面に感光性ド
ライフィルム（図示せず）を張り付け、露光現像してエ
ッチングレジスト膜を形成させる。その後、エッチング
液を樹脂基板１１の上下両面に吹き付け、エッチングレ
ジスト膜のない露出した銅メッキ層を除去する。このエ
ッチング後、残ったエッチングレジスト膜を除去する。
この工程によって、図１０および図１２に示すように、
樹脂基板１１の上面側には、半導体チップ２９のダイア
タッチパターン１７およびワイヤーボンディング用の接
続電極１９を、下面側には半田バンプを形成するための
パッド電極２１が設けられる。なおダイアタッチパター
ン１７とパッド電極２１は、サーマルビアホール１５を
介して、また接続電極１９とパッド電極２１はスルーホ
ール１３を介して接続されている。Next, a photosensitive dry film (not shown) is attached to the upper and lower surfaces of the resin substrate 11, and is exposed and developed to form an etching resist film. Thereafter, an etching solution is sprayed on the upper and lower surfaces of the resin substrate 11 to remove the exposed copper plating layer having no etching resist film. After this etching, the remaining etching resist film is removed.
By this step, as shown in FIGS. 10 and 12,
The die attach pattern 17 of the semiconductor chip 29 and the connection electrode 19 for wire bonding are provided on the upper surface side of the resin substrate 11, and the pad electrode 21 for forming solder bumps is provided on the lower surface side. The die attach pattern 17 and the pad electrode 21 are connected via the thermal via hole 15, and the connection electrode 19 and the pad electrode 21 are connected via the through hole 13.
【００１４】さらに、樹脂基板１１の銅メッキ層４５の
両面にメッキレジストをラミネートし、露光現像を行う
ことによって、ソルダーレジスト２３を設け、ダイアタ
ッチパターン１７、接続電極１９、パッド電極２１に
は、ソルダーレジスト２３の開口部を設ける。Further, a plating resist is laminated on both surfaces of the copper plating layer 45 of the resin substrate 11 and subjected to exposure and development to provide a solder resist 23, and the die attach pattern 17, the connection electrode 19, and the pad electrode 21 are provided with: An opening for the solder resist 23 is provided.
【００１５】つぎに図１１に示すように、樹脂基板１１
の上下両面のソルダーレジスト２３から露出している電
極の銅メッキ層の表面に、２μｍ〜５μｍ程度のニッケ
ルメッキ層４７を設ける。Next, as shown in FIG.
A nickel plating layer 47 of about 2 μm to 5 μm is provided on the surface of the copper plating layer of the electrode exposed from the solder resist 23 on the upper and lower surfaces.
【００１６】最後にニッケルメッキ層４７の上にボンデ
ィングワイヤーと導通性の優れた厚さ０．３μｍ〜０．
７μｍ程度の金メッキ層４９を設ける。これで図１２に
示すように、回路基板２５が完成される。Finally, on the nickel plating layer 47, a thickness of 0.3 .mu.m to 0.1.
A gold plating layer 49 of about 7 μm is provided. Thus, the circuit board 25 is completed as shown in FIG.
【００１７】つぎに以上説明したＰＢＧＡ構造を得るた
めの製造方法を、図７と図８を用いて説明する。Next, a manufacturing method for obtaining the above-described PBGA structure will be described with reference to FIGS.
【００１８】回路基板２５のダイアタッチパターン１７
の上に、接着剤２７を塗布し、その上に半導体チップ２
９をのせ、接着剤２７が硬化するまで乾燥させる。これ
で半導体チップ２９は、回路基板２５上に固定される。Die attach pattern 17 of circuit board 25
Is applied with an adhesive 27, and the semiconductor chip 2
9 and dry until the adhesive 27 is cured. Thus, the semiconductor chip 29 is fixed on the circuit board 25.
【００１９】つぎに半導体チップ２９の電極と、回路基
板２５上の接続電極１９をボンディングワイヤ３１で電
気的に接続する。Next, the electrodes of the semiconductor chip 29 and the connection electrodes 19 on the circuit board 25 are electrically connected by bonding wires 31.
【００２０】つぎに半導体チップ２９およびボンディン
グワイヤ３１は、封止樹脂３３で、トランスファモール
ドにより封止される。Next, the semiconductor chip 29 and the bonding wires 31 are sealed with a sealing resin 33 by transfer molding.
【００２１】つぎに回路基板２５の下面側のパッド電極
２１に、直径０．６ｍｍから０．８ｍｍの半田ボールを
供給し、加熱炉で加熱することによって、半田バンプ３
５が設けられる。これでＰＢＧＡ４１が完成する。Next, a solder ball having a diameter of 0.6 mm to 0.8 mm is supplied to the pad electrode 21 on the lower surface side of the circuit board 25, and the solder ball 3 is heated by a heating furnace.
5 are provided. Thus, the PBGA 41 is completed.
【００２２】[0022]
【発明が解決しようとする課題】ＰＢＧＡは、表面実装
可能で半田バンプのピッチを微細化せずに多ピンに対応
でき、一括加熱による実装のため、高歩留まりであると
いう利点がある。The PBGA has an advantage that it can be mounted on the surface, can cope with many pins without miniaturizing the pitch of solder bumps, and has a high yield because it is mounted by batch heating.
【００２３】しかし前述した従来技術におけるＰＢＧＡ
には、以下に記載するような問題点がある。一般にＰＢ
ＧＡ４１は保管中に程度の差はあれ、回路基板２５、封
止樹脂３３より吸湿する。この状態でＰＢＧＡ４１をマ
ザーボード基板に実装するために、加熱炉で加熱する
と、吸湿した水分が気化膨張し、応力が発生する。この
応力によって、密着力の弱い回路基板２５上の接続電極
１９と、封止樹脂３３との界面で剥離が発生する。However, the PBGA in the prior art described above is used.
Has the following problems. Generally PB
The GA 41 absorbs moisture from the circuit board 25 and the sealing resin 33 to some extent during storage. In this state, when the PBGA 41 is mounted on a motherboard substrate and heated in a heating furnace, the absorbed moisture vaporizes and expands, generating stress. Due to this stress, peeling occurs at the interface between the connection electrode 19 on the circuit board 25 having a weak adhesion and the sealing resin 33.
【００２４】接続電極の表面は、金メッキ処理が施され
ており、金は不活性金属であり、封止樹脂であるエポキ
シ系樹脂との密着力は非常に小さいため、剥離が発生す
る。The surface of the connection electrode is subjected to a gold plating treatment, and gold is an inert metal, and the adhesion to the epoxy resin as a sealing resin is very small, so that peeling occurs.
【００２５】この剥離によってボンディングワイヤ３１
の切れや、接合部からの剥離が発生し、半導体装置の信
頼性を損なってきた。This peeling causes bonding wire 31
The semiconductor device has been cut off or peeled off from the junction, which has reduced the reliability of the semiconductor device.
【００２６】〔発明の目的〕本発明の目的は、上記の課
題を解決して、ＰＢＧＡが吸湿した状態で加熱しても、
回路基板上の接続電極と封止樹脂との界面で剥離せず、
信頼性の高い半導体装置を提供することである。[Object of the Invention] An object of the present invention is to solve the above-mentioned problems and to heat the PBGA while absorbing moisture.
Does not peel off at the interface between the connection electrode on the circuit board and the sealing resin,
It is to provide a highly reliable semiconductor device.
【００２７】[0027]
【課題を解決するための手段】上記目的を達成するため
に、本発明における半導体装置は、下記記載の構成を採
用する。In order to achieve the above object, a semiconductor device according to the present invention employs the following configuration.
【００２８】本発明の半導体装置は、回路基板と半導体
チップを備えるプラスチック・ボールグリッドアレイで
あって、半導体チップは回路基板の一方の面に搭載し、
回路基板の一方の面に接着剤を用いて半導体チップを搭
載するためのダイアタッチパターンと、半導体チップの
電極とボンディングワイヤで接続する接続電極とを有
し、回路基板の他方の面にマザーボードと接続するため
の半田バンプを設けるパッド電極を有し、回路基板は接
続電極とパッド電極とを電気的に接続するためのスルー
ホールを有し、半導体チップとボンディングワイヤとを
被覆するように設ける封止樹脂と、回路基板の接続電極
とこの接続電極に接続するボンディングワイヤとを被覆
するように設ける熱可塑性樹脂とを有することを特徴と
するものである。The semiconductor device of the present invention is a plastic ball grid array including a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one surface of the circuit board.
It has a die attach pattern for mounting a semiconductor chip on one surface of a circuit board using an adhesive, and a connection electrode connected to the electrode of the semiconductor chip with a bonding wire, and a motherboard on the other surface of the circuit board. The circuit board has a pad electrode on which a solder bump for connection is provided, and the circuit board has a through hole for electrically connecting the connection electrode and the pad electrode, and is provided so as to cover the semiconductor chip and the bonding wire. It is characterized by having a stop resin, and a thermoplastic resin provided so as to cover the connection electrodes of the circuit board and the bonding wires connected to the connection electrodes.
【００２９】本発明の半導体装置は、回路基板と半導体
チップを備えるプラスチック・ボールグリッドアレイで
あって、半導体チップは回路基板の一方の面に搭載し、
回路基板の一方の面に接着剤を用いて半導体チップを搭
載するためのダイアタッチパターンと、半導体チップの
電極とボンディングワイヤで接続する接続電極とを有
し、回路基板の他方の面にマザーボードと接続するため
の半田バンプを設けるパッド電極を有し、回路基板は接
続電極とパッド電極とを電気的に接続するためのスルー
ホールを有し、半導体チップとボンディングワイヤとを
被覆するように設ける封止樹脂と、回路基板の接続電極
とこの接続電極に接続するボンディングワイヤとを被覆
するように設ける熱可塑性ポリエーテルアミドとを有す
ることを特徴とするものである。The semiconductor device of the present invention is a plastic ball grid array including a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one surface of the circuit board.
It has a die attach pattern for mounting a semiconductor chip on one surface of a circuit board using an adhesive, and a connection electrode connected to the electrode of the semiconductor chip with a bonding wire, and a motherboard on the other surface of the circuit board. The circuit board has a pad electrode on which a solder bump for connection is provided, and the circuit board has a through hole for electrically connecting the connection electrode and the pad electrode, and is provided so as to cover the semiconductor chip and the bonding wire. It is characterized by having a stop resin and a thermoplastic polyetheramide provided so as to cover a connection electrode of the circuit board and a bonding wire connected to the connection electrode.
【００３０】本発明の半導体装置は、回路基板と半導体
チップを備えるプラスチック・ボールグリッドアレイで
あって、半導体チップは回路基板の一方の面に搭載し、
回路基板の一方の面に接着剤を用いて半導体チップを搭
載するためのダイアタッチパターンと、半導体チップの
電極とボンディングワイヤで接続する接続電極とを有
し、回路基板の他方の面にマザーボードと接続するため
の半田バンプを設けるパッド電極を有し、回路基板は接
続電極とパッド電極とを電気的に接続するためのスルー
ホールと、半導体チップの搭載面内に設け半導体チップ
の発熱を放散するためのサーマルビアホールを有し、半
導体チップとボンディングワイヤとを被覆するように設
ける封止樹脂と、回路基板の接続電極とこの接続電極に
接続するボンディングワイヤとを被覆するように設ける
熱可塑性樹脂とを有することを特徴とするものである。The semiconductor device of the present invention is a plastic ball grid array including a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one surface of the circuit board,
It has a die attach pattern for mounting a semiconductor chip on one surface of a circuit board using an adhesive, and a connection electrode connected to the electrode of the semiconductor chip with a bonding wire, and a motherboard on the other surface of the circuit board. It has a pad electrode on which a solder bump for connection is provided, and the circuit board dissipates heat generated by the semiconductor chip provided on a mounting surface of the semiconductor chip and a through hole for electrically connecting the connection electrode and the pad electrode. A sealing resin having a thermal via hole for covering the semiconductor chip and the bonding wire, and a thermoplastic resin providing to cover the connection electrode of the circuit board and the bonding wire connected to the connection electrode. It is characterized by having.
【００３１】本発明の半導体装置は、回路基板と半導体
チップを備えるプラスチック・ボールグリッドアレイで
あって、半導体チップは回路基板の一方の面に搭載し、
回路基板の一方の面に接着剤を用いて半導体チップを搭
載するためのダイアタッチパターンと、半導体チップの
電極とボンディングワイヤで接続する接続電極とを有
し、回路基板の他方の面にマザーボードと接続するため
の半田バンプを設けるパッド電極を有し、回路基板は接
続電極とパッド電極とを電気的に接続するためのスルー
ホールと、半導体チップの搭載面内に設け半導体チップ
の発熱を放散するためのサーマルビアホールを有し、半
導体チップとボンディングワイヤとを被覆するように設
ける封止樹脂と、回路基板の接続電極とこの接続電極に
接続するボンディングワイヤとを被覆するように設ける
熱可塑性ポリエーテルアミドとを有することを特徴とす
るものである。The semiconductor device of the present invention is a plastic ball grid array including a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one surface of the circuit board,
It has a die attach pattern for mounting a semiconductor chip on one surface of a circuit board using an adhesive, and a connection electrode connected to the electrode of the semiconductor chip with a bonding wire, and a motherboard on the other surface of the circuit board. It has a pad electrode on which a solder bump for connection is provided, and the circuit board dissipates heat generated by the semiconductor chip provided on a mounting surface of the semiconductor chip and a through hole for electrically connecting the connection electrode and the pad electrode. Resin having a thermal via hole for covering a semiconductor chip and a bonding wire, and a thermoplastic polyether provided to cover a connection electrode of a circuit board and a bonding wire connected to the connection electrode. And an amide.
【００３２】〔作用〕本発明の半導体装置において、接
続電極とこの接続電極に接続するボンディングワイヤ
が、熱可塑性樹脂で被覆されている。[Operation] In the semiconductor device of the present invention, the connection electrodes and the bonding wires connected to the connection electrodes are covered with a thermoplastic resin.
【００３３】本発明の半導体装置において、接続電極と
この接続電極に接続するボンディングワイヤが、熱可塑
性ポリエーテルアミドで被覆されている。In the semiconductor device of the present invention, the connection electrodes and the bonding wires connected to the connection electrodes are covered with thermoplastic polyetheramide.
【００３４】接続電極の表面は、金メッキ処理が施され
ている。金メッキが施されている理由は、腐食防止のた
めで、さらには電気特性が優れているためである。しか
し金は不活性金属であり、封止樹脂であるエポキシ系樹
脂との密着力は、非常に小さい。The surface of the connection electrode is plated with gold. The reason for the gold plating is to prevent corrosion and to have excellent electrical characteristics. However, gold is an inert metal, and its adhesion to an epoxy resin as a sealing resin is extremely small.
【００３５】そこで本発明では、接続電極とこの接続電
極に接続するボンディングワイヤを被覆するように、熱
可塑性樹脂が塗布されている。Therefore, in the present invention, a thermoplastic resin is applied so as to cover the connection electrodes and the bonding wires connected to the connection electrodes.
【００３６】そこで本発明では、接続電極とこの接続電
極に接続するボンディングワイヤを被覆するように、熱
可塑性ポリエーテルアミドが塗布されている。Therefore, in the present invention, thermoplastic polyetheramide is applied so as to cover the connection electrode and the bonding wire connected to the connection electrode.
【００３７】熱可塑性樹脂は、金属との密着力が大き
く、金との密着力も大きい。The thermoplastic resin has a large adhesive force with metal and a large adhesive force with gold.
【００３８】熱可塑性ポリエーテルアミドは、可撓性が
あり、外部からの応力に対する緩和性が高い。また熱可
塑性ポリエーテルアミドは、耐湿性に優れている。The thermoplastic polyether amide is flexible and has a high degree of relaxation against external stress. Further, thermoplastic polyetheramide has excellent moisture resistance.
【００３９】接続電極が、熱可塑性樹脂で被覆されるこ
とより、接続電極と封止樹脂の密着強度が強まり、ＰＢ
ＧＡが吸湿した状態で加熱しても、接続電極と封止樹脂
の界面で剥離することはない。Since the connection electrode is covered with the thermoplastic resin, the adhesion strength between the connection electrode and the sealing resin is increased, and the PB
Even if the GA is heated while absorbing moisture, it does not peel off at the interface between the connection electrode and the sealing resin.
【００４０】接続電極が、熱可塑性ポリエーテルアミド
で被覆されることより、接続電極と封止樹脂の密着強度
が強まり、ＰＢＧＡが吸湿した状態で加熱しても、接続
電極と封止樹脂の界面で剥離することはない。Since the connection electrode is coated with the thermoplastic polyetheramide, the adhesion strength between the connection electrode and the sealing resin is increased, and even if the PBGA is heated while absorbing moisture, the interface between the connection electrode and the sealing resin is increased. Does not peel off.
【００４１】[0041]
【発明の実施の形態】以下、図面を用いて本発明のＰＢ
ＧＡを実施するための最適な形態について説明する。図
１は、本発明の実施形態におけるＰＢＧＡの断面図であ
る。図２は、本発明の実施形態におけるＰＢＧＡの平面
図である。図１および図２を用いて、本発明のＰＢＧＡ
の構造について説明する。図において、従来技術と同一
部材は同一符号で示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An optimal mode for performing GA will be described. FIG. 1 is a sectional view of a PBGA according to an embodiment of the present invention. FIG. 2 is a plan view of the PBGA according to the embodiment of the present invention. The PBGA of the present invention will be described with reference to FIGS.
Will be described. In the drawings, the same members as those of the prior art are denoted by the same reference numerals.
【００４２】半導体チップ２９は、回路基板２５上面の
中央に配置されているダイアタッチパターン１７の上
に、接着剤２７を用いて固定されている。接着剤２７の
層厚は６０μｍである。接着剤２７には、エポキシ系の
導電性ペーストが用いられる。The semiconductor chip 29 is fixed on the die attach pattern 17 arranged at the center of the upper surface of the circuit board 25 using an adhesive 27. The layer thickness of the adhesive 27 is 60 μm. As the adhesive 27, an epoxy-based conductive paste is used.
【００４３】回路基板２５は、樹脂基板１１の上下両面
に厚さ１８μｍの銅箔をエッチングして形成されたパタ
ーンを有し、そのパターンがソルダーレジスト２３によ
って覆われている。このパターンのうち、ダイアタッチ
パターン１７と、接続電極１９と、パッド電極２１の部
分は、ソルダーレジスト２３が開口している。このため
ダイアタッチパターン１７と、接続電極１９と、パッド
電極２１は、ソルダーレジスト２３より露出している。
これらの膜構成は、１８μｍの銅箔上に５μｍから１５
μｍのニッケルメッキ層を有し、さらにその上に０．３
μｍから０．７μｍの金メッキを有する。The circuit board 25 has a pattern formed by etching a 18 μm-thick copper foil on both upper and lower surfaces of the resin substrate 11, and the pattern is covered with a solder resist 23. In this pattern, the solder resist 23 has an opening at the die attach pattern 17, the connection electrode 19, and the pad electrode 21. For this reason, the die attach pattern 17, the connection electrode 19, and the pad electrode 21 are exposed from the solder resist 23.
These film configurations are 5 μm to 15 μm on 18 μm copper foil.
with a nickel plating layer of 0.3 μm
It has a gold plating of μm to 0.7 μm.
【００４４】樹脂基板１１は、板厚０．２ｍｍから０．
４ｍｍのビスマレイミド―トリアジン系樹脂が用いられ
る。ソルダーレジスト２３は、膜厚７５μｍのアクリル
系樹脂が用いられる。The resin substrate 11 has a thickness of 0.2 mm to 0.1 mm.
A 4 mm bismaleimide-triazine resin is used. An acrylic resin having a thickness of 75 μm is used for the solder resist 23.
【００４５】樹脂基板１１には、三菱瓦斯化学株式会社
のＣＣＬ−８３２（商品名）が、ソルダーレジスト２３
には、日立化成工業株式会社のＳＲ２３００Ｇ（商品
名）が用いられる。The resin substrate 11 is made of CCL-832 (trade name) of Mitsubishi Gas Chemical Co., Ltd.
Used is SR2300G (trade name) of Hitachi Chemical Co., Ltd.
【００４６】ダイアタッチパターン１７の表面は、金メ
ッキ処理が施されている。金メッキが施されている理由
は、腐食防止のためで、さらには電気特性が優れている
ためである。しかし金は不活性金属であり、接着剤２７
の主成分エポキシ系樹脂との密着力は、非常に小さい。The surface of the die attach pattern 17 is subjected to gold plating. The reason for the gold plating is to prevent corrosion and to have excellent electrical characteristics. However, gold is an inert metal and the adhesive 27
Has a very small adhesive strength with an epoxy resin.
【００４７】ダイアタッチパターン１７と接着剤２７の
密着強度を少しでも高めるために、ダイアタッチパター
ン１７の面積を減少させ、接着剤２７と樹脂基板１１の
接触面積を大きくしている。このために、ダイアタッチ
パターンの形状としては、図２に示すような形状を採用
している。In order to slightly increase the adhesion strength between the die attach pattern 17 and the adhesive 27, the area of the die attach pattern 17 is reduced, and the contact area between the adhesive 27 and the resin substrate 11 is increased. For this reason, the shape as shown in FIG. 2 is adopted as the shape of the die attach pattern.
【００４８】ダイアタッチパターン１７は、半導体チッ
プ２９の電源グランドと、半導体チップ２９の発熱を放
散させる役割を兼ねている。The die attach pattern 17 also has a role of dissipating heat of the semiconductor chip 29 and a power ground of the semiconductor chip 29.
【００４９】ダイアタッチパターン１７の領域内には、
直径０．３ｍｍのサーマルビアホール１５が複数個設け
られている。サーマルビアホール１５内は、銅メッキが
施され、回路基板２５の上下面が電気的に接続されてい
る。サーマルビアホール１５は、ダイアタッチパターン
１７で受けた半導体チップ２９の熱を回路基板２５の下
面側へ逃がす役割と、ダイアタッチパターン１７と回路
基板２５の下面側のパット電極２１とを電気的に接続す
る役割とを兼ねている。In the area of the die attach pattern 17,
A plurality of thermal via holes 15 having a diameter of 0.3 mm are provided. The inside of the thermal via hole 15 is plated with copper, and the upper and lower surfaces of the circuit board 25 are electrically connected. The thermal via hole 15 serves to release the heat of the semiconductor chip 29 received by the die attach pattern 17 to the lower surface side of the circuit board 25, and electrically connects the die attach pattern 17 to the pad electrode 21 on the lower surface side of the circuit board 25. It also has a role to do.
【００５０】サーマルビアホール１５は、半導体チップ
２９の放熱効率を高めるため、半導体チップ２９の搭載
した面内に設けることが望ましい。The thermal via hole 15 is desirably provided in the surface on which the semiconductor chip 29 is mounted, in order to increase the heat radiation efficiency of the semiconductor chip 29.
【００５１】半導体チップ２９の電極と回路基板２５上
の接続電極１９は、ボンディングワイヤ３１で電気的に
接続されている。このときボンディングワイヤ３１は、
直径０．０３ｍｍ前後の金線が用いられる。金線が用い
られる理由は、金は展延性が大きくて断線しにくく、不
活性で安定しているため、腐食しない。さらに、大気中
でも酸化することなく容易に真球ができるため、生産性
に優れているからである。The electrodes of the semiconductor chip 29 and the connection electrodes 19 on the circuit board 25 are electrically connected by bonding wires 31. At this time, the bonding wire 31
A gold wire having a diameter of about 0.03 mm is used. The reason why the gold wire is used is that gold has a large spreadability and is hardly broken, and is inactive and stable, so that it does not corrode. Further, since a true sphere can be easily formed in the atmosphere without being oxidized, the productivity is excellent.
【００５２】接続電極１９とパッド電極２１は、直径
０．３ｍｍのスルーホール１３を介して、電気的に接続
されている。The connection electrode 19 and the pad electrode 21 are electrically connected via the through hole 13 having a diameter of 0.3 mm.
【００５３】スルーホール１３は、接続電極１９よりパ
ターンが引き回され、回路基板２５の外周に位置してい
る。The pattern of the through hole 13 is routed from the connection electrode 19 and is located on the outer periphery of the circuit board 25.
【００５４】スルーホール１３内は、銅メッキが施さ
れ、スルーホール１３の上下面が電気的に接続されてい
る。The inside of the through hole 13 is plated with copper, and the upper and lower surfaces of the through hole 13 are electrically connected.
【００５５】接続電極１９とこの接続電極１９に接続す
るボンディングワイヤ３１を被覆するように、熱可塑性
ポリエーテルアミド３７が塗布されている。この熱可塑
性ポリエーテルアミド３７としては、日立化成工業株式
会社のＨＬ―１２００（商品名）が用いられる。A thermoplastic polyetheramide 37 is applied so as to cover the connection electrodes 19 and the bonding wires 31 connected to the connection electrodes 19. As the thermoplastic polyetheramide 37, HL-1200 (trade name) of Hitachi Chemical Co., Ltd. is used.
【００５６】熱可塑性ポリエーテルアミド３７の形成膜
厚は、１０μｍ〜２０μｍであり、接続電極１９の金メ
ッキ部をすべて覆うように塗布する。また熱可塑性ポリ
エーテルアミド３７の成形膜は、接続電極１９をひとつ
ひとつ断片的に塗布しても、接続電極１９をすべてつな
げるように連続的に塗布してもよい。The film thickness of the thermoplastic polyetheramide 37 is 10 μm to 20 μm, and is applied so as to cover all the gold-plated portions of the connection electrodes 19. Further, the formed film of the thermoplastic polyetheramide 37 may be applied one by one to the connection electrodes 19 or may be applied continuously so as to connect all the connection electrodes 19.
【００５７】半導体チップ２９およびボンディングワイ
ヤ３１は、遮蔽と保護のために、封止樹脂３３で樹脂封
止される。封止樹脂３３は、熱硬化性樹脂のエポキシ系
樹脂が用いられる。The semiconductor chip 29 and the bonding wires 31 are sealed with a sealing resin 33 for shielding and protection. As the sealing resin 33, an epoxy resin of a thermosetting resin is used.
【００５８】さらに、回路基板２５の下面側のパッド電
極２１には、半田バンプ３５を有する。半田バンプ３５
は、半導体チップ２９の電極がボンディングワイヤ３１
と、接続電極１９と、スルーホール１３と、パッド電極
２１を通して、ＰＢＧＡ４１の外側に出た接続端子であ
る。半田バンプ３５には、すずと鉛の比率が約６：４の
組成の半田を用いる。なお半田バンプ３５は、図示しな
いＰＢＧＡを実装するマザーボード基板の電極パターン
上に実装される。よってＰＢＧＡとマザーボード基板が
電気的に接続される。Further, the pad electrodes 21 on the lower surface side of the circuit board 25 have solder bumps 35. Solder bump 35
Means that the electrode of the semiconductor chip 29 is a bonding wire 31
, The connection electrode 19, the through-hole 13, and the connection terminal protruding outside the PBGA 41 through the pad electrode 21. For the solder bump 35, a solder having a composition of tin and lead having a ratio of about 6: 4 is used. The solder bump 35 is mounted on an electrode pattern of a motherboard substrate on which a PBGA (not shown) is mounted. Therefore, the PBGA and the motherboard substrate are electrically connected.
【００５９】つぎに本発明のＰＢＧＡ４１における回路
基板２５の製造方法を説明する。図３〜図６は、本発明
のＰＢＧＡ４１における回路基板２５の製造工程を示す
図である。図３〜図５は、本発明のＰＢＧＡ４１におけ
る回路基板２５の製造工程を示す断面図である。そして
図６は、本発明のＰＢＧＡ４１における回路基板２５の
製造工程を示す平面図である。図３〜図６を用いて、回
路基板２５の製造方法について説明する。Next, a method of manufacturing the circuit board 25 in the PBGA 41 of the present invention will be described. FIG. 3 to FIG. 6 are views showing the steps of manufacturing the circuit board 25 in the PBGA 41 of the present invention. 3 to 5 are cross-sectional views illustrating the steps of manufacturing the circuit board 25 in the PBGA 41 of the present invention. FIG. 6 is a plan view showing a manufacturing process of the circuit board 25 in the PBGA 41 of the present invention. A method of manufacturing the circuit board 25 will be described with reference to FIGS.
【００６０】樹脂基板１１は四角形で板厚が０．２ｍｍ
から０．４ｍｍのビスマレイミド―トリアジン系樹脂よ
りなり、その上下両面に厚さ１８μｍ程度の銅箔を有す
る。The resin substrate 11 is square and has a thickness of 0.2 mm.
And a 0.4 mm thick bismaleimide-triazine resin, and a copper foil with a thickness of about 18 μm on both upper and lower surfaces.
【００６１】図３に示すように、樹脂基板１１には複数
個のスルーホール１３とサーマルビアホール１５が、切
削ドリル加工により設けられる。As shown in FIG. 3, a plurality of through holes 13 and thermal via holes 15 are formed in the resin substrate 11 by cutting drilling.
【００６２】スルーホール１３とサーマルビアホール１
５との壁面を含む基板面を洗浄後、樹脂基板１１の全表
面には、無電解銅メッキおよび電解銅メッキにより厚さ
１２μｍ〜２２μｍの銅メッキ層４５を設ける。銅メッ
キ層４５は、スルーホール１３とサーマルビアホール１
５の開口内面にも形成される。このときのメッキ処理条
件は、電流密度が５７．８Ａ／ｄｍ2 である。The through hole 13 and the thermal via hole 1
After cleaning the substrate surface including the wall surface of No. 5, a copper plating layer 45 having a thickness of 12 μm to 22 μm is provided on the entire surface of the resin substrate 11 by electroless copper plating and electrolytic copper plating. The copper plating layer 45 includes the through hole 13 and the thermal via hole 1.
5 is also formed on the inner surface of the opening. The plating conditions at this time are such that the current density is 57.8 A / dm 2 .
【００６３】つぎに樹脂基板１１の上下両面に感光性ド
ライフィルムを張り付け、露光現像してエッチングレジ
スト膜を形成させる。その後、一般的なエッチング液で
ある塩化第二銅を樹脂基板１１の上下両面に吹き付け、
エッチングレジスト膜のない露出した銅メッキ層を除去
する。この工程によって、図４に示すように、樹脂基板
１１の上面側には、半導体チップ２９のダイアタッチパ
ターン１７およびワイヤーボンディング用の接続電極１
９を、下面側には半田バンプを形成するためのパット電
極２１が形成される。なおダイパターン１７とパッド電
極２１は、サーマルビアホール１５の開口面内の銅メッ
キ層４５を介して、また接続電極１９とパット電極２１
はスルーホール１３の開口面内の銅メッキ層４５を介し
て接続されている。Next, a photosensitive dry film is stuck on the upper and lower surfaces of the resin substrate 11 and exposed and developed to form an etching resist film. Thereafter, cupric chloride, which is a general etching solution, is sprayed on the upper and lower surfaces of the resin substrate 11,
The exposed copper plating layer without the etching resist film is removed. By this step, as shown in FIG. 4, the die attach pattern 17 of the semiconductor chip 29 and the connection electrode 1 for wire bonding are formed on the upper surface side of the resin substrate 11.
9, and a pad electrode 21 for forming a solder bump is formed on the lower surface side. The die pattern 17 and the pad electrode 21 are connected to each other via the copper plating layer 45 in the opening surface of the thermal via hole 15 and between the connection electrode 19 and the pad electrode 21.
Are connected via a copper plating layer 45 in the opening surface of the through hole 13.
【００６４】さらに、樹脂基板１１の銅メッキ層４５の
両面にメッキレジストをラミネートし、露光現像を行う
ことによって、ソルダーレジスト２３を設け、ダイアタ
ッチパターン１７、接続電極１９、パット電極２１に
は、図６に示すようにソルダーレジスト２３の開口部を
設ける。Further, a plating resist is laminated on both surfaces of the copper plating layer 45 of the resin substrate 11 and subjected to exposure and development to provide a solder resist 23, and the die attach pattern 17, the connection electrode 19, and the pad electrode 21 are provided with: As shown in FIG. 6, an opening of the solder resist 23 is provided.
【００６５】つぎに図５に示すように、樹脂基板１１の
上下両面の露出している電極の銅メッキ層４５の表面
に、厚さ５〜１５μｍ程度のニッケルメッキ層４７を設
ける。このときのメッキ処理条件は、電流密度が１．０
Ａ／ｄｍ2 である。Next, as shown in FIG. 5, a nickel plating layer 47 having a thickness of about 5 to 15 μm is provided on the surface of the copper plating layer 45 of the exposed electrodes on the upper and lower surfaces of the resin substrate 11. The plating conditions at this time were such that the current density was 1.0
A / dm 2 .
【００６６】最後に図５に示すように、ニッケルメッキ
層４７の上にボンディングワイヤーと導通性の優れた厚
さ０．３μｍ〜０．７μｍ程度の金メッキ層４９を設け
る。このときのメッキ処理条件は、電流密度が０．１６
Ａ／ｄｍ2 である。Finally, as shown in FIG. 5, on the nickel plating layer 47, a gold plating layer 49 having a thickness of about 0.3 μm to 0.7 μm excellent in conductivity with the bonding wire is provided. The plating conditions at this time were such that the current density was 0.16.
A / dm 2 .
【００６７】これで図６に示すように、本発明のＰＢＧ
Ａ４１における回路基板２５が、完成される。Now, as shown in FIG. 6, the PBG of the present invention
The circuit board 25 in A41 is completed.
【００６８】つぎに本発明におけるＰＢＧＡ４１の製造
方法を、図１と図２を用いて説明する。Next, a method of manufacturing the PBGA 41 according to the present invention will be described with reference to FIGS.
【００６９】回路基板２５のダイアタッチパターン１７
の上に、接着剤２７を塗布し、その上に半導体チップ２
９をのせ、接着剤２７が完全に硬化するまで乾燥する。
これで半導体チップ２９は、回路基板２５上に固定され
る。Die attach pattern 17 of circuit board 25
Is applied with an adhesive 27, and the semiconductor chip 2
9 and dry until the adhesive 27 is completely cured.
Thus, the semiconductor chip 29 is fixed on the circuit board 25.
【００７０】つぎに半導体チップ２９上面の電極と、回
路基板２５上の接続電極１９をボンディングワイヤ３１
で接続する。この接続によって、半導体チップ２９と回
路基板２５が電気的に接続される。Next, the electrodes on the upper surface of the semiconductor chip 29 and the connection electrodes 19 on the circuit board 25 are connected to the bonding wires 31.
Connect with. With this connection, the semiconductor chip 29 and the circuit board 25 are electrically connected.
【００７１】つぎにボンディングワイヤ３１が接続され
た回路基板２５上の接続電極１９の上に液状の熱可塑性
ポリエーテルアミドをディスペンスによって塗布する。
これを１５０℃で３時間乾燥させると、膜が形成され
る。Next, a liquid thermoplastic polyetheramide is applied by dispensing onto the connection electrodes 19 on the circuit board 25 to which the bonding wires 31 are connected.
When this is dried at 150 ° C. for 3 hours, a film is formed.
【００７２】つぎに半導体チップ２９およびボンディン
グワイヤ３１は、封止樹脂３３で封止される。この封止
方法は、封止樹脂を型の中に挿入し、加熱しながらプラ
ンジャで加圧することにより、溶融した封止樹脂がラン
ナを通って型の所要部に供給され、形成されるトランス
ファモールドで行う。Next, the semiconductor chip 29 and the bonding wires 31 are sealed with a sealing resin 33. In this sealing method, by inserting a sealing resin into a mold and pressing it with a plunger while heating, the molten sealing resin is supplied to a required portion of the mold through a runner, and a transfer mold is formed. Do with.
【００７３】つぎに回路基板２５の下面側に半田バンプ
３５を設ける。回路基板２５の下面側のパット電極２１
上に、半田ぬれ性を良くするためにフラックス液を塗布
し、そのパット電極２１上に直径０．６〜０．８ｍｍの
半田ボールを供給する。その後加熱炉で、約２２０〜２
３０℃の温度で加熱することにより、半田ボールがパッ
ト電極２１上に接合され、半田バンプ３５が設けられ
る。このときフラックス液は、ロジン系の材料で構成
し、半田ボールはすずと鉛が約６：４の組成の半田を使
用する。Next, solder bumps 35 are provided on the lower surface side of the circuit board 25. The pad electrode 21 on the lower surface side of the circuit board 25
A flux liquid is applied thereon to improve the solder wettability, and a solder ball having a diameter of 0.6 to 0.8 mm is supplied onto the pad electrode 21. Then, in a heating furnace, about 220-2
By heating at a temperature of 30 ° C., the solder balls are joined on the pad electrodes 21, and the solder bumps 35 are provided. At this time, the flux liquid is composed of a rosin-based material, and the solder ball uses solder having a composition of tin and lead of about 6: 4.
【００７４】最後に回路基板２５の下面側に残ったフラ
ックス液を、アルコール系の洗浄液で洗浄し、ＰＢＧＡ
４１が完成する。Finally, the flux liquid remaining on the lower surface side of the circuit board 25 is cleaned with an alcohol-based cleaning liquid, and the PBGA
41 is completed.
【００７５】本発明において、接続電極は半導体チップ
の電極とボンディングワイヤで接続後、熱可塑性ポリエ
ーテルアミドで被覆されている。In the present invention, the connection electrodes are connected to the electrodes of the semiconductor chip by bonding wires, and then covered with thermoplastic polyetheramide.
【００７６】接続電極の表面は、金メッキ処理が施され
ている。金は不活性金属であり、封止樹脂であるエポキ
シ系樹脂との密着力は、非常に小さい。The surfaces of the connection electrodes are plated with gold. Gold is an inert metal, and has a very small adhesive force with an epoxy resin as a sealing resin.
【００７７】そこで、接続電極が半導体チップの電極と
ボンディングワイヤで接続後、接続電極の表面に熱可塑
性ポリエーテルアミドを塗布する。Then, after the connection electrodes are connected to the electrodes of the semiconductor chip by bonding wires, thermoplastic polyetheramide is applied to the surfaces of the connection electrodes.
【００７８】熱可塑性ポリエーテルアミドは、可撓性が
あり、外部からの応力に対する緩和性が高い。また熱可
塑性ポリエーテルアミドは、耐湿性に優れている。The thermoplastic polyetheramide is flexible and has a high degree of relaxation against external stress. Further, thermoplastic polyetheramide has excellent moisture resistance.
【００７９】熱可塑性樹脂は、金属との密着大きく、金
との密着力も大きい。The thermoplastic resin has a large adhesion to metal and a large adhesion to gold.
【００８０】接続電極が、熱可塑性ポリエーテルアミド
で皮膜されることより、接続電極と封止樹脂の密着強度
が強まり、ＰＢＧＡが吸湿した状態で加熱しても、接続
電極と封止樹脂の界面で剥離することはない。Since the connection electrode is coated with the thermoplastic polyetheramide, the adhesion strength between the connection electrode and the sealing resin is increased, and even if the PBGA is heated while absorbing moisture, the interface between the connection electrode and the sealing resin is increased. Does not peel off.
【００８１】[0081]
【発明の効果】以上の説明で明らかなように、本発明に
おいては、回路基板の接続電極は、半導体チップの電極
とボンディングワイヤで接続後、熱可塑性ポリエーテル
アミドで被覆されている。As is apparent from the above description, in the present invention, the connection electrodes of the circuit board are connected to the electrodes of the semiconductor chip by bonding wires and then covered with thermoplastic polyetheramide.
【００８２】したがって、従来技術の半導体装置と異な
り、ＰＢＧＡが吸湿した状態で加熱しても、接続電極と
封止樹脂の界面で剥離することなく、信頼性の高い半導
体装置が得られる。Therefore, unlike the prior art semiconductor device, even if the PBGA is heated while absorbing moisture, a highly reliable semiconductor device can be obtained without peeling off at the interface between the connection electrode and the sealing resin.
【図１】本発明の実施形態における半導体装置を示す断
面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.
【図２】本発明の実施形態における半導体装置を示す平
面図である。FIG. 2 is a plan view showing a semiconductor device according to the embodiment of the present invention.
【図３】本発明の実施形態における回路基板構造を得る
ための製造工程を示す断面図である。FIG. 3 is a cross-sectional view illustrating a manufacturing process for obtaining a circuit board structure according to the embodiment of the present invention.
【図４】本発明の実施形態における回路基板構造を得る
ための製造工程を示す断面図である。FIG. 4 is a cross-sectional view showing a manufacturing process for obtaining a circuit board structure according to the embodiment of the present invention.
【図５】本発明の実施形態における回路基板構造を得る
ための製造工程を示す断面図である。FIG. 5 is a cross-sectional view showing a manufacturing process for obtaining a circuit board structure according to the embodiment of the present invention.
【図６】本発明の実施形態における回路基板構造を得る
ための製造工程を示す平面図である。FIG. 6 is a plan view showing a manufacturing process for obtaining a circuit board structure according to the embodiment of the present invention.
【図７】従来技術における半導体装置を示す断面図であ
る。FIG. 7 is a cross-sectional view showing a semiconductor device according to a conventional technique.
【図８】従来技術における半導体装置を示す平面図であ
る。FIG. 8 is a plan view showing a semiconductor device according to a conventional technique.
【図９】従来技術における回路基板構造を得るための製
造工程を示す断面図である。FIG. 9 is a cross-sectional view showing a manufacturing process for obtaining a circuit board structure according to a conventional technique.
【図１０】従来技術における回路基板構造を得るための
製造工程を示す断面図である。FIG. 10 is a cross-sectional view showing a manufacturing process for obtaining a circuit board structure according to a conventional technique.
【図１１】従来技術における回路基板構造を得るための
製造工程を示す断面図である。FIG. 11 is a cross-sectional view showing a manufacturing process for obtaining a circuit board structure according to a conventional technique.
【図１２】従来技術における回路基板構造を得るための
製造工程を示す平面図である。FIG. 12 is a plan view showing a manufacturing process for obtaining a circuit board structure in a conventional technique.
２５ 回路基板 ２９ 半導体チップ ３１ ボンディングワイヤ ３７ 熱可塑性ポリエーテルアミド ４１ ＰＢＧＡ Reference Signs List 25 circuit board 29 semiconductor chip 31 bonding wire 37 thermoplastic polyetheramide 41 PBGA
Claims (4)
チック・ボールグリッドアレイであって、 半導体チップは回路基板の一方の面に搭載し、回路基板
の一方の面に接着剤を用いて半導体チップを搭載するた
めのダイアタッチパターンと、半導体チップの電極とボ
ンディングワイヤで接続する接続電極とを有し、 回路基板の他方の面にマザーボードと接続するための半
田バンプを設けるパッド電極を有し、 回路基板は接続電極とパッド電極とを電気的に接続する
ためのスルーホールを有し、 半導体チップとボンディングワイヤとを被覆するように
設ける封止樹脂と、回路基板の接続電極とこの接続電極
に接続するボンディングワイヤとを被覆するように設け
る熱可塑性樹脂とを有することを特徴とする半導体装
置。1. A plastic ball grid array comprising a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one side of the circuit board, and the semiconductor chip is mounted on one side of the circuit board using an adhesive. A circuit board having a die attach pattern for connection to the semiconductor chip, a connection electrode connected to the electrode of the semiconductor chip by a bonding wire, and a pad electrode for providing a solder bump for connection to a motherboard on the other surface of the circuit board. Has a through hole for electrically connecting the connection electrode and the pad electrode, and a sealing resin provided so as to cover the semiconductor chip and the bonding wire, and a connection electrode of the circuit board and the connection electrode. A thermoplastic resin provided so as to cover the bonding wire.
チック・ボールグリッドアレイであって、 半導体チップは回路基板の一方の面に搭載し、回路基板
の一方の面に接着剤を用いて半導体チップを搭載するた
めのダイアタッチパターンと、半導体チップの電極とボ
ンディングワイヤで接続する接続電極とを有し、 回路基板の他方の面にマザーボードと接続するための半
田バンプを設けるパッド電極を有し、 回路基板は接続電極とパッド電極とを電気的に接続する
ためのスルーホールを有し、 半導体チップとボンディングワイヤとを被覆するように
設ける封止樹脂と、回路基板の接続電極とこの接続電極
に接続するボンディングワイヤとを被覆するように設け
る熱可塑性ポリエーテルアミドとを有することを特徴と
する半導体装置。2. A plastic ball grid array comprising a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one side of the circuit board, and the semiconductor chip is mounted on one side of the circuit board using an adhesive. A circuit board having a die attach pattern for connection to the semiconductor chip, a connection electrode connected to the electrode of the semiconductor chip by a bonding wire, and a pad electrode for providing a solder bump for connection to a motherboard on the other surface of the circuit board. Has a through hole for electrically connecting the connection electrode and the pad electrode, and a sealing resin provided so as to cover the semiconductor chip and the bonding wire, and a connection electrode of the circuit board and the connection electrode. A thermoplastic polyetheramide provided so as to cover the bonding wire.
チック・ボールグリッドアレイであって、 半導体チップは回路基板の一方の面に搭載し、回路基板
の一方の面に接着剤を用いて半導体チップを搭載するた
めのダイアタッチパターンと、半導体チップの電極とボ
ンディングワイヤで接続する接続電極とを有し、 回路基板の他方の面にマザーボードと接続するための半
田バンプを設けるパッド電極を有し、 回路基板は、接続電極とパッド電極とを電気的に接続す
るためのスルーホールと、半導体チップの搭載面内に設
け半導体チップの発熱を放散するためのサーマルビアホ
ールを有し、 半導体チップとボンディングワイヤとを被覆するように
設ける封止樹脂と、回路基板の接続電極とこの接続電極
に接続するボンディングワイヤとを被覆するように設け
る熱可塑性樹脂とを有することを特徴とする半導体装
置。3. A plastic ball grid array comprising a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one side of the circuit board, and the semiconductor chip is mounted on one side of the circuit board using an adhesive. A circuit board having a die attach pattern for connection to the semiconductor chip, a connection electrode connected to the electrode of the semiconductor chip by a bonding wire, and a pad electrode for providing a solder bump for connection to a motherboard on the other surface of the circuit board. Has a through hole for electrically connecting the connection electrode and the pad electrode, and a thermal via hole provided on the mounting surface of the semiconductor chip for dissipating heat generated by the semiconductor chip. Covers the sealing resin provided so as to cover, the connection electrodes of the circuit board, and the bonding wires connected to the connection electrodes. Wherein a and a thermoplastic resin provided on so that.
チック・ボールグリッドアレイであって、 半導体チップは回路基板の一方の面に搭載し、回路基板
の一方の面に接着剤を用いて半導体チップを搭載するた
めのダイアタッチパターンと、半導体チップの電極とボ
ンディングワイヤで接続する接続電極とを有し、 回路基板の他方の面にマザーボードと接続するための半
田バンプを設けるパッド電極を有し、 回路基板は、接続電極とパッド電極とを電気的に接続す
るためのスルーホールと、半導体チップの搭載面内に設
け半導体チップの発熱を放散するためのサーマルビアホ
ールを有し、 半導体チップとボンディングワイヤとを被覆するように
設ける封止樹脂と、回路基板の接続電極とこの接続電極
に接続するボンディングワイヤとを被覆するように設け
る熱可塑性ポリエーテルアミドとを有することを特徴と
する半導体装置。4. A plastic ball grid array comprising a circuit board and a semiconductor chip, wherein the semiconductor chip is mounted on one side of the circuit board, and the semiconductor chip is mounted on one side of the circuit board using an adhesive. A circuit board having a die attach pattern for connection to the semiconductor chip, a connection electrode connected to the electrode of the semiconductor chip by a bonding wire, and a pad electrode for providing a solder bump for connection to a motherboard on the other surface of the circuit board. Has a through hole for electrically connecting the connection electrode and the pad electrode, and a thermal via hole provided on the mounting surface of the semiconductor chip for dissipating heat generated by the semiconductor chip. Covers the sealing resin provided so as to cover, the connection electrodes of the circuit board, and the bonding wires connected to the connection electrodes. Wherein a and a thermoplastic polyetheramide provided so that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22809797A JP3768653B2 (en) | 1997-08-25 | 1997-08-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22809797A JP3768653B2 (en) | 1997-08-25 | 1997-08-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1167953A true JPH1167953A (en) | 1999-03-09 |
| JP3768653B2 JP3768653B2 (en) | 2006-04-19 |
Family
ID=16871151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22809797A Expired - Lifetime JP3768653B2 (en) | 1997-08-25 | 1997-08-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3768653B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002542627A (en) * | 1999-04-16 | 2002-12-10 | マイクロン テクノロジー インコーポレイテッド | Conductor system for semiconductor device and method of manufacturing the same |
| JP2011199309A (en) * | 2011-06-06 | 2011-10-06 | Rohm Co Ltd | Semiconductor device |
| JP2013085007A (en) * | 2008-09-09 | 2013-05-09 | Lsi Corp | Package supplied power and connected to ground through via |
| US8810016B2 (en) | 2005-06-06 | 2014-08-19 | Rohm Co., Ltd. | Semiconductor device, substrate and semiconductor device manufacturing method |
-
1997
- 1997-08-25 JP JP22809797A patent/JP3768653B2/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002542627A (en) * | 1999-04-16 | 2002-12-10 | マイクロン テクノロジー インコーポレイテッド | Conductor system for semiconductor device and method of manufacturing the same |
| US8810016B2 (en) | 2005-06-06 | 2014-08-19 | Rohm Co., Ltd. | Semiconductor device, substrate and semiconductor device manufacturing method |
| US9520374B2 (en) | 2005-06-06 | 2016-12-13 | Rohm Co., Ltd. | Semiconductor device, substrate and semiconductor device manufacturing method |
| JP2013085007A (en) * | 2008-09-09 | 2013-05-09 | Lsi Corp | Package supplied power and connected to ground through via |
| JP2011199309A (en) * | 2011-06-06 | 2011-10-06 | Rohm Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3768653B2 (en) | 2006-04-19 |
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