JP2002076215A - Semiconductor device package and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device package, that has improved radiation properties of a semiconductor chip that is subjected to facedown bonding, has little deformation of a substrate, and has improved connectivity with an external circuit. SOLUTION: The semiconductor device package 10 comprises a semiconductor chip 14 and electronic components 16 that are fixed in one piece with a resin as a resin body 12, and wiring patterns 18A-18C where one surface is electrically connected to the semiconductor chip and electronic parts within the resin body, and the other is exposed to the outside of the resin body. The semiconductor chip is subjected to face-down bonding to a die pad 20, is covered with a resin layer, while exposing the rear at the opposite side of the down bonding junction surface of the die pad to the outside, and a first metal projection section 28 projects from the rear of the die pad. A second metal projection section 36 projects from the rear of a wiring pattern. The first and second metal projection sections are the laminated film comprising first and second metal films 32 and 34. A radiator 32 is joined to the first metal projection section, a terminal 38 of an external circuit is connected to the second metal projection section, and the second metal projection section functions as the connection terminal with the external circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package having a semiconductor chip mounted thereon and a method of manufacturing the same, and more particularly, to a method of radiating heat generated by a heat-generating device such as a semiconductor chip in a semiconductor device package. Is good,
The present invention relates to a semiconductor device package free from deformation such as undulation and bending and a method for manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor device having an integrated circuit formed on a semiconductor substrate is sometimes used alone.
It is often used as a system mounted semiconductor device in which a semiconductor chip such as an LSI chip and electronic components other than the semiconductor chip are systematically mounted on a mounting board, that is, a system semiconductor device package.

Here, a configuration of a conventional semiconductor device package will be described with reference to FIG. FIG. 4 is a sectional view showing a configuration of a conventional semiconductor device package. The conventional semiconductor device package 50 uses an organic substrate as a mounting substrate. As shown in FIG. 4, the semiconductor device package 50 is mounted on a die pad 54 provided on an organic substrate 52 such as a polyimide tape through a solder bump 56 through face-down mounting. Bonded LS
An electrode is formed on a semiconductor chip 58 such as an I chip and a wiring pattern 60 provided on the organic substrate 52 by the cream solder portion 6.
It has electronic components 64 such as an inductor element, a capacitor element, and a resistance element connected through the second element 2. A radiator 68 is provided on the back surface of the organic substrate 52 via a connecting member 66 such as solder or resin to radiate heat generated in the semiconductor chip 58 and the like.

The die pad 54 and the wiring pattern 60 are
This is a metal layer formed of a copper foil having a surface layer plated with gold, and is provided on the organic substrate 52 in advance. The solder bump 56 is a protruding solder bump made of a solder metal having excellent thermal conductivity and electrical conductivity, and is formed on the semiconductor chip 58 in an area bump array shape. Die pad 54
The solder bumps 56 are brought into contact with the semiconductor chip 58 by melting the solder bumps 56 in a reflow furnace.
Can be face-down bonded to the die pad 54. The cream solder portion 62 is formed by applying cream solder to a predetermined portion of the wiring pattern 60 by a solder printing method, bringing the electronic component 64 into contact with the cream solder, and placing the cream component in a reflow furnace to melt the cream solder. The electronic component 64 can be connected to the wiring pattern 60 as a unit.

[0005]

However, the above-mentioned conventional semiconductor device package has various problems as described below. The first problem is that since the heat generated in the semiconductor chip or the like is difficult to be dissipated, the environmental temperature of the semiconductor chip or the like increases, which adversely affects the operation of the semiconductor chip or the like. Second, when the organic substrate is made thinner in accordance with the miniaturization of the semiconductor device package, the organic substrate is bent, twisted, and undulated when mounting the semiconductor chip and the like, and the positioning of the semiconductor chip and the electronic component is performed. And the like, and furthermore, there is a problem that the manufactured semiconductor device package is deformed. Third, when connection terminals for an external circuit are provided on the back surface of the organic substrate, it is necessary to provide through holes for connection with a semiconductor chip or the like provided on the front surface of the organic substrate. It is a problem that it is difficult, and a process of forming an organic substrate is complicated due to the opening of a through hole.

Accordingly, an object of the present invention is to provide a semiconductor device package which has good heat radiation from a heat-generating device such as a mounted semiconductor chip, has a small deformation of a substrate, and has good connectivity with an external circuit. Another object of the present invention is to provide a method for manufacturing such a semiconductor device package.

[0007]

In the course of research for achieving the above object, the present inventor has found that the above-mentioned first to third problems of the conventional semiconductor device package all use an organic substrate as a substrate. It turns out that it is caused by doing. That is, the first problem is caused by the low thermal conductivity of the organic substrate. The heat generated from the semiconductor chip mounted on the surface of the organic substrate passes through the organic substrate to the radiator provided on the back surface of the organic substrate because the organic substrate has a significantly lower thermal conductivity than metal. It is difficult to transfer heat, and the temperature of the semiconductor device package rises. The second problem is due to the low rigidity of the organic substrate. Since the rigidity is low, when a semiconductor chip or the like is mounted, the substrate is deformed by the connection force of the connection material, and twisting and undulation are generated. The third problem is caused by the fact that the organic substrate is electrically insulating. For electrical connection between an external circuit and a semiconductor chip or the like, a through hole penetrating the organic substrate,
And wiring is required.

Accordingly, the present inventor has noticed that the thermal conductivity of a metal is more than 1000 times as large as that of an organic material, and has adopted a conventional mounting concept of fixing and mounting a semiconductor chip or the like on a mounting substrate. Instead, the semiconductor chip or the like is covered with a resin such as an epoxy resin or the like, a resin body in which the semiconductor chip or the like is integrally fixed with the resin is formed, and a radiator is joined to an exposed surface of the semiconductor chip via a metal layer. With the idea of a new implementation concept, and repeated experiments, the present invention was invented.

To achieve the above object, based on the above findings, a semiconductor device package according to the present invention comprises a semiconductor chip face-down bonded to a thermally conductive die pad and a wiring pattern; A surface opposite to the semiconductor chip (hereinafter referred to as a back surface) is exposed to cover the semiconductor chip with a resin layer, and a resin body formed integrally with the resin layer and the semiconductor chip, and a protrusion from the rear surface of the die pad. A first metal protrusion having a radiator provided at a tip thereof, and a second metal protrusion serving as a connection terminal with an external circuit, protruding from a back surface of at least one wiring pattern. It is characterized by.

In a semiconductor device package in which electronic parts such as an inductor element, a capacitor element, and an electric resistance element are mounted in addition to a semiconductor chip having an integrated circuit formed on a semiconductor substrate, a heat conductive die pad and a wiring pattern are provided. Semiconductor chip face-down bonded to the semiconductor chip, an electronic component other than the semiconductor chip electrically connected to the wiring pattern, and a surface of the die pad and the wiring pattern opposite to the semiconductor chip or the electronic component (hereinafter referred to as a back surface). The semiconductor chip and the electronic component are covered with a resin layer, the resin body formed integrally with the semiconductor chip and the electronic component and the resin layer, and a resin body protruding from the back surface of the die pad. A first metal protrusion provided, and a protrusion protruding from a back surface of at least one wiring pattern;
A second metal projection functioning as a connection terminal for an external circuit.

In the present invention, the term “semiconductor chip” refers to a chip-shaped semiconductor device in which an integrated circuit is formed on a substrate.
The present invention is not limited to this, and is a broad concept including a heat-generating device similar to a semiconductor chip. An electronic component is an element having a lower heat generation than a semiconductor chip, and includes an inductor element,
It refers to so-called LCR components such as a capacitor element and a resistance element. The radiator may be of any type, shape, model, etc. as long as it can radiate heat. In the present invention, the semiconductor chip and the electronic component are:
Instead of the mounting substrate, it is integrally fixed by a resin body. The resin constituting the resin body is not particularly limited as long as it is insulative. The semiconductor chip is face-down bonded (flip chip bonded) onto the die pad via solder bumps by a reflow method.
The electronic component is directly connected to the wiring pattern by a cream solder portion whose electrodes are formed by applying a solder printing method or the like and melting the applied solder by a reflow method.
In the present invention, since the semiconductor chip is bonded to the radiator through the solder bump, the die pad, and the first metal protrusion each having good thermal conductivity, the heat generated in the semiconductor chip is not radiated. Heat is smoothly transferred to the vessel, and the heat is efficiently radiated to the outside from the radiator.

Each of the first metal projection and the second metal projection includes a first metal layer and a second metal layer having the same outer shape and laminated on the first metal layer. . Preferably, the first metal layer is a copper alloy plate, a die pad,
The wiring pattern and the second metal layer are plated metal layers formed by an electrolytic plating method.

[0013] A method of manufacturing a semiconductor device package according to the present invention comprises a first pattern forming step of forming a heat conductive die pad and a conductive wiring pattern on one surface of a heat conductive / conductive sheet; Forming a heat conductive / conductive etching mask having etching selectivity with respect to the thin plate and having substantially the same shape as the die pad and the wiring pattern, respectively, at a position corresponding to the die pad and the wiring pattern on the other surface; 2) A semiconductor chip is face-down bonded onto a die pad and a wiring pattern by a reflow method, and
A step of electrically connecting electronic components other than the semiconductor chip on the wiring pattern; and a step of taking out the surface opposite to the bonding surface of the die pad and the surface opposite to the connection surface of the wiring pattern to the semiconductor chip. And a step of covering the electronic component with a resin to form a resin body integral with the semiconductor chip and the electronic component, and etching the thin plate from above the etching mask to form a gap between the etching mask and the die pad and between the etching mask and the wiring pattern. Exposing the resin of the resin body while leaving the thin plate layer therebetween.

In a practical embodiment of the method of the present invention, a copper alloy thin plate is used as the thin plate. In the first pattern forming step, a first pattern mask is formed by a photoresist film, and then the thin film is formed on the thin plate by electrolytic plating. Forming a first metal film and then removing the first pattern mask by a registry mover to form a die pad and a wiring pattern; and a second pattern forming step, using a photoresist film to form a second metal film. Is formed, and then a second metal film is formed on the thin plate by electrolytic plating,
Subsequently, the second pattern mask is removed by a registry mover to form an etching mask.

[0015]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment of Semiconductor Device Package This embodiment is an example of an embodiment of a semiconductor device package according to the present invention, and FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device package of the present embodiment. The semiconductor device package 10 according to the present embodiment has a semiconductor chip 14 and an electronic component 16 which are each covered with a resin layer and fixed integrally with the resin as a resin body 12. To electrically connect to at least one of the semiconductor chip 14 and the electronic component 16, and to the other surface (hereinafter, referred to as the
(Referred to as a back surface) are provided with wiring patterns 18A to 18C extending outside the resin body 12.

The resin body 12 is formed of a non-conductive resin such as an epoxy resin, for example. The semiconductor chip 14
A semiconductor chip provided with solder bumps on the upper surface in an area bump array shape, wherein the solder bumps 19 are brought into contact with the thermally conductive die pad 20 and the wiring pattern 18B and are connected by face-down bonding (flip chip bonding). I have. The electronic component 18 is
The electrode of the electronic component 18 is any of so-called LCR elements such as an inductor element, a capacitor element, and an electric resistance element, and is electrically connected to the wiring patterns 18A and 18C directly by the cream solder portion 22. The wiring patterns 18A to 18C and the die pad 20 are sequentially laminated by electrolytic plating to form a nickel (N
i) layer, copper (Cu) layer having a plating thickness of 10 μm, plating thickness 1
0 μm nickel (Ni) layer and plating thickness 0.5 μm
To 1 μm of a gold (Au) layer.

The die pad 20 is covered with a resin layer by projecting a surface (hereinafter, referred to as a back surface) opposite to a bonding surface with the semiconductor chip 14, and is provided with a first metal protrusion from the back surface of the die pad 20. The part 24 protrudes. In addition, second metal projections 26A and 26B project from the back surfaces of the wiring patterns 18A and 18B, respectively. The first metal protrusion 24 and the second metal protrusions 26A and 26B are formed as a stacked film of a first metal film 28 and a second metal film 30, respectively. The first metal film 28 has a thickness of 100 μm, which is similar to the thickness of a lead frame used when manufacturing a semiconductor package.
It is formed using a copper alloy plate of m to 200 μm.
The second metal film 30 is sequentially formed with the first metal film 30 by an electrolytic plating method.
Is a laminated metal film composed of a nickel (Ni) layer having a plating thickness of 2 μm and a gold (Au) layer having a plating thickness of 0.5 μm to 1 μm laminated on the metal film 28 of FIG.

The second metal film 30 of the first metal projection 24
On the side, a radiator 32 such as a radiation fin is joined by a solder layer 34 for connection. On the second metal film 30 side of the second metal protrusions 26A, B, the connection is made to the terminals 38A, B of the external circuit by the connection solder layer 36, respectively. 26 functions as a connection terminal with an external circuit.

The semiconductor device package 10 according to the present embodiment.
Since the semiconductor chip 14 is joined to the radiator 32 via the solder bump 19, the thermally conductive die pad 20, the thermally conductive first metal protrusion 24, and the solder layer 34 for connection, The heat generated at 14 is smoothly transmitted to the radiator 32 and then efficiently radiated from the radiator 32 to the outside. Further, the semiconductor chip 14 and the electronic component 16
Is formed integrally with the resin body 12 with high rigidity, so that deformation, bending and the like do not occur. In the present embodiment, the number of the semiconductor chips 14 and the electronic components 16 is one each, and therefore, the number of the terminals 38 is two. However, the number of the semiconductor chips 14 and the electronic components 16 is not limited. Therefore, there are actually several tens to several hundreds of second metal protrusions 26 and terminals 38.

The manufacturing method embodiment of the semiconductor device package, an example embodiment of a method for manufacturing a semiconductor device package according to the present invention is applied to manufacturing a semiconductor device package 10 described above, FIGS. 2 (a) From (d)
FIGS. 3E and 3F are cross-sectional views for respective steps when a semiconductor device package is manufactured by the method of the present embodiment. First, as shown in FIG. 2A, a substrate 40 for manufacturing a semiconductor device package is formed using a copper alloy plate having a thickness of 100 μm to 200 μm similar to a lead frame used when manufacturing a semiconductor package. .

Next, a photoresist film is formed on the substrate 40 and then subjected to photolithography to form a mask (not shown) having a die pad and a wiring pattern. Next, a laminated metal film is formed on the substrate 40 by an electrolytic plating method, and subsequently, the resist film is removed, and as shown in FIG.
And the wiring patterns 18A to 18C are formed. Die pad 2
0 and the laminated metal films constituting the wiring patterns 18A to 18C are sequentially laminated on the substrate 40, and have a plating thickness of 2 μm.
Nickel (Ni) layer, copper (Cu) with a plating thickness of 10 μm
This is a laminated metal film including a layer, a nickel (Ni) layer having a plating thickness of 10 μm, and a gold (Au) layer having a plating thickness of 0.5 μm to 1 μm.

Next, a photoresist film is formed on the surface of the substrate 40 opposite to the wiring pattern 18 and the die pad 20, and then a photolithography process is performed to form a mask pattern (not shown). The mask pattern is
At a position facing the die pad 20, a pattern having substantially the same shape as the die pad 20 is provided, and at a position facing the wiring patterns 18A and 18B, a pattern having substantially the same shape as the wiring patterns 18A and B is provided. Next, a laminated metal film is formed by electrolytic plating, and subsequently, the resist film is removed.
As shown in (c), the second metal film 30 of the first metal projection 24 and the second metal films 30A and 30B of the second metal projections 26A and 26B are formed. Thereby, the second metal film 30 has a pattern having substantially the same shape as the die pad 20 at a position facing the die pad 20,
A and B are positions facing the wiring patterns 18A and 18B,
It has substantially the same shape as the wiring patterns 18A and 18B. The laminated metal film forming the second metal films 30, 30A, and B includes a nickel (Ni) layer having a plating thickness of 2 μm and a plating thickness of 0.5 μm.
It is a laminated film composed of a gold (Au) layer of μm to 1 μm.

Next, a cream solder 22 is applied to predetermined portions of the wiring patterns 18A to 18C by a solder printing method or the like, and then the electrodes of the electronic component 14 are brought into contact with the cream solder 22; Is brought into contact with the die pad 20. Subsequently, the solder bumps 19 and the cream solder 22 were melted by being put into a reflow furnace, and FIG.
As shown in (d), the semiconductor chip 14 is attached to the die pad 2.
0 and the electronic component 14 is connected to the wiring patterns 18A to 18C.

Next, as shown in FIG. 3E, the bonded semiconductor chip 14 and the connected electronic component 16 are covered with a resin such as an epoxy resin, and the semiconductor chip 14 and the electronic component 16 are mounted on a substrate 40 by a resin. To form a resin body 12 integrally fixed therewith.

Next, as shown in FIG. 3F, the substrate 40 is formed using the second metal films 30A and 30B as an etching mask.
Is etched by a wet etching method so that the first
And the second metal protrusions 26A and 26B are formed, and the wiring pattern 18C is exposed. As the etchant, an alkaline solution is used so as not to attack the nickel in the wiring patterns 18A to 18C formed by the electrolytic plating method and the die pad 20.

Next, a radiator 32 is joined on the second metal film 30 of the first metal projection 24 by a solder layer 34,
In addition, the second metal film 30 of the second metal protrusions 26A and 26B
When terminals 38A and 38B of the external circuit are joined to A and B by the solder layer 36, the semiconductor device package 10 shown in FIG.
Can be obtained.

In this embodiment, since the wiring pattern 18 is formed by using a photo process and an electrolytic plating method, a line having a shape and a path with higher precision than a conventional wiring pattern obtained by etching a copper foil. Is obtained. Thus, the number of pins of the semiconductor device package can be increased. Further, when connecting the semiconductor chip 14 and the electronic component 16 to the wiring pattern 18, the copper plywood substrate 40 has a structure supporting the wiring pattern 18. Connection work. Further, since the radiator 32 and the terminals 38A and 38B are on the same side of the semiconductor device package 10, the connection of the external circuit and the attachment of the radiator plate can be performed simultaneously in one joining step.

[0028]

According to the present invention, a resin body is formed by covering a semiconductor chip or the like with a resin and integrally fixing the semiconductor chip or the like with the resin, and bonding a radiator to the semiconductor chip via a metal layer. As a result, a semiconductor device package having good heat dissipation, no deformation during manufacture, and easy to manufacture is realized. Furthermore, since a heat-generating device such as a semiconductor chip is directly connected to a metal having a small thermal resistance, mounting with excellent heat radiation characteristics can be performed even in a thin circuit.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device package according to an embodiment.

FIGS. 2A to 2D are cross-sectional views for respective steps when a semiconductor device package is manufactured by the method of the embodiment.

3 (e) and 3 (f) respectively show FIG. 2 (d)
4A to 4C are cross-sectional views for each step in manufacturing a semiconductor device package by the method of the embodiment.

FIG. 4 is a cross-sectional view illustrating a configuration of a conventional semiconductor device package.

[Explanation of symbols]

10. Semiconductor device package of embodiment example, 12 ...
Resin body, 14: semiconductor chip, 16: electronic component, 1
8 ... wiring pattern, 20 ... thermally conductive die pad, 2
2 cream solder portion, 24 first metal protrusion, 26 second metal protrusion, 28 first metal film, 30 second metal film, 32 Radiator, 34 ...
Solder layer 36 Solder layer 38A, B Terminal of external circuit 40 Substrate 50 Conventional semiconductor device package 52 Organic substrate 54 Die pad 56
Solder bumps, 58, semiconductor chip, 60, wiring pattern, 62, cream solder part, 64, electronic component, 6
6 ... connecting material, 68 ... radiator.

Claims (7)

[Claims] 1. A semiconductor chip which is face-down bonded to a thermally conductive die pad and a wiring pattern, and a semiconductor chip having a surface (hereinafter referred to as a back surface) of the die pad and the wiring pattern opposite to the semiconductor chip. A resin body formed by integrally forming the resin layer and the semiconductor chip, a first metal protrusion protruding from the back surface of the die pad and provided with a radiator at the tip, and at least one A second metal protrusion protruding from the back surface of the wiring pattern and functioning as a connection terminal for an external circuit. 2. A semiconductor chip face-down bonded to a thermally conductive die pad and a wiring pattern; an electronic component other than the semiconductor chip electrically connected to the wiring pattern; and a semiconductor chip or an electronic component of the die pad and the wiring pattern. A resin body formed by taking out a surface opposite to the component (hereinafter referred to as a back surface) and covering the semiconductor chip and the electronic component with a resin layer, and integrally forming the semiconductor chip and the electronic component with the resin layer; A first metal protrusion protruding from the back surface of the die pad and having a radiator provided at the tip; and a second metal protrusion protruding from the back surface of at least one wiring pattern and functioning as a connection terminal with an external circuit. A semiconductor device package comprising: 3. The first metal protrusion and the second metal protrusion each include a first metal layer and a second metal layer having the same outer shape and laminated on the first metal layer. The semiconductor device package according to claim 1, wherein: 4. The method according to claim 3, wherein the first metal layer is a copper alloy layer, and the die pad, the wiring pattern and the second metal layer are plated metal layers formed by an electrolytic plating method. Electronic devices. 5. A first pattern forming step of forming a heat conductive die pad and a conductive wiring pattern on one surface of a heat conductive / conductive thin plate, and corresponding to a die pad and a wiring pattern on the other surface of the thin plate. A second pattern forming step of forming a heat conductive / conductive etching mask having etching selectivity with respect to the thin plate and having substantially the same shape as the die pad and the wiring pattern, respectively, at a position where Bonding the semiconductor chip to the die pad and the wiring pattern by face-down bonding, and electrically connecting electronic components other than the semiconductor chip to the wiring pattern. Take out the surface of the wiring pattern opposite to the connection surface and cover the semiconductor chip and electronic components with resin. Forming a resin body integral with the child component, etching the thin plate from above the etching mask, and leaving the thin plate layer between the etching mask and the die pad and between the etching mask and the wiring pattern, Exposing the resin as described above. 6. A copper alloy thin plate is used as a thin plate. In a first pattern forming step, a first pattern mask is formed by a photoresist film, and then a first metal film is formed on the thin plate by an electrolytic plating method. Then, the first pattern mask is removed by a registry mover to form a die pad and a wiring pattern, and in the second pattern forming step, a second pattern mask is formed by a photoresist film, and then the electrolytic pattern is formed. 7. The semiconductor device package according to claim 6, wherein a second metal film is formed on the thin plate by a plating method, and subsequently, the second pattern mask is removed by a registry remover to form an etching mask. Method of manufacturing. 7. The method according to claim 1, wherein the first metal film and the second metal film are formed of a nickel (Ni) layer, a copper (Cu) layer, a nickel (Ni) layer,
A gold (Au) layer or a nickel (Ni) layer,
8. The method for manufacturing a semiconductor device package according to claim 7, wherein the semiconductor device package is formed as a laminated film of a gold (Au) layer and a gold (Au) layer.