JP7192523B2 - Semiconductor packages and electronic devices - Google Patents

Description

The present invention relates to semiconductor packages and electronic devices.

Conventionally, there has been known an electronic circuit package in which electronic components, circuit elements, etc. are embedded in molding resin so that electrode surfaces are exposed, and a wiring pattern formed in the molding resin forms a circuit (for example, Patent Document 1).

JP-A-7-66570

By the way, there is known a FO-WLP (Fan-out wafer level package) in which a device is sealed with mold resin and connected by rewiring to form a package. FO-WLP is capable of high-speed transmission without using solder, and its application to high-frequency circuits has been studied in recent years. In this case, not only devices but also many chip parts such as chip capacitors must be mixed and connected by rewiring. However, when a large number of chip parts are mounted, the rewiring distance between the semiconductor chip and the chip parts becomes long, and it is conceivable that the improvement of characteristics at high frequencies is restricted and the package size becomes large. Patent Document 1 can include many electronic components, circuit elements, and the like, but no consideration is given to shortening the wiring that connects them.

In one aspect, an object of the invention disclosed in this specification is to shorten the wiring length between a device and a chip component in a semiconductor package.

In one aspect, the semiconductor package is laminated on a metal plate and is laminated on a device whose periphery is surrounded by mold resin, and on the side opposite to the side on which the metal plate is laminated of the device, and is connected to the device. an insulating film provided in the mold resin on the side of the device and in contact with the metal plate in the mold resin; and between the metal plate in the mold resin a metal plate-side chip component arranged on the side of the device with the insulating film interposed therebetween; and a via connected to the wiring layer.

In another aspect, an electronic device is an electronic device having a semiconductor package mounted on a printed circuit board, wherein the semiconductor package is laminated on a metal plate and surrounded by a mold resin; a rewiring layer laminated on the side opposite to the side on which the metal plate of the device is laminated and connected to the device; a metal plate-side chip component disposed on the side of the device in the mold resin with the insulating film interposed between the metal plate and the metal plate side chip component provided in the mold resin; a via having one end connected to the electrode of the metal plate-side chip component and the other end connected to the rewiring layer.

The present invention can shorten the wiring length between a device and a chip part in a semiconductor package.

FIG. 1 is an explanatory view of the semiconductor package of the embodiment viewed from the side. FIG. 2 is an explanatory diagram of the semiconductor package of the embodiment viewed from above. FIG. 3 is a cross-sectional view taken along line AA in FIG. 4 is a cross-sectional view taken along the line BB in FIG. 2. FIG. FIG. 5 is an explanatory diagram of the electronic device of the embodiment. FIG. 6A is an explanatory diagram showing the first step of the manufacturing process of the semiconductor package according to the embodiment, and FIG. 6B is an explanatory diagram showing the second process of the manufacturing process of the semiconductor package according to the embodiment. FIG. 7A is an explanatory diagram showing the third step of the manufacturing process of the semiconductor package according to the embodiment, and FIG. 7B is an explanatory diagram showing the fourth process of the manufacturing process of the semiconductor package according to the embodiment. FIG. 8A is an explanatory diagram showing the fifth step of the manufacturing process of the semiconductor package of the embodiment, and FIG. 8B is an explanatory diagram showing the sixth process of the manufacturing process of the semiconductor package of the embodiment. FIG. 9 is an explanatory diagram of the semiconductor package of the comparative example viewed from the side.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. At this time, the width direction, the depth direction and the thickness direction of the semiconductor package are set to the directions shown in FIGS. However, in the drawings, the dimensions, ratios, etc. of each part may not be illustrated so as to completely match the actual ones. In addition, depending on the drawings, for the convenience of explanation, there are cases where components that actually exist are omitted, or dimensions are drawn with exaggeration. For example, in each drawing, the dimension in the thickness direction is enlarged compared to the dimension in the width direction and the depth direction.

Referring to FIG. 1, the semiconductor package 10 of the embodiment includes a device 11, a metal plate 12, a first insulating film 14a, a second insulating film 14b, a first chip component 15, a second chip component 16 and a third chip component 17. , fourth chip component 18 , mold resin 19 and rewiring layer 21 . A first via 23 a , a second via 23 b , a third via 23 c and a fourth via 23 d are formed in the mold resin 19 . In the rewiring layer 21, first wirings 24a to eighth wirings 24h are provided. The semiconductor package 10 is a FO-WLP with a redistribution layer 21 . A semiconductor package is sometimes called a semiconductor device.

The device 11 is generally an active component such as a CMOS LSI (Complementary Metal-Oxide Semiconductor Large-Scale Integration), a memory, a power amplifier, and a power device. Also, the device 11 may be an AD converter, a DC/DC converter, MEMS (Micro Electro Mechanical Systems), a capacitor, an inductor, a sensor, or the like. The device 11 of this embodiment is a Si (silicon) device, and has a first surface 11a as a circuit formation surface and a second surface 11b as a rear surface of the first surface 11a. Note that the device 11 may also be called a semiconductor chip or a semiconductor element. The first surface 11a of the device 11 is provided with first pads 20a to fourth pads 20d.

The metal plate 12 is provided to dissipate heat from the second surface 11 b of the device 11 . The metal plate 12 is laminated on the device 11 by bonding to the second surface 11b of the device 11 via an adhesive layer 13 using metal paste. Since the metal plate 12 functions as a heat spreader that releases heat to the sides of the device 11, the widthwise dimension of the metal plate 12 is larger than the widthwise dimension of the device 11 as shown in FIGS. It's becoming Further, as shown in FIG. 2, the dimension of the metal plate 12 in the depth direction is also larger than the dimension of the device 11 in the depth direction. Although the metal plate 12 of this embodiment is made of Cu (copper), the material can be appropriately selected in consideration of heat dissipation. For example, single metals selected from Au (gold), Ag (silver), Al (aluminum), Ni (nickel), Sn (tin), In (indium), Pd (palladium), alloys containing these metals can be selected as the material for the metal plate 12. AuSn (gold tin) paste is used for the adhesive layer 13, but a material with good thermal conductivity such as Ag (silver) paste can be used.

The laminated device 11 and metal plate 12 are surrounded by a mold resin 19 . A first insulating film 14 a and a second insulating film 14 b are provided in the mold resin 19 . The first insulating film 14a and the second insulating film 14b are made of epoxy resin, but may be made of SiO2 (silicon dioxide) or SiN (silicon nitride). Both the first insulating film 14 a and the second insulating film 14 b are arranged on the sides of the device 11 and provided in contact with the metal plate 12 . Also, in the mold resin 19 , a first chip component 15 is arranged on the side of the device 11 with a first insulating film 14 a interposed between it and the metal plate 12 . A second chip component 16 is arranged on the side of the device 11 with a second insulating film 14 b interposed between it and the metal plate 12 . Both the first chip component 15 and the second chip component 16 are examples of metal plate side chip components. The reason why the first insulating film 14a and the second insulating film 14b are provided is to avoid electrical connection between the first chip component 15 and the second chip component 16 through the metal plate 12 . The metal plate-side chip component may be provided on the front side or the back side of the device 11 .

The first chip component 15 has a first electrode 15a and a second electrode 15b. The second chip component 16 similarly has a first electrode 16a and a second electrode 16b. A first via 23 a , a second via 23 b , a third via 23 c and a fourth via 23 d are formed in the mold resin 19 . One end of the first via 23 a is connected to the first electrode 15 a of the first chip component 15 . One end of the second via 23 b is connected to the second electrode 15 b of the first chip component 15 . One end of the third via 23 c is connected to the first electrode 16 a of the second chip component 16 . One end of the fourth via 23 d is connected to the second electrode 16 b of the second chip component 16 .

A rewiring layer 21 is laminated on the side opposite to the side of the device 11 on which the metal plate 12 is laminated, that is, on the side of the first surface 11a. An insulating layer 21 a is provided between the rewiring layer 21 and the mold resin 19 as part of the rewiring layer 21 . On the surface of the rewiring layer 21, fifth pads 22a to eighth pads 22d are provided.

A third chip component 17 and a fourth chip component 18 are provided in the mold resin 19 at the boundary with the rewiring layer 21 . Both the third chip component 17 and the fourth chip component 14 are examples of rewiring layer side chip components. The rewiring layer side chip component may be provided on the front side or the back side of the device 11 . The first chip component 15 to the fourth chip component 18 are generally passive components such as chip capacitors. The third chip component 17 has a first electrode 17a and a second electrode 17b. The fourth chip component 18 similarly has a first electrode 18a and a second electrode 18b.

The first wiring 24a to the eighth wiring 24h provided in the rewiring layer 21 appropriately connect vias, electrodes, and pads, respectively. Specifically, referring to FIGS. 1, 2 and 3, the first wiring 24a connects the first via 23a and the first pad 20a. The second wiring 24b connects the second via 23b and the fifth pad 22a. The third wiring 24c connects the third via 23c and the second pad 20b. The fourth wiring 24d connects the fourth via 23d and the sixth pad 22b.

1, 2 and 4, the fifth wiring 24e connects the first electrode 17a of the third chip component 17 and the third pad 20c. The sixth wiring 24f connects the second electrode 17b of the third chip component 17 and the seventh pad 22c. The seventh wiring 24g connects the first electrode 18a of the fourth chip component 18 and the fourth pad 20d. The eighth wiring 24h connects the second electrode 18b of the fourth chip component 18 and the eighth pad 22d.

Here, the positional relationship of the first chip component 15 to the fourth chip component 18 will be described while comparing with the semiconductor package 50 of the comparative example shown in FIG. First, regarding the semiconductor package 10 of the present embodiment, referring to FIG. 1 and FIG. In terms of orientation, it is arranged closer to the rewiring layer 21 than the first chip component 15 and the second chip component 16 are. In addition, the third chip component 17 is arranged slightly outside the first chip component 15 in the width direction, that is, on the side away from the device 11 . Similarly, the fourth chip component 18 is arranged slightly outside the second chip component 16 in the width direction, that is, on the side away from the device 11 .

Next, referring to FIG. 9, a semiconductor package 50 of the comparative example includes first chip components 51 to fourth chip components 54, like the semiconductor package 10. FIG. The first chip component 51 corresponds to the first chip component 15 . The second chip component 52 corresponds to the second chip component 16 . A third chip component 53 corresponds to the third chip component 17 . A fourth chip component 54 corresponds to the fourth chip component 18 . Also, the semiconductor package 50 includes a mold resin 19 and a rewiring layer 21, like the semiconductor package 10. As shown in FIG.

However, the arrangement of the first chip component 51 to the fourth chip component 54 in the semiconductor package 50 is different from the arrangement of the first chip component 15 to the fourth chip component 18 in the semiconductor package 10 . That is, in the semiconductor package 50 , the first chip component 51 to the fourth chip component 54 are arranged in series at the boundary between the mold resin 19 and the rewiring layer 21 . The positions in the thickness direction of the first chip component 51 to the fourth chip component 54 are the same. Therefore, in FIG. 9, on the right side of the device 11, the first chip component 51 and the third chip component 53 are arranged with a space therebetween. Similarly, in FIG. 9, on the left side of the device, a second chip component 52 and a fourth chip component 54 are spaced apart. Each electrode of the first chip component 51 to the fourth chip component 54 is connected to a pad or the like by wiring provided in the rewiring layer 21 .

When the chip components are arranged at the boundary between the mold resin 19 and the rewiring layer 21 in this manner, one chip component is spaced further from the device 11 than the other chip components so that the chip components do not come into contact with each other. need to be placed in position. Therefore, as shown in FIG. 9, the distance between the device 11 and the third chip component 53, which is located farther from the device 11 than the first chip component 51, is S50. The distance S50 is longer than the distance S10 between the third chip component 17 and the device 11 shown in FIG.

The shortening of the wiring distance in the semiconductor package 10 is achieved by arranging the chip parts in the mold resin 19 with an insulating film interposed between them and the metal plate 12 to avoid interference between the chip parts. In other words, by shifting the chip parts in the thickness direction, the chip parts can be brought closer to the device 11 in the width direction and the depth direction, and the wiring distance can be shortened. In FIG. 1, the wiring distance in the thickness direction is drawn to be longer than that in FIG. The semiconductor package 10 of the embodiment is shorter than the semiconductor package 50 of the comparative example.

Thus, the semiconductor package 10 of this embodiment can shorten the wiring length between the device and the chip component in the semiconductor package. Such a semiconductor package 10 forms an electronic device 100 by being mounted on a printed circuit board 40 via solder balls 42, as shown in FIG. Such a semiconductor package 10 can be suitably used, for example, in a high-frequency region of millimeter waves or higher because the wiring can be shortened. Also, the package itself can be made smaller.

Next, a method for manufacturing the semiconductor package 10 will be described with reference to FIGS. 6A to 8B. First, referring to FIG. 6A, an adhesive layer 13 is formed at the center of a metal plate 12 made of copper to adhere the device 11 to the metal plate 12 . The adhesive layer 13 is formed with AuSn paste. A first insulating film 14a and a second insulating film 14b are formed on the sides of the adhesive layer 13 using epoxy resin. Both the first insulating film 14 a and the second insulating film 14 b are provided so that a gap is formed between them and the adhesive layer 13 . The first insulating film 14a and the second insulating film 14b are formed by spin-coating a photosensitive epoxy resin, exposing it, and developing it.

Next, referring to FIG. 6B, the device 11 is mounted on the adhesive layer 13, the first chip component 15 is mounted on the first insulating film 14a, and the second chip component is mounted on the second insulating film 14b. 16 is implemented. Specifically, the device 11 is mounted on the adhesive layer 13, the first chip component 15 is mounted on the first insulating film 14a, and the second chip component 16 is mounted on the second insulating film 14b by a flip chip bonder. Thus, a pseudo chip 45 is formed.

Next, referring to FIG. 7A, the pseudo chip 45, the third chip component 17 and the fourth chip component 18 are temporarily fixed on the adhesive layer 71 provided on the support substrate 70. Then, as shown in FIG. The support substrate 70 was a SUS (stainless steel) substrate, and the adhesive layer 71 was formed by laminating resin films having double-sided adhesive layers on the support substrate 70 at room temperature. By placing the first chip component 15 on the first insulating film 14a and placing one third chip component 17 on the adhesive layer 71, the first chip component 15 and the third chip component 17 are arranged in the thickness direction. Can be placed apart. Similarly, by placing the second chip component 16 on the second insulating film 14b and placing one fourth chip component 18 on the adhesive layer 71, the second chip component 16 and the fourth chip component 18 are bonded together. They can be spaced apart in the thickness direction. The first chip component 15 is provided on the first insulating film 14a, and the second chip component 16 is provided on the second insulating film 14b. The position in the thickness direction can be maintained.

Then, as shown in FIG. 7B, the pseudo chip 45, the third chip component 17 and the fourth chip component 18 are covered with the molding resin 19. Then, as shown in FIG. The mold resin 19 is formed into a pseudo-wafer-shaped molded body in a 120° C. environment. Then, the molded body is separated from the adhesive layer 71 and cured in an environment of 150° C. for 1 hour to obtain the pseudo wafer 46 .

Next, referring to FIG. 8(A), a laser beam is emitted from the first via hole 19a toward the electrodes of the first chip component 15 and the second chip component 16 embedded in the mold resin 19 of the pseudo wafer 46. A fourth via hole 19d is formed. Here, a carbon dioxide laser is used considering that the mold resin 19 contains a filler.

After forming the first via hole 19a to the fourth via hole 19d, a rewiring layer 21 is formed as shown in FIG. 8B by using a conventionally known rewiring process. Specifically, after forming a seed layer made of Ti (titanium) and Cu by sputtering, a positive resist is applied by spin coating and exposed. As a result, via hole portions and wiring portions were opened, and connection portions with the first chip component 15 and the second chip component 16 were completed by electroplating and resist stripping steps.

After that, the rewiring layer 21 was formed by repeating the formation of a photosensitive positive resist, electroplating, and resist stripping.

In the semiconductor package 10, as shown in FIG. electrically connected. Thus, the electronic device 100 is formed.

Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications, Change is possible.

10 semiconductor package 11 device 12 metal plate 13 adhesive layer 15 first chip component 16 second chip component 17 third chip component 18 fourth chip component 19 mold resin 21 rewiring layer 23a first via 23b second via 23c third via 23d fourth via 40 printed board 42 solder ball 100 electronic device

Claims (4)

a device laminated on a metal plate and surrounded by molding resin;
a rewiring layer laminated on the opposite side of the device to the side where the metal plate is laminated and connected to the device;
an insulating film disposed in the mold resin on the side of the device and in contact with the metal plate;
a metal plate-side chip component arranged on the side of the device in the mold resin with the insulating film interposed between the metal plate and the metal plate;
a via provided in the mold resin and having one end connected to the electrode of the metal plate-side chip component and the other end connected to the rewiring layer;
a rewiring layer side chip component arranged closer to the rewiring layer than the metal plate side chip component in the mold resin,
A semiconductor package in which the metal plate side chip component and the rewiring layer side chip component are arranged with being shifted in a thickness direction . 2. The semiconductor package according to claim 1 , wherein a distance in plan view between said metal plate side chip component and said device is different from a distance in plan view between said rewiring layer side chip component and said device. 3. The device according to claim 2, wherein an end portion of said rewiring layer side chip component on a side closer to said device is arranged at a position closer to said device than an end portion of said metal plate side chip component on a side farther from said device. A semiconductor package as described. An electronic device having a semiconductor package mounted on a printed circuit board,
The semiconductor package is
a device laminated on a metal plate and surrounded by molding resin;
a rewiring layer laminated on the opposite side of the device to the side where the metal plate is laminated and connected to the device;
an insulating film disposed in the mold resin on the side of the device and in contact with the metal plate;
a metal plate-side chip component arranged on the side of the device in the mold resin with the insulating film interposed between the metal plate and the metal plate;
a via provided in the mold resin, one end of which is connected to the electrode of the metal plate-side chip component, and the other end of which is connected to the rewiring layer ;
a rewiring layer side chip component arranged closer to the rewiring layer than the metal plate side chip component in the mold resin,
The metal plate side chip component and the rewiring layer side chip component are arranged to be shifted in the thickness direction,
electronic device.

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