JPH11111749A - Semiconductor device, circuit member using the same, and method for manufacturing them - Google Patents
Semiconductor device, circuit member using the same, and method for manufacturing themInfo
- Publication number
- JPH11111749A JPH11111749A JP28799397A JP28799397A JPH11111749A JP H11111749 A JPH11111749 A JP H11111749A JP 28799397 A JP28799397 A JP 28799397A JP 28799397 A JP28799397 A JP 28799397A JP H11111749 A JPH11111749 A JP H11111749A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- die pad
- pad portion
- circuit member
- internal terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1433—Application-specific integrated circuit [ASIC]
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体素子を搭載し
た樹脂封止型の半導体装置とそれに用いられる回路部材
およびそれらの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device having a semiconductor element mounted thereon, a circuit member used for the semiconductor device, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】近年、半導体装置は、高集積化や小型化
技術の進歩、電気機器の高性能化と軽薄短小化の傾向
(時流)から、LSIのASICに代表されるように、
ますます高集積化、高機能化になってきている。2. Description of the Related Art In recent years, semiconductor devices have been typified by LSI ASICs due to advances in high integration and miniaturization technologies, and the trend toward higher performance and lighter, thinner and smaller electric appliances (current trend).
It is becoming more and more highly integrated and highly functional.
【0003】これに伴い、リードフレームを用いた封止
型の半導体装置においても、その開発のトレンドが、S
OJ(Small Outline J−Leaded
Package)やQFP(Quad Flat P
ackage)のような表面実装型のパッケージを経
て、TSOP(Thin Small Outline
Package)の開発による薄型化を主軸としたパッ
ケージの小型化へ、さらにはパッケージ内部の3次元化
によるチップ収納効率向上を目的としたLOC(Lea
d On Chip)の構造へと進展してきた。Accordingly, the development trend of the sealing type semiconductor device using the lead frame has been
OJ (Small Outline J-Leaded
Package or QFP (Quad Flat P)
through a surface mount type package such as a TSOP (Thin Small Outline).
LOC (Lea) for the purpose of package miniaturization with the main axis of thinning due to the development of Package) and improvement of chip storage efficiency by making the package three-dimensional.
d On Chip).
【0004】[0004]
【発明が解決しようとする課題】しかし、樹脂封止型の
半導体装置パッケージには、高集積化、高機能化ととも
に、更に一層の多ピン化、薄型化、小型化が求められて
おり、上記従来のパッケージにおいても半導体素子外周
部分のリードの引き回しがあるため、パッケージの小型
化に限界が見えてきた。However, resin-encapsulated semiconductor device packages are required to have higher integration, higher functionality, more pins, thinner, and smaller. Even in a conventional package, there is a limit to miniaturization of the package because there is a routing of a lead in an outer peripheral portion of the semiconductor element.
【0005】また、TSOP等の小型パッケージにおい
ては、リードの引き回し、ピンピッチの点で、多ピン化
に対しても限界が見えてきた。[0005] In a small package such as a TSOP or the like, there is a limit to increasing the number of pins in terms of lead routing and pin pitch.
【0006】本発明は、上記のような事情に鑑みてなさ
れたものであり、半導体素子の占有率が高く小型化が可
能で、回路基板への実装密度を向上させることができ、
さらに、多ピン化への対応が可能な樹脂封止型の半導体
装置と、この半導体装置に用いられる回路部材、およ
び、これら回路部材と半導体装置の製造方法を提供する
ことを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a high occupancy rate of a semiconductor element, can be reduced in size, and can improve a mounting density on a circuit board.
It is still another object of the present invention to provide a resin-sealed semiconductor device capable of coping with an increase in the number of pins, a circuit member used in the semiconductor device, and a method of manufacturing the circuit member and the semiconductor device.
【0007】[0007]
【課題を解決するための手段】このような目的を達成す
るために、本発明の半導体装置は、表面側に内部端子を
裏面側に外部端子を表裏一体的に有し内部端子面が略一
平面上に位置するように電気的に独立して配設された複
数の端子部と、前記端子部の内部端子側へ突出して内部
端子面に対し表面側が段差をなすように設けられたダイ
パッド部と、該ダイパッド部の裏面に回路形成面側が電
気的に絶縁して固着された半導体素子と、各端子部の内
部端子と半導体素子の端子とを電気的に接続するボンデ
ィングワイヤと、各端子部の外部端子の一部を外部に露
出させるように前記端子部、ダイパッド部、半導体素子
およびボンディングワイヤを封止する封止部材と、を備
えるような構成とした。In order to achieve the above object, a semiconductor device according to the present invention has an internal terminal on the front side and an external terminal on the back side integrated with the front and back sides, and the internal terminal surface is substantially one. A plurality of terminal portions that are electrically independently disposed so as to be located on a plane, and a die pad portion that is provided so as to protrude toward the internal terminal of the terminal portion so that a surface side of the terminal portion forms a step with respect to the internal terminal surface. A semiconductor element fixed on the back surface of the die pad portion on the circuit forming surface side while being electrically insulated, a bonding wire for electrically connecting an internal terminal of each terminal portion and a terminal of the semiconductor element, And a sealing member for sealing the terminal portion, the die pad portion, the semiconductor element, and the bonding wire so that a part of the external terminal is exposed to the outside.
【0008】また、本発明の半導体装置は、前記ダイパ
ッドの表面側の少なくとも一部が外部に露出しているよ
うな構成とした。Further, the semiconductor device of the present invention is configured such that at least a part of the surface side of the die pad is exposed to the outside.
【0009】さらに、本発明の半導体装置は、外部に露
出している外部端子に半田からなる外部電極を設けたよ
うな構成とした。Further, the semiconductor device of the present invention has a configuration in which external electrodes made of solder are provided on external terminals exposed to the outside.
【0010】本発明の回路部材は、外枠部材と、該外枠
部材から各々接続リードを介して相互に独立して配設さ
れた複数の端子部と、前記外枠部材から接続リードを介
して配設されたダイパッド部とを備え、各端子部は表面
側に内部端子を裏面側に外部端子を表裏一体的に有する
とともに、各端子部の内部端子面は略一平面上に位置
し、前記ダイパッド部は前記内部端子面側へ突出してそ
の表面側が前記内部端子面に対して段差をなす位置にあ
るような構成とした。A circuit member according to the present invention comprises an outer frame member, a plurality of terminals arranged independently from the outer frame member via connection leads, and a plurality of terminal portions provided from the outer frame member via connection leads. And a die pad portion arranged on the front side, each terminal portion integrally has an internal terminal on the front side and an external terminal on the back side, and the internal terminal surface of each terminal portion is located on substantially one plane, The die pad portion is configured to protrude toward the internal terminal surface side so that its surface side is at a position where a step is formed with respect to the internal terminal surface.
【0011】また、本発明の回路部材は、前記ダイパッ
ド部の裏面側に電気絶縁性の両面接着テープが設けられ
ているような構成とした。Further, the circuit member of the present invention is configured such that an electrically insulating double-sided adhesive tape is provided on the back side of the die pad portion.
【0012】本発明の回路部材の製造方法は、導電性基
板をエッチングして、表面側に内部端子を裏面側に外部
端子を表裏一体的に有する複数の端子部と、ダイパッド
部と、各端子部が相互に独立して接続リードを介して一
体的に連結され、かつ、前記ダイパッド部が接続リード
を介して一体的に連結された外枠部材とを備えた回路部
材用パターンを作成した後、該回路部材用パターンのダ
イパッド部を端子部の内部端子面側へ突出させ、ダイパ
ッド部の表面側が内部端子面に対して段差をなす位置に
加工するような構成とした。According to the method of manufacturing a circuit member of the present invention, a plurality of terminal portions having an internal terminal on the front side and external terminals on the back side integrally, a die pad portion, and a plurality of terminal portions are formed by etching the conductive substrate. After forming a circuit member pattern comprising an outer frame member wherein the parts are integrally connected to each other independently via connection leads, and the die pad part is integrally connected via the connection leads. The configuration is such that the die pad portion of the circuit member pattern protrudes toward the internal terminal surface of the terminal portion, and the die pad portion is processed at a position where the surface side of the die pad portion forms a step with respect to the internal terminal surface.
【0013】また、本発明の回路部材の製造方法は、さ
らに、ダイパッド部の裏面側に電気絶縁性の両面接着テ
ープを貼り付けるような構成とした。Further, the method of manufacturing a circuit member according to the present invention is configured such that an electrically insulating double-sided adhesive tape is attached to the back side of the die pad portion.
【0014】本発明の半導体装置の製造方法は、上記の
製造方法により製造した回路部材のダイパッド部の裏面
側に半導体素子の回路形成面側を電気的に絶縁して固着
することにより搭載する半導体素子搭載工程と、回路部
材の内部端子と半導体素子の端子とをボンディングワイ
ヤで電気的に接続するワイヤボンディング工程と、外部
端子の一部を外部に露出させ、前記端子部、ダイパッド
部、半導体素子およびボンディングワイヤを樹脂材料で
封止する封止工程と、回路部材の各接続リードを切断
し、外枠部材を除去する外枠部材分離除去工程と、を備
えるような構成とした。According to a method of manufacturing a semiconductor device of the present invention, a semiconductor mounted on a circuit member manufactured by the above manufacturing method by electrically insulating and fixing a circuit forming surface side of a semiconductor element to a back surface side of a die pad portion. An element mounting step, a wire bonding step of electrically connecting an internal terminal of the circuit member and a terminal of the semiconductor element with a bonding wire, and exposing a part of the external terminal to the outside, the terminal section, the die pad section, and the semiconductor element. And a sealing step of sealing the bonding wire with a resin material, and an outer frame member separating and removing step of cutting each connection lead of the circuit member and removing the outer frame member.
【0015】このような本発明では、内部端子面とダイ
パッド部の表面側との間の段差により、ダイパッド部裏
面側に回路形成面が固着された半導体素子の端子と内部
端子とを電気的に接続するボンディングワイヤのループ
高さの許容が大きくなり、また、上記ダイパッド部が半
導体素子の回路形成面で発生した熱の放熱板の作用をな
し、さらに、外部端子に半田電極を形成することによ
り、BGA(BallGrid Array)タイプの
半導体装置が可能となり取扱性、ショート防止性が向上
する。According to the present invention, the step between the internal terminal surface and the front surface of the die pad portion electrically connects the terminal of the semiconductor element having the circuit formation surface to the rear surface of the die pad portion and the internal terminal. The tolerance of the loop height of the bonding wire to be connected is increased, and the die pad portion acts as a heat radiating plate for heat generated on the circuit forming surface of the semiconductor element, and further, by forming a solder electrode on an external terminal. , BGA (Ball Grid Array) type semiconductor device becomes possible, and the handling property and the short prevention property are improved.
【0016】[0016]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0017】図1は本発明の回路部材の一実施形態を示
す平面図、図2は図1に示される回路部材のII−II線に
おける縦断面図である。図1および図2において、本発
明の回路部材1は、外枠部材2と、この外枠部材2から
接続リード3を介して相互に独立して配設された複数の
端子部4と、外枠部材2から接続リード8を介して配設
されたダイパッド部6とを備えるものである。FIG. 1 is a plan view showing an embodiment of the circuit member of the present invention, and FIG. 2 is a longitudinal sectional view taken along the line II-II of the circuit member shown in FIG. 1 and 2, a circuit member 1 of the present invention includes an outer frame member 2, a plurality of terminal portions 4 arranged independently from each other via a connection lead 3 from the outer frame member 2, And a die pad portion 6 provided from the frame member 2 via connection leads 8.
【0018】外枠部材2は、外形形状および内側開口形
状が矩形であり、各接続リード3は外枠部材2の内側開
口の各辺から同一平面内に突設されている。The outer frame member 2 has a rectangular outer shape and an inner opening shape, and each connection lead 3 projects from each side of the inner opening of the outer frame member 2 in the same plane.
【0019】端子部4は、接続リード3の先端に設けら
れ、表面側に内部端子4Aを裏面側に外部端子4Bを表
裏一体的に有している。図示例では、内部端子4A上に
銀めっき層5が設けられており、各内部端子4A面は同
一平面(図2に1点鎖線P1で示される面)上に位置し
ている。The terminal portion 4 is provided at the tip of the connection lead 3, and has an internal terminal 4A on the front side and an external terminal 4B on the rear side integrally. In the illustrated example, the silver plating layer 5 is provided on the internal terminals 4A, and the surfaces of the internal terminals 4A are located on the same plane (the surface indicated by a chain line P1 in FIG. 2).
【0020】ダイパッド部6は、外枠部材2の内側開口
の各隅部から延設された4本の接続リード8に支持され
ている。そして、このダイパッド部6は内部端子4A面
側(図2において上方向)へ突出しており、ダイパッド
部6の表面側6aのなす面(図2に1点鎖線P2で示さ
れる面)が内部端子4A面に対して段差Gをなすように
構成されている。この段差Gの大きさは、例えば、10
0〜500μm程度の範囲内で設定することができる。The die pad 6 is supported by four connection leads 8 extending from each corner of the inner opening of the outer frame member 2. The die pad 6 protrudes toward the surface of the internal terminal 4A (upward in FIG. 2), and the surface formed by the front side 6a of the die pad 6 (the surface indicated by the one-dot chain line P2 in FIG. 2) is the internal terminal. It is configured to form a step G with respect to the 4A surface. The size of the step G is, for example, 10
It can be set within a range of about 0 to 500 μm.
【0021】このような回路部材1の材質は、42合金
(Ni42%のFe合金)、銅、銅合金等とすることが
できる。The material of the circuit member 1 can be 42 alloy (Ni 42% Fe alloy), copper, copper alloy or the like.
【0022】また、本発明の回路部材は、図3に示され
るように、ダイパッド部6の裏面側6bに電気絶縁性の
両面接着テープ7を設けた回路部材1´であってもよ
い。両面接着テープ7は、電気絶縁性のベースフィルム
の両面に接着剤層を備えたもの、例えば、ユーピレック
ス(宇部興産(株)製の電気絶縁性のベースフィルム)
の両面にRXF((株)巴川製紙所製の接着剤)層を備
えたUX1W((株)巴川製紙所製)のような両面接着
テープを使用することができる。As shown in FIG. 3, the circuit member of the present invention may be a circuit member 1 'in which an electrically insulating double-sided adhesive tape 7 is provided on the back surface 6b of the die pad portion 6. The double-sided adhesive tape 7 is provided with an adhesive layer on both sides of an electrically insulating base film, for example, Upilex (an electrically insulating base film manufactured by Ube Industries, Ltd.).
A double-sided adhesive tape such as UX1W (manufactured by Hamakawa Paper Mills) having RXF (adhesive manufactured by Hamakawa Paper Mills) layers on both sides can be used.
【0023】図4は図1に示される本発明の回路部材を
使用した本発明の半導体装置の一実施形態を示す平面
図、図5は図4に示される半導体装置のV−V線におけ
る縦断面図である。図4および図5において、本発明の
半導体装置11は、ダイパッド部6の裏面側6bに、電
気絶縁性の両面接着テープ7を用いて半導体素子12が
固着されており、半導体素子12の回路形成面がダイパ
ッド部6の裏面側6bに対向している。この半導体素子
12の各端子12aは、端子部4の内部端子4A(銀め
っき層5)にボンディングワイヤ14によって接続され
ている。FIG. 4 is a plan view showing one embodiment of the semiconductor device of the present invention using the circuit member of the present invention shown in FIG. 1, and FIG. 5 is a longitudinal section of the semiconductor device shown in FIG. FIG. 4 and 5, in a semiconductor device 11 of the present invention, a semiconductor element 12 is fixed to a rear surface 6b of a die pad portion 6 by using an electrically insulating double-sided adhesive tape 7, and a circuit formation of the semiconductor element 12 is performed. The surface faces the back surface 6b of the die pad portion 6. Each terminal 12 a of the semiconductor element 12 is connected to an internal terminal 4 A (silver plating layer 5) of the terminal section 4 by a bonding wire 14.
【0024】そして、外部端子4Bの一部を外部に露出
させるように端子部4、ダイパッド部6、半導体素子1
2およびボンディングワイヤ14が封止部材16により
封止されている。封止部材16は、封止型半導体装置に
使用されている公知の樹脂材料を用いて形成することが
できる。図示例では、外部に露出している外部端子4B
に、半田からなる外部電極18が設けられている。これ
により、BGA(Ball Grid Array)タ
イプの半導体装置となっている。Then, the terminal portion 4, the die pad portion 6, and the semiconductor element 1 are so exposed as to expose a part of the external terminal 4B to the outside.
2 and the bonding wire 14 are sealed by a sealing member 16. The sealing member 16 can be formed using a known resin material used for a sealing type semiconductor device. In the illustrated example, the external terminals 4B exposed to the outside
Is provided with an external electrode 18 made of solder. Thus, a BGA (Ball Grid Array) type semiconductor device is obtained.
【0025】尚、半導体装置11の構成を理解しやすく
するために、図4では封止部材16を省略し、図5では
封止部材16を仮想線(2点鎖線)で示している。For easy understanding of the configuration of the semiconductor device 11, the sealing member 16 is omitted in FIG. 4, and the sealing member 16 is shown by a virtual line (two-dot chain line) in FIG.
【0026】このような半導体装置11では、ダイパッ
ド部6が半導体素子12の放熱板の作用をなす。すなわ
ち、半田からなる外部電極18を介して半導体装置11
を回路基板に実装した状態で、半導体素子12の回路形
成面で発生した熱は熱伝導率の高いダイパッド部6へ伝
わり、半導体装置11の上部に流れる冷却風により効率
よく除去されるので、半導体装置11は放熱性が極めて
良好なものとなる。また、本発明では、半導体装置の放
熱性をより向上させるため、図6に示されるように、ダ
イパッド部6の表面側6aが外部に露出するように封止
部材16を設けてもよい。In such a semiconductor device 11, the die pad portion 6 functions as a heat sink of the semiconductor element 12. That is, the semiconductor device 11 is connected via the external electrodes 18 made of solder.
Is mounted on the circuit board, the heat generated on the circuit forming surface of the semiconductor element 12 is transmitted to the die pad portion 6 having high thermal conductivity, and is efficiently removed by the cooling air flowing over the semiconductor device 11. The device 11 has extremely good heat dissipation. In the present invention, in order to further improve the heat dissipation of the semiconductor device, as shown in FIG. 6, a sealing member 16 may be provided so that the front side 6a of the die pad portion 6 is exposed to the outside.
【0027】また、本発明の半導体装置11は、内部端
子4A面(図5に1点鎖線P1で示される面)とダイパ
ッド部6の表面側6a(図5に1点鎖線P2で示される
面)との間の段差Gにより、ダイパッド部6の裏面側6
bに固着された半導体素子12の回路形成面が、端子部
4の内部端子4A面と略同一面となるので、半導体素子
12の端子と内部端子4Aとを電気的に接続するボンデ
ィングワイヤ14のループ高さの許容が大きいものとな
る。In the semiconductor device 11 of the present invention, the surface of the internal terminal 4A (the surface indicated by a dashed line P1 in FIG. 5) and the front side 6a of the die pad portion 6 (the surface indicated by the dashed line P2 in FIG. 5). ), The back side 6 of the die pad portion 6 is formed.
Since the circuit formation surface of the semiconductor element 12 fixed to the terminal b is substantially the same as the internal terminal 4A surface of the terminal portion 4, the bonding wire 14 for electrically connecting the terminal of the semiconductor element 12 and the internal terminal 4A is formed. The tolerance of the loop height is large.
【0028】尚、上述の回路部材1および半導体装置1
1における端子数、端子配列等は例示であり、本発明の
回路部材および半導体装置がこれに限定されないことは
勿論である。The above-described circuit member 1 and semiconductor device 1
The number of terminals, terminal arrangement, and the like in 1 are merely examples, and the circuit member and the semiconductor device of the present invention are not limited thereto.
【0029】次に、本発明の回路部材の製造方法につい
て説明する。Next, a method of manufacturing a circuit member according to the present invention will be described.
【0030】図7は、図1および図2に示される本発明
の回路部材1を例とした本発明の回路部材の製造方法の
一実施形態を示す工程図である。各工程は、上記の図2
に対応する回路部材の縦断面図で示してある。FIG. 7 is a process chart showing an embodiment of a method for manufacturing a circuit member of the present invention using the circuit member 1 of the present invention shown in FIGS. 1 and 2 as an example. Each step is described in FIG.
Is shown in a longitudinal sectional view of a circuit member corresponding to FIG.
【0031】図7において、まず、導電性基板21の表
裏に感光性レジストを塗布、乾燥し、これを所望のフォ
トマスクを介して露光した後、現像してレジストパター
ン22A,22Bを形成する(図7(A))。導電性基
板21としては、上述のように42合金(Ni42%の
Fe合金)、銅、銅合金等の金属基板(厚み100〜2
50μm)を使用することができ、この導電性基板21
は、両面を脱脂等を行い洗浄処理を施したものを使用す
ることが好ましい。また、感光性レジストとしては、従
来公知のものを使用することができる。In FIG. 7, first, a photosensitive resist is applied to the front and back surfaces of the conductive substrate 21, dried, exposed through a desired photomask, and developed to form resist patterns 22A and 22B (FIG. 7). (FIG. 7 (A)). As described above, the conductive substrate 21 is made of a metal substrate (thickness of 100 to 2) made of 42 alloy (Ni 42% Fe alloy), copper, copper alloy, or the like.
50 μm) can be used.
It is preferable to use a material which has been subjected to a cleaning treatment after degreasing both surfaces. Further, as the photosensitive resist, conventionally known ones can be used.
【0032】次に、レジストパターン22A,22Bを
耐腐蝕膜として導電性基板21に腐蝕液でエッチングを
行う(図7(B))。腐蝕液は、通常、塩化第二鉄水溶
液を使用し、導電性基板21の両面からスプレーエッチ
ングにて行う。Next, the conductive substrate 21 is etched with a corrosion liquid using the resist patterns 22A and 22B as a corrosion-resistant film (FIG. 7B). The etchant is usually an aqueous solution of ferric chloride, and is spray-etched from both sides of the conductive substrate 21.
【0033】次いで、レジストパターン22A,22B
を剥離して除去することにより、端子部4とダイパッド
部6がそれぞれ接続リード3と接続リード8(図示せ
ず)により外枠部材2に一体的に連結された回路部材用
パターンが得られる(図7(C))。この回路部材用パ
ターンでは、図から明らかなように、内部端子4A面と
ダイパッド部6の表面側6aとは、同一平面内にある。Next, resist patterns 22A and 22B
By peeling off and removing, a circuit member pattern is obtained in which the terminal portion 4 and the die pad portion 6 are integrally connected to the outer frame member 2 by the connection leads 3 and the connection leads 8 (not shown), respectively. (FIG. 7 (C)). In this circuit member pattern, the surface of the internal terminal 4A and the surface side 6a of the die pad portion 6 are in the same plane, as is apparent from the drawing.
【0034】次に、端子部4の内部端子4Aの位置に銀
めっき層5を形成した後、所定の金型でダイパッド部6
を内部端子4A側へ突出させ、ダイパッド部6の表面側
6aと内部端子4A面との間に段差を形成する(図7
(D))。これにより、本発明の回路部材1が得られ
る。さらに、ダイパッド部6の裏面側6bに電気絶縁性
の両面接着テープ7を貼付することにより、回路部材1
´を得ることができる。Next, after the silver plating layer 5 is formed at the position of the internal terminal 4A of the terminal part 4, the die pad part 6 is formed with a predetermined die.
Protrudes toward the internal terminals 4A to form a step between the surface side 6a of the die pad portion 6 and the surface of the internal terminals 4A (FIG. 7).
(D)). Thereby, the circuit member 1 of the present invention is obtained. Further, by attaching an electrically insulating double-sided adhesive tape 7 to the back surface 6b of the die pad portion 6, the circuit member 1 is formed.
'Can be obtained.
【0035】次に、本発明の半導体装置の製造方法につ
いて説明する。Next, a method of manufacturing a semiconductor device according to the present invention will be described.
【0036】図8は、図4および図5に示される本発明
の半導体装置の製造方法の一実施形態を示す工程図であ
る。各工程は、上記の図5に対応する半導体装置の縦断
面図で示してある。FIG. 8 is a process chart showing one embodiment of a method of manufacturing the semiconductor device of the present invention shown in FIGS. 4 and 5. Each step is shown in a longitudinal sectional view of the semiconductor device corresponding to FIG. 5 described above.
【0037】図8において、まず、上述の本発明の製造
方法により製造した回路部材1´を用い、この回路部材
1´のダイパッド部6の裏面側6bに半導体素子12の
回路形成面側を電気絶縁性の両面接着テープ7を介して
固着することにより、半導体素子12を搭載する(図8
(A)半導体素子搭載工程)。In FIG. 8, first, the circuit member 1 'manufactured by the above-described manufacturing method of the present invention is used, and the circuit forming surface side of the semiconductor element 12 is electrically connected to the back surface 6b of the die pad portion 6 of the circuit member 1'. The semiconductor element 12 is mounted by being fixed via the insulating double-sided adhesive tape 7 (FIG. 8).
(A) Semiconductor element mounting step).
【0038】次に、搭載した半導体素子12の端子と、
回路部材の内部端子4Aの銀めっき層5とを、ボンディ
ングワイヤ14で電気的に接続する(図8(B)ワイヤ
ボンディング工程)。Next, the terminals of the mounted semiconductor element 12 are:
The silver plating layer 5 of the internal terminal 4A of the circuit member is electrically connected with the bonding wire 14 (FIG. 8 (B) wire bonding step).
【0039】次いで、外部端子4Bの一部を外部に露出
させるようにして、端子部4、ダイパッド部6、半導体
素子12およびボンディングワイヤ14を封止部材16
で封止する(図8(C)封止工程)。Next, the terminal part 4, the die pad part 6, the semiconductor element 12, and the bonding wire 14 are sealed with the sealing member 16 so that a part of the external terminal 4B is exposed to the outside.
(FIG. 8 (C) sealing step).
【0040】次に、回路部材1´の各接続リードを切断
し外枠部材2を除去して、本発明の半導体装置11とす
る(図8(D)外枠部材分離除去工程)。その後、外部
に露出している外部端子4Bに半田からなる外部電極1
8を形成する。Next, each connection lead of the circuit member 1 'is cut and the outer frame member 2 is removed to obtain a semiconductor device 11 of the present invention (FIG. 8 (D) outer frame member separation / removal step). Thereafter, the external electrodes 1 made of solder are connected to the external terminals 4B exposed to the outside.
8 is formed.
【0041】[0041]
【実施例】次に、具体的な実施例を挙げて本発明を更に
詳細に説明する。 (回路部材の作製)導電性基板として厚み0.15mm
の銅板(古河電気工業(株)製EFTEC64T−1/
2H)を準備し、脱脂処理、洗浄処理を行った後、この
銅板の両面に紫外線硬化型レジスト(東京応化工業
(株)製OFPR1305)を掛け流し法により塗布し
て乾燥した。次いで、表面側および裏面側のレジスト層
をそれぞれ所定のフォトマスクを介して露光した後、現
像してレジストパターンを形成した。その後、銅板の両
面から塩化第二鉄水溶液を使用してスプレーエッチング
を行い、洗浄後、有機アルカリ溶液を用いてレジストパ
ターンを剥離除去した。Next, the present invention will be described in more detail with reference to specific examples. (Production of a circuit member) 0.15 mm thick as a conductive substrate
Copper plate (EFTEC64T-1 / Furukawa Electric Co., Ltd.)
2H) was prepared, subjected to a degreasing treatment and a washing treatment, and then coated with an ultraviolet-curable resist (OFPR1305 manufactured by Tokyo Ohka Kogyo Co., Ltd.) on both surfaces of the copper plate by a flowing method and dried. Next, the resist layers on the front side and the back side were respectively exposed through a predetermined photomask, and then developed to form a resist pattern. Thereafter, spray etching was performed on both surfaces of the copper plate using an aqueous ferric chloride solution, and after cleaning, the resist pattern was peeled off using an organic alkali solution.
【0042】次に、内部端子面に銀めっき層(厚み約5
μm)を形成した後、所定の金型でダイパッド部を内部
端子面側へ突出させた。これにより、ダイパッド部の表
面側と内部端子の銀めっき層との間に約250μmの段
差を形成した。その後、このダイパッド部の裏面側に電
気絶縁性の両面接着テープ(巴川製紙所(株)製UH1
W)を貼り付けて回路部材とした。 (半導体装置の作製)上記の回路部材のダイパッド部裏
面側の両面接着テープに半導体素子(厚み約0.25m
m)の回路形成面側を圧着して加熱(140℃)するこ
とにより固着して半導体素子を搭載した。次いで、回路
部材の内部端子上の銀めっき層と搭載した半導体素子の
端子とを金線により結線し、その後、外部端子の一部を
外部に露出させるようにして、端子部、ダイパッド部、
半導体素子および金線を樹脂材料(日東電工(株)製M
P−7400)で封止した。Next, a silver plating layer (having a thickness of about 5
μm), the die pad portion was made to protrude toward the internal terminal surface with a predetermined mold. As a result, a step of about 250 μm was formed between the surface side of the die pad portion and the silver plating layer of the internal terminal. Then, the electrically insulating double-sided adhesive tape (UH1 manufactured by Tomagawa Paper Mill Co., Ltd.)
W) was attached to form a circuit member. (Fabrication of semiconductor device) A semiconductor element (about 0.25 m thick) was placed on the double-sided adhesive tape on the back side of the die pad portion of the circuit member.
The semiconductor element was mounted on the circuit formation surface side of m) by pressing and heating (140 ° C.). Next, the silver plating layer on the internal terminal of the circuit member and the terminal of the mounted semiconductor element are connected by a gold wire, and thereafter, a part of the external terminal is exposed to the outside, a terminal part, a die pad part,
The semiconductor element and the gold wire are made of a resin material (Nitto Denko Corporation M
P-7400).
【0043】次に、回路部材の各接続リードを切断して
外枠部材を除去し、外部に露出している外部端子に半田
からなるボールを接着して外部電極を形成した。Next, each connection lead of the circuit member was cut to remove the outer frame member, and a ball made of solder was bonded to an external terminal exposed outside to form an external electrode.
【0044】このようにして作製した半導体装置は外部
端子数が80ピンであり、その外形寸法は10mm四方
と小型であり、かつ、厚みが0.8mmであり非常に薄
いものであった。The semiconductor device manufactured in this way had 80 external terminals, and its external dimensions were as small as 10 mm square, and the thickness was 0.8 mm, which was very thin.
【0045】[0045]
【発明の効果】以上詳述したように、本発明によれば半
導体素子の占有率が高くなり小型化が可能となって回路
基板への実装密度を向上させることができ、また、ダイ
パッド部が半導体素子の回路形成面で発生する熱の放熱
板の作用をなすので、外部端子側にて半導体装置を回路
基板に実装した状態での半導体装置の放熱性が極めて良
好であり、さらに、内部端子面とダイパッド部の表面側
との間の段差により、ダイパッド部裏面側に回路形成面
が固着された半導体素子の端子と内部端子とを電気的に
接続するボンディングワイヤのループ高さの許容が大き
くなり、また、外部端子に半田電極を形成することによ
り、BGA(Ball Grid Array)タイプ
の半導体装置が可能となり、実装作業性、ショート防止
性が向上するとともにさらに、多ピン化への対応が可能
となり、本発明の回路部材を使用することにより、上記
のような効果を奏する半導体装置を容易に作製すること
ができ、このような本発明の回路部材および半導体装置
は、本発明の製造方法により簡便に製造することができ
る。As described above in detail, according to the present invention, the occupancy of the semiconductor element is increased, the size of the semiconductor element can be reduced, the mounting density on the circuit board can be improved, and the die pad portion can be formed. Since it acts as a heat radiating plate for heat generated on the circuit forming surface of the semiconductor element, the heat dissipation of the semiconductor device when the semiconductor device is mounted on the circuit board on the external terminal side is extremely good. Due to the step between the surface and the front side of the die pad portion, the tolerance of the loop height of the bonding wire for electrically connecting the terminal of the semiconductor element having the circuit forming surface fixed to the rear side of the die pad portion and the internal terminal is large. Also, by forming a solder electrode on an external terminal, a BGA (Ball Grid Array) type semiconductor device becomes possible, and the mounting workability and short-circuit prevention property are improved. Further, it is possible to cope with the increase in the number of pins, and by using the circuit member of the present invention, a semiconductor device having the above-described effects can be easily manufactured. A semiconductor device can be easily manufactured by the manufacturing method of the present invention.
【図1】本発明の回路部材の一実施形態を示す平面図で
ある。FIG. 1 is a plan view showing one embodiment of a circuit member of the present invention.
【図2】図1に示される回路部材のII−II線における縦
断面図である。FIG. 2 is a vertical sectional view of the circuit member shown in FIG. 1 taken along the line II-II.
【図3】本発明の回路部材の他の実施形態を示す縦断面
図である。FIG. 3 is a longitudinal sectional view showing another embodiment of the circuit member of the present invention.
【図4】図1に示される本発明の回路部材を使用した本
発明の半導体装置の一実施形態を示す平面図である。FIG. 4 is a plan view showing one embodiment of a semiconductor device of the present invention using the circuit member of the present invention shown in FIG. 1;
【図5】図4に示される半導体装置のV−V線における
縦断面図である。5 is a vertical sectional view of the semiconductor device shown in FIG. 4, taken along line VV.
【図6】本発明の半導体装置の他の実施形態を示す縦断
面図である。FIG. 6 is a longitudinal sectional view showing another embodiment of the semiconductor device of the present invention.
【図7】本発明の回路部材の製造方法の一実施形態を示
す工程図である。FIG. 7 is a process chart showing one embodiment of a method for manufacturing a circuit member of the present invention.
【図8】本発明の半導体装置の製造方法の一実施形態を
示す工程図である。FIG. 8 is a process chart showing one embodiment of a method for manufacturing a semiconductor device of the present invention.
1,1´…回路部材 2…外枠部材 3…接続リード 4…端子部 4A…内部端子 4B…外部端子 6…ダイパッド部 7…電気絶縁性の両面接着テープ 8…接続リード 11…半導体装置 12…半導体素子 14…ボンディングワイヤ 16…封止部材 18…半田外部電極 21…導電性基板 1, 1 '... circuit member 2 ... outer frame member 3 ... connection lead 4 ... terminal portion 4A ... internal terminal 4B ... external terminal 6 ... die pad portion 7 ... electrically insulating double-sided adhesive tape 8 ... connection lead 11 ... semiconductor device 12 ... semiconductor element 14 ... bonding wire 16 ... sealing member 18 ... solder external electrode 21 ... conductive substrate
Claims (8)
表裏一体的に有し内部端子面が略一平面上に位置するよ
うに電気的に独立して配設された複数の端子部と、前記
端子部の内部端子側へ突出して内部端子面に対し表面側
が段差をなすように設けられたダイパッド部と、該ダイ
パッド部の裏面に回路形成面側が電気的に絶縁して固着
された半導体素子と、各端子部の内部端子と半導体素子
の端子とを電気的に接続するボンディングワイヤと、各
端子部の外部端子の一部を外部に露出させるように前記
端子部、ダイパッド部、半導体素子およびボンディング
ワイヤを封止する封止部材と、を備えることを特徴とす
る半導体装置。1. A plurality of terminal portions having an internal terminal on a front surface side and an external terminal on a back surface integrated front and back, and electrically disposed independently so that the internal terminal surface is located on substantially one plane. And a die pad portion protruding toward the internal terminal of the terminal portion and provided such that the surface side forms a step with respect to the internal terminal surface, and the circuit forming surface side is electrically insulated and fixed to the back surface of the die pad portion. A semiconductor element, a bonding wire for electrically connecting an internal terminal of each terminal section and a terminal of the semiconductor element, and the terminal section, the die pad section, and the semiconductor so as to expose a part of an external terminal of each terminal section to the outside. A semiconductor device comprising: a sealing member for sealing an element and a bonding wire.
一部が外部に露出していることを特徴とする請求項1に
記載の半導体装置。2. The semiconductor device according to claim 1, wherein at least a part of the surface of the die pad portion is exposed to the outside.
なる外部電極を設けたことを特徴とする請求項1または
請求項2に記載の半導体装置。3. The semiconductor device according to claim 1, wherein an external electrode made of solder is provided on the external terminal exposed to the outside.
ードを介して相互に独立して配設された複数の端子部
と、前記外枠部材から接続リードを介して配設されたダ
イパッド部とを備え、各端子部は表面側に内部端子を裏
面側に外部端子を表裏一体的に有するとともに、各端子
部の内部端子面は略一平面上に位置し、前記ダイパッド
部は前記内部端子面側へ突出してその表面側が前記内部
端子面に対して段差をなす位置にあることを特徴とする
回路部材。4. An outer frame member, a plurality of terminal portions arranged independently from each other via connection leads from the outer frame member, and a plurality of terminal portions provided from the outer frame member via connection leads. A die pad portion, each terminal portion has an internal terminal on the front surface side and an external terminal on the back surface integrally front and back, and the internal terminal surface of each terminal portion is located on substantially one plane, and the die pad portion is A circuit member protruding toward an internal terminal surface, the surface of which is located at a position forming a step with respect to the internal terminal surface.
の両面接着テープが設けられていることを特徴とする請
求項4に記載の回路部材。5. The circuit member according to claim 4, wherein an electrically insulating double-sided adhesive tape is provided on a back surface side of the die pad portion.
内部端子を裏面側に外部端子を表裏一体的に有する複数
の端子部と、ダイパッド部と、各端子部が相互に独立し
て接続リードを介して一体的に連結され、かつ、前記ダ
イパッド部が接続リードを介して一体的に連結された外
枠部材とを備えた回路部材用パターンを作成した後、該
回路部材用パターンのダイパッド部を端子部の内部端子
面側へ突出させ、ダイパッド部の表面側が内部端子面に
対して段差をなす位置に加工することを特徴とする回路
部材の製造方法。6. A plurality of terminal portions having an internal terminal on the front side and external terminals on the back side integrally formed by etching the conductive substrate, a die pad portion, and each terminal portion are connected independently of each other. After forming a circuit member pattern including an outer frame member integrally connected via a lead and the die pad portion integrally connected via a connection lead, the die pad of the circuit member pattern is formed. A method of manufacturing a circuit member, comprising: projecting a portion toward an internal terminal surface side of a terminal portion;
縁性の両面接着テープを貼り付けることを特徴とする請
求項6に記載の回路部材の製造方法。7. The method according to claim 6, further comprising attaching an electrically insulating double-sided adhesive tape to the back surface of the die pad portion.
法により製造した回路部材のダイパッド部の裏面側に半
導体素子の回路形成面側を電気的に絶縁して固着するこ
とにより搭載する半導体素子搭載工程と、回路部材の内
部端子と半導体素子の端子とをボンディングワイヤで電
気的に接続するワイヤボンディング工程と、外部端子の
一部を外部に露出させ、前記端子部、ダイパッド部、半
導体素子およびボンディングワイヤを樹脂材料で封止す
る封止工程と、回路部材の各接続リードを切断し、外枠
部材を除去する外枠部材分離除去工程と、を備えること
を特徴とする半導体装置の製造方法。8. A semiconductor mounted on a back surface of a die pad portion of a circuit member manufactured by the manufacturing method according to claim 6 by electrically insulating and fixing a circuit forming surface side of a semiconductor element. An element mounting step, a wire bonding step of electrically connecting an internal terminal of the circuit member and a terminal of the semiconductor element with a bonding wire, and exposing a part of the external terminal to the outside, the terminal section, the die pad section, and the semiconductor element. Manufacturing a semiconductor device, comprising: a sealing step of sealing a bonding wire with a resin material; and an outer frame member separating and removing step of cutting each connection lead of a circuit member and removing an outer frame member. Method.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28799397A JP3699573B2 (en) | 1997-10-03 | 1997-10-03 | Semiconductor device, circuit member used therefor, and manufacturing method thereof |
US09/052,984 US6201292B1 (en) | 1997-04-02 | 1998-04-01 | Resin-sealed semiconductor device, circuit member used therefor |
KR1019980011659A KR100297464B1 (en) | 1997-04-02 | 1998-04-02 | A resin sealed semiconductor device, a circuit member usedthereto and a method for fabricating a resin sealedsemiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28799397A JP3699573B2 (en) | 1997-10-03 | 1997-10-03 | Semiconductor device, circuit member used therefor, and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11111749A true JPH11111749A (en) | 1999-04-23 |
JP3699573B2 JP3699573B2 (en) | 2005-09-28 |
Family
ID=17724421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28799397A Expired - Fee Related JP3699573B2 (en) | 1997-04-02 | 1997-10-03 | Semiconductor device, circuit member used therefor, and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3699573B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2002037563A3 (en) * | 2000-10-31 | 2003-04-17 | Motorola Inc | A leadframe and semiconductor package |
KR100864781B1 (en) * | 1999-06-30 | 2008-10-22 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device |
-
1997
- 1997-10-03 JP JP28799397A patent/JP3699573B2/en not_active Expired - Fee Related
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100864781B1 (en) * | 1999-06-30 | 2008-10-22 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device |
KR100878939B1 (en) * | 1999-06-30 | 2009-01-19 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device |
KR100885606B1 (en) * | 1999-06-30 | 2009-02-24 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device |
US7777312B2 (en) | 1999-06-30 | 2010-08-17 | Renesas Technology Corp. | Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device |
US7804159B2 (en) | 1999-06-30 | 2010-09-28 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device |
US7821119B2 (en) | 1999-06-30 | 2010-10-26 | Renesas Electronics Corporation | Semiconductor device |
US8115298B2 (en) | 1999-06-30 | 2012-02-14 | Renesas Electronics Corporation | Semiconductor device |
US8637965B2 (en) | 1999-06-30 | 2014-01-28 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device |
US8969138B2 (en) | 1999-06-30 | 2015-03-03 | Renesas Electronics Corporation | Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device |
US9484288B2 (en) | 1999-06-30 | 2016-11-01 | Renesas Technology Corporation | Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device |
WO2002037563A3 (en) * | 2000-10-31 | 2003-04-17 | Motorola Inc | A leadframe and semiconductor package |
Also Published As
Publication number | Publication date |
---|---|
JP3699573B2 (en) | 2005-09-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3947292B2 (en) | Manufacturing method of resin-encapsulated semiconductor device | |
KR100297464B1 (en) | A resin sealed semiconductor device, a circuit member usedthereto and a method for fabricating a resin sealedsemiconductor device | |
US6025640A (en) | Resin-sealed semiconductor device, circuit member for use therein and method of manufacturing resin-sealed semiconductor device | |
JPH08125066A (en) | Resin-sealed semiconductor device and lead frame used for it, and manufacture of resin-sealed semiconductor device | |
JP2006210807A (en) | Method for manufacturing semiconductor device | |
US6700198B2 (en) | Resin for semiconductor wire | |
JP3983930B2 (en) | Circuit member manufacturing method | |
JP2000091488A (en) | Resin-sealed semiconductor device and circuit member used therein | |
JPH09307043A (en) | Lead frame member and manufacture thereof, and semiconductor device using lead frame member | |
JPH10335566A (en) | Resin-sealed semiconductor device and circuit member used therein, and manufacture of resin-sealed semiconductor device | |
JP2000332162A (en) | Resin-sealed semiconductor device | |
JP2000299423A (en) | Lead frame, semiconductor device using the same and manufacture thereof | |
JP3529915B2 (en) | Lead frame member and method of manufacturing the same | |
JP3699573B2 (en) | Semiconductor device, circuit member used therefor, and manufacturing method thereof | |
JP3992877B2 (en) | Manufacturing method of resin-encapsulated semiconductor device | |
JP3884552B2 (en) | Semiconductor device, circuit member used therefor, and method for manufacturing semiconductor device | |
JPH09116045A (en) | Resin-sealed semiconductor device of bga type using lead frame and its manufacture | |
JP3576228B2 (en) | Surface mount type semiconductor device | |
JPH1041432A (en) | Lead frame member and surface mount semiconductor device | |
JP4068729B2 (en) | Resin-sealed semiconductor device and circuit member used therefor | |
JP4176092B2 (en) | Resin-sealed semiconductor device and manufacturing method thereof | |
JPH1174411A (en) | Resin-sealed semiconductor device and circuit used in device thereof | |
JPH08139259A (en) | Lead frame and lead frame member, and surface mount semiconductor device using them | |
JPH1056122A (en) | Surface mount semiconductor device, its manufacturing method and lead frame member used for the device | |
JPH10200010A (en) | Lead frame for surface-mount semiconductor device, and surface-mount semiconductor device using lead frame |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040928 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050629 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20050705 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20050708 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090715 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090715 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100715 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100715 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110715 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120715 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120715 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130715 Year of fee payment: 8 |
|
LAPS | Cancellation because of no payment of annual fees |