JPS629639A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS629639A
JPS629639A JP60148864A JP14886485A JPS629639A JP S629639 A JPS629639 A JP S629639A JP 60148864 A JP60148864 A JP 60148864A JP 14886485 A JP14886485 A JP 14886485A JP S629639 A JPS629639 A JP S629639A
Authority
JP
Japan
Prior art keywords
printed wiring
sealed
isolated
resin
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60148864A
Other languages
Japanese (ja)
Inventor
Tsuneo Kamata
鹿俣　常郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP60148864A priority Critical patent/JPS629639A/en
Publication of JPS629639A publication Critical patent/JPS629639A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce the irregularity in shape and size of the titled semiconductor device by a method wherein a semiconductor pellet is mounted on the printed wiring substrate on which the patterning corresponded to an element structure is provided in advance, and after the surface of the element is sealed with resin, the sealed printed wiring substrate is cut and isolated. CONSTITUTION:A semiconductor pellet 3 is mounted and fixed on a printed wiring substrate 1 using solder 2, and a wiring is performed thereon using a bonding wire 4. Then, the surface of an element is sealed by resin 5, and lastly, the element is isolated by cutting and a finished article is obtained. The substrate can be isolated without damaging the coupling with the contact to be used for mounting on the back side by cutting the center part of a through hole accurately. As a result, a small-sized leadless chip carrier element of high working accuracy and excellent quality can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法ＫｌｆＪｌし、特に小
型トランジスタ、ダイオード、小屋ＩＣのチップ部品を
信頼度高くかつ安価に提供するものであるＯ 〔従来の技術〕 従来、この種の半導体チップ部品は、バンチングされた
リードフレームに半導体ペレットを搭載・結線を行った
のち、リード形状の加工を行いチップ形状にするものや
、セラミック部品に半導体ペレットを搭載・結線し樹脂
封止するものがある。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a method for manufacturing semiconductor devices, particularly for providing chip components for small transistors, diodes, and ICs with high reliability and at low cost. [Conventional technology] Conventionally, this type of semiconductor chip component has been produced by mounting semiconductor pellets on a bunched lead frame and connecting them, and then processing the leads into a chip shape, or by mounting semiconductor pellets on a ceramic component. There are some that are equipped with, wired and sealed with resin.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の製法に基づくものは、前者の例では封止後にリー
ド加工を行うために耐湿性等の面で劣化が見られる外、
形状寸法のバラツキが大きいという欠点があシ、実装工
程でのトラブルの要因となっている。In the case of products based on conventional manufacturing methods, lead processing is performed after sealing in the former example, which causes deterioration in terms of moisture resistance, etc.
The drawback is that there is large variation in shape and dimensions, which causes trouble during the mounting process.

又、後者の例では、材料が高価である事の外に材料基板
の寸法バラツキ、封止寸法バラツキが大きいという欠点
があシ、やはシ実装工程でのトラプぞの要因となってい
る。In addition, in the latter example, in addition to the expensive materials, there are large variations in the dimensions of the material substrate and the sealing dimensions, which is a cause for failure in the mounting process.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、あらかじめ素子構造に合致したパターンニン
グを施したプリント配線基板に半導体ペレットを搭載し
、必要な内部結線を行い、その後素子面を樹脂で封止し
、しかる後封止済プリント配線基板を切断分離し、個々
の半導体素子に分離するものである。この時、素子の電
気特性の測定やマーキング等の工程は切断・分離の前後
いずれでもよく、素子構造やプロセスの最適化により最
もやシやすい工程で行えはよい。In the present invention, semiconductor pellets are mounted on a printed wiring board that has been patterned in advance to match the element structure, the necessary internal connections are made, the element surface is then sealed with resin, and then the sealed printed wiring board This is to cut and separate the semiconductor elements into individual semiconductor elements. At this time, processes such as measuring the electrical characteristics of the element and marking may be performed either before or after cutting/separation, and can be performed in the most convenient process by optimizing the element structure and process.

〔実施例〕〔Example〕

次に１本発明について図面を参照して説明する。 Next, one embodiment of the present invention will be explained with reference to the drawings.

第１図は完成した装置の側面及び断面を表わしている。FIG. 1 shows a side view and cross-section of the completed device.

第２図（５）は本装置の組立に用いるプリント配線基板
の側断面図、同図（均はこのプリント配線基板の平面部
分図である。以降図面に従い組立工程を説明する。FIG. 2(5) is a side cross-sectional view of a printed wiring board used for assembling this device, and the figure (the figure is a partial plan view of this printed wiring board). Hereinafter, the assembly process will be explained with reference to the drawings.

プリント配線基板１に半導体ペレット３をソルダー２で
取シつけ固定し、ボンディングワイヤー４で結線する。A semiconductor pellet 3 is attached and fixed to a printed wiring board 1 with a solder 2, and connected with a bonding wire 4.

この様子を第３図に示す。次に、素子面を樹脂５で封止
する。封止は全面でも部分的に行ってもよい。第４図に
これを示す。最後に素子を切断分離し完成品となる。こ
の様子を第５図に示す。切断はスルーホールの中央部を
正確に行う事により、裏面の実装用コンタクトとの連結
を損うことなく分離出来る。This situation is shown in FIG. Next, the element surface is sealed with resin 5. Sealing may be performed entirely or partially. This is shown in Figure 4. Finally, the elements are cut and separated to form a finished product. This situation is shown in FIG. By cutting accurately in the center of the through hole, it can be separated without damaging the connection with the mounting contact on the back side.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明によれば加工精度が高く品質
のよい、小型リードレスチップキャリア素子が得られる
。外形は従来のリード加工によるチップキャリアに比較
し３０〜５０チ小型化する事ができ、今後の小型化志向
にも十分対応できる。As explained above, according to the present invention, a small leadless chip carrier element with high processing accuracy and good quality can be obtained. The external size can be reduced by 30 to 50 inches compared to the conventional lead-processed chip carrier, and can fully accommodate future miniaturization trends.

素子は小型のダイオードやトランジスタから、大形のＬ
ＴＩ素子まで広く適用出来、その効果は測シ知れない。Elements range from small diodes and transistors to large L
It can be widely applied to TI elements, and its effects are immeasurable.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例による半導体装置の部分断面
を示した側面図である。 第２図（〜および第２回出）はそれぞれプリント配線基
板の断面および平面図である。 第３図はプリント配線基板に半導体ペレットを搭載し外
部端子と結線した様子を表わしている側面図である。 第４図は半導体素子面を保護用樹脂で封止した様子を表
わす断面図である。 第５図は樹脂封止後の基板を切断分離し、個々の装置と
して完成した様子を示している断面図である。 １・・・・・・プリント配線基板、２・・・・・・マウ
ントソルダー、３・・・・・・半導体ペレット、４・・
・・・・ボンディングワイヤー、５・・−・・・封止樹
脂。 代理人　弁理士　　内　原　　　晋、。 ＼１．−FIG. 1 is a side view showing a partial cross section of a semiconductor device according to an embodiment of the present invention. FIG. 2 (through and second appearance) are a cross-sectional view and a plan view of the printed wiring board, respectively. FIG. 3 is a side view showing a semiconductor pellet mounted on a printed wiring board and connected to external terminals. FIG. 4 is a cross-sectional view showing the semiconductor element surface sealed with a protective resin. FIG. 5 is a cross-sectional view showing the state in which the resin-sealed substrate is cut and separated to form individual devices. 1...Printed wiring board, 2...Mount solder, 3...Semiconductor pellet, 4...
... Bonding wire, 5 ... Sealing resin. Agent: Susumu Uchihara, patent attorney. \1. −

Claims (1)

【特許請求の範囲】[Claims] パターンニングされた配線を有するプリント配線基板に
半導体チップを搭載し、該半導体チップの電極と前記配
線との結線を行い、樹脂封止後これを切断分離すること
を特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device, which comprises mounting a semiconductor chip on a printed wiring board having patterned wiring, connecting electrodes of the semiconductor chip to the wiring, and cutting and separating the chips after resin sealing. .
JP60148864A 1985-07-05 1985-07-05 Manufacture of semiconductor device Pending JPS629639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60148864A JPS629639A (en) 1985-07-05 1985-07-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60148864A JPS629639A (en) 1985-07-05 1985-07-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS629639A true JPS629639A (en) 1987-01-17

Family

ID=15462441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60148864A Pending JPS629639A (en) 1985-07-05 1985-07-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS629639A (en)

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5950074A (en) * 1997-04-18 1999-09-07 Amkor Technology, Inc. Method of making an integrated circuit package
US5962810A (en) * 1997-09-09 1999-10-05 Amkor Technology, Inc. Integrated circuit package employing a transparent encapsulant
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
US6433277B1 (en) 1998-06-24 2002-08-13 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6448633B1 (en) 1998-11-20 2002-09-10 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6448635B1 (en) 1999-08-30 2002-09-10 Amkor Technology, Inc. Surface acoustical wave flip chip
US6469369B1 (en) 1999-06-30 2002-10-22 Amkor Technology, Inc. Leadframe having a mold inflow groove and method for making
US6472598B1 (en) 1998-08-28 2002-10-29 Amkor Technology, Inc. Electromagnetic interference shield device with conductive encapsulant and dam
US6475827B1 (en) 1999-10-15 2002-11-05 Amkor Technology, Inc. Method for making a semiconductor package having improved defect testing and increased production yield
US6476478B1 (en) 1999-11-12 2002-11-05 Amkor Technology, Inc. Cavity semiconductor package with exposed leads and die pad
US6501161B1 (en) 1999-10-15 2002-12-31 Amkor Technology, Inc. Semiconductor package having increased solder joint strength
US6512288B1 (en) 1999-06-07 2003-01-28 Amkor Technology, Inc. Circuit board semiconductor package
US6515356B1 (en) 1999-05-07 2003-02-04 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US6555899B1 (en) 1999-10-15 2003-04-29 Amkor Technology, Inc. Semiconductor package leadframe assembly and method of manufacture
US6605866B1 (en) 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6616436B1 (en) 1999-10-15 2003-09-09 Amkor Technology, Inc. Apparatus for manufacturing semiconductor packages
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6627976B1 (en) 1999-10-15 2003-09-30 Amkor Technology, Inc. Leadframe for semiconductor package and mold for molding the same
US6646339B1 (en) 1999-10-15 2003-11-11 Amkor Technology, Inc. Thin and heat radiant semiconductor package and method for manufacturing
US6677662B1 (en) 1999-10-15 2004-01-13 Amkor Technology, Inc. Clamp and heat block assembly for wire bonding a semiconductor package assembly
US6677663B1 (en) 1999-12-30 2004-01-13 Amkor Technology, Inc. End grid array semiconductor package
US6696747B1 (en) 1999-10-15 2004-02-24 Amkor Technology, Inc. Semiconductor package having reduced thickness
US6700187B2 (en) 2001-03-27 2004-03-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US6713322B2 (en) 2001-03-27 2004-03-30 Amkor Technology, Inc. Lead frame for semiconductor package
US6730544B1 (en) 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6753597B1 (en) 1999-12-16 2004-06-22 Amkor Technology, Inc. Encapsulated semiconductor package including chip paddle and leads
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6803645B2 (en) 2000-12-29 2004-10-12 Amkor Technology, Inc. Semiconductor package including flip chip
US6833609B1 (en) 1999-11-05 2004-12-21 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6847103B1 (en) 1999-11-09 2005-01-25 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US6853059B1 (en) 1999-10-15 2005-02-08 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US6858919B2 (en) 2000-03-25 2005-02-22 Amkor Technology, Inc. Semiconductor package
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6927478B2 (en) 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US8154111B2 (en) 1999-12-16 2012-04-10 Amkor Technology, Inc. Near chip size semiconductor package
US8501539B2 (en) 2009-11-12 2013-08-06 Freescale Semiconductor, Inc. Semiconductor device package
US8841758B2 (en) 2012-06-29 2014-09-23 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
US8866278B1 (en) 2011-10-10 2014-10-21 Amkor Technology, Inc. Semiconductor device with increased I/O configuration
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
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Cited By (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981314A (en) * 1996-10-31 1999-11-09 Amkor Technology, Inc. Near chip size integrated circuit package
US6962829B2 (en) 1996-10-31 2005-11-08 Amkor Technology, Inc. Method of making near chip size integrated circuit package
US6150193A (en) * 1996-10-31 2000-11-21 Amkor Technology, Inc. RF shielded device
US6228676B1 (en) 1996-10-31 2001-05-08 Amkor Technology, Inc. Near chip size integrated circuit package
US6268654B1 (en) 1997-04-18 2001-07-31 Ankor Technology, Inc. Integrated circuit package having adhesive bead supporting planar lid above planar substrate
US5950074A (en) * 1997-04-18 1999-09-07 Amkor Technology, Inc. Method of making an integrated circuit package
US6034429A (en) * 1997-04-18 2000-03-07 Amkor Technology, Inc. Integrated circuit package
US6117705A (en) * 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
US6143588A (en) * 1997-09-09 2000-11-07 Amkor Technology, Inc. Method of making an integrated circuit package employing a transparent encapsulant
US5962810A (en) * 1997-09-09 1999-10-05 Amkor Technology, Inc. Integrated circuit package employing a transparent encapsulant
US6433277B1 (en) 1998-06-24 2002-08-13 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US6684496B2 (en) 1998-06-24 2004-02-03 Amkor Technology, Inc. Method of making an integrated circuit package
US6472598B1 (en) 1998-08-28 2002-10-29 Amkor Technology, Inc. Electromagnetic interference shield device with conductive encapsulant and dam
US6601293B1 (en) 1998-08-28 2003-08-05 Amkor Technology, Inc. Method of making an electromagnetic interference shield device
US6521987B1 (en) 1998-10-21 2003-02-18 Amkor Technology, Inc. Plastic integrated circuit device package and method for making the package
US6281568B1 (en) 1998-10-21 2001-08-28 Amkor Technology, Inc. Plastic integrated circuit device package and leadframe having partially undercut leads and die pad
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US6825062B2 (en) 1998-11-20 2004-11-30 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6515356B1 (en) 1999-05-07 2003-02-04 Amkor Technology, Inc. Semiconductor package and method for fabricating the same
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US6469369B1 (en) 1999-06-30 2002-10-22 Amkor Technology, Inc. Leadframe having a mold inflow groove and method for making
US6448635B1 (en) 1999-08-30 2002-09-10 Amkor Technology, Inc. Surface acoustical wave flip chip
US6696747B1 (en) 1999-10-15 2004-02-24 Amkor Technology, Inc. Semiconductor package having reduced thickness
US6627976B1 (en) 1999-10-15 2003-09-30 Amkor Technology, Inc. Leadframe for semiconductor package and mold for molding the same
US6501161B1 (en) 1999-10-15 2002-12-31 Amkor Technology, Inc. Semiconductor package having increased solder joint strength
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US6475827B1 (en) 1999-10-15 2002-11-05 Amkor Technology, Inc. Method for making a semiconductor package having improved defect testing and increased production yield
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US6616436B1 (en) 1999-10-15 2003-09-09 Amkor Technology, Inc. Apparatus for manufacturing semiconductor packages
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US6677662B1 (en) 1999-10-15 2004-01-13 Amkor Technology, Inc. Clamp and heat block assembly for wire bonding a semiconductor package assembly
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US6476478B1 (en) 1999-11-12 2002-11-05 Amkor Technology, Inc. Cavity semiconductor package with exposed leads and die pad
US6753597B1 (en) 1999-12-16 2004-06-22 Amkor Technology, Inc. Encapsulated semiconductor package including chip paddle and leads
US8154111B2 (en) 1999-12-16 2012-04-10 Amkor Technology, Inc. Near chip size semiconductor package
US6605866B1 (en) 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6730544B1 (en) 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6677663B1 (en) 1999-12-30 2004-01-13 Amkor Technology, Inc. End grid array semiconductor package
US6858919B2 (en) 2000-03-25 2005-02-22 Amkor Technology, Inc. Semiconductor package
US7042068B2 (en) 2000-04-27 2006-05-09 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US8258613B1 (en) 2000-09-06 2012-09-04 Amkor Technology, Inc. Semiconductor memory card
US6624005B1 (en) 2000-09-06 2003-09-23 Amkor Technology, Inc. Semiconductor memory cards and method of making same
US6803645B2 (en) 2000-12-29 2004-10-12 Amkor Technology, Inc. Semiconductor package including flip chip
US6927478B2 (en) 2001-01-15 2005-08-09 Amkor Technology, Inc. Reduced size semiconductor package with stacked dies
US6605865B2 (en) 2001-03-19 2003-08-12 Amkor Technology, Inc. Semiconductor package with optimized leadframe bonding strength
US6713322B2 (en) 2001-03-27 2004-03-30 Amkor Technology, Inc. Lead frame for semiconductor package
US6700187B2 (en) 2001-03-27 2004-03-02 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US6756658B1 (en) 2001-04-06 2004-06-29 Amkor Technology, Inc. Making two lead surface mounting high power microleadframe semiconductor packages
US6611047B2 (en) 2001-10-12 2003-08-26 Amkor Technology, Inc. Semiconductor package with singulation crease
US6798046B1 (en) 2002-01-22 2004-09-28 Amkor Technology, Inc. Semiconductor package including ring structure connected to leads with vertically downset inner ends
US6885086B1 (en) 2002-03-05 2005-04-26 Amkor Technology, Inc. Reduced copper lead frame for saw-singulated chip package
US6608366B1 (en) 2002-04-15 2003-08-19 Harry J. Fogelson Lead frame with plated end leads
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
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US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US6847099B1 (en) 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
US8501539B2 (en) 2009-11-12 2013-08-06 Freescale Semiconductor, Inc. Semiconductor device package
US10546833B2 (en) 2009-12-07 2020-01-28 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US8866278B1 (en) 2011-10-10 2014-10-21 Amkor Technology, Inc. Semiconductor device with increased I/O configuration
US10410967B1 (en) 2011-11-29 2019-09-10 Amkor Technology, Inc. Electronic device comprising a conductive pad on a protruding-through electrode
US11043458B2 (en) 2011-11-29 2021-06-22 Amkor Technology Singapore Holding Pte. Ltd. Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode
US9947623B1 (en) 2011-11-29 2018-04-17 Amkor Technology, Inc. Semiconductor device comprising a conductive pad on a protruding-through electrode
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US10014240B1 (en) 2012-03-29 2018-07-03 Amkor Technology, Inc. Embedded component package and fabrication method
US9455216B2 (en) 2012-06-29 2016-09-27 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
US9093436B2 (en) 2012-06-29 2015-07-28 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
US8841758B2 (en) 2012-06-29 2014-09-23 Freescale Semiconductor, Inc. Semiconductor device package and method of manufacture
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method

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