JPS58191460A - Electronic parts - Google Patents

Electronic parts

Info

Publication number
JPS58191460A
JPS58191460A JP57074979A JP7497982A JPS58191460A JP S58191460 A JPS58191460 A JP S58191460A JP 57074979 A JP57074979 A JP 57074979A JP 7497982 A JP7497982 A JP 7497982A JP S58191460 A JPS58191460 A JP S58191460A
Authority
JP
Japan
Prior art keywords
chip
parts
terminals
lead frame
capacitors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57074979A
Other languages
Japanese (ja)
Inventor
Shugo Endo
遠藤　修吾
Tatsuhiko Irie
達彦 入江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP57074979A priority Critical patent/JPS58191460A/en
Publication of JPS58191460A publication Critical patent/JPS58191460A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To construct a semiconductor integrated circuit assembling capacitors of large capacity to the circuit by a method wherein the chip capacitors are connected to the necessary part between the terminals of a lead frame, and are insulatingly sealed with synthetic resin leaving the terminal tip parts. CONSTITUTION:Gold plating is applied to the die attaching parts 1a at the central part and the wire bonding parts 1b of the lead frame 1. The chip 2 of the semiconductor integrated circuit is die bonded to the die attaching part 1a, and the bonding pads of the chip 2 and the terminals 1c are connected according to wire bonding 3. The chip capacitors 5 are mounted on the necessary parts between the terminals 1c to be soldered or to be connected by a conductive adhesive. The chip 2 and the chip capacitors 5 are insulatingly sealed with synthetic resin leaving the tip parts of the terminals 1c. The parts 1d provided with guide holes 1e used when the frame is put on a conveyer are cut off to produce the final product.

Description

【発明の詳細な説明】 この発明は半導体集積回路のチップとチップコンデンサ
を組込んだ電子部品に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic component incorporating a semiconductor integrated circuit chip and a chip capacitor.

従来より半導体集積回路中には大容量のコンデンサを組
込み構成することができないためコンデンサは別個に取
付けていた。このため回路組上げ上の手間がかかるとい
う欠点があった。Conventionally, capacitors have been installed separately because it has not been possible to incorporate large capacitors into semiconductor integrated circuits. Therefore, there is a drawback that it takes time and effort to assemble the circuit.

この発明は上記欠点を除去せんとするものであり、その
概要は、リードフレームに半導体集積回路のチップをダ
イボンドし、該チップのポンディングパッドとリードフ
レームの端子をワイヤボンドにより接続し、リードフレ
ームの端子間の必要部分にチップコンデンサを接続し、
その上で端子先端部を残して合成樹脂で絶縁封止して成
ることを特徴とする電子部品である。The present invention aims to eliminate the above-mentioned drawbacks, and its outline is to die-bond a semiconductor integrated circuit chip to a lead frame, connect the bonding pad of the chip to the terminal of the lead frame by wire bonding, and then attach the chip to the lead frame. Connect the chip capacitor to the necessary part between the terminals of
This electronic component is characterized by being insulated and sealed with a synthetic resin, leaving only the tip of the terminal.

以下この発明を第１図乃至第７図に図示せる一実施例に
基づいて説明する。The present invention will be explained below based on an embodiment shown in FIGS. 1 to 7.

リードフレーム（１１は金属板から打ち抜き加工、エツ
チング加工等により形成される。The lead frame (11) is formed from a metal plate by punching, etching, etc.

リードフレーム（１）は通例所１１１４２合金より形成
される。The lead frame (1) is typically formed from 11142 alloy.

このリードフレーム（１）の中心部のダイヤタッチ部（
１１）及びワイヤボンド部（ｌｂ）には、第２図の如く
金メッキを施こされている。The diamond touch part (
11) and the wire bond part (lb) are plated with gold as shown in FIG.

第３図の如く、このリードフレーム（１］のダイヤタッ
チ部（Ｌｍ　）に半導体集積回路のチップ（２１がダイ
ボンドされている。ダイボンドは金シリコン共晶法ある
いは接着剤使用等によりおこなわれている。As shown in Fig. 3, a semiconductor integrated circuit chip (21) is die-bonded to the die-touch portion (Lm) of this lead frame (1). Die-bonding is performed by the gold-silicon eutectic method or by using an adhesive. .

第４図の如く、チップ（２１のポンディングパッドとリ
ードフレーム（１）の端子（ＩＣ）をワイヤボンドによ
り接続されている。ワイヤボンドは金線（３）を用いて
超音波併用熱圧着法によりなされるのが一般である。As shown in Figure 4, the bonding pads of the chip (21) and the terminals (IC) of the lead frame (1) are connected by wire bonding. This is generally done by

第５図の如くリードフレーム（１）の端子（ＩＣ）間の
必要部分にチップコンデンサ（５）は塔載され半田付け
あるいは導電接着剤により接続されている。As shown in FIG. 5, chip capacitors (5) are mounted on necessary portions between the terminals (ICs) of the lead frame (1) and connected by soldering or conductive adhesive.

叙上の如くリードフレーム（１）に配されたチップ（２
）及びチップコンデンサ（５）は端子（ＩＣ）の先端部
を残して合成樹脂で絶縁封止されている。第６図はこの
状態を示す。この場合合成樹脂としてはエポキシ樹脂が
賞月されている。As mentioned above, the chip (2) placed on the lead frame (1)
) and the chip capacitor (5) are insulated and sealed with synthetic resin except for the tip of the terminal (IC). FIG. 6 shows this state. In this case, epoxy resin is used as the synthetic resin.

尚、第１図及び第６図において両側番こ示されているリ
ード部分（１ｄ）は、コンベヤにかける際のガイド孔（
１ｅ）を設けた部分であるので最終的には第７図の如く
切除されて最終製品となる。In addition, the lead part (1d) shown with numbers on both sides in FIGS. 1 and 6 is the guide hole (
1e), so it is ultimately cut out as shown in FIG. 7 to form the final product.

以上の如（本発明による電子部品は半導体集積回路のチ
ップとチップ抵抗を一体化すると共に合成樹脂で封止し
でいるので回路組立作業上取扱いが便利であると共に合
成樹脂による封止により精度、品質保持上きわめてすぐ
れているものである。As described above, the electronic component according to the present invention integrates the chip of the semiconductor integrated circuit and the chip resistor and seals it with synthetic resin, so it is convenient to handle during circuit assembly work, and the sealing with synthetic resin improves accuracy. It is extremely excellent in maintaining quality.

【図面の簡単な説明】[Brief explanation of drawings]

第１図乃至第７図は本発明の一実施例を示す図で、第１
図乃至第６図は製造順序側に表わした分解斜視図、第７
図は完成商品を示す斜視図である。 特許出願人 松下電工株式会社 代理人弁理士　　竹　元　敏　丸 （ほか２名） 第１図 一４ヴ 第５図 竿７図Figures 1 to 7 are diagrams showing one embodiment of the present invention.
Figures 6 to 6 are exploded perspective views shown on the manufacturing order side;
The figure is a perspective view of the finished product. Patent applicant Matsushita Electric Works Co., Ltd. Patent attorney Toshimaru Takemoto (and 2 others) Figure 1-4V Figure 5-7 Figure 7

Claims (1)

【特許請求の範囲】[Claims] （１１リードフレームに半導体集積回路のチップ及びチ
ップコンデンサを接続すると共にこれらをリードフレー
ムの端子先端部を残して合成樹脂で絶縁封止して成る電
子部品。(11) An electronic component in which a semiconductor integrated circuit chip and a chip capacitor are connected to a lead frame, and these are insulated and sealed with synthetic resin, leaving the terminal tips of the lead frame intact.
JP57074979A 1982-04-30 1982-04-30 Electronic parts Pending JPS58191460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57074979A JPS58191460A (en) 1982-04-30 1982-04-30 Electronic parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57074979A JPS58191460A (en) 1982-04-30 1982-04-30 Electronic parts

Publications (1)

Publication Number Publication Date
JPS58191460A true JPS58191460A (en) 1983-11-08

Family

ID=13562912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57074979A Pending JPS58191460A (en) 1982-04-30 1982-04-30 Electronic parts

Country Status (1)

Country Link
JP (1) JPS58191460A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582697A (en) * 1991-09-20 1993-04-02 Nippondenso Co Ltd Lead frame of semiconductor device
JPH05206373A (en) * 1992-01-28 1993-08-13 Nec Kyushu Ltd Semiconductor integrated circuit device
JP2003086756A (en) * 2001-09-11 2003-03-20 Denso Corp Ic package and manufacturing method therefor
IT201700055987A1 (en) * 2017-05-23 2018-11-23 St Microelectronics Srl PROCEDURE FOR MANUFACTURING SEMICONDUCTOR AND CORRESPONDING PRODUCT DEVICES

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582697A (en) * 1991-09-20 1993-04-02 Nippondenso Co Ltd Lead frame of semiconductor device
JPH05206373A (en) * 1992-01-28 1993-08-13 Nec Kyushu Ltd Semiconductor integrated circuit device
JP2003086756A (en) * 2001-09-11 2003-03-20 Denso Corp Ic package and manufacturing method therefor
IT201700055987A1 (en) * 2017-05-23 2018-11-23 St Microelectronics Srl PROCEDURE FOR MANUFACTURING SEMICONDUCTOR AND CORRESPONDING PRODUCT DEVICES

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