JPH04180640A - Method of wiring semiconductor element - Google Patents

Method of wiring semiconductor element

Info

Publication number
JPH04180640A
JPH04180640A JP2309711A JP30971190A JPH04180640A JP H04180640 A JPH04180640 A JP H04180640A JP 2309711 A JP2309711 A JP 2309711A JP 30971190 A JP30971190 A JP 30971190A JP H04180640 A JPH04180640 A JP H04180640A
Authority
JP
Japan
Prior art keywords
terminals
chip
conductors
coupling board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2309711A
Other languages
Japanese (ja)
Inventor
Yoichi Ishikawa
Original Assignee
Nec Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Yamagata Ltd filed Critical Nec Yamagata Ltd
Priority to JP2309711A priority Critical patent/JPH04180640A/en
Publication of JPH04180640A publication Critical patent/JPH04180640A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector

Abstract

PURPOSE: To wire a semiconductor element by one time of wiring operations by putting a coupling board with provided conductors on a chip and sticking the electrode terminals and lead terminals of the chip to the conductors of the coupling board.
CONSTITUTION: Conductors 2 for connecting electrode terminals 4 of a chip 3 to lead terminals 5 of a package are printed on the lower surface of a coupling board 1 at locations for connecting the terminals 4 and 5 to each other. A plurality of terminals 4 and 5 are wired at once by putting the coupling board 1 on the chip 3, an chip island 6, and terminals 5 after positioning the board 1 and connecting the conductors 2 to the terminals 4 and 5 by ultrasonic compression bonding, etc.
COPYRIGHT: (C)1992,JPO&Japio
JP2309711A 1990-11-15 1990-11-15 Method of wiring semiconductor element Pending JPH04180640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2309711A JPH04180640A (en) 1990-11-15 1990-11-15 Method of wiring semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2309711A JPH04180640A (en) 1990-11-15 1990-11-15 Method of wiring semiconductor element

Publications (1)

Publication Number Publication Date
JPH04180640A true JPH04180640A (en) 1992-06-26

Family

ID=17996373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2309711A Pending JPH04180640A (en) 1990-11-15 1990-11-15 Method of wiring semiconductor element

Country Status (1)

Country Link
JP (1) JPH04180640A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002086970A3 (en) * 2001-04-18 2003-05-30 Toshiba Kk Semiconductor device and method of manufacturing the same
JP2008172120A (en) * 2007-01-15 2008-07-24 Sharp Corp Power module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002086970A3 (en) * 2001-04-18 2003-05-30 Toshiba Kk Semiconductor device and method of manufacturing the same
US6903450B2 (en) 2001-04-18 2005-06-07 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US7230322B2 (en) 2001-04-18 2007-06-12 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US7364950B2 (en) 2001-04-18 2008-04-29 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN100418217C (en) * 2001-04-18 2008-09-10 株式会社东芝 Semiconductor device and method of manufacturing same
JP2008172120A (en) * 2007-01-15 2008-07-24 Sharp Corp Power module

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