JP2715965B2 - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JP2715965B2
JP2715965B2 JP7052243A JP5224395A JP2715965B2 JP 2715965 B2 JP2715965 B2 JP 2715965B2 JP 7052243 A JP7052243 A JP 7052243A JP 5224395 A JP5224395 A JP 5224395A JP 2715965 B2 JP2715965 B2 JP 2715965B2
Authority
JP
Japan
Prior art keywords
resin
lead
inner lead
semiconductor element
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7052243A
Other languages
Japanese (ja)
Other versions
JPH07254677A (en
Inventor
昭弘 矢口
朝雄 西村
誠 北野
竜治 河野
奈柄 米田
一郎 安生
村上  元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7052243A priority Critical patent/JP2715965B2/en
Publication of JPH07254677A publication Critical patent/JPH07254677A/en
Application granted granted Critical
Publication of JP2715965B2 publication Critical patent/JP2715965B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、樹脂封止型半導体装置
に係り、特に樹脂クラックの防止に好適な樹脂封止型半
導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device suitable for preventing resin cracks.

【0002】[0002]

【従来の技術】従来より樹脂封止型半導体装置において
は、半導体素子をタブ(素子搭載部)の上に固定すると
共にタブの周囲に複数のリードを配設し、半導体素子と
の端子とリードを金属細線によって電気的に接続して、
その周囲を樹脂で封止する構造が採用されている。
2. Description of the Related Art Conventionally, in a resin-encapsulated semiconductor device, a semiconductor element is fixed on a tab (element mounting portion), and a plurality of leads are arranged around the tab. Are electrically connected by a thin metal wire,
A structure in which the periphery is sealed with a resin is employed.

【0003】ところが近年は半導体素子の高集積化によ
って素子寸法が大型化する傾向にあり、その反面、半導
体装置の外形は高密度実装上の要求から自由に拡大でき
ないか或いは逆に小型化される傾向がある。しかし従来
のようにタブ上に半導体素子を搭載する構造では外形寸
法一定のままで半導体素子の寸法を大型化していくと、
リードを樹脂に固定する部分の長さ(インナーリード部
の樹脂埋め込み部の距離)が不足し、リードに充分な固
定強度を与えられないという問題が生じた。
In recent years, however, there has been a tendency for the dimensions of the semiconductor device to be increased due to the high integration of the semiconductor device. Tend. However, in the conventional structure where the semiconductor element is mounted on the tab, if the dimensions of the semiconductor element are increased while keeping the external dimensions constant,
The length of the portion where the lead is fixed to the resin (the distance between the resin embedded portion of the inner lead portion) is insufficient, and there has been a problem that the lead cannot be provided with sufficient fixing strength.

【0004】そこで、このような問題を回避するため、
複数のインナーリードを半導体素子の回路形成面上に絶
縁部材を介在させて接着し、インナーリードと半導体素
子とを金属細線で電気的に接続して、これらの周囲を樹
脂で封止する方法が、特開昭61−241959号公報
により提案されている。この構造をリード・オン・チッ
プと呼ぶことがある。同じ趣旨でタブを用いない構造に
はリード・オン・チップの逆構造すなわちチップ・オン
・リードがある。チップ・オン・リードの例として特開
平1−154545号公報や特開平1−143344号
公報記載の技術がある。
Therefore, in order to avoid such a problem,
A method of bonding a plurality of inner leads to a circuit forming surface of a semiconductor element with an insulating member interposed therebetween, electrically connecting the inner leads and the semiconductor element with a thin metal wire, and sealing the periphery thereof with a resin. And Japanese Patent Application Laid-Open No. 61-241959. This structure is sometimes called a lead-on-chip. A structure that does not use a tab for the same purpose is a reverse structure of a lead-on-chip, that is, a chip-on-lead. Examples of the chip-on-lead include techniques described in JP-A-1-154545 and JP-A-1-143344.

【0005】[0005]

【発明が解決しようとする課題】チップ・オン・リード
に比べ、高密度化にはリード・オン・チップの方が適し
ている反面、半導体素子の回路形成面と各リードとの絶
縁をとる工夫が必要となり、特開昭61−241959
号公報に代表される技術では、インナーリードと回路形
成面との間に電気絶縁物として絶縁フィルムを介在させ
ている。
The lead-on-chip is more suitable for high density than the chip-on-lead, but the device for insulating the circuit forming surface of the semiconductor element from each lead. Is required, and Japanese Unexamined Patent Publication No. 61-241959
In the technique typified by Japanese Patent Application Laid-Open No. H11-163, an insulating film is interposed between an inner lead and a circuit formation surface as an electrical insulator.

【0006】この絶縁フィルムには基材としてポリイミ
ド等が用いられているが一般に絶縁フィルム基材は封止
樹脂との接着性に欠ける。
A polyimide or the like is used as a substrate for this insulating film, but the insulating film substrate generally lacks adhesiveness with a sealing resin.

【0007】一方、半導体素子の回路形成面と各リード
とはワイヤ等により電気的な接続をとる必要があること
等から通常は絶縁フィルムは必要箇所すなわちインナー
リードを半導体素子上面に搭載する領域にしか用いられ
ない。
On the other hand, since it is necessary to electrically connect the circuit formation surface of the semiconductor element and each lead with a wire or the like, the insulating film is usually provided at a necessary portion, that is, in a region where the inner lead is mounted on the upper surface of the semiconductor element. Only used.

【0008】ところで、樹脂封止型半導体装置において
は、これを構成する半導体素子、インナーリード、絶縁
フィルム及び封止樹脂の線膨張係数が通常互いに異なっ
ていることから、装置の製造過程や使用過程において装
置の温度変化によって装置内部に熱応力が発生する。特
にインナーリードと封止樹脂とは線膨張係数の差が大き
い。インナーリード材料と封止樹脂とは接着性(密着
性)にも欠けるので熱応力のかかっている状況では何ら
かの原因で容易に界面剥離が起こる。
In a resin-encapsulated semiconductor device, since the semiconductor elements, inner leads, insulating film, and encapsulating resin which constitute the semiconductor device usually have different coefficients of linear expansion, the process of manufacturing the device and the process of using the device are different. In this case, thermal stress is generated inside the device due to the temperature change of the device. In particular, there is a large difference in the coefficient of linear expansion between the inner lead and the sealing resin. Since the inner lead material and the sealing resin also lack adhesion (adhesion), interface delamination easily occurs for some reason in a situation where thermal stress is applied.

【0009】本来インナーリードが回路形成面に絶縁フ
ィルムを介してきっちり接着固定されているなら界面剥
離は起こらないか、最小限にとどまるはずである。しか
しながら接着土台となる絶縁フィルム端面と封止樹脂と
の間も先に述べた通り接着力に欠けることから、インナ
ーリードと封止樹脂との離れようとする力によって絶縁
フィルム端面と封止樹脂との間にも界面剥離が発生し、
増々界面剥離を成長させることになる。
[0009] If the inner lead is tightly adhered and fixed to the circuit forming surface via an insulating film, interfacial peeling should not occur or should be minimized. However, since the adhesive strength between the end surface of the insulating film serving as the adhesive base and the sealing resin also lacks as described above, the end face of the insulating film and the sealing resin are separated by the force separating the inner lead and the sealing resin. Interfacial delamination also occurs during
More and more interfacial delamination will grow.

【0010】このような界面剥離はインナーリードの上
端において樹脂クラックとなり、半導体装置の外観を損
ねたり、金属細線の断線等の原因にもなる。特にこの危
険が大きいインナーリードは共用(バス)バーともよば
れる電気接続用インナーリードである。
[0010] Such interfacial peeling causes a resin crack at the upper end of the inner lead, which impairs the appearance of the semiconductor device and causes disconnection of fine metal wires. Particularly, the inner lead in which this danger is large is an inner lead for electrical connection, also called a common (bus) bar.

【0011】本発明は電気接続用インナーリード上端部
からの樹脂クラックの発生を防止して、限られた外形寸
法のもとで可能な限り大型の半導体素子を搭載し得る樹
脂封止型半導体装置を提供することを目的とする。
According to the present invention, a resin-encapsulated semiconductor device capable of preventing the occurrence of a resin crack from the upper end of an inner lead for electrical connection and mounting a semiconductor element as large as possible under a limited external dimension. The purpose is to provide.

【0012】[0012]

【課題を解決するための手段】上記目的は電気接続用
(共用)リードと封止樹脂との界面で発生した剥離を、
絶縁フィルム端部と封止樹脂との界面にまで成長しない
よう剥離成長阻止手段を講ずることによって達成され
る。
The object of the present invention is to remove the peeling generated at the interface between the electrical connection (common) lead and the sealing resin.
This is achieved by providing a means for preventing peeling growth so as not to grow to the interface between the end portion of the insulating film and the sealing resin.

【0013】剥離成長阻止手段として本発明者は次なる
手段を提案する。第一のリードと樹脂との界面から上記
樹脂中にクラックが発生しない程度に前記第一のリード
下に介在する前記絶縁フイルムを前記第一のリードの幅
方向の端部よりも突出して前記半導体素子の一主面上に
延在させること。第一のリード下に介在する絶縁フイル
ムを第一のリードの幅方向両サイドにおける半導体素子
の一主面上にそれぞれ延在させ、第二のリード下に介在
する絶縁フイルムを半導体素子の端部よりも内側の主面
で終端させること。複数のリードの内2つのリードを半
導体素子の一主面における長手方向に沿って互いに対向
して配置させ、2つのリード下に介在する絶縁フイルム
を互いに対向する2つのリード間における半導体素子の
一主面上にそれぞれ延在させること。
The present inventor proposes the following means as a means for preventing peeling growth. Wherein the interface between the first lead and the resin to an extent not cracks occur in the resin first lead
The insulating film interposed under the width of the first lead
Projecting from the end in the
To extend. The insulating film interposed under the first lead is extended on one main surface of the semiconductor element on both sides in the width direction of the first lead, and the insulating film interposed under the second lead is connected to the end of the semiconductor element. Terminate on the inner main surface. Two of the plurality of leads are disposed so as to face each other along the longitudinal direction of one main surface of the semiconductor element, and an insulating film interposed under the two leads is provided with one insulating film between the two opposing leads. To extend on the main surface respectively.

【0014】[0014]

【0015】[0015]

【0016】[0016]

【0017】[0017]

【0018】[0018]

【0019】[0019]

【作用】上記のように工夫することにより、インナーリ
ード(共用の電気接続用インナーリード)と封止樹脂と
の界面の剥離を起点とする剥離が絶縁フィルムと封止樹
脂との界面に至るまでに曲点があることから直進でき
ず、少なくとも両者の剥離がつながるように成長するの
を阻止するという効果がある。また、第二のリード下に
介在する絶縁フイルムを半導体素子の端部よりも内側の
主面で終端させることにより、封止樹脂と半導体素子の
膨張係数の差により生ずる樹脂クラックを防止する効果
がある。すなわち、封止樹脂と半導体素子の膨張係数の
差により半導体素子の端部では熱応力が発生している。
この熱応力の発生している箇所に絶縁フィルムがある
と、絶縁フィルムは応力をあまり負担しないため、その
端部に接する樹脂に熱応力が集中して樹脂クラックが発
生する。そこで、絶縁フイルムを半導体素子の端部より
も内側の主面で終端させ、熱応力の発生箇所から絶縁フ
ィルムを遠ざけることにより、樹脂クラックを防止する
ことができる。
By devising as described above, the separation starting from the separation at the interface between the inner lead (shared inner lead for electrical connection) and the sealing resin reaches the interface between the insulating film and the sealing resin. Has a curved point, the straight line cannot travel straight, and at least there is an effect that growth is prevented so that the two are separated from each other. Also under the second lead
Insert the intervening insulating film inside the edge of the semiconductor device.
By terminating on the main surface, the sealing resin
Effect of preventing resin cracks caused by differences in expansion coefficients
There is. That is, the expansion coefficient of the sealing resin and the semiconductor element is
Due to the difference, thermal stress is generated at the end of the semiconductor element.
There is an insulating film at the place where this thermal stress is generated
Because the insulating film does not bear much stress,
Thermal stress concentrates on the resin in contact with the edge, causing resin cracks
Live. Therefore, insulate the insulating film from the end of the semiconductor element.
Termination on the inner main surface, and from the point where thermal stress occurs
Prevent resin cracks by keeping film away
be able to.

【0020】共用のインナーリードの周囲と絶縁部材の
側面に発生していた樹脂界面の剥離は、上記工夫により
分離されるため、共用インナーリード上部での樹脂の変
形量が増大することがなく、共用のインナーリードの上
端部に大きな応力が発生することがなくなるので、この
部分からの樹脂クラックの発生を防止することができ、
大型の半導体素子を搭載しても高信頼性の樹脂封止型半
導体装置が得られる。
The separation of the resin interface generated around the common inner lead and the side surface of the insulating member is separated by the above-described device, so that the amount of deformation of the resin at the upper portion of the common inner lead does not increase. Since no large stress is generated at the upper end of the common inner lead, it is possible to prevent the occurrence of resin cracks from this portion,
Even if a large semiconductor element is mounted, a highly reliable resin-encapsulated semiconductor device can be obtained.

【0021】[0021]

【0022】[0022]

【実施例】以下、本発明の一実施例を図1,図2によっ
て説明する。図1は、本発明の一実施例である樹脂封止
型半導体装置の部分断面斜視図、図2は第1のイ−イ線
で切った断面図。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a partial cross-sectional perspective view of a resin-sealed semiconductor device according to one embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along a first line II.

【0023】図において、共用インナーリード3及び信
号用インナーリード4はその一端側をアウターリード5
と一体に構成しており、アウターリード5は、樹脂封止
型半導体装置の2方向(長手面)に配設されている。
In the drawing, the common inner lead 3 and the signal inner lead 4 have one ends thereof connected to outer leads 5.
The outer leads 5 are disposed in two directions (longitudinal surfaces) of the resin-encapsulated semiconductor device.

【0024】共用インナーリード3は、半導体素子1の
中央部分をその長辺と平行に引き伸ばされており、半導
体素子1の回路形成面1a上で半導体素子1と金属細線
(ワイヤ)7によって電気接続が行われている。回路形
成面1aは大部分がポリイミドなどのパッシベーション
膜で覆われているが、この電気接続部分の領域について
はパッシベーション膜がなく回路形成面が露出してい
る。
The common inner lead 3 has a central portion of the semiconductor element 1 extended in parallel with its long side, and is electrically connected to the semiconductor element 1 on the circuit forming surface 1 a of the semiconductor element 1 by a thin metal wire (wire) 7. Has been done. Although the circuit forming surface 1a is mostly covered with a passivation film such as polyimide, the circuit forming surface is exposed without the passivation film in the area of the electric connection portion.

【0025】また、信号用インナーリード4は、長手形
状の半導体素子1の夫々の長辺を横切って半導体素子1
の中央側に引き伸ばされて、半導体素子1の回路形成面
1a上で半導体素子1とその先端部とが金属細線7によ
って電気接続されている。◆こうして2本の共用インナ
ーリード3の主要部同士は互いに略平行に対向面として
向かい合うことになる。
The signal inner lead 4 extends across each of the long sides of the elongated semiconductor element 1.
The semiconductor element 1 and its tip are electrically connected by a thin metal wire 7 on the circuit forming surface 1 a of the semiconductor element 1. Thus, the main portions of the two common inner leads 3 face each other substantially parallel to each other as opposing surfaces.

【0026】共用インナーリード3の下面、及び信号用
インナーリード4の下面と半導体素子1の回路形成面1
aの間には、共用インナーリード3及び信号用インナー
リード4と半導体素子1とを電気的に絶縁するためのシ
ート状の絶縁部材(絶縁フィルム)2が設けられてお
り、絶縁部材2は、半導体素子1と接着剤9によって接
着されている。本例においては絶縁部材2は2枚用いら
れ、絶縁部材2同士の対向側面に沿って夫々略平行に前
記2本の共用インナーリード3の長手方向部分が位置し
ている 共用インナーリード3と絶縁部材2の側面同士は図2に
示すように絶縁部材2が共用インナーリード3の長手部
側面からはみ出すように形成されている。◆本実施例で
は、半導体素子1,絶縁部材2,共用インナーリード
3,信号用インナーリード4及び金属細線7を樹脂8で
封止して半導体装置を形成する。
The lower surface of the common inner lead 3, the lower surface of the signal inner lead 4, and the circuit forming surface 1 of the semiconductor element 1
A sheet-like insulating member (insulating film) 2 for electrically insulating the common inner lead 3 and the signal inner lead 4 from the semiconductor element 1 is provided between the insulating members 2a. The semiconductor element 1 and the adhesive 9 are bonded together. In the present embodiment, two insulating members 2 are used, and the longitudinal portions of the two shared inner leads 3 are positioned substantially parallel to each other along the opposing side surfaces of the insulating members 2. As shown in FIG. 2, the side surfaces of the member 2 are formed such that the insulating member 2 protrudes from the side surface of the longitudinal portion of the common inner lead 3. In this embodiment, the semiconductor device is formed by sealing the semiconductor element 1, the insulating member 2, the common inner lead 3, the signal inner lead 4, and the thin metal wire 7 with the resin 8.

【0027】半導体素子1の回路形成面1aと絶縁部材
2との接着、絶縁部材2と共用インナーリード3、絶縁
部材2と信号用インナーリード4及び絶縁部材2と支持
用インナーリード6との接着は、図2に示すように接着
剤9によって接着する。尚、共用インナーリード3と絶
縁部材2の接着は、それらの全面で行っていも良いし、
一部であっても良い。
Bonding between the circuit forming surface 1a of the semiconductor element 1 and the insulating member 2, bonding between the insulating member 2 and the common inner lead 3, bonding between the insulating member 2 and the signal inner lead 4, and bonding between the insulating member 2 and the supporting inner lead 6. Are bonded by an adhesive 9 as shown in FIG. The bonding of the common inner lead 3 and the insulating member 2 may be performed on the entire surface thereof,
It may be a part.

【0028】次に、共用インナーリード3、信号用イン
ナーリード4及び支持用インナーリード6を絶縁部材2
を介在させ、接着剤9を用いて半導体素子1の回路形成
面1aに接着する方法について説明する。半導体素子1
の回路形成面1aの共用インナーリード3,信号用イン
ナーリード4及び支持用インナーリード6の夫々に対向
する位置の上にシート状の絶縁部材2を分割して接着剤
9により貼り付ける。次いで、共用インナーリード3、
信号用インナーリード4及び支持用インナーリード6を
接着剤9により絶縁部材2を介して半導体素子1の回路
形成面1aに接着固定する。
Next, the common inner lead 3, the signal inner lead 4, and the supporting inner lead 6 are
A method of bonding the semiconductor element 1 to the circuit forming surface 1a using the adhesive 9 will be described. Semiconductor element 1
The sheet-shaped insulating member 2 is divided and bonded with an adhesive 9 on positions of the circuit forming surface 1a facing the common inner lead 3, the signal inner lead 4, and the supporting inner lead 6, respectively. Next, the common inner lead 3,
The signal inner lead 4 and the supporting inner lead 6 are bonded and fixed to the circuit forming surface 1a of the semiconductor element 1 via the insulating member 2 with an adhesive 9.

【0029】絶縁部材2には、エポキシ系樹脂、ビスマ
レイミドトリアジン樹脂、フェーノール樹脂、ポリイミ
ド樹脂などを主成分とし、これに無機質フィラー、各種
添加剤などを加えた材料を使用する。また、接着剤9と
しては、例えばエポキシ,ポリエーテルアミド,ポリイ
ミド前駆体,エポキシ変成ポリイミドなどの材料を使用
する。
The insulating member 2 is made of a material mainly composed of an epoxy resin, a bismaleimide triazine resin, a phenol resin, a polyimide resin, and the like, to which an inorganic filler, various additives and the like are added. Further, as the adhesive 9, for example, a material such as epoxy, polyetheramide, polyimide precursor, or epoxy-modified polyimide is used.

【0030】共用インナーリード3,信号用インナーリ
ード4及び支持用インナーリード6は、樹脂8によって
封止されるまでは互いに接続されており、一連のリード
フレームを形成しているが、樹脂封止後に切断・分離さ
れかつ成型される。リードフレームは、例えばFe−N
i合金(Fe−42Niなど)、Cuなどで形成されて
いる。
The common inner lead 3, the signal inner lead 4 and the supporting inner lead 6 are connected to each other until sealed by the resin 8, and form a series of lead frames. It is later cut, separated and molded. The lead frame is made of, for example, Fe-N
It is formed of an i-alloy (such as Fe-42Ni), Cu, or the like.

【0031】金属細線7にはアルミニウム(Al),金
(Au)あるいは銅(Cu)などの細線を使用する。◆
封止樹脂8には、フェノール系硬化剤、シリコーンゴム
及びフィラーが添加されたエポキシ系樹脂を使用する。
As the thin metal wire 7, a thin wire such as aluminum (Al), gold (Au) or copper (Cu) is used. ◆
As the sealing resin 8, an epoxy resin to which a phenolic curing agent, silicone rubber and a filler are added is used.

【0032】アウターリード5が樹脂8の外部に引き出
されている方向は、図1に示したような2方向、すなわ
ち樹脂封止型半導体装置の長辺側に限定するものではな
く、1方向或いは3方向以上であっても良い。また、樹
脂8の側面からだけでなく、樹脂8の上面或いは下面か
らアウターリード5が引き出されていても良い。更に図
では、アウターリード5を下方に折り曲げ、その先端を
樹脂8の下面まで曲げたJベンド型を例にとって示して
あるが、アウターリード5は任意の方向、形状に折り曲
げても良いし、また折り曲げなくとも良い。
The directions in which the outer leads 5 are drawn out of the resin 8 are not limited to the two directions shown in FIG. 1, that is, the long side of the resin-encapsulated semiconductor device, but may be one direction or The directions may be three or more. Further, the outer leads 5 may be drawn not only from the side surfaces of the resin 8 but also from the upper surface or the lower surface of the resin 8. Further, in the drawing, a J-bend type in which the outer lead 5 is bent downward and its tip is bent to the lower surface of the resin 8 is shown as an example, but the outer lead 5 may be bent in any direction and shape. It is not necessary to bend.

【0033】以上の実施例では、共用インナーリード3
と信号用インナーリード4を区別して示してあるが、共
用インナーリード3と信号用インナーリード4が区別さ
れないような半導体装置、或いは共用インナーリード3
が設けられていない半導体装置であっても、本発明の範
囲を逸脱しない限り適用することが可能である。
In the above embodiment, the common inner lead 3
And the signal inner lead 4 are distinguished from each other, but a semiconductor device in which the shared inner lead 3 and the signal inner lead 4 are not distinguished, or the shared inner lead 3
However, the present invention can be applied to a semiconductor device having no semiconductor device without departing from the scope of the present invention.

【0034】本実施例の特徴は、絶縁部材2を共用イン
ナーリード3の主要部側面からはみ出させ延長部2aを
形成した点にある。こうすることにより半導体素子1と
絶縁部材2端部のつけ根で万一樹脂8との界面剥離が生
じても、絶縁部材2端面と共用インナーリード3主要部
側面とは面一ではないので界面剥離が直進せず剥離作用
は拡散、減衰される。
The present embodiment is characterized in that the insulating member 2 protrudes from the side of the main part of the common inner lead 3 to form an extension 2a. By doing so, even if the interface between the resin 8 and the semiconductor element 1 should be separated at the base of the end of the insulating member 2, the interface between the end of the insulating member 2 and the side of the main part of the common inner lead 3 is not flush. However, the peeling action is diffused and attenuated without going straight.

【0035】本発明が対象としている従来のタブレス型
の樹脂封止型半導体装置の部分断面斜視図を図3に、ま
た図3のロ−ロ線で切った断面図を図4に示す。支持用
インナーリード6によって支持(接着固定)された半導
体素子1の回路形成面1aに、共用インナーリード(バ
スバーインナーリードとも呼ばれている)3及び信号用
インナーリード4が半導体素子1と電気的に絶縁する絶
縁部材2を介して接着剤9によって接着され、共用イン
ナーリード3及び信号用インナーリード4と半導体素子
とが夫々金属細線7で電気的に接続されている。そし
て、これらは樹脂8で封止されパッケージを形成してい
る。
FIG. 3 is a partial cross-sectional perspective view of a conventional tabless resin-sealed semiconductor device to which the present invention is directed, and FIG. 4 is a cross-sectional view taken along a roll line in FIG. A common inner lead (also called a bus bar inner lead) 3 and a signal inner lead 4 are electrically connected to the semiconductor element 1 on the circuit forming surface 1a of the semiconductor element 1 supported (adhered and fixed) by the supporting inner lead 6. The common inner lead 3, the signal inner lead 4, and the semiconductor element are electrically connected to each other by a thin metal wire 7. These are sealed with the resin 8 to form a package.

【0036】また、共用インナーリード3及び信号用イ
ンナーリード4の金属細線接合部には、インナーリード
と金属細線の接合を良好にするために金(Au)或いは
(Ag)などの貴金属被膜が設けられている。ところ
が、貴金属被膜と封止樹脂の接着性が悪いため、貴金属
被膜が設けられているインナーリードと封止樹脂との界
面は容易に剥離が起こり易くなっている。そのため、信
号用インナーリード4は貴金属被膜14を設ける領域を
信号用インナーリード4先端の金属細線接合部のみに限
っている。
A noble metal film such as gold (Au) or (Ag) is provided at the joint between the common inner lead 3 and the signal inner lead 4 in order to improve the joint between the inner lead and the thin metal wire. Have been. However, since the adhesion between the noble metal film and the sealing resin is poor, the interface between the inner lead provided with the noble metal film and the sealing resin is easily peeled off. Therefore, the area of the signal inner lead 4 where the noble metal coating 14 is provided is limited to only the thin metal wire joint at the tip of the signal inner lead 4.

【0037】しかしながら共用インナーリード3につい
ては、金属細線接合本数が多く、更に広い範囲にわたっ
ているため絶縁部材2上部に存在する共用インナーリー
ド3の全面に貴金属被膜14が施されている。尚、図3
の斜線部は、貴金属被膜14が設けられている領域を示
す。
However, the common inner lead 3 has a large number of thin metal wires joined and extends over a wider range, so that the noble metal coating 14 is applied to the entire surface of the common inner lead 3 existing above the insulating member 2. FIG.
A hatched portion indicates a region where the noble metal film 14 is provided.

【0038】樹脂封止型半導体装置においては、これを
構成する半導体素子、インナーリード、絶縁部材及び封
止樹脂の線膨張係数が通常互いに異なっているため、装
置の温度変化によって装置内に熱応力が発生する。特に
共用インナーリード及び絶縁部材夫々の封止樹脂との界
面が剥離することによって共用インナーリードの上端部
に高い応力が発生し、この部分より樹脂クラックが発生
する。
In a resin-encapsulated semiconductor device, the semiconductor elements, inner leads, insulating members, and the encapsulating resin that constitute the semiconductor device usually have different coefficients of linear expansion. Occurs. In particular, when the interface between the common inner lead and the insulating member is separated from the sealing resin, high stress is generated at the upper end of the common inner lead, and a resin crack is generated from this portion.

【0039】樹脂クラックの発生メカニズムを模式的に
図5の断面図に示す。共用インナーリード(線膨張係数
5×10~6/℃)と封止樹脂(熱線膨張係数約20×10~
6/℃)との線膨張係数差が大きいため、半導体装置樹脂
封止後の冷却や温度サイクル試験時の温度低下によっ
て、接着性の悪い共用インナーリード3と封止樹脂8の
界面が容易に剥離12する。ちなみに半導体素子1の厚
さは例えば0.4mm程度であり、絶縁部材2の厚さは
0.15〜0.2mm程度であり、各インナーリードの厚
さはおよそ0.2mm程度である。この剥離12が発生
すると、樹脂は第5図に矢印で示すように中心方向に収
縮する。この為、共用インナーリード側面3dとほぼ同
じ位置に存在する絶縁部材側面2dの樹脂との界面にも
剥離12が発生する。剥離部分12が長くなったことに
よって共用インナーリード上部での樹脂の変形量が増大
するため、共用インナーリード3の上端部に大きな応力
が発生し、この部分に樹脂クラック13が発生する。
FIG. 5 is a cross-sectional view schematically showing the mechanism of occurrence of resin cracks. Common inner lead (linear expansion coefficient 5 × 10 6 / ° C) and sealing resin (thermal linear expansion coefficient about 20 × 10
6 / ° C.), the interface between the common inner lead 3 and the sealing resin 8 having poor adhesion can be easily formed by cooling after sealing the resin of the semiconductor device or lowering the temperature during the temperature cycle test. Peeling 12 is performed. Incidentally, the thickness of the semiconductor element 1 is, for example, about 0.4 mm, the thickness of the insulating member 2 is about 0.15 to 0.2 mm, and the thickness of each inner lead is about 0.2 mm. When this peeling 12 occurs, the resin contracts in the center direction as shown by the arrow in FIG. For this reason, peeling 12 also occurs at the interface between the insulating member side surface 2d and the resin at the same position as the common inner lead side surface 3d. Since the length of the peeled portion 12 increases the amount of deformation of the resin at the upper portion of the common inner lead, a large stress is generated at the upper end of the common inner lead 3, and a resin crack 13 occurs at this portion.

【0040】共用インナーリード3の上端部より樹脂ク
ラック13が発生すると、半導体装置の外観を損ねるだ
けでなく、共用インナーリード3又は信号用インナーリ
ード4と半導体素子1とを電気的に接続する金属細線7
をも断線させるという問題が起こる。◆本発明の上記実
施例はこのような界面剥離の発生及至は成長が確実に阻
止できることになる。
When the resin crack 13 occurs from the upper end of the common inner lead 3, not only does the appearance of the semiconductor device deteriorate, but also the metal that electrically connects the common inner lead 3 or the signal inner lead 4 and the semiconductor element 1 is formed. Thin line 7
The problem that the wire is broken also occurs. In the above embodiment of the present invention, the occurrence and growth of such interface delamination can be reliably prevented.

【0041】[0041]

【発明の効果】本発明によれば、半導体装置樹脂封止後
の冷却や温度サイクル試験時の温度低下によって、大き
な応力が発生することがないので、樹脂クラックの発生
を防止することができ、更に限られた外形寸法のもとで
可能な限り大型の半導体素子を搭載しうる樹脂封止型半
導体装置を得ることができる。
According to the present invention, since a large stress is not generated due to cooling after resin sealing of a semiconductor device or a decrease in temperature during a temperature cycle test, generation of a resin crack can be prevented. Further, it is possible to obtain a resin-encapsulated semiconductor device capable of mounting as large a semiconductor element as possible under limited external dimensions.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の樹脂封止型半導体装置の一実施例を示
す部分断面斜視図である。
FIG. 1 is a partial sectional perspective view showing one embodiment of a resin-sealed semiconductor device of the present invention.

【図2】図1のイ−イ線断面図である。FIG. 2 is a sectional view taken along the line II in FIG.

【図3】従来のタブレス型半導体装置の例を示す部分断
面斜視図である。
FIG. 3 is a partial sectional perspective view showing an example of a conventional tabless semiconductor device.

【図4】図3のロ−ロ線断面図である。FIG. 4 is a sectional view taken along the line 2-2 of FIG. 3;

【図5】樹脂クラックの発生メカニズムを説明するため
の部分断面図である。
FIG. 5 is a partial cross-sectional view for explaining a mechanism of generation of a resin crack.

【符号の説明】[Explanation of symbols]

1…半導体素子、1a…半導体素子の回路形成面、2…
絶縁部材、3…共用インナーリード、4…信号用インナ
ーリード、7…金属細線、8…樹脂。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 1a ... Circuit formation surface of a semiconductor element, 2 ...
Insulating member, 3 ... common inner lead, 4 ... inner lead for signal, 7 ... thin metal wire, 8 ... resin.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 河野 竜治 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 米田 奈柄 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 安生 一郎 東京都小平市上水本町五丁目20番1号 株式会社 日立製作所 半導体設計開発 センタ内 (72)発明者 村上 元 東京都小平市上水本町五丁目20番1号 株式会社 日立製作所 半導体設計開発 センタ内 (56)参考文献 特開 昭61−241959(JP,A) 特開 昭63−208255(JP,A) ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ryuji Kono 502 Kandate-cho, Tsuchiura-city, Ibaraki Pref. Machinery Research Laboratory, Hitachi, Ltd. Inside the laboratory (72) Inventor Ichiro Yasui 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Design & Development Center, Hitachi, Ltd. (72) Gen Murakami 5-2-1, Kamimizuhonmachi, Kodaira-shi, Tokyo No. Hitachi Semiconductor Co., Ltd. Semiconductor Design & Development Center (56) References JP-A-61-241959 (JP, A) JP-A-63-208255 (JP, A)

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 一主面を有する半導体素子と、この半導
体素子の前記一主面上において一つの方向に沿う領域を
持つ第一のリードと、この第一のリードの前記領域と交
差する方向に配置された複数の第二のリードと、前記両
リードと前記半導体素子との間に介在する絶縁フイルム
と、前記半導体素子の前記一主面を封止する樹脂とを有
する半導体装置において、前記第一のリードと前記樹脂
との界面から前記樹脂中にクラックが発生しない程度に
前記第一のリード下に介在する前記絶縁フイルムが前記
第一のリードの幅方向の端部よりも突出して前記半導体
素子の一主面上に延在されてなることを特徴とする半導
体装置。
1. A semiconductor device having one main surface, a first lead having a region along one direction on the one main surface of the semiconductor device, and a direction intersecting the region of the first lead. A plurality of second leads, an insulating film interposed between the two leads and the semiconductor element, and a resin sealing the one main surface of the semiconductor element , the semiconductor device, From the interface between the first lead and the resin so that cracks do not occur in the resin.
The insulating film interposed under the first lead is
The semiconductor which protrudes beyond the widthwise end of the first lead;
A semiconductor device characterized by being extended on one main surface of an element .
【請求項2】 一主面を有する半導体素子と、この半導
体素子の前記一主面上において一つの方向に沿う領域を
持つ第一のリードと、この第一のリードの前記領域と交
差する方向に配置された複数の第二のリードと、前記両
リードと前記半導体素子との間に介在する絶縁フイルム
と、前記半導体素子の前記一主面を封止する樹脂とを有
する半導体装置において、前記第一のリード下に介在す
る前記絶縁フイルムが前記第一のリードの幅方向両サイ
ドにおける前記半導体素子の前記一主面上にそれぞれ延
在されてなり、前記第二のリード下に介在する前記絶縁
フイルムが前記半導体素子の端部よりも内側の主面で終
端してなることを特徴とする半導体装置。
2. A semiconductor device having one main surface, a first lead having a region along one direction on the one main surface of the semiconductor device, and a direction intersecting the region of the first lead. A plurality of second leads, an insulating film interposed between the two leads and the semiconductor element, and a resin sealing the one main surface of the semiconductor element , the semiconductor device, The insulating film interposed under the first lead extends on the one main surface of the semiconductor element on both sides in the width direction of the first lead, and the insulating film interposed under the second lead. A semiconductor device, wherein an insulating film is terminated on a main surface inside an end of the semiconductor element.
【請求項3】 長方形の一主面を有する半導体素子と、
この半導体素子にワイヤーボンデイングされる複数のリ
ードと、このリードと前記半導体素子の上記一主面との
間に介在する絶縁フイルムと、前記半導体素子の前記一
主面を封止する樹脂とを備え、前記複数のリードの内2
つのリードは前記半導体素子の前記一主面における長手
方向に沿って対向して配置されており、前記2つのリー
ド下に介在する絶縁フイルムが前記対向する2つのリー
ド間における前記半導体素子の一主面上にそれぞれ延在
されてなることを特徴とする半導体装置。
3. A semiconductor element having one main surface of a rectangle;
A plurality of leads wire-bonded to the semiconductor element; an insulating film interposed between the leads and the one main surface of the semiconductor element ;
And a resin for sealing the main surface , wherein two of the plurality of leads are provided.
The two leads are disposed so as to face each other along the longitudinal direction of the one main surface of the semiconductor element, and an insulating film interposed under the two leads is connected to the main part of the semiconductor element between the two opposing leads. A semiconductor device characterized by being extended on a surface.
JP7052243A 1995-03-13 1995-03-13 Resin-sealed semiconductor device Expired - Lifetime JP2715965B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7052243A JP2715965B2 (en) 1995-03-13 1995-03-13 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7052243A JP2715965B2 (en) 1995-03-13 1995-03-13 Resin-sealed semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP4541290A Division JP2528991B2 (en) 1990-02-28 1990-02-28 Resin-sealed semiconductor device and lead frame

Publications (2)

Publication Number Publication Date
JPH07254677A JPH07254677A (en) 1995-10-03
JP2715965B2 true JP2715965B2 (en) 1998-02-18

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JP (1) JP2715965B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1238119A (en) * 1985-04-18 1988-06-14 Douglas W. Phelps, Jr. Packaged semiconductor chip
JPS63208255A (en) * 1987-02-25 1988-08-29 Hitachi Ltd Electronic device

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