JP2569008B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2569008B2 JP2569008B2 JP61094518A JP9451886A JP2569008B2 JP 2569008 B2 JP2569008 B2 JP 2569008B2 JP 61094518 A JP61094518 A JP 61094518A JP 9451886 A JP9451886 A JP 9451886A JP 2569008 B2 JP2569008 B2 JP 2569008B2
- Authority
- JP
- Japan
- Prior art keywords
- tab
- resin
- semiconductor device
- lead frame
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に係り、特に樹脂封止型半導体
装置の樹脂クラツクの発生防止に好適なリードフレーム
構造に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a lead frame structure suitable for preventing resin cracks in a resin-sealed semiconductor device.
樹脂封止型半導体装置においては、これを構成する半
導体素子，リードフレーム及び樹脂の線膨張係数が通常
互いに異なつているため、装置の温度変化によつて、装
置内に熱応力が発生する。近年、半導体素子の高集積化
によつて、素子寸法が大型化する傾向にあり、これとと
もに、半導体素子を搭載するリードフレームのタブの寸
法も大型化している。このため、タブ端部の熱応力が増
大し、樹脂クラツクの発生が問題となつている。In a resin-encapsulated semiconductor device, the semiconductor elements, the lead frame, and the resin that constitute the semiconductor device usually have different coefficients of linear expansion. Therefore, a change in the temperature of the device generates thermal stress in the device. 2. Description of the Related Art In recent years, device dimensions have tended to increase due to higher integration of semiconductor devices, and tab dimensions of lead frames on which semiconductor devices have been mounted have also increased. For this reason, the thermal stress at the end of the tab increases, and the occurrence of resin crack is a problem.
第５図は、一般的なリードフレームを使用した樹脂封
止型半導体装置の平面図である。同図においては、半導
体装置内部の構造を説明するため、リードフレームより
上部の樹脂を除去して示してある。FIG. 5 is a plan view of a resin-sealed semiconductor device using a general lead frame. In FIG. 1, in order to explain the internal structure of the semiconductor device, the resin above the lead frame is removed.
第５図において、半導体素子１は、リードフレーム10
中央部に設けられたタブ２の上に接着剤などを用いて固
定され、半導体素子１上の端子は、タブ２の周囲に配設
された複数のリード３と金属細線４によつて電気接続さ
れている。リード３及びタブ２を指示するタブ吊りリー
ド６は、いずれも最初、図示していない共通の外枠に連
結されて、タブ２とともにリードフレーム10を形成して
おり、樹脂５によつて封止を行つた後、外枠から切離さ
れる。In FIG. 5, the semiconductor element 1 includes a lead frame 10.
The terminal on the semiconductor element 1 is fixed on a tab 2 provided at the center using an adhesive or the like. The terminals on the semiconductor element 1 are electrically connected to a plurality of leads 3 arranged around the tab 2 by thin metal wires 4. Have been. The tab suspension leads 6 for indicating the leads 3 and the tabs 2 are first connected to a common outer frame (not shown) to form a lead frame 10 together with the tabs 2, and are sealed with the resin 5. And then cut off from the outer frame.
リードフレーム10の材料としては、通常、線膨張係数
が約５×10-6/℃の42アロイ、あるいは、線膨張係数約1
7×10-6/℃の銅合金などが使用される。リードフレーム
材料として42アロイ及び銅合金を使用した場合の樹脂ク
ラツク発生メカニズムを模式的にそれぞれ第６図及び第
７図の断面図に示す。As a material of the lead frame 10, a 42 alloy having a linear expansion coefficient of about 5 × 10 −6 / ° C. or a linear expansion coefficient of about 1
A copper alloy of 7 × 10 −6 / ° C. or the like is used. FIGS. 6 and 7 are cross-sectional views schematically showing a resin crack generation mechanism when a 42 alloy and a copper alloy are used as a lead frame material.
リードフレーム材料として42アロイを使用する場合、
リードフレーム10と樹脂５（線膨張係数約20×10-6/
℃）との線膨張係数差が大きいため、半導体装置樹脂封
止後の冷却や、温度サイクル試験時の温度低下によつ
て、タブ２の反素子搭載面側2bの樹脂接着界面には高い
熱応力が作用し、はく離を生じやすくなる。このはく離
が発生すると、樹脂５は第６図に矢印で示すように、タ
ブ２の中心方向にすべつて収縮するため、タブ２の下端
部に応力が集中し、この部分に樹脂クラツク７が発生す
る。When using 42 alloy as the lead frame material,
Lead frame 10 and resin 5 (linear expansion coefficient about 20 × 10 -6 /
C), the cooling after the resin sealing of the semiconductor device and the temperature drop during the temperature cycle test cause a high heat at the resin bonding interface on the opposite element mounting surface side 2b of the tab 2. Stress acts, and peeling tends to occur. When this peeling occurs, the resin 5 contracts in the direction of the center of the tab 2 as indicated by an arrow in FIG. 6, so that stress concentrates on the lower end of the tab 2 and a resin crack 7 is generated in this portion. I do.
一方、リードフレーム材料に銅合金を使用する場合に
は、樹脂５との線膨張係数差は小さくなるものの、他方
で、半導体素子１（線膨張係数約３×10-6/℃）との線
膨張係数差が大きくなり、半導体素子１とタブ２の接着
界面にはく離を生じやすくなる。半導体素子１とタブ２
の接着界面がはく離すると、温度低下時の半導体素子１
の熱収縮が、樹脂５及びタブ２に比べて小さいため、樹
脂５及びタブ２と半導体素子１との間には第７図に矢印
で示すような相対的なすべりが生じ、タブ２の側面にす
き間８が発生するようになる。このクラック７はタブの
タブ吊りリードのない側辺に発生しやすい。これは、タ
ブ吊りリードのある側辺は、温度低下時の樹脂５の熱収
縮によりタブ吊りリードの長手方向の収縮が拘束される
ことによりタブ自体の長手方向の熱収縮も拘束されるの
に対して、タブ吊りリードのない側辺は、タブの幅方向
の熱収縮を拘束するものがないからだと考えられる。こ
のすき間８はタブ２の下端部に応力を集中させるので、
この場合にも42アロイの場合と同様、樹脂クラツク７が
発生する。On the other hand, when a copper alloy is used as a lead frame material, the difference between the coefficient of linear expansion and the resin 5 is small, but the difference between the coefficient of linear expansion and the semiconductor element 1 (the coefficient of linear expansion is about 3 × 10 −6 / ° C.). The difference in expansion coefficient becomes large, and the adhesive interface between the semiconductor element 1 and the tab 2 is likely to peel off. Semiconductor element 1 and tab 2
When the bonding interface of the semiconductor device 1 is separated, the
7 has a smaller thermal shrinkage than the resin 5 and the tab 2, a relative slip occurs between the resin 5 and the tab 2 and the semiconductor element 1 as shown by an arrow in FIG. A gap 8 is generated. This crack 7 is likely to occur on the side of the tab where there is no tab suspension lead. This is because the longitudinal side of the tab suspending lead is restrained by the thermal contraction of the resin 5 at the time of the temperature drop, so that the thermal contraction in the longitudinal direction of the tab itself is also restrained. On the other hand, it is considered that the side without the tab suspension lead has nothing to restrict thermal contraction in the width direction of the tab. Since this gap 8 concentrates stress at the lower end of the tab 2,
In this case, as in the case of the 42 alloy, a resin crack 7 is generated.
上記のようなタブ下端部での樹脂クラツクを防止する
方法としては、従来、特開昭58−199547号公報に記載さ
れているように、タブ側辺に矩形あるいは波形などの凹
凸を設け、タブ下端部の熱応力を分散させる方法が知ら
れている。この方法は、42アロイのリードフレームを使
用した場合のように、樹脂とタブの線膨張係数差が直接
の応力発生原因となつている場合には、樹脂とタブの間
のすべりを防止できるので、樹脂クラツク防止に顕著な
効果がある。しかしながら、銅合金など、線膨張係数が
樹脂に近い材料のリードフレームに使用する場合には、
第７図に示したように、タブ側面におけるすき間の発生
が樹脂クラツクの原因となるため、あまり効果がない。As a method of preventing the resin crack at the lower end of the tab as described above, conventionally, as described in JP-A-58-199547, a rectangular or wavy irregularity is provided on the side of the tab to form the tab. A method of dispersing the thermal stress at the lower end is known. This method can prevent slippage between the resin and the tab when the difference in linear expansion coefficient between the resin and the tab directly causes stress generation, such as when a 42 alloy lead frame is used. Has a remarkable effect on preventing resin cracks. However, when used for a lead frame made of a material whose coefficient of linear expansion is close to that of resin, such as copper alloy,
As shown in FIG. 7, the formation of a gap on the side surface of the tab causes a resin crack, so that it is not so effective.
本発明の目的は、銅合金など、半導体素子との線膨張
係数差の大きい材料からなる半導体装置において、タブ
側面のすき間発生による樹脂クラツクの発生を防止する
ことにある。An object of the present invention is to prevent the occurrence of resin crack due to the generation of a gap on the side surface of a tab in a semiconductor device made of a material having a large difference in linear expansion coefficient from a semiconductor element such as a copper alloy.
上記目的はタブ側辺のうち少なくとも前記タブ吊りリ
ードのない側辺に複数の凹部を有し、この凹部のタブ側
辺に沿った方向の幅が開口部側において凹部内部よりも
狭く形成することにより達成される。The object is to form a plurality of recesses on at least the side of the tab side not having the tab suspension lead, and to form the recess in the direction along the tab side on the opening side narrower than the inside of the recess. Is achieved by
上記凹部は半導体装置組立時に樹脂によつて満たさ
れ、樹脂と強固にかみ合うので、装置の温度が低下して
も樹脂及びタブと半導体素子との間には第７図に矢印で
示すような相対すべりは生ぜず、タブの側面にすき間も
発生しない。上記凹部は少なくともすき間が発生しやす
いタブ吊りリードのない側辺に設けられているので効果
的に作用する。The recesses are filled with the resin at the time of assembling the semiconductor device and are firmly engaged with the resin. Therefore, even if the temperature of the device is reduced, the relative position between the resin and the tab and the semiconductor element as indicated by an arrow in FIG. No slippage and no gaps on the sides of the tabs. The recess works effectively because it is provided at least on the side where there is no tab suspension lead where a gap easily occurs.
以下、本発明の実施例を図面によつて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例である半導体装置用リー
ドフレームのタブ部分を示す平面図である。タブ２の側
辺にはエツチングあるいはプレスなどの方法によつて台
形状の凹凸９が形成されており、その凹部9aの形状は、
その開口部が内部よりも狭くなるように形成されてい
る。タブ側辺の形状をこのように形成することによつ
て、タブ２の側面と樹脂５との間には強固な結合が得ら
れ、タブ２側面のすき間発生を防止することができる。FIG. 1 is a plan view showing a tab portion of a lead frame for a semiconductor device according to one embodiment of the present invention. The trapezoidal unevenness 9 is formed on the side of the tab 2 by a method such as etching or pressing, and the shape of the concave portion 9a is as follows.
The opening is formed so as to be narrower than the inside. By forming the shape of the side of the tab in this manner, a strong connection is obtained between the side surface of the tab 2 and the resin 5, and it is possible to prevent the generation of a gap on the side surface of the tab 2.
タブ側辺の凹凸９を設ける位置は、第１図に示したよ
うな、半導体装置の長手方向に沿つた２辺だけでなく、
４辺の全周としてもよく、これとは逆に、樹脂クラツク
の発生が問題となる特定箇所のみに凹部を設けたもので
も良い。The position where the unevenness 9 on the side of the tab is provided is not limited to two sides along the longitudinal direction of the semiconductor device as shown in FIG.
The entire periphery of the four sides may be used. Conversely, a concave portion may be provided only at a specific location where the occurrence of resin crack is a problem.
タブ２の側辺における凹凸９の形状も、凹部9aの開口
部の幅が内部より狭くなる形状であれば、第２図の
ａ）,b）に示すように、部分円弧状，部分円弧と直接の
組合せ形状など任意の形状であつてよい。As long as the shape of the unevenness 9 on the side of the tab 2 is a shape in which the width of the opening of the concave portion 9a is smaller than the inside, as shown in a) and b) of FIG. Any shape such as a direct combination shape may be used.
また、第２図のｃ）に示すように、幅を狭くする部分
をタブ２の板厚方向の一部だけとしても同様の効果を得
ることができる。この場合には、予め矩形などの凹凸を
付したタブの端部をプレス加工することによつても製作
できる。Further, as shown in FIG. 2 (c), the same effect can be obtained even if the portion for reducing the width is only a part of the tab 2 in the thickness direction. In this case, it can also be manufactured by pressing an end portion of a tab having irregularities such as a rectangle in advance.
さらに、第２図のｄ）に示すように、タブ最外部より
やや内側に入つた位置において最も幅が狭くなるように
しても、上記と同様の効果を得ることができる。この場
合には、凹凸９の輪郭を滑らかな曲線とすることができ
るので、凹凸９自体による応力集中を低減することがで
きる。Further, as shown in FIG. 2D, the same effect as described above can be obtained even when the width is narrowest at a position slightly inside the outermost tab. In this case, since the contour of the unevenness 9 can be a smooth curve, stress concentration due to the unevenness 9 itself can be reduced.
第３図は本発明の他の実施例であり、半導体装置用リ
ードフレームのタブ部分を反素子搭載面から見た斜視図
を示している。タブ２の側辺に凹凸９を設けると、半導
体素子固定時に接着剤が凹部9aに流入し易くなる。これ
を防ぐには、より大きいタブ２を用いれば良いが、限ら
れた半導体装置寸法内でタブ２を大きくすることは難し
い。このため、本実施例では、半導体素子搭載面の凹部
の深さをその反対面（反素子搭載面）よりも浅くしてい
る。これによつて、上記問題を解決している。FIG. 3 shows another embodiment of the present invention, and is a perspective view of a tab portion of a lead frame for a semiconductor device as viewed from an opposite element mounting surface. When the unevenness 9 is provided on the side of the tab 2, the adhesive easily flows into the recess 9a when the semiconductor element is fixed. To prevent this, a larger tab 2 may be used, but it is difficult to enlarge the tab 2 within a limited semiconductor device size. For this reason, in the present embodiment, the depth of the concave portion on the semiconductor element mounting surface is made shallower than the opposite surface (anti-element mounting surface). This solves the above problem.
第４図は、本発明のさらに他の実施例による半導体装
用リードフレームのタブ部分を、反素子搭載面側から見
た斜視図である。この場合には、タブ２の反素子搭載面
2b側にのみ凹部9aが設けられている。このように凹部9a
を形成することによつて、タブ２の素子搭載面2a側に何
ら影響を及ぼすことなく、タブ２側面の樹脂５との結合
を強固にできるので、半導体素子１の固定が容易になる
とともに、タブ２の寸法が許容する最大限の寸法の半導
体素子１を搭載することができる。FIG. 4 is a perspective view of a tab portion of a semiconductor mounting lead frame according to still another embodiment of the present invention as viewed from the side opposite to the element mounting surface. In this case, the opposite element mounting surface of the tab 2
The recess 9a is provided only on the side 2b. Thus, the recess 9a
By forming the above, the coupling with the resin 5 on the side surface of the tab 2 can be strengthened without any influence on the element mounting surface 2a side of the tab 2, so that the semiconductor element 1 can be easily fixed and The semiconductor element 1 having the maximum size allowed by the size of the tab 2 can be mounted.
以上述べたように、本発明によれば、タブ側面の樹脂
との界面におけるすき間の発生を防止できるので、樹脂
クラツクの発生を防止することができる。As described above, according to the present invention, the occurrence of a gap at the interface between the tab side surface and the resin can be prevented, so that the occurrence of resin crack can be prevented.
第１図は本発明の一実施例による半導体装置用リードフ
レームのタブ部分を示す斜視図、第２図は本発明の他の
実施例による半導体装置用リードフレームの、タブ側辺
に形成する凹凸形状の例を示す図、第３図および第４図
は本発明のさらに他の実施例による半導体装置用リード
フレームのタブ部分を示す斜視図、第５図は従来の半導
体装置用リードフレームを使用した樹脂封止型半導体装
置の平面図、第６図及び第７図は従来の半導体装置用リ
ードフレームを使用した樹脂封止型半導体装置の樹脂ク
ラツク発生メカニズムを説明するための要部断面側面図
である。 １……半導体素子、２……タブ、３……リード、４……
金属細線、５……樹脂、６……タブ吊りリード、７……
樹脂クラツク、８……すき間、９……凹凸、9a……凹
部、10……リードフレーム。FIG. 1 is a perspective view showing a tab portion of a semiconductor device lead frame according to one embodiment of the present invention, and FIG. 2 is an unevenness formed on a tab side of a semiconductor device lead frame according to another embodiment of the present invention. FIGS. 3 and 4 are perspective views showing a tab portion of a semiconductor device lead frame according to still another embodiment of the present invention, and FIG. 5 is a diagram showing a conventional semiconductor device lead frame. FIGS. 6 and 7 are plan views of a resin-encapsulated semiconductor device, and FIGS. 6 and 7 are cross-sectional side views of an essential part for explaining a resin crack generation mechanism of a resin-encapsulated semiconductor device using a conventional semiconductor device lead frame. It is. 1 ... semiconductor element, 2 ... tab, 3 ... lead, 4 ...
Thin metal wire, 5 ... resin, 6 ... tab suspension lead, 7 ...
Resin crack, 8 ... gap, 9 ... unevenness, 9a ... recess, 10 ... lead frame.
フロントページの続き (72)発明者 北野 誠 土浦市神立町502番地 株式会社日立製 作所機械研究所内 (72)発明者 立道 昭弘 土浦市神立町502番地 株式会社日立製 作所機械研究所内 (72)発明者 河合 末男 土浦市神立町502番地 株式会社日立製 作所機械研究所内 (72)発明者 村上 元 小平市上水本町1450番地 株式会社日立 製作所武蔵工場内 (56)参考文献 特開 昭58−199547（ＪＰ，Ａ) 実願 昭56−58020号（実開 昭57− 170561号）の願書に添付した明細書及び 図面の内容を撮影したマイクロフィルム （ＪＰ，Ｕ)Continued on the front page (72) Inventor Makoto Kitano 502 Kandate-cho, Tsuchiura-shi, Hitachi, Ltd.Mechanical Research Laboratories, Ltd. Inventor Sueo Kawai 502 Kandate-cho, Tsuchiura-shi Inside Hitachi, Ltd.Machine Research Institute Co., Ltd. -199547 (JP, A) Practical application Microfilm (JP, U) photographing the contents of the specification and drawings attached to the application of Japanese Patent Application No. 56-58020 (Japanese Utility Model Application No. 57-170561)
Claims (1)
た平板状のタブと、このタブの側辺に設けられたタブ吊
りリードと、前記半導体素子の端子と電気接続されたイ
ンナーリードを備え、前記半導体素子の線膨張係数Esと
前記タブの線膨張係数Etと前記封止樹脂の線膨張係数Er
との関係が （Et−Es）＞（Er−Et）であり、 前記タブ側辺のうち少なくとも前記タブ吊りリードのな
い側辺に複数の凹部を有し、この凹部のタブ側辺に沿っ
た方向の幅が開口部側において凹部内部よりも狭く形成
されているとを特長とする半導体装置。1. A semiconductor device comprising: a semiconductor element; a flat tab on which the semiconductor element is mounted; a tab suspension lead provided on a side of the tab; and an inner lead electrically connected to a terminal of the semiconductor element. , The linear expansion coefficient Es of the semiconductor element, the linear expansion coefficient Et of the tab, and the linear expansion coefficient Er of the sealing resin.
And (Et−Es)> (Er−Et), wherein the tab side has at least a plurality of recesses on the side without the tab suspension lead, and the recess along the tab side of the recess. A semiconductor device characterized in that the width in the direction is formed narrower on the opening side than on the inside of the recess.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61094518A JP2569008B2 (en) | 1986-04-25 | 1986-04-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61094518A JP2569008B2 (en) | 1986-04-25 | 1986-04-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62252159A JPS62252159A (en) | 1987-11-02 |
| JP2569008B2 true JP2569008B2 (en) | 1997-01-08 |
Family
ID=14112546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61094518A Expired - Fee Related JP2569008B2 (en) | 1986-04-25 | 1986-04-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2569008B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5021864A (en) * | 1989-09-05 | 1991-06-04 | Micron Technology, Inc. | Die-mounting paddle for mechanical stress reduction in plastic IC packages |
| JPH0992776A (en) * | 1995-09-28 | 1997-04-04 | Mitsubishi Electric Corp | Lead frame and semiconductor device |
| JP3051376B2 (en) | 1998-08-24 | 2000-06-12 | 松下電子工業株式会社 | Lead frame, method for manufacturing the same, and semiconductor device using lead frame |
| JP2008034416A (en) * | 2006-07-26 | 2008-02-14 | Denso Corp | Semiconductor device |
| JP5401242B2 (en) * | 2009-09-30 | 2014-01-29 | 新電元工業株式会社 | Semiconductor package and manufacturing method thereof |
| KR101186030B1 (en) | 2010-08-24 | 2012-09-25 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor device and fabricating method thereof |
| JP6210818B2 (en) | 2013-09-30 | 2017-10-11 | 三菱電機株式会社 | Semiconductor device and manufacturing method thereof |
| JP2017201726A (en) * | 2017-08-16 | 2017-11-09 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6223096Y2 (en) * | 1981-04-20 | 1987-06-12 | ||
| JPS58199547A (en) * | 1982-05-17 | 1983-11-19 | Hitachi Ltd | Lead frame |
-
1986
- 1986-04-25 JP JP61094518A patent/JP2569008B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62252159A (en) | 1987-11-02 |
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