JPS6056309B2 - Lead frame and its manufacturing method - Google Patents
Lead frame and its manufacturing methodInfo
- Publication number
- JPS6056309B2 JPS6056309B2 JP55161174A JP16117480A JPS6056309B2 JP S6056309 B2 JPS6056309 B2 JP S6056309B2 JP 55161174 A JP55161174 A JP 55161174A JP 16117480 A JP16117480 A JP 16117480A JP S6056309 B2 JPS6056309 B2 JP S6056309B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- substrate support
- layer
- resin
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】
本発明は、電力用樹脂封止型半導体装置等で使用され
るリードフレームならびにこれを製造する方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame used in a resin-sealed semiconductor device for electric power, and a method for manufacturing the lead frame.
樹脂封止型半導体装置は、通常リードフレームを用い
て半導体素子組立構体を形成し、これを樹脂によつて封
した構造となつている。A resin-sealed semiconductor device usually has a structure in which a semiconductor element assembly structure is formed using a lead frame, and this is sealed with resin.
この樹脂封止型半導体装置における１つの問題は、成型
用樹脂の熱伝導度が低いため、動作時に発生する熱の放
散が十分でなく、電力損失が１０ワット程度に達 、
→ 鐸掌鴎」」れす、Ｉ’ １槽−ｉＬＬ、レμ江１
＾ャ＋フで口 Ｌ゛ｒｒコ±Ｊ４ｊ、、１、一 ↓ る
。この問題を解決するため、半導体基板の支持部となる
部分に放熱板を兼ねさせるようにしたリードフレームが
提案されるに至つている。 第１図は、かかるリードフ
レームの構造をパワートランジスタ用リードフレームを
例に示す図であり、ａは平面図、をは第１図ａ（１）Ｂ
−Ｂ線に沿つた断面図である。One problem with this resin-sealed semiconductor device is that the heat generated during operation is not sufficiently dissipated due to the low thermal conductivity of the molding resin, resulting in power loss of about 10 watts.
→ Takusho-o” “Resu, I' 1 tank-iLL, Lemue 1
＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾＾ from the mouth L゛rrko±J4j,,1,1 ↓. In order to solve this problem, lead frames have been proposed in which a portion that serves as a support for a semiconductor substrate also serves as a heat sink. FIG. 1 is a diagram showing the structure of such a lead frame using a lead frame for a power transistor as an example, where a is a plan view and FIG.
- It is a sectional view along the B line.
このリードフレームは、熱伝導の良好な銅などの金属板
に打ち抜き加工を施すことによつて形成されるものであ
り、移送ピッチを決定する孔１をもつ共通連結部２から
、同一方向へ向けて導出されるコレクタリード３、ベー
スリード４ならびにエミッタリード５ならびにコレクタ
リード３の先端部に繋る基板支持部６とによつてトラン
ジスタの組立部が形成される。このトランジスタの組立
部が共通連結部２によつて多数連結され、また、個々の
基板支持部の変形を避けるために、基板支持部相互間が
連結細条７によつて連結された構造となつている。なお
、８は、完成した樹脂封止型半導体装置を外部放熱体へ
とり”つける際にねじ等が挿通される孔である。 第１
図をで示すように、リード部の厚みにくらべて基板支持
部６の厚みが大きくなつているが、これは基板支持部６
を放熱板そのものとして積極的に利用とする意図に基く
ものである。このよう・な構造とするためには、打ち抜
き加工を施すり一ドフレーム用原板の厚みを予め２部分
で異らせておけばよい。第２図は、上記のリードフレー
ムを用いて形成した樹脂封止型パワートランジスタの断
面構造を示す図であり、基板支持部６へ半田９″等を介
してトランジスタ素子９を接着するとともに、トランジ
スタ素子９の電極とベースリードならびにエミッタリー
ドとの間を金属細線１０で接続したのち、樹脂１１によ
つて封止して樹脂封止パワートランジスタが形成されて
いるが、図示するように、基板支持部６の裏面ならびに
先端部分を露出させる関係を成立させて樹脂封止がなさ
れている。This lead frame is formed by punching a metal plate such as copper, which has good thermal conductivity, and is formed by punching metal plates such as copper that have good thermal conductivity. The collector lead 3, the base lead 4, the emitter lead 5, and the substrate support part 6 connected to the tip of the collector lead 3 form a transistor assembly. A large number of assembly parts of this transistor are connected by a common connecting part 2, and in order to avoid deformation of the individual substrate supporting parts, the substrate supporting parts are connected to each other by connecting strips 7. ing. Note that 8 is a hole through which a screw or the like is inserted when attaching the completed resin-sealed semiconductor device to an external heat sink.
As shown in the figure, the thickness of the board support part 6 is larger than the thickness of the lead part;
This is based on the intention of actively using the heat sink as a heat sink itself. In order to obtain such a structure, it is sufficient to punch out the original plate for the frame and make the thicknesses of the two parts different in advance. FIG. 2 is a diagram showing a cross-sectional structure of a resin-sealed power transistor formed using the lead frame described above, in which the transistor element 9 is bonded to the substrate support portion 6 via solder 9'' or the like, and the transistor A resin-sealed power transistor is formed by connecting the electrode of the element 9 and the base lead and emitter lead with a thin metal wire 10 and then sealing it with a resin 11. The resin sealing is performed in such a manner that the back surface and the tip portion of the portion 6 are exposed.
従来のリードフレームでは、上記のように基板支持部６
が放熱板を兼ねるところとなり、したがつて、この部分
で効果的に熱の放熱がなされる。In the conventional lead frame, as described above, the substrate support part 6
This portion also serves as a heat sink, and therefore heat is effectively radiated from this portion.
また、基板支持部６の露呈する裏面を外部放熱体へ熱的
に結合させるならば、放熱効果はよソー層大きくなる。
しかしながら、従来のリードフレームでは基板支持部６
がトランジスタのコレクタと電気的に接続されるため、
外部放熱体Ａへの取り付けに際して両者間を電気的に絶
縁する必要があり、両者間に別体の絶縁シートＢ″など
を介在させることが不可避となる。図示したリードフレ
ームによれば、電力損失に関する問題の解決ははかれる
ものの、上記のようにこのリードフレームを用いて形成
した半導体装置の実装時にわずられしさが生じるだかり
でなく、絶シートＢ″の位置決めが不正確であると絶縁
性が損われ、短絡事故を起すおそれもあつた。Moreover, if the exposed back surface of the substrate support part 6 is thermally coupled to an external heat sink, the heat radiation effect will be increased.
However, in the conventional lead frame, the substrate support part 6
is electrically connected to the collector of the transistor, so
When attaching to the external heat sink A, it is necessary to electrically insulate the two, and it is unavoidable to interpose a separate insulating sheet B'' between the two.According to the lead frame shown in the figure, power loss is Although this problem can be solved, it is difficult to mount the semiconductor device formed using this lead frame as described above, and if the positioning of the insulation sheet B'' is inaccurate, the insulation properties There was also a risk of damage and a short-circuit accident.
本発明は、以上説明した従来のリードフレームに存在し
た問題点の排除を意図してなされたもので、リードフレ
ームの基板支持部を、第１の金属層、絶縁層ならびに第
２の金属層の３層構造からなる積層板となすとともに、
第１の金属層を基板！支持部外まで延在させ、この金属
層により外部リードを形成するようにしたリードフレー
ムとその製造方法を提供するものである。以下に図面を
参照して本発明の詳細な説明する。The present invention has been made with the intention of eliminating the problems that existed in the conventional lead frame described above, and the present invention has been made with the intention of eliminating the problems that existed in the conventional lead frame described above. In addition to being a laminate board with a three-layer structure,
The first metal layer is the substrate! The present invention provides a lead frame in which external leads are formed from the metal layer and extends outside the support portion, and a method for manufacturing the lead frame. The present invention will be described in detail below with reference to the drawings.
第３図は、本発明のリードフレームの構造をｚ示す図で
あり、ａは平面図、ｂは第３図ａのＢ一Ｂ線に沿つた断
面図である。図示するように、本発明のリードフレーム
の形状ならびに構造は、第１図で示した従来のものと殆
んど同じであり、基板支持部６が、第１の金属層１２、
絶縁層１３ならびに第２の金属層１４の３層構造となつ
ている点で従来のものと相違している。FIG. 3 is a diagram showing the structure of the lead frame of the present invention in z, where a is a plan view and b is a sectional view taken along line B--B in FIG. 3a. As shown in the figure, the shape and structure of the lead frame of the present invention are almost the same as the conventional lead frame shown in FIG.
It differs from the conventional one in that it has a three-layer structure of an insulating layer 13 and a second metal layer 14.
ところで、第１の金属層１２は第３図ｂから明らかなよ
うにリードフレームの外部リードならびに共通連結部の
形成材料としても利用されるものであり、その厚みは外
部リードの厚み考慮して決定されている。By the way, as is clear from FIG. 3b, the first metal layer 12 is also used as a material for forming the external leads and common connection part of the lead frame, and its thickness is determined by taking into account the thickness of the external leads. has been done.
また、絶縁層１３はトランジスタノ素子を接着するため
の熱処理工程で特性が劣化するものであつてはならない
。この要件みたす絶縁層としては、例えばポリイミド樹
脂層が挙げられる。第４図は、以上説明したリードフレ
ームを形成．する方法を説明するための図であり、先ず
第４図ａで示すように第１の金属層となる金属板１５と
第２の金属層となる金属板１６を準備する。Further, the characteristics of the insulating layer 13 must not deteriorate during the heat treatment process for bonding the transistor elements. An example of an insulating layer that meets this requirement is a polyimide resin layer. Figure 4 shows how the lead frame described above is formed. First, as shown in FIG. 4a, a metal plate 15 that will become a first metal layer and a metal plate 16 that will become a second metal layer are prepared.
金属板１５の幅１１と厚みｔ１は得ようとするリードフ
レームの共通連結部、外部リード部ならびに基板支持部
の長さと外部リードの厚みを考慮して決定する。また、
金属板１６の卿２の厚みＴ２は、基板支持部の長さとリ
ードフレームとして完成したときの基板支持部の厚みを
考慮して決定する。次いで金属板１５と１６を絶縁層を
形成する樹脂、例えばポリイミド樹脂によつて貼合せ、
第４図ｂで示すように一部が３層構造を呈するリードフ
レーム原板を形成する。The width 11 and thickness t1 of the metal plate 15 are determined in consideration of the lengths of the common connection portion, external lead portion, and substrate support portion of the lead frame to be obtained, and the thickness of the external lead. Also,
The thickness T2 of the base 2 of the metal plate 16 is determined by taking into consideration the length of the substrate support portion and the thickness of the substrate support portion when completed as a lead frame. Next, the metal plates 15 and 16 are bonded together using a resin that forms an insulating layer, such as polyimide resin,
As shown in FIG. 4b, a lead frame original plate having a three-layer structure in part is formed.
図中１３はポリイミド樹脂層である。こののち、打ち抜
き加工を施すことによつて第４図ｃに示すようにリード
フレームが形成される。このようにして得られる本発明
のリードフレームでは、あらかじめトランジスタ素子が
接着される第１の金属層１２が絶縁層１３によつて第２
の金属層１４と電気的に絶縁されている。In the figure, 13 is a polyimide resin layer. Thereafter, a lead frame is formed by punching as shown in FIG. 4c. In the lead frame of the present invention obtained in this way, the first metal layer 12 to which the transistor element is bonded in advance is connected to the second metal layer 12 by the insulating layer 13.
It is electrically insulated from the metal layer 14 of.
したがつて、このリードフレームを用いるとともに、第
２図で示したような関係を成立させて樹脂封止して得た
樹脂封止型パワートランジスタの裏面に露呈する第２の
金属層は、従来のごとく別体の絶縁シートＢ″を用いる
ことなくトランジスタ素子とは電気的に絶縁されるとこ
ろとなり、この面を外部放熱体へ直接当接させても何等
支障をきたさない。なお、絶縁層１３の厚みは、これが
厚すぎると放熱特性面で支障があり、一方、薄すぎると
絶縁性の面で支障がある。このため、厚みの選定はこれ
らを考慮する必要があり、実験的には５０〜１１０μｍ
程度の範囲で好結果が得られた。また、絶縁層１３に気
泡あるいはピンホールがあると電気的絶縁性が損われる
ところとなるが、絶縁層１３の一部を同種の絶縁シート
するならばかかる不都合を排除する面ですぐれた効果の
発揮されることが確認された。さらに、第１の金属層と
第２の金属層の絶縁層１３に接する側の表面を酸化ある
いは窒化させることにより、電気絶縁性のよソー層の向
上がはかられること、同面を予め粗面化しておくことに
より、積層体の接着力が高められることも確認された。Therefore, the second metal layer exposed on the back surface of a resin-sealed power transistor obtained by using this lead frame and resin-sealing with the relationship shown in FIG. As shown in FIG. 13, it is electrically insulated from the transistor element without using a separate insulating sheet B'', and there is no problem even if this surface is brought into direct contact with an external heat sink. Note that the insulating layer 13 If the thickness of the ~110μm
Good results were obtained within a range of degrees. In addition, if there are bubbles or pinholes in the insulating layer 13, the electrical insulation will be impaired, but if a part of the insulating layer 13 is made of the same type of insulating sheet, it is highly effective in eliminating such disadvantages. It has been confirmed that it works. Furthermore, by oxidizing or nitriding the surfaces of the first metal layer and the second metal layer that are in contact with the insulating layer 13, the electrically insulating properties of the layer can be improved. It was also confirmed that the adhesive strength of the laminate was increased by making it planar.
以上説明したところから明らかなように本発明によれば
、実装時のわずられしさをことごとく排除することので
きる電力用樹脂封止型半導体装置が実現され、半導体装
置の製造、組立に大なる工業的価値を有する。As is clear from the above explanation, according to the present invention, a power resin-encapsulated semiconductor device that can completely eliminate the troublesomeness during mounting is realized, which greatly improves the manufacturing and assembly of semiconductor devices. Has industrial value.
なお、実施例ではパワートランジスタ用リードフレーム
を例示したが、本発明はこの例に限られるものではない
。In addition, although the lead frame for power transistors was illustrated in the Example, the present invention is not limited to this example.
第１図Ａ，ｂは従来のリードフレームの構造を示す平面
図、Ｂ−Ｂ線断面図、第２図は同リードフレームを用い
て形成された樹脂封止型パワートランジスタの断面図、
第３図ａは本発明の一実施例リードフレームの平面構造
を示す図、同ｂはａのＢ−Ｂ線断面図、第４図はａ−ｃ
本発明のリードフレームの製造方法を説明するための製
造工程図である。
１・・・・・・移送ピッチ決定用の孔、２・・・・・・
共通連結部、３・・・・・・コレクタリード、４・・・
・・・ベースリード、５・・・・・・エミッタリード、
６・・・・・基板支持部、７・・・・・・連結細条、８
・・・・・とりつけ用の孔、９・・・トランジスタ素子
、１０・・・・・・金属細線、１１・・・樹脂、１２・
・・・・・第１の金属層、１３・・・・・絶縁層、１４
・・・・・・第２の金属層、１５，１６・・・・・リー
ドフレーム原板形成用の金属板。FIGS. 1A and 1B are plan views showing the structure of a conventional lead frame, and a cross-sectional view taken along the line B-B. FIG. 2 is a cross-sectional view of a resin-sealed power transistor formed using the same lead frame.
FIG. 3a is a diagram showing the planar structure of a lead frame according to an embodiment of the present invention, FIG. 3b is a sectional view taken along the line B-B of a, and FIG.
FIG. 3 is a manufacturing process diagram for explaining a method for manufacturing a lead frame according to the present invention. 1... Hole for determining the transfer pitch, 2...
Common connection part, 3... Collector lead, 4...
...Base lead, 5...Emitter lead,
6...Substrate support part, 7...Connection strip, 8
...Mounting hole, 9...Transistor element, 10...Metal thin wire, 11...Resin, 12...
...First metal layer, 13...Insulating layer, 14
...Second metal layer, 15, 16...Metal plate for forming lead frame original plate.
Claims (1)
に第２の金属層の３層構造からなる積層板で形成され、
外部リード部ならびに共通連結部が前記第１の金属層の
延在部で形成されていることを特徴とするリードフレー
ム。 ２ 基板支持部、外部リード部および共通連結部の３部
を打ち抜くことが可能な面積をもつ第１の金属板の前記
基板支持部打ち抜き領域部分に、耐熱性絶縁接着材を用
いて第２の金属板を貼着して前記基板支持部打ち抜き領
域部分のみ３層構造とした原板を形成し、次いで同原板
に打ち抜き加工を施すことを特徴とするリードフレーム
の製造方法。[Claims] 1. The semiconductor substrate support part is formed of a laminate having a three-layer structure of a first metal layer, an insulating layer, and a second metal layer,
A lead frame characterized in that an external lead portion and a common connection portion are formed by an extension of the first metal layer. 2. A heat-resistant insulating adhesive is used to attach a second metal plate to the substrate support punching region of the first metal plate, which has an area that allows punching out the three parts of the substrate support, the external lead portion, and the common connection portion. A method for producing a lead frame, comprising: pasting a metal plate to form an original plate having a three-layer structure only in the punched region of the substrate support portion, and then punching the original plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161174A JPS6056309B2 (en) | 1980-11-14 | 1980-11-14 | Lead frame and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55161174A JPS6056309B2 (en) | 1980-11-14 | 1980-11-14 | Lead frame and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5784156A JPS5784156A (en) | 1982-05-26 |
| JPS6056309B2 true JPS6056309B2 (en) | 1985-12-09 |
Family
ID=15729986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55161174A Expired JPS6056309B2 (en) | 1980-11-14 | 1980-11-14 | Lead frame and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6056309B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61121109U (en) * | 1985-01-12 | 1986-07-30 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2632100B1 (en) * | 1988-05-25 | 1992-02-21 | Schlumberger Ind Sa | PROCESS FOR PRODUCING AN ELECTRONIC MEMORY CARD AND ELECTRONIC MEMORY CARDS OBTAINED BY IMPLEMENTING SAID METHOD |
-
1980
- 1980-11-14 JP JP55161174A patent/JPS6056309B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61121109U (en) * | 1985-01-12 | 1986-07-30 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5784156A (en) | 1982-05-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS63205935A (en) | Resin-sealed type semiconductor device equipped with heat sink | |
| JP2001156219A (en) | Semiconductor device | |
| JPH09232341A (en) | Semiconductor device | |
| JP2905609B2 (en) | Resin-sealed semiconductor device | |
| JPS6050354B2 (en) | Resin-encapsulated semiconductor device | |
| JPS6056309B2 (en) | Lead frame and its manufacturing method | |
| JPH04236434A (en) | Semiconductor device and manufacture thereof | |
| JP2564771B2 (en) | Semiconductor device with heat sink and method of manufacturing the same | |
| JPS60170248A (en) | Semiconductor device | |
| JPH05166979A (en) | Semiconductor device and manufacture thereof | |
| JPS60160624A (en) | Dielectric isolation for semiconductor chip | |
| JPH0770653B2 (en) | High power hybrid integrated circuit assembly method | |
| JPS6050355B2 (en) | Lead frame and its manufacturing method | |
| JP2815462B2 (en) | Metal laminated board | |
| JP3040235B2 (en) | Lead frame and resin-sealed semiconductor device using the same | |
| JP2822989B2 (en) | Lead frame, method of manufacturing the same, and resin-sealed semiconductor device | |
| JP2713141B2 (en) | Semiconductor device | |
| WO2022224340A1 (en) | Power semiconductor device | |
| JPS61194755A (en) | Semiconductor device | |
| JP3855941B2 (en) | Manufacturing method of semiconductor device with convex heat sink | |
| JPS61198658A (en) | Resin-sealed semiconductor device | |
| JPS6138193Y2 (en) | ||
| JPH06326227A (en) | Structure of multilayer lead frame and manufacture thereof | |
| JPS6234452Y2 (en) | ||
| JPH0590336A (en) | Tape carrier package |