JPS63233552A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63233552A
JPS63233552A JP62069416A JP6941687A JPS63233552A JP S63233552 A JPS63233552 A JP S63233552A JP 62069416 A JP62069416 A JP 62069416A JP 6941687 A JP6941687 A JP 6941687A JP S63233552 A JPS63233552 A JP S63233552A
Authority
JP
Japan
Prior art keywords
semiconductor chip
resin
sealing resin
semiconductor device
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62069416A
Other languages
Japanese (ja)
Inventor
Takehiko Matsunaga
松永　毅彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62069416A priority Critical patent/JPS63233552A/en
Publication of JPS63233552A publication Critical patent/JPS63233552A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To reduce stress from a packaging resin to the upper surface of a semiconductor chip, by making the thickness of the packaging resin at the upper surface part of the semiconductor chip thin. CONSTITUTION:A semiconductor chip 3 and a lead frame 2 are wire-bonded and thereafter packaged with a packaging resin 1. At this time, a recess part 1a, which makes the thickness of the packaging resin at the upper surface part of the chip thin, is formed. Then stress from the resin 1 to a circuit on the surface of the chip 3 is alleviated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置、特に樹脂封止型半導体装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, particularly a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

第３図、第４図は従来の樹脂封止型半導体装置を示す外
観斜視図および側面図である。これらの図において、１
は封止樹脂で、第４図に示すように、外部と導通させる
ためのフレームリード２と半導体チップ３とをワイヤ４
で接続した後、樹脂封止したものである。3 and 4 are an external perspective view and a side view showing a conventional resin-sealed semiconductor device. In these figures, 1
is a sealing resin, and as shown in FIG.
After connecting them, they were sealed with resin.

第４図に示すように従来の封止樹脂１は、半導体チップ
３表面の上部の厚みが厚く、半導体チップ３．封止樹脂
１．フレームリード２のそれぞれの膨張係数の違いによ
り応力が生じ、半導体チップ３表面上に加わる応力は、
封止樹脂１の厚さが増すに従い大きくなっていた。As shown in FIG. 4, the conventional sealing resin 1 is thicker at the upper part of the surface of the semiconductor chip 3. Sealing resin 1. Stress is generated due to the difference in expansion coefficient of each frame lead 2, and the stress applied on the surface of the semiconductor chip 3 is
The size increased as the thickness of the sealing resin 1 increased.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の半導体装置は、以上のように構成されているので
、半導体チップ３表面上への封止樹脂１からの応力が大
きく、半導体チップ３表面上に配線されている回路が、
スライドを生じたり、クラックを生じ、温度の急峻な変
化に対する信頼性を低下させていた。Since the conventional semiconductor device is configured as described above, the stress from the sealing resin 1 on the surface of the semiconductor chip 3 is large, and the circuits wired on the surface of the semiconductor chip 3 are
This caused sliding and cracking, reducing reliability against sudden changes in temperature.

この発明は、上記のような問題点を解消するためになさ
れたもので、封止樹脂からの応力を緩和し、温度の急峻
な変化に対して、半導体チップ表面上のスライド、クラ
ックの発生率を低減した半導体装置を得ることを目的と
している。This invention was made in order to solve the above-mentioned problems, and it alleviates the stress from the sealing resin and reduces the incidence of sliding and cracking on the surface of semiconductor chips in response to sudden changes in temperature. The objective is to obtain a semiconductor device with reduced .

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、樹脂封止された半導体チ
ップ上部の封止樹脂の厚みを薄くするための凹形部を形
成したものである。The semiconductor device according to the present invention has a concave portion formed in order to reduce the thickness of the sealing resin above the resin-sealed semiconductor chip.

（作用〕 この発明においては、半導体チップの上面部分の封止樹
脂の厚みを薄くしたことから、強度的には従来のものと
変らず、半導体チップ表面上へ加わる応力が緩和される
。(Function) In this invention, since the thickness of the sealing resin on the upper surface of the semiconductor chip is reduced, the stress applied to the surface of the semiconductor chip is alleviated, while the strength remains the same as in the conventional case.

〔実施例〕〔Example〕

以下、この発明の一実施例を第１図、第２図について説
明する。An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

これらの図において、１〜４は、第３図、第４図と同じ
ものであり、１ａは前記半導体チップ３の上面部分の封
止樹脂１の厚みを薄くするために封止樹脂１の上面に形
成した凹形部である。In these figures, 1 to 4 are the same as those in FIGS. 3 and 4, and 1a is the upper surface of the encapsulating resin 1 in order to reduce the thickness of the encapsulating resin 1 on the upper surface of the semiconductor chip 3. This is a concave portion formed in the

上記のように、半導体チップ３の上面部分ガ封止樹脂１
の厚さを薄くすることにより、封止樹脂１の厚さに比例
する応力を緩和させることができ、半導体チップ３表面
上の回路への封止樹脂１からの応力を緩和できる。As described above, the upper surface portion of the semiconductor chip 3 is sealed with the sealing resin 1.
By reducing the thickness of the sealing resin 1, stress proportional to the thickness of the sealing resin 1 can be relaxed, and stress from the sealing resin 1 to the circuits on the surface of the semiconductor chip 3 can be relaxed.

なお、上記実施例ではデュアルインライン形半導体装置
を例にとって説明したが、シングルインライン等類似構
造の半導体装置すべてに適用可能である。Note that although the above embodiment has been explained by taking a dual in-line type semiconductor device as an example, the present invention is applicable to all semiconductor devices having a similar structure such as a single in-line type.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、半導体チップの上面
部分の封止樹脂の厚みを薄くしたので、封止樹脂から半
導体チップ上面への応力を小さくすることができるとと
もに、封止樹脂の総量も少なくできる等の効果がある。As explained above, the present invention reduces the thickness of the encapsulating resin on the top surface of the semiconductor chip, thereby making it possible to reduce the stress from the encapsulating resin to the top surface of the semiconductor chip, and also to reduce the total amount of encapsulating resin. It has the effect of reducing the amount of water used.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの発明の一実施例を示す半導体装置の外観斜
視図、第２図は、第１図の側面図、第３図は従来の半導
体装置を示す外観斜視図、第４図は、第３図の側面図で
ある。 図において、１は封止樹脂、１ａは凹形部、２はフレー
ムリード、３は半導体チップ、４はワイヤである。 なお、各図中の同一符号は同一または相当部分を示す。 代理人　大　岩　増　雄　　　　（外２名）第１図 第２図 第３図 第４図FIG. 1 is an external perspective view of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a side view of FIG. 1, FIG. 3 is an external perspective view of a conventional semiconductor device, and FIG. FIG. 4 is a side view of FIG. 3; In the figure, 1 is a sealing resin, 1a is a concave portion, 2 is a frame lead, 3 is a semiconductor chip, and 4 is a wire. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップとフレームリードとがワイヤボンディン
グされた後、封止樹脂により樹脂封止された半導体装置
において、前記半導体チップ上面部分の封止樹脂の厚み
を薄くするための凹形部を形成したことを特徴とする半
導体装置。In a semiconductor device that is resin-sealed with a sealing resin after a semiconductor chip and a frame lead are wire-bonded, a concave portion is formed to reduce the thickness of the sealing resin on the upper surface of the semiconductor chip. Characteristic semiconductor devices.
JP62069416A 1987-03-23 1987-03-23 Semiconductor device Pending JPS63233552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62069416A JPS63233552A (en) 1987-03-23 1987-03-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62069416A JPS63233552A (en) 1987-03-23 1987-03-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63233552A true JPS63233552A (en) 1988-09-29

Family

ID=13401983

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62069416A Pending JPS63233552A (en) 1987-03-23 1987-03-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63233552A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015144314A (en) * 2010-09-14 2015-08-06 クアルコム，インコーポレイテッド Electronic packaging with variable thickness mold cap

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015144314A (en) * 2010-09-14 2015-08-06 クアルコム，インコーポレイテッド Electronic packaging with variable thickness mold cap

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