JPH01293642A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01293642A
JPH01293642A JP12613788A JP12613788A JPH01293642A JP H01293642 A JPH01293642 A JP H01293642A JP 12613788 A JP12613788 A JP 12613788A JP 12613788 A JP12613788 A JP 12613788A JP H01293642 A JPH01293642 A JP H01293642A
Authority
JP
Japan
Prior art keywords
stress
resin
thermal expansion
expansion coefficient
die pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12613788A
Other languages
Japanese (ja)
Inventor
Masanori Obata
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12613788A priority Critical patent/JPH01293642A/en
Publication of JPH01293642A publication Critical patent/JPH01293642A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE: To eliminate a stress between a molding resin and a semiconductor chip and to relax a stress to be exerted on a die pad by a method wherein a thermal expansion coefficient of the molding resin is made nearly equal to a thermal expansion coefficient of the semiconductor chip and a hole used to relax the stress is made in the die pad.
CONSTITUTION: Roles 6 used to relax a stress are made at regular intervals in a die pad 5. A semiconductor chip 2, the die pad 5, wires 3 and one part of connection pins 4 are resin-sealed with a molding resin 1. A thermal expansion coefficient of the resin 1 is selected so as to be nearly equal to a thermal expansion coefficient of the chip 2. Then, when this assembly is cooled after the resin sealing operation, a stress to be exerted on the pad 5 from the resin 1 is scattered because the holes 6 exist. Also a stress from the chip 2 is scattered and relaxed through the holes 6. By this setup, the stress to be exerted on the pad 5 is relaxed.
COPYRIGHT: (C)1989,JPO&Japio
JP12613788A 1988-05-23 1988-05-23 Semiconductor device Pending JPH01293642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12613788A JPH01293642A (en) 1988-05-23 1988-05-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12613788A JPH01293642A (en) 1988-05-23 1988-05-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01293642A true JPH01293642A (en) 1989-11-27

Family

ID=14927589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12613788A Pending JPH01293642A (en) 1988-05-23 1988-05-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01293642A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684328A (en) * 1992-07-29 1997-11-04 Samsung Electronics Co., Ltd. Semiconductor chip package using improved tape mounting
KR100302559B1 (en) * 1998-12-31 2001-11-30 마이클 디. 오브라이언 Semiconductor Package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684328A (en) * 1992-07-29 1997-11-04 Samsung Electronics Co., Ltd. Semiconductor chip package using improved tape mounting
KR100302559B1 (en) * 1998-12-31 2001-11-30 마이클 디. 오브라이언 Semiconductor Package

Similar Documents

Publication Publication Date Title
JPH04306865A (en) Semiconductor device and manufacture thereof
JPH04214643A (en) Resin-sealed semiconductor device
JPH01293642A (en) Semiconductor device
JPS62115834A (en) Semiconductor sealing device
JPS5814557A (en) Semiconductor device
EP0401017A3 (en) Method of producing a post molded cavity package with internal dam bar for integrated circuit
JPH04317363A (en) Resin sealed semiconductor device without die pad and its manufacturing method
JPH03228339A (en) Bonding tool
JPH02144946A (en) Semiconductor device
JPH0318048A (en) Semiconductor device
JPS6380554A (en) Resin-sealed semiconductor device
JPH04262543A (en) Die bonding device
JPH01278757A (en) Lead frame
JPH0338842A (en) Semiconductor device
JPS54578A (en) Resin seal semiconductor device
JPH03152966A (en) Semiconductor device lead frame
JPH04307760A (en) Resin-sealed semiconductor device
JPH02218143A (en) Semiconductor device and manufacture thereof
JPH0378246A (en) Resin-sealed type semiconductor device
JPS63182841A (en) Semiconductor device
JPH0294463A (en) Semiconductor device
JPH04100250A (en) Manufacture of semiconductor device
JPH0371646A (en) Semiconductor device and its manufacture
JPH03192735A (en) Semiconductor device and manufacture thereof
JPS63156346A (en) Lead frame