JP5378693B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the inter-chip signal quality of a semiconductor device having a plurality of semiconductor chips. <P>SOLUTION: A microcomputer chip 1 and a memory chip 2 are loaded on a wiring board 3, and the microchip 1 and the memory chip 2 are connected, and a first wiring 3d formed on the wiring board 3 includes three signal lines 3e and a GND line 3f arranged at both the sides of the three signal lines 3e, and the three signal lines 3e are arranged so as to be interposed by the two GND lines 3f in the first wiring 3d so that the impedance of the signal lines 3e is maintained by reducing the L of the signal lines 3e in the first wiring 3d. Thus, the inter-chip signal quality is improved in the semiconductor device by maintaining the miniaturization of a semiconductor device (BGA8) having a plurality of semiconductor chips. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device on which a microcomputer chip and a memory chip are mounted.

  As a semiconductor device having a plurality of semiconductor devices (semiconductor chips) mounted on a mounting substrate, a plurality of semiconductor memory devices that are operated in synchronization with a clock signal and a semiconductor data processing device that controls access to the semiconductor memory devices are mounted. There is a semiconductor device technology of a system-in-package mounted on a substrate and a ball grid array type (for example, see Patent Document 1).

Further, in a multi-chip semiconductor device in which a plurality of element chips are mounted in one package, a plurality of element chips and a film circuit are mounted on an island of a lead frame, an intermediate wiring and an element chip provided in the film circuit, and There is a technique for connecting an external lead of a lead frame with a thin metal wire (see, for example, Patent Document 2).
JP 2006-237385 A Japanese Patent Laid-Open No. 9-232500

  In recent years, with the miniaturization of electronic devices such as portable telephones, there is an increasing demand for miniaturization of semiconductor devices mounted inside the electronic devices. In order to realize this requirement, for example, as shown in Patent Document 1 (Japanese Patent Laid-Open No. 2006-237385), a microcomputer semiconductor chip (microcomputer chip) and a memory semiconductor chip (memory chip) are combined into one package. There has been proposed a SIP (System In Package) technology that is mounted in a (semiconductor device) and constitutes a system.

  In recent years, with the aim of easily responding to changes in capacity and reducing the manufacturing cost of packages, there is a tendency for microcomputer chips to be installed on the market and memory chips to be installed on the market. is there. This eliminates the need for a new capital investment for manufacturing a memory-based semiconductor chip, thereby reducing the manufacturing cost of the package.

  However, when a microcomputer chip for internal sales and a memory chip for external sales are mixed in one package, if signals are input / output between the respective semiconductor chips (hereinafter also simply referred to as chips), the semiconductor chip side of the internal sales products 42, when the signal waveform rises (or falls), as shown in the comparative example of FIG. 42, ringing (a wavy waveform generated when a signal having a sharp change such as a square wave passes through the circuit network) There has occurred. This ringing caused an overshoot (or an undershoot in which the signal waveform temporarily falls below the specified range 9) where the signal waveform temporarily exceeds the specified range (signal level at which the chip normally operates) 9. .

  Therefore, the inventor of the present application examined the reason why the overshoot (or undershoot) occurred on the chip side of the internally sold product.

  As a result, overshooting due to ringing is likely to occur particularly when an internally sold chip and an externally sold chip (memory chip) are mounted in a SIP package (SIP product). discovered.

  This was found to be due to the difference in manufacturing process and quality standards between internally sold chips and externally sold chips.

  In other words, the externally sold chip has an I / O output level so that a signal can be reliably transmitted to a chip mounted at a distant position on the mounting substrate on which the externally sold chip is mounted. Often designed high. However, in the case of a SIP product, since the arrangement distance (transmission path) between the signal supply destination chip (microcomputer chip) and the memory chip is very close, a signal with a high output level is supplied from the memory chip to the microcomputer chip. As a result, strong ringing occurs in the receiving microcomputer chip, which causes overshoot (or undershoot).

  If an overshoot (or undershoot) occurs, an element (circuit) formed on the chip may be broken, and therefore it is necessary to suppress ringing that causes overshoot (or undershoot).

  In addition, in the said patent document 1 and the said patent document 2 (Unexamined-Japanese-Patent No. 9-232500), in order to suppress the ringing generate | occur | produced in the SIP type package which mixedly mounted the chip | tip of the external sales goods and the chip | There is no description about specific means.

  An object of the present invention is to provide a technique capable of improving signal quality between chips in a semiconductor device having a plurality of semiconductor chips.

  Another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device having a plurality of semiconductor chips.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a wiring board having a main surface on which a plurality of first bonding leads and a plurality of second bonding leads are formed, and a back surface opposite to the main surface, and a main electrode on which a plurality of electrode pads are formed. A first semiconductor chip mounted on the main surface of the wiring board, and a main surface formed with a plurality of electrode pads, and mounted on the main surface of the wiring board. Two semiconductor chips, a plurality of first conductive members that electrically connect the plurality of electrode pads of the first semiconductor chip and the plurality of first bonding leads of the wiring board, respectively, and the second semiconductor chip A plurality of second conductive members for electrically connecting the plurality of electrode pads and the plurality of second bonding leads of the wiring board, respectively, and the plurality of first bondings formed on the wiring board. A plurality of wirings that electrically connect each of the first and second bonding leads, the first semiconductor chip, the second semiconductor chip, the plurality of first conductive members, and the plurality of second conductives. An I / O output level in the second semiconductor chip is higher than an I / O output level in the first semiconductor chip, and the plurality of wirings include: It has a plurality of signal lines and a plurality of GND lines.

  Further, the present invention provides a wiring board having a main surface and a back surface, a first semiconductor chip mounted on the main surface of the wiring board, mounted on the main surface of the wiring board, and the first A second semiconductor chip having an I / O output level higher than that of the semiconductor chip; and a signal line formed on the wiring board and electrically connecting the first semiconductor chip and the second semiconductor chip. . Further, according to the present invention, a metallized electrode to which a GND potential is supplied is formed on the back surface of the first semiconductor chip, and the signal line faces the metallized electrode on the back surface side of the first semiconductor chip. Formed on the main surface.

  The present invention also provides a first semiconductor chip having an electrode pad formed on the main surface and having an input / output circuit electrically connected to the electrode pad inside, and electrically connected to the first semiconductor chip. And a second semiconductor chip having an I / O output level higher than that of the first semiconductor chip, wherein a capacitor is formed between the electrode pad and the input / output circuit in the first semiconductor chip. It is.

  Further, the present invention provides a wiring board having a main surface and a back surface, a first semiconductor chip mounted on the main surface of the wiring board, mounted on the main surface of the wiring board, and the first A second semiconductor chip having an I / O output level higher than that of the semiconductor chip, and a signal wiring formed on the back side of the wiring substrate and electrically connecting the first semiconductor chip and the second semiconductor chip It has. Furthermore, the present invention includes a metal tab larger than the wiring board, bonded to the back surface of the wiring board, and a GND wire for connecting the GND terminal of the wiring board and the tab. The wiring board and the tab are GND connected by the GND wire.

  The present invention also includes a first semiconductor chip having an electrode pad formed on the main surface and a metallized electrode to which a GND potential is supplied on the back surface opposite to the main surface, and an electrode pad formed on the main surface. A signal lead wiring electrically connected to the electrode pad is formed on the main surface, the first semiconductor chip is stacked on the main surface, and an I / O output is output from the first semiconductor chip. And a second semiconductor chip having a high level. The present invention further includes a wire connecting the electrode pad of the first semiconductor chip and the lead wiring of the second semiconductor chip, and the metallized electrode on the back surface of the first semiconductor chip and the second The signal lead-out wiring on the main surface of the semiconductor chip is arranged to face the semiconductor chip.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The first wiring connected to the first semiconductor chip and the second semiconductor chip and formed on the wiring board includes three signal lines and GND lines disposed on both sides of the three signal lines, Since the three signal lines are disposed between the two GND lines in the first wiring, the L of the signal lines in the first wiring can be reduced and the impedance of the signal lines can be maintained. Thereby, it is possible to improve the signal quality between the chips in the semiconductor device while maintaining the miniaturization of the semiconductor device having a plurality of semiconductor chips.

  In a semiconductor device having a plurality of semiconductor chips, a semiconductor chip having a high I / O output level such as an externally sold product can be mounted, and the cost of the semiconductor device can be reduced.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a cross-sectional view showing an example of the structure of the semiconductor device according to the first embodiment of the present invention, FIG. 2 is a plan view showing an example of the structure of the semiconductor device shown in FIG. 1, and FIG. 3 is a plan view of the semiconductor device shown in FIG. FIG. 4 is a perspective view showing an example of a connection state in the wiring board, FIG. 4 is a comparative view showing an example of a condition setting item of the first wiring in the semiconductor device shown in FIG. 1, and FIG. 5 is an effect obtained by the semiconductor device shown in FIG. It is a simulation figure which shows an example. 6 is a schematic diagram showing a first wiring of a modification of the semiconductor device shown in FIG. 1, and FIG. 7 is a waveform diagram showing an example of a phase shift of the waveform of the signal line in the first wiring shown in FIG. .

  The semiconductor device according to the first embodiment shown in FIGS. 1 to 3 is a semiconductor package in which a plurality of semiconductor chips are mounted on a wiring board 3, and a memory chip 2 having a memory circuit and a microcomputer chip for controlling them. (Also referred to as a controller chip) 1 has a SIP (System In Package) structure mounted on a wiring board 3. In the first embodiment, as an example, a plurality of solder balls 5 are used as external terminals of a semiconductor device. A BGA (Ball Grid Array) 8 provided with the above will be described. That is, the semiconductor device according to the first embodiment shown in FIGS. 1 to 3 is a BGA 8 having a SIP structure.

  In the BGA 8, a microcomputer chip (first semiconductor chip) 1 and a memory chip (second semiconductor chip) 2 are mounted side by side on the wiring board 3. The wiring substrate 3 has a main surface (upper surface) 3a and a back surface (lower surface) 3b located on the opposite side of the main surface 3a. The microcomputer chip 1 and the memory chip 2 are mounted on the main surface 3a. ing. Both the microcomputer chip 1 and the memory chip 2 are mounted by so-called face-up mounting with the main surfaces 1a and 2a facing upward.

  On the other hand, on the back surface 3b side of the wiring board 3, as shown in FIG. 1, a plurality of solder balls 5 as external terminals are arranged in a grid pattern.

  Further, each of the microcomputer chip 1 and the memory chip 2 is a conductive member, and is electrically connected to the wiring board 3 via a wire 4 made of, for example, gold. The microcomputer chip 1 and the memory chip 2 have quadrilateral main surfaces 1a and 2a and opposite quadrilateral back surfaces 1b and 2b, respectively, and each main surface 1a and 2a has a plurality of pads (electrode pads). ) 1c and 2c are provided.

  As shown in FIG. 3, for example, in the microcomputer chip 1, the electrode pads 1c provided on the main surface 1a are pads corresponding to the main surface 3a of the wiring board 3 (microcomputer chip pads, bonding leads, The first bonding lead 3c and the wire (first wire, first conductive member) 4 are electrically connected. On the other hand, the memory chip 2 has an electrode pad 2c provided on the main surface 2a. The wiring board 3 is electrically connected to pads (memory chip pads, bonding leads, second bonding leads) 3c and wires (second wires, second conductive members) 4 on the main surface 3a of the corresponding wiring board 3. . In addition, although not shown, a plurality of pads (bonding leads) 3c formed on the main surface 3a of the wiring board 3 are used to input signals with external devices via wirings (internal wirings) provided on the wiring board 3. Each is electrically connected to a plurality of external terminals for outputting.

  As shown in FIGS. 1 and 2, on the main surface 3a side of the wiring board 3, the microcomputer chip 1, the memory chip 2, and the plurality of wires 4 are resin-sealed by a sealing body 6 made of a sealing resin. .

  In the first embodiment, when the I / O output level (first output level) in the microcomputer chip 1 and the I / O output level (second output level) in the memory chip 2 are compared, the memory chip 2 The I / O output level is higher. This is because a relatively inexpensive externally sold product is often used for the memory chip 2 for the purpose of reducing the manufacturing cost of the BGA 8. That is, the memory chip 2 manufactured with a manufacturing process and quality standards different from those of the microcomputer chip 1 is designed to have a high I / O output level. For example, in the case of the memory chip 2 that is sold externally, there are cases where signals are supplied at high speed to a microcomputer chip of another different package. The output level is designed to be relatively large.

  The wiring board 3 incorporated in the BGA 8 is, for example, a two-layer wiring board as shown in FIG. That is, for the purpose of reducing the manufacturing cost of the BGA 8, a relatively inexpensive two-layer wiring board is employed. Since the structure of the wiring board 3 is a two-layer wiring structure, wirings 3h are formed on both front and back surfaces of the core material 3i, and these wirings 3h are covered and insulated and protected by a solder resist 3j which is an insulating film. ing.

  A subtractive method is known as a method for manufacturing the wiring substrate 3 having a two-layer wiring structure at a low cost. At this time, if the wiring board 3 has a two-layer wiring structure (including a one-layer wiring structure), the wiring board 3 is very thin and easily warps. Further, in the case of the structure like the BGA 8 of the first embodiment, since the area in the planar direction of the package body is larger than the area in the planar direction of each semiconductor chip, it is unavoidable that an electrically large L is generated. Absent. However, since the wiring board 3 having a two-layer wiring structure is thin and easily warped, a power plane effective for reducing L cannot be formed in the wiring board 3. Furthermore, in the wiring board 3 having a two-layer wiring structure, when one of the two wiring layers is used as a power plane, the remaining wiring layer is only one layer, so that the wiring is routed on the wiring board 3. Will become difficult.

  Therefore, in the BGA 8 according to the first embodiment, as shown in FIG. 3, a plurality of wirings (interchip wirings that are electrically connected between the microcomputer chip 1 and the memory chip 2 formed on the wiring substrate 3 ( As shown in part A, the first wiring 3d has two GNDs arranged on both sides of the three signal lines 3e so as to sandwich the three signal lines 3e and the three signal lines 3e. Line 3f. That is, in the first wiring 3 d that electrically connects the microcomputer chip 1 and the memory chip 2 on the wiring substrate 3, the three signal lines 3 e are disposed between the two GND lines 3 f.

  Therefore, since the three signal lines 3e are sandwiched between the GND lines 3f, the impedance of the signal line 3e can be maintained, and thereby the signal quality can be maintained.

  Here, the reason why the number of the signal lines 3e sandwiched between the GND lines 3f on both sides of the first wiring 3d in the BGA 8 of the first embodiment is three will be described with reference to FIG. In FIG. 4, when the arrangement of the signal lines 3e and the GND lines 3f in the fixed area frame 3k on the wiring board 3 and the condition of the number thereof are set as five types, for example, as types A, B, C, D, and E. These five types were compared and examined. Of the comparison items, the signal quality symbol “<” indicates that the signal quality is better from type A to type E.

  Under the condition of a certain area on the wiring board 3, the larger the number of effective signal wirings as in the case of Type A, the better. In addition, the range in which the signal quality is kept effective is better as the GND line 3f is closer to the signal line 3e as shown in Type E. That is, if the GND line 3f is inserted and arranged in the dark clouds, the number of wirings arranged between the microcomputer chip 1 and the memory chip 2 increases, and the area of the wiring board 3 increases (the semiconductor device is downsized). Difficult). On the other hand, when the area of the wiring board 3 is not increased, all the wirings cannot be routed.

  Therefore, it is preferable to select the type C in which the required number of signal lines 3e, the GND line 3f are arranged in the vicinity of the signal line 3e, and the three signal lines 3e are arranged between the GND lines 3f in consideration of area restrictions. Got.

  Further, as shown in FIG. 6, the phase of the first signal 3m of FIG. 7 flowing in the middle signal line 3e (signal Q) of the three signal lines 3e sandwiched between the GND lines 3f and FIG. It is preferable that the phase of the second signal 3n of FIG. 7 flowing in the signal line 3e (signal P) on both sides of the middle signal line 3e is shifted and different. That is, the phase of the first signal 3m flowing in the middle signal line 3e (signal Q) of the three signal lines 3e sandwiched between the GND lines 3f and the signal lines 3e (signal P on both sides of the middle signal line 3e). As shown in FIG. 7, the phase of the second signal 3n flowing in () is shifted by T in the time axis direction, so that the middle signal line with respect to the signal line 3e (signal P) on both sides at the time T portion. 3e (signal Q) can be a virtual GND line. Thereby, in the portion of time T, the signal lines 3e (signal P) on both sides are sandwiched between the GND line 3f and the virtual GND line. That is, a situation close to type E in FIG. 4 can be created.

  As a result, the phase of the first signal 3m flowing in the middle signal line 3e (signal Q) of the three signal lines 3e and the second flowing in the signal line 3e (signal P) on both sides of the middle signal line 3e. The signal quality can be further improved by shifting the phase of the signal 3n in the time axis direction.

  According to the BGA 8 of the first embodiment, the microcomputer chip 1 and the memory chip 2 are connected, and the first wiring 3d formed on the wiring board 3 includes the three signal lines 3e and the three signal lines. 3e and the GND line 3f arranged on both sides of the first wiring 3d, and the three signal lines 3e are sandwiched between the two GND lines 3f in the first wiring 3d, so that the signal line of the first wiring 3d The impedance of the signal line 3e can be maintained by reducing L of 3e.

  As a result, while suppressing an increase in the area of the wiring board 3, the signal waveform of the signal line 3e can be within the specified range 9 as shown in FIG. 5, and the occurrence of overshoot (or undershoot) can be prevented. Can do.

  Therefore, in the BGA 8 having a plurality of semiconductor chips such as the microcomputer chip 1 and the memory chip 2, the quality of signals input / output between the chips can be maintained. That is, it is possible to stabilize the signal waveform input and output between chips.

  As a result, it is possible to improve the signal quality between the chips in the BGA 8 while maintaining the downsizing of the BGA 8 having the microcomputer chip 1 and the memory chip 2.

  In addition, in the BGA 8 having a plurality of semiconductor chips such as the microcomputer chip 1 and the memory chip 2, even a semiconductor chip (memory chip 2) having a high I / O output level such as an inexpensive externally sold product can be mounted. In addition, the cost of the BGA 8 can be reduced by employing the wiring substrate 3 having a two-layer wiring structure formed by an inexpensive subtractive construction method.

  Next, an example of an assembly procedure of the BGA 8 according to the first embodiment will be described with reference to FIGS. 8 is a cross-sectional view showing an example of the structure of the wiring board used for assembling the semiconductor device shown in FIG. 1, FIG. 9 is a plan view showing an example of the structure of the wiring board shown in FIG. 8, and FIG. 10 is shown in FIG. FIG. 11 is a plan view showing an example of the structure shown in FIG. 10. FIG. 11 is a cross-sectional view showing an example of the structure after mounting the memory chip in the assembly of the semiconductor device. 12 is a cross-sectional view showing an example of a structure after mounting a microcomputer chip in the assembly of the semiconductor device shown in FIG. 1, FIG. 13 is a plan view showing an example of the structure shown in FIG. 12, and FIG. 14 is a semiconductor shown in FIG. FIG. 15 is a plan view showing an example of the structure shown in FIG. 14. FIG. 15 is a cross-sectional view showing an example of the structure after wire bonding of the memory chip in the assembly of the device. 16 is a sectional view showing an example of the structure after wire bonding of the microcomputer chip in the assembly of the semiconductor device shown in FIG. 1, FIG. 17 is a plan view showing an example of the structure shown in FIG. 16, and FIG. FIG. 19 is a plan view showing an example of the structure shown in FIG. 18. FIG. 19 is a cross-sectional view showing an example of the structure after resin molding in the assembly of the semiconductor device shown. 20 is a cross-sectional view showing an example of a structure after ball attachment in the assembly of the semiconductor device shown in FIG. 1, and FIG. 21 is a plan view showing an example of the structure shown in FIG.

  First, the wiring board 3 shown in FIGS. 8 and 9 is prepared. The wiring board 3 employed in the first embodiment is a two-layer wiring board as shown in FIG. 23, which will be described later. The structure is such that the wiring 3h is formed on both the front and back surfaces of the core material 3i, and the wiring 3h is It is covered and insulated and protected by a solder resist 3j which is an insulating film. Although not shown, the main surface 3a of the wiring board 3 includes a pad (electrode pad) 1c of the microcomputer chip 1 and a pad (electrode pad) 2c of the memory chip 2 to be mounted in a later process, and conductive members. A plurality of pads (bonding leads) 3c that are electrically connected to each other via a plurality of wires 4 are formed. The bonding lead (first bonding lead) 3c electrically connected to the microcomputer chip 1 and the bonding lead (second bonding lead) 3c electrically connected to the memory chip 2 are composed of a plurality of wirings (first wirings). ) It is electrically connected via 3d. Although not shown, the wiring board 3 is electrically connected through a plurality of pads (bonding leads) 3c and a plurality of wirings (internal wirings) to input / output signals to / from an external device. A plurality of pads (lands) for electrically connecting a plurality of external terminals are provided. In the first embodiment, a plurality of pads (lands) are provided on the back surface 3 b of the wiring board 3. In a later step, solder balls as external terminals are connected to the pads (lands).

  Thereafter, as shown in FIGS. 10 and 11, the memory chip (second semiconductor chip) 2 is mounted on the main surface 3 a of the wiring substrate 3 via a die bond material (not shown). More specifically, the memory chip 2 is fixed on the main surface 3a of the wiring board 3 by so-called face-up mounting with the main surface 2a of the memory chip 2 facing upward. A die bond material is disposed between the main surface 3 a of the substrate 3. Here, the die-bonding material is either a tape-like adhesive having an adhesive layer on a base material or a paste-like adhesive. However, in order to reduce the size of the semiconductor device, it is necessary to reduce the external dimensions (the area on which the chip is mounted) of the wiring board 3. Therefore, if a tape-like adhesive is used, the tape-like adhesive has a lower fluidity than the paste-like adhesive, so that the wiring board is in the vicinity of the chip mounting area (chip mounting portion for the memory chip). 3 pads (bonding leads) 3c can be arranged, and the wiring board 3 can be downsized.

  Thereafter, as shown in FIG. 12 and FIG. 13, on the main surface 3 a of the wiring substrate 3, the microcomputer chip is connected to a region adjacent to the memory chip 2 (chip mounting portion for the microcomputer chip) via a die bond material (not shown). (First semiconductor chip) 1 is mounted. At that time, the microcomputer chip 1 is fixed on the main surface 3a of the wiring board 3 by so-called face-up mounting with the main surface 1a facing upward, and the back surface 1b of the microcomputer chip 1 and the main surface 3a of the wiring board 3 A die-bonding material is disposed between the two. Here, the die bonding material for fixing the microcomputer chip 1 is the same as the die bonding material for fixing the memory chip 2 described above.

  Thereafter, wire bonding is performed as shown in FIGS. First, as shown in FIGS. 14 and 15, wire bonding of the memory chip 2 is performed. Here, as shown in FIG. 3, the pads (electrode pads) 2c on the main surface 2a of the memory chip 2 and the pads (bonding leads) 3c on the main surface 3a of the wiring substrate 3 corresponding thereto are conductive members. Connect by wire 4.

  Thereafter, as shown in FIGS. 16 and 17, wire bonding of the microcomputer chip 1 is performed. Here, as shown in FIG. 3, a pad (electrode pad) 1 c on the main surface 1 a of the microcomputer chip 1 and a pad (bonding lead) 3 c on the main surface 3 a of the wiring board 3 corresponding to this are connected by a wire 4. .

  Thereby, the microcomputer chip 1 and the memory chip 2 are electrically connected via the plurality of wirings (first wirings) 3 d and the wires 4 which are interchip wirings formed on the wiring substrate 3. The plurality of wirings (first wirings) 3d include three signal lines 3e and GND lines 3f disposed on both sides of the three signal lines 3e as shown in part A of FIG. Yes. That is, in the first wiring 3 d that electrically connects the microcomputer chip 1 and the memory chip 2 on the wiring substrate 3, the three signal lines 3 e are disposed between the two GND lines 3 f.

  Thereafter, resin molding is performed as shown in FIGS. Here, a sealing body 6 made of a sealing resin is formed on the main surface 3 a of the wiring board 3, and the microcomputer chip 1, the memory chip 2, and the plurality of wires 4 are resin-sealed by the sealing body 6.

  Thereafter, as shown in FIG. 20 and FIG. 21, ball attachment as an external terminal is performed. That is, a plurality of solder balls 5 serving as external terminals of the semiconductor device are bonded to pads (lands) on the back surface 3b of the wiring board 3. At that time, the solder balls 5 are provided in a grid pattern.

  Thereby, the assembly of the BGA 8 of the first embodiment shown in FIG. 1 is completed. In the BGA 8, as shown in FIG. 3, in the first wiring 3d that electrically connects the microcomputer chip 1 and the memory chip 2 on the wiring board 3, the three signal lines 3e are sandwiched between the two GND lines 3f. Are arranged.

(Embodiment 2)
22 is a perspective view showing an example of the internal structure of the semiconductor device according to the second embodiment of the present invention. FIG. 23 is an enlarged partial sectional view showing an example of the structure cut along the line AA in FIG. FIG. 25 is a perspective view showing an internal structure of a semiconductor device according to a modification of the second embodiment of the present invention, and FIG. 25 is an enlarged partial sectional view showing a structure cut along the line AA in FIG.

  The semiconductor device of the second embodiment shown in FIGS. 22 and 23 is a microcomputer chip (first semiconductor chip) via a die bonding material 10 on the main surface 3a of the wiring board 3, as with the BGA 8 of the first embodiment. 1 and a memory chip (second semiconductor chip) 2 are mounted. The memory chip 2 has a higher I / O output level than the microcomputer chip 1, and a metallized electrode 1 d to which a GND potential is supplied is formed on the back surface 1 b of the microcomputer chip 1.

  The wiring board 3 has a two-layer wiring structure, and a signal line 3g for electrically connecting the microcomputer chip 1 and the memory chip 2 is formed on the main surface 3a. The signal line 3g on the main surface 3a is disposed on the back surface 1b side of the microcomputer chip 1 in a region corresponding to the metallized electrode 1d of the microcomputer chip 1 so as to face the metalized electrode 1d.

  That is, as shown in FIG. 23, by forming a metallized electrode 1d to which the GND potential is supplied on the back surface 1b of the microcomputer chip 1, this is regarded as a GND plane, and further on the main surface 3a of the wiring board 3 therebelow. A microstrip line is formed by disposing the signal line 3g on the line. That is, in the case of the wiring board 3 having a two-layer wiring structure, it is a countermeasure against the difficulty in forming a microstrip line with the wiring board 3 alone, and the wiring board 3 and the microcomputer chip 1 form a microstrip line. It is.

  By forming a microstrip line with the wiring board 3 and the microcomputer chip 1 in this way, the L of the signal line 3g of the first wiring 3d is reduced and the impedance of the signal line 3g is reduced as in the BGA 8 of the first embodiment. Can keep.

  As a result, the signal waveform of the signal line 3g (interchip wiring) can be kept within the specified range 9, and the occurrence of overshoot (or undershoot) can be prevented.

  Therefore, as in the first embodiment, in a semiconductor device having a plurality of semiconductor chips such as the microcomputer chip 1 and the memory chip 2, the quality of signals input and output between the chips can be maintained. That is, it is possible to stabilize the signal waveform input and output between chips.

  As a result, signal quality between chips in the semiconductor device can be improved.

  In addition, in a semiconductor device having a plurality of semiconductor chips, even a semiconductor chip (memory chip 2) having a high I / O output level such as an inexpensive externally sold product can be mounted. By adopting the wiring substrate 3 having a two-layer wiring structure formed by the subtractive construction method, the cost of the semiconductor device can be reduced.

  Next, the semiconductor device shown in FIG. 24 and FIG. 25 is a semiconductor device according to a modification of the second embodiment, and the capacitance (C) is increased by forming the capacitance (C) under the microcomputer chip 1. The signal quality is maintained.

  That is, by forming the metallized electrode 1d to which the GND potential is supplied on the back surface 1b of the microcomputer chip 1, this is regarded as a GND plane, and the signal line 3g is disposed on the main surface 3a of the wiring board 3 below the metallized electrode 1d. In addition, a flat plate portion (wide portion) 3p wider than the signal line 3g is formed at a position facing the metallized electrode 1d of the microcomputer chip 1 of the signal line 3g. That is, by disposing a large area metal flat plate (flat plate portion 3p) on the main surface 3a of the wiring board 3 below the metallized electrode 1d to which the GND potential of the back surface 1b of the microcomputer chip 1 is supplied, the GND potential is reduced. A capacitor (C) is formed under the microcomputer chip 1 by the metallized electrode 1d and the metal flat plate (flat plate portion 3p).

  Thus, by forming the capacitance (C) under the microcomputer chip 1 by the metallized electrode 1d on the back surface 1b of the microcomputer chip 1 and the flat plate portion 3p of the wiring board 3, the capacitance (C) of the signal line 3g between the chips is formed. The impedance can be maintained by increasing the value.

  As a result, the signal waveform of the signal line 3g (interchip wiring) can be kept within the specified range 9, and the occurrence of overshoot (or undershoot) can be prevented.

  Therefore, as in the first embodiment, in a semiconductor device having a plurality of semiconductor chips such as the microcomputer chip 1 and the memory chip 2, the quality of signals input and output between the chips can be maintained. That is, it is possible to stabilize the signal waveform input and output between chips.

  As a result, signal quality between chips in the semiconductor device can be improved.

  In addition, in a semiconductor device having a plurality of semiconductor chips, even a semiconductor chip (memory chip 2) having a high I / O output level such as an inexpensive externally sold product can be mounted. By adopting the wiring substrate 3 having a two-layer wiring structure formed by the subtractive construction method, the cost of the semiconductor device can be reduced.

(Embodiment 3)
FIG. 26 is a schematic diagram showing an example of the layout of the I / O circuit of the microcomputer chip mounted on the semiconductor device according to the third embodiment of the present invention, and FIG. 27 shows an example of the I / O circuit of the microcomputer chip shown in FIG. FIG. 28 is a partial plan view showing a specific example of an I / O cell region to which the I / O circuit of the microcomputer chip shown in FIG. 26 is applied.

  The semiconductor device according to the third embodiment includes a microcomputer chip (first semiconductor chip) 1 and a memory chip (second semiconductor chip) 2 having an I / O output level higher than that of the microcomputer chip 1. A capacitor (C) is formed in 1 to maintain the quality of signals input and output in the microcomputer chip 1.

  That is, the semiconductor device of the third embodiment is a microcomputer that is a first semiconductor chip having an input / output circuit 1j in which an electrode pad 1c is formed on the main surface 1a and electrically connected to the electrode pad 1c. The chip 1 has a memory chip 2 (see FIG. 24) that is electrically connected to the microcomputer chip 1 and is a second semiconductor chip having a higher I / O output level than the microcomputer chip 1. In the third embodiment, in the microcomputer chip 1, a capacitor (C) is formed between the electrode pad 1c and the input / output circuit 1j.

  That is, as shown in FIGS. 26 to 28, the I / O system circuit of the microcomputer chip 1 includes, for example, an electrode pad 1c and a protection circuit 1i connected thereto, and further electrically connected to the electrode pad 1c and the protection circuit 1i. The I / O cell region 1j connected to the I / O cell region 1e (provided that only the input or only the output may be provided) is provided in the third embodiment as shown in FIGS. As described above, the capacitor (C) is formed in the output transistor region 1h in the I / O cell region 1e.

  This is because in the input / output circuit 1j in the I / O cell region 1e, the drive capability may be weak because of transmission between internal signals. Therefore, the size of the output transistor composed of the nMOS 1f and the pMOS 1g may be small. This is because a part of the output transistor region 1h that is free can be used as a capacitor (C) and is effective in terms of space. The capacitor (C) can be formed, for example, by forming a metal layer or a gate layer, whereby the capacitor (C) can be formed while suppressing an increase in cost.

  That is, in the semiconductor device according to the third embodiment, in the I / O cell region 1e in the microcomputer chip 1, the unnecessary output transistor region 1h is used without securing the capacitance (C) region. By forming the capacitor (C) using a metal layer, a gate layer, or the like, the increase in cost can be suppressed and the capacitor (C) can be formed. It should be noted that any capacitance (C) may be formed in terms of process, and this setting can be switched in the form of metal or register setting.

  Also in the semiconductor device according to the third embodiment, the quality of signals input and output in the microcomputer chip 1 can be maintained by forming a capacitor (C) in the I / O cell region 1e of the microcomputer chip 1. Thereby, it is possible to stabilize the signal waveform input / output between the chips, and to improve the signal quality between the chips in the semiconductor device.

(Embodiment 4)
29 is a plan view showing an example of the structure of the semiconductor device according to the fourth embodiment of the present invention, FIG. 30 is a front view showing an example of the structure shown in FIG. 29, and FIG. 31 shows the internal structure of the semiconductor device shown in FIG. FIG. 32 is a cross-sectional view showing an example of a cross-sectional structure taken along the longitudinal direction of the semiconductor device shown in FIG. 29, and FIG. 33 is a detail of the cross-section shown in FIG. It is sectional drawing which shows a structure. Further, FIG. 34 is a manufacturing process flow chart showing an example of the assembly procedure of the semiconductor device shown in FIG. 29, FIG. 35 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the fourth embodiment of the present invention, and FIG. FIG. 37 is a manufacturing process flow diagram showing an example from the second wire bonding to the resin mold in the assembling procedure of the semiconductor device shown in FIG. 35. FIG.

  The semiconductor device of the fourth embodiment shown in FIG. 29 to FIG. 33 is a small, resin-sealed semiconductor package that is assembled using the lead frame 7. In the fourth embodiment, the chip is mounted. A description will be given by taking up an SSOP (Shrink Small Outline Package) 11 in which a microcomputer chip (first semiconductor chip) 1 and a memory chip (second semiconductor chip) 2 are mounted on a tab 7c as a part.

  In the SSOP 11, as shown in FIGS. 31 and 32, the wiring board 3 is mounted on the tab (die pad) 7c, and the microcomputer chip 1 and the memory chip 2 are arranged side by side on the wiring board 3. Is arranged.

  The overall configuration of the SSOP 11 will be described. A wiring board 3 having a main surface 3a and a back surface 3b provided on the opposite side of the main surface 3a, and a microcomputer chip (first semiconductor) mounted on the main surface 3a of the wiring board 3 Chip) 1, a memory chip (second semiconductor chip) 2 mounted on the main surface 3 a of the wiring substrate 3 and having a higher I / O output level than the microcomputer chip 1, and a back surface 3 b of the wiring substrate 3. And a metal tab 7 c larger than the wiring board 3.

  That is, the wiring board 3 is mounted on the tab 7 c, and the microcomputer chip 1 and the memory chip 2 are mounted on the wiring board 3.

  Further, the tab 7c is supported by the suspension lead 7d, and an inner lead 7a, which is a plurality of leads, is disposed around the tab 7c. Each inner lead 7 a is formed integrally with an outer lead 7 b that is an external terminal of the SSOP 11. The tab 7c, the suspension lead 7d, the wiring board 3, the microcomputer chip 1, the memory chip 2, the plurality of wires 4, and the plurality of inner leads 7a are resin-sealed by a sealing body 6 formed of a sealing resin. ing. Also, as shown in FIGS. 29 and 30, a plurality of outer leads 7b connected to the respective inner leads 7a protrude from two opposing side portions 6a of the sealing body 6, and these outer leads 7b serve as external terminals as gull wings. It is bent into a shape.

  Further, the microcomputer chip 1 and the memory chip 2 are electrically connected to the wiring board 3 via wires 4, respectively, and the wiring board 3 and the plurality of inner leads 7 a are electrically connected to each other via the wires 4. doing. Therefore, the microcomputer chip 1 and the memory chip 2 are electrically connected to the corresponding inner leads 7a through the wires 4 and the wiring board 3, respectively.

  In the SSOP 11 of the fourth embodiment, as shown in FIG. 33, the GND terminal 3r of the wiring board 3 and the tab 7c are electrically connected by the GND wire 4a. That is, the wiring board 3 and the tab 7c are GND-connected by the GND wire 4a, and the tab 7c is at the GND potential.

  Further, as shown in FIG. 33, a signal wiring (second wiring) 3 q that electrically connects the microcomputer chip 1 and the memory chip 2 is formed on the back surface 3 b side of the wiring substrate 3. Thereby, a microstrip line structure can be formed as shown in part A of FIG.

  Therefore, according to the SSOP 11 of the fourth embodiment, by forming the microstrip line in the signal second wiring 3q for connecting the chips, the second wiring 3q as in the BGA 8 of the first embodiment. The impedance can be maintained, and the signal quality can be maintained.

  That is, even in the lead frame type SSOP 11 in which the microcomputer chip 1 and the memory chip 2 are mounted, it is possible to prevent the occurrence of overshoot (or undershoot) in signals between chips. That is, it is possible to stabilize the signal waveform input / output between the chips and improve the signal quality between the chips in the semiconductor device.

  Next, the assembly procedure of the SSOP 11 according to the fourth embodiment will be described with reference to FIG.

  First, substrate mounting shown in step S1 is performed. Here, the wiring board 3 is mounted on the tab 7 c of the lead frame 7.

  Thereafter, first wire bonding shown in step S2 is performed. Here, the inner lead 7a and the wiring board 3 are electrically connected by the wire 4, and the GND terminal 3r of the wiring board 3 and the tab 7c are electrically connected by the GND wire 4a as shown in FIG. .

  Thereafter, memory chip mounting shown in step S3 is performed. Here, the memory chip 2 is mounted on the wiring substrate 3 with its main surface 2a facing upward. At that time, the memory chip 2 and the wiring substrate 3 are bonded together by a film adhesive.

  Then, the microcomputer chip mounting shown in step S4 is performed. Here, the microcomputer chip 1 is mounted on the wiring board 3 with the main surface 1a facing upward, next to the memory chip 2. At that time, the microcomputer chip 1 and the wiring board 3 are bonded together by a film adhesive.

  Thereafter, second wire bonding shown in step S5 is performed. Here, the microcomputer chip 1 and the wiring board 3 are further electrically connected to the memory chip 2 and the wiring board 3, or the microcomputer chip 1 and the inner lead 7 a are respectively electrically connected by the wires 4.

  Thereafter, resin molding shown in step S6 is performed. Here, the inner lead 7a, the tab 7c, the wiring board 3, the microcomputer chip 1, the memory chip 2 and the plurality of wires 4 are molded with a sealing resin to form a sealing body 6, and the sealing body 6 is used to form a resin. Seal.

  Thereafter, the outer lead 7b protruding from the sealing body 6 is cut and molded to form a gull wing shape. Thereby, the assembly of the SSOP 11 of the fourth embodiment is completed.

  Next, a modification of the fourth embodiment will be described. FIG. 35 shows the structure of a modified semiconductor device, in which memory chips 2 are stacked. That is, the SSOP 14 is formed by stacking the upper memory chip 13 on the memory chip 2. The upper memory chip 13 is stacked on the first-stage memory chip 2 via the spacer 12.

  That is, in the SSOP 14 which is the semiconductor device of the modification, one microcomputer chip 1, the memory chip 2, and the upper memory chip 13 stacked thereon are mounted on the wiring substrate 3 on the tab 7c.

  Note that the other structures of the SSOP 14 according to the modified example and the effects obtained by the SSOP 14 are the same as those of the SSOP 11, and thus redundant description thereof is omitted.

  Next, the assembly procedure of the SSOP 14 will be described with reference to FIGS.

  First, substrate mounting shown in step S11 is performed. Here, the wiring board 3 is mounted on the tab 7 c of the lead frame 7.

  Thereafter, first wire bonding shown in step S12 is performed.

  Here, the inner lead 7a and the wiring board 3 are electrically connected by the wire 4, and the GND terminal 3r of the wiring board 3 and the tab 7c are electrically connected by the GND wire 4a as shown in FIG. .

  Thereafter, the first-stage memory chip is mounted as shown in step S13. Here, the memory chip 2 is mounted on the wiring substrate 3 with its main surface 2a facing upward. At that time, the memory chip 2 and the wiring substrate 3 are bonded together by a film adhesive.

  Thereafter, spacer mounting shown in step S14 is performed. Here, the spacers 12 are stacked on the main surface 2 a of the memory chip 2. At that time, the memory chip 2 and the spacer 12 are joined by a film adhesive.

  Then, the microcomputer chip mounting shown in step S15 is performed. Here, the microcomputer chip 1 is mounted on the wiring board 3 with the main surface 1a facing upward, next to the memory chip 2. At that time, the microcomputer chip 1 and the wiring board 3 are bonded together by a film adhesive.

  Thereafter, second wire bonding shown in step S16 is performed. Here, the microcomputer chip 1 and the wiring board 3 are further electrically connected to the memory chip 2 and the wiring board 3, or the microcomputer chip 1 and the inner lead 7 a are respectively electrically connected by the wires 4.

  Thereafter, the upper memory chip is mounted in step S17. Here, the upper memory chip 13 is mounted on the spacer 12 with the main surface 13a facing upward. At that time, the upper memory chip 13 and the spacer 12 are joined by a film adhesive.

  Thereafter, third wire bonding shown in step S18 is performed. Here, the upper memory chip 13 and the wiring substrate 3 are electrically connected by the wire 4.

  Thereafter, resin molding shown in step S19 is performed. Here, the inner lead 7a, the tab 7c, the wiring board 3, the microcomputer chip 1, the memory chip 2, the upper memory chip 13, the plurality of wires 4 and the GND wire 4a are resin-molded with a sealing resin, and the sealing body 6 is formed. And sealed with resin by the sealing body 6.

  Thereafter, the outer lead 7b protruding from the sealing body 6 is cut and molded to form a gull wing shape. Thereby, the assembly of the SSOP 14 according to the fourth embodiment is completed.

(Embodiment 5)
FIG. 38 is a cross-sectional view showing an example of a chip stack structure incorporated in the semiconductor device according to the fifth embodiment of the present invention. FIG. 39 shows a chip according to the first modification incorporated in the semiconductor device according to the fifth embodiment of the present invention. 40 is a perspective view showing a laminated structure, FIG. 40 is an enlarged cross-sectional view showing a structure cut along line AA in FIG. 39, and FIG. 41 shows a structure of a semiconductor device according to a second modification of the fifth embodiment of the present invention. It is sectional drawing shown.

  In the fifth embodiment, semiconductor chips are stacked, and rewiring is formed on the main surface of at least one semiconductor chip, and the quality of signal wiring between the chips is maintained by using this rewiring. It is what you want to do.

  The chip stacked structure shown in FIG. 38 shows a structure in which the memory chip (second semiconductor chip) 2 is arranged in the lower stage and the microcomputer chip (first semiconductor chip) 1 is stacked thereon.

  The microcomputer chip 1 has an electrode pad 1c formed on the main surface 1a and a metallized electrode 1d to which a GND potential is supplied on the back surface 1b opposite to the main surface 1a.

  On the other hand, the memory chip 2 has an electrode pad 2c formed on the main surface 2a, a signal rewiring (lead-out wiring) 2d electrically connected to the electrode pad 2c formed on the main surface 2a, and a microcomputer. The output level of I / O is set higher than that of chip 1.

  The microcomputer chip 1 is laminated on the main surface 2a of the memory chip 2 via a die bond material 10, and an electrode pad 1c of the microcomputer chip 1 and a rearrangement pad 2e connected to the rewiring 2d of the memory chip 2 are provided. The metallized electrode 1d on the back surface 1b of the microcomputer chip 1 and the signal rewiring 2d on the main surface 2a of the memory chip 2 are arranged to face each other while being electrically connected by the wire 4.

  In other words, the memory chip 2 is provided with the rearrangement pads 2e on the main surface 2a in which the original electrode pads 2c for signals are drawn out by the rewiring 2d and rearranged. A metallized electrode 1d to which a GND potential is supplied is formed on the back surface 1b of the microcomputer chip 1 on the memory chip 2. Further, the electrode pad 1c on the main surface 1a of the microcomputer chip 1 and the rearrangement pad 2e on the main surface 2a of the memory chip 2 are connected by a wire 4, whereby the electrode pad 1c of the microcomputer chip 1 and the memory chip 2 are connected. The original electrode pad 2c is electrically connected through the rewiring 2d. At that time, the metallization electrode 1d on the back surface 1b to which the GND potential of the microcomputer chip 1 is supplied and the rewiring 2d which is a signal lead-out wiring on the main surface 2a of the memory chip 2 form the insulating film 2f covering the rewiring 2d. Therefore, the microstrip line structure can be formed at the portion A in FIG.

  Therefore, according to the chip laminated structure of the fifth embodiment shown in FIG. 38, the impedance of the rewiring 2d can be maintained and the signal quality can be maintained by forming the microstrip line structure.

  That is, the occurrence of overshoot (or undershoot) can be prevented even in signals between chips having a chip stack structure as shown in FIG. 38, and the signal waveform input / output between chips can be stabilized. As a result, signal quality between chips can be improved.

  Next, a modification of the fifth embodiment will be described. The first modification shown in FIGS. 39 and 40 is similar to the chip stacking structure shown in FIG. 38, and the rewiring 2d of the main surface 2a of the memory chip 2 is connected to the metallized electrode 1d on the back surface 1b of the microcomputer chip 1. The opposing region has a flat plate portion (wide portion) 2g wider than the rewiring 2d.

  That is, a large area metal flat plate (flat plate portion 2g) is disposed on the main surface 2a of the memory chip 2 below the metallized electrode 1d to which the GND potential of the back surface 1b of the microcomputer chip 1 is supplied, as shown in FIG. Thus, the capacitor (C) can be formed on the signal rewiring 2d of the memory chip 2 by the metallized electrode 1d having the GND potential and the metal flat plate (flat plate portion 2g).

  Therefore, the impedance can be maintained by increasing the capacitance (C) on the wiring between chips (rewiring 2d), and as a result, the occurrence of overshoot (or undershoot) in the wiring between chips can be prevented. it can.

  Thereby, stabilization of the signal waveform input / output between chips can be achieved. As a result, signal quality between chips can be improved.

  Next, the second modification shown in FIG. 41 is a further application example of the first modification, and a semiconductor package having stacked microcomputer chip (first semiconductor chip) 1 and memory chip (second semiconductor chip) 2. In the (semiconductor device) 15, a microstrip line structure is formed on the rewirings 1k and 2d of the microcomputer chip 1 and the memory chip 2, respectively.

  The structure of the semiconductor package 15 shown in FIG. 41 will be described. A memory chip 2 in which a rearrangement pad 2e in which a signal electrode pad 2c is drawn out by a rewiring (drawing wiring) 2d and rearranged is formed on the main surface 2a; Similarly, a relocation pad 1m in which a signal electrode pad 1c is drawn out by a rewiring (leading wiring) 1k and rearranged is formed on the main surface 1a, and the microcomputer chip 1 is stacked on the main surface 2a of the memory chip 2. have. Further, the main surface 1a of the microcomputer chip 1 and the tab 7c are joined. The rewiring 1k formed on the main surface 1a of the microcomputer chip 1 is covered with an insulating film 1n, while a metallized electrode 1d to which a GND potential is supplied is formed on the back surface 1b. Also in the memory chip 2, the rewiring 2d on the main surface 2a is covered with the insulating film 2f.

  The microcomputer chip 1 is stacked on the main surface 2a of the memory chip 2 with the main surface 1a facing upward, and a tab 7c is stacked on the main surface 1a of the microcomputer chip 1 so that the tab 7c and the microcomputer are stacked. The main surface 1a of the chip 1 is joined. Therefore, the memory chip 2 is arranged face-up on the first level, the microcomputer chip 1 is stacked on the second level in the same manner, and the tab 7c is stacked on the third level. . Since the GND potential is supplied to the tab 7c by the wire 4 or the like, the tab 7c is connected to GND.

  Further, the microcomputer chip 1 and the inner lead 7a, the memory chip 2 and the inner lead 7a, and the microcomputer chip 1 and the memory chip 2 are electrically connected by wires 4, respectively.

  Further, the microcomputer chip 1, the memory chip 2, the tab 7c, and the plurality of wires 4 are resin-sealed by a sealing body 6 made of a sealing resin. Further, a plurality of outer leads 7b integrally connected to the inner leads 7a protrude from the side portion 6a of the sealing body 6, and the plurality of outer leads 7b are bent and formed into a gull wing shape.

  As shown in part A of FIG. 41, the signal rewiring 1k on the main surface 1a of the microcomputer chip 1 is disposed under the tab 7c to which the GND potential is supplied via the insulating film 1n. A microstrip line structure can be formed.

  Furthermore, as shown in part B of FIG. 41, the signal re-transmission on the main surface 2a of the memory chip 2 is provided below the metallized electrode 1d on the back surface 1b of the microcomputer chip 1 to which the GND potential is supplied via an insulating film 2f. Since the wiring 2d is disposed, a microstrip line structure can be formed here as well.

  Therefore, also in the semiconductor package 15, the impedance of the rewiring 1k and the rewiring 2d can be maintained, and the signal quality can be maintained. That is, overshoot (or undershoot) can be prevented even in signals between chips of the semiconductor package 15, and signal waveforms input and output between chips can be stabilized. As a result, signal quality between chips can be improved.

  Further, by arranging a metal flat plate having a larger area than the respective wirings on the rewiring 1k under the tab 7c and the rewiring 2d under the metallization electrode 1d of the microcomputer chip 1, the metal flat plate on the rewiring 1k or A capacitor (C) can be formed on the metal flat plate of the rewiring 2d.

  As a result, the impedance can be maintained by increasing the capacitance (C) on the wiring between the chips (rewiring 1k and rewiring 2d). As a result, overshoot (or undershoot) in the wiring between the chips can be maintained. Occurrence can be prevented. Thereby, it is possible to stabilize the signal waveform input / output between the chips, and as a result, it is possible to improve the signal quality between the chips.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the first to fifth embodiments, the case where the first semiconductor chip is the microcomputer chip 1 and the second semiconductor chip is the memory chip 2 is described as an example, but the first and second semiconductor chips are as follows. If the second semiconductor chip has a higher I / O output level than the first semiconductor chip, the function of each semiconductor chip is not particularly limited. For example, both the first and second semiconductor chips are memory chips. It may be.

  Further, the GND line, the GND terminal, and the GND wire described in the first to fifth embodiments may be a power supply line, a power supply terminal, and a power supply wire. That is, the GND described in the first to fifth embodiments may be replaced with a power source.

  In the first to fifth embodiments described above, the pads of the plurality of semiconductor chips (the microcomputer chip 1 and the memory chip 2) and the pads of the wiring board 3 are electrically connected through the plurality of wires 4, respectively. However, it is not limited to this, and may be connected via a plurality of bump electrodes. That is, so-called flip chip connection in which the semiconductor chip is mounted on the main surface 3 a of the wiring substrate 3 so that the main surface of the semiconductor chip faces the main surface 3 a of the wiring substrate 3. By electrically connecting via the bump electrode, the signal processing of the semiconductor device can be speeded up because the current path is shorter than the length of the wire.

  In the first embodiment, the BGA type semiconductor device (package) has been described. However, the present invention is not limited to this, and the wiring board 3 is formed on the tab 7c of the lead frame 7 described in the fourth embodiment. May be a SSOP type semiconductor device (package). In this case, the wiring board 3 described in the first embodiment corresponds to the wiring board 3 described in the fourth embodiment. The same applies to the second and third embodiments.

  The present invention is suitable for an electronic device having a plurality of semiconductor chips.

It is sectional drawing which shows an example of the structure of the semiconductor device of Embodiment 1 of this invention. FIG. 2 is a plan view illustrating an example of a structure of the semiconductor device illustrated in FIG. 1. FIG. 2 is a perspective view illustrating an example of a connection state in a wiring board of the semiconductor device illustrated in FIG. 1. FIG. 3 is a comparative diagram illustrating an example of a condition setting item for a first wiring in the semiconductor device illustrated in FIG. 1. It is a simulation figure which shows an example of the effect acquired by the semiconductor device shown in FIG. FIG. 6 is a schematic diagram showing a first wiring of a modification of the semiconductor device shown in FIG. 1. FIG. 7 is a waveform diagram illustrating an example of a phase shift of a waveform of a signal line in the first wiring illustrated in FIG. 6. It is sectional drawing which shows an example of the structure of the wiring board used for the assembly of the semiconductor device shown in FIG. It is a top view which shows an example of the structure of the wiring board shown in FIG. FIG. 2 is a cross-sectional view showing an example of a structure after mounting a memory chip in the assembly of the semiconductor device shown in FIG. 1. It is a top view which shows an example of the structure shown in FIG. It is sectional drawing which shows an example of the structure after the microcomputer chip mounting in the assembly of the semiconductor device shown in FIG. It is a top view which shows an example of the structure shown in FIG. FIG. 2 is a cross-sectional view showing an example of a structure after wire bonding of a memory chip in the assembly of the semiconductor device shown in FIG. 1. It is a top view which shows an example of the structure shown in FIG. It is sectional drawing which shows an example of the structure after the wire bonding of the microcomputer chip in the assembly of the semiconductor device shown in FIG. It is a top view which shows an example of the structure shown in FIG. It is sectional drawing which shows an example of the structure after the resin mold in the assembly of the semiconductor device shown in FIG. It is a top view which shows an example of the structure shown in FIG. It is sectional drawing which shows an example of the structure after ball attachment in the assembly of the semiconductor device shown in FIG. It is a top view which shows an example of the structure shown in FIG. It is a perspective view which shows an example of the internal structure of the semiconductor device of Embodiment 2 of this invention. FIG. 23 is an enlarged partial cross-sectional view showing an example of a structure cut along line AA in FIG. 22. It is a perspective view which shows the internal structure of the semiconductor device of the modification of Embodiment 2 of this invention. FIG. 25 is an enlarged partial cross-sectional view illustrating a structure cut along line AA in FIG. 24. It is a schematic diagram which shows an example of the layout of the I / O circuit of the microcomputer chip mounted in the semiconductor device of Embodiment 3 of this invention. FIG. 27 is a circuit block diagram showing an example of an I / O circuit of the microcomputer chip shown in FIG. 26. FIG. 27 is a partial plan view showing a specific example of an I / O cell region to which the I / O circuit of the microcomputer chip shown in FIG. 26 is applied. It is a top view which shows an example of the structure of the semiconductor device of Embodiment 4 of this invention. FIG. 30 is a front view showing an example of the structure shown in FIG. 29. FIG. 30 is a plan view showing an example of the internal structure of the semiconductor device shown in FIG. 29 through a sealing body. 30 is a cross-sectional view showing an example of a cross-sectional structure taken along the longitudinal direction of the semiconductor device shown in FIG. 29. FIG. It is sectional drawing which shows the detailed structure of the cross section shown in FIG. FIG. 30 is a manufacturing process flow diagram illustrating an example of an assembly procedure of the semiconductor device illustrated in FIG. 29. It is sectional drawing which shows the structure of the semiconductor device of the modification of Embodiment 4 of this invention. FIG. 36 is a manufacturing process flow diagram illustrating an example of mounting up a microcomputer chip in the assembly procedure of the semiconductor device illustrated in FIG. 35; FIG. 36 is a manufacturing process flow chart showing an example from second wire bonding to resin molding in the assembly procedure of the semiconductor device shown in FIG. 35. It is sectional drawing which shows an example of the chip | tip laminated structure integrated in the semiconductor device of Embodiment 5 of this invention. It is a perspective view which shows the chip | tip laminated structure of the 1st modification integrated in the semiconductor device of Embodiment 5 of this invention. It is an expanded sectional view which shows the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows the structure of the semiconductor device of the 2nd modification of Embodiment 5 of this invention. It is a simulation figure obtained by the semiconductor device of a comparative example.

Explanation of symbols

1 Microcomputer chip (first semiconductor chip)
1a main surface 1b back surface 1c pad (electrode pad)
1d Metallized electrode 1e I / O cell region 1f nMOS
1g pMOS
1h Output transistor area 1i Protection circuit 1j Input / output circuit 1k Re-wiring (lead-out wiring)
1m rearrangement pad 1n insulating film 2 memory chip (second semiconductor chip)
2a Main surface 2b Back surface 2c Pad (electrode pad)
2d Rewiring (drawer wiring)
2e Relocation pad 2f Insulating film 2g Flat plate part (wide part)
3 Wiring board 3a Main surface (upper surface)
3b Back side (lower side)
3c pad (bonding lead)
3d wiring (first wiring)
3e Signal line 3f GND line 3g Signal line 3h Wiring 3i Core material 3j Solder resist 3k Fixed area frame 3m First signal 3n Second signal 3p Flat part (wide part)
3q wiring (second wiring)
3r GND terminal 4 Wire 4a GND wire 5 Solder ball 6 Sealing body 6a Side 7 Lead frame 7a Inner lead (lead)
7b Outer lead 7c Tab (die pad)
7d Hanging lead 8 BGA (semiconductor device)
9 Specified range 10 Die bond material 11 SSOP (semiconductor device)
12 Spacers 13 Upper Memory Chip 13a Main Surface 14 SSOP (Semiconductor Device)
15 Semiconductor package (semiconductor device)

Claims (2)

A wiring board having a main surface on which a plurality of first bonding leads and a plurality of second bonding leads are formed, and a back surface opposite to the main surface;
A first semiconductor chip having a main surface on which a plurality of electrode pads are formed and mounted on the main surface of the wiring board;
A second semiconductor chip having a main surface on which a plurality of electrode pads are formed and mounted on the main surface of the wiring board;
A plurality of first conductive members that respectively electrically connect the plurality of electrode pads of the first semiconductor chip and the plurality of first bonding leads of the wiring board;
A plurality of second conductive members that electrically connect the plurality of electrode pads of the second semiconductor chip and the plurality of second bonding leads of the wiring board, respectively.
A plurality of wirings formed on the wiring board and electrically connecting the plurality of first bonding leads and the plurality of second bonding leads;
A sealing body for sealing the first semiconductor chip, the second semiconductor chip, the plurality of first conductive members, and the plurality of second conductive members;
Including
The output level of I / O in the second semiconductor chip is higher than the output level of I / O in the first semiconductor chip,
The plurality of wirings have a plurality of signal lines and a plurality of GND lines ,
The first semiconductor chip is a microcomputer chip, and the second semiconductor chip is a memory chip;
The plurality of wirings include a semiconductor device having three signal lines and two GND lines arranged on both sides of the three signal lines so as to sandwich the three signal lines . 2. The semiconductor device according to claim 1 , wherein a phase of a first signal that flows in a middle signal line of the three signal lines and a phase of a second signal that flows in signal lines on both sides of the middle signal line. semi-conductor devices that are different.

Images