JP2013225638A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2013225638A
JP2013225638A JP2012184085A JP2012184085A JP2013225638A JP 2013225638 A JP2013225638 A JP 2013225638A JP 2012184085 A JP2012184085 A JP 2012184085A JP 2012184085 A JP2012184085 A JP 2012184085A JP 2013225638 A JP2013225638 A JP 2013225638A
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Japan
Prior art keywords
semiconductor package
portion
provided
semiconductor
connection
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Pending
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JP2012184085A
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Japanese (ja)
Inventor
Osamu Minaminaka
理 南中
Yoshimune Kodama
義宗 小玉
Yukio Katamura
幸雄 片村
Original Assignee
Toshiba Corp
株式会社東芝
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Priority to JP2012068379 priority Critical
Priority to JP2012068379 priority
Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP2012184085A priority patent/JP2013225638A/en
Priority claimed from CN201210320295.1A external-priority patent/CN103325745B/en
Publication of JP2013225638A publication Critical patent/JP2013225638A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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    • H01L2225/1041Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
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    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

When a plurality of semiconductor packages or the like are stacked, it contributes to prevention of poor connection and misalignment between the upper and lower sides.
A resin-encapsulated semiconductor device, a semiconductor chip mounted on a wiring medium, and a plurality of connection conductors provided on the wiring medium and used for connection to an external device. A covering member 15 having a plurality of recesses 110 provided so as to cover the body 12, the wiring medium 11, the semiconductor chip 13, and the connecting conductor 12, and exposing the upper portion of each connecting conductor 12. It has. The recess 110 of the covering member 15 has a structure having a portion where the distance from the center to the side wall is short and a portion where the distance from the center to the side wall is long.
[Selection] Figure 1

Description

  Embodiments described herein relate generally to a resin-sealed semiconductor device.

  In recent years, attention has been focused on manufacturing a package-on-package (PoP) by stacking a plurality of resin-encapsulated semiconductor packages (semiconductor devices). When producing this PoP, it is as follows.

  As a first semiconductor package, a connection conductor for external connection with a semiconductor chip is provided on a wiring board, and after resin sealing, a circular recess is formed in the resin so that the upper surface of the connection conductor is exposed. Provide. Solder balls on the lower surface of the second semiconductor package are mounted on the first package in alignment with the recesses on the upper surface of the first semiconductor package. Then, the PoP is completed by reflowing the solder balls.

  However, this type of apparatus has the following problems. That is, if the opening of the recess of the semiconductor package is small, when the second semiconductor package is stacked on the first semiconductor package and passed through the reflow furnace, the gas generated from the periphery of the connecting conductor and the solder ball is In some cases, the connection conductor and the solder ball may be poorly bonded without coming out from under the ball.

  If the opening of the recess is enlarged to remove the gas generated from the periphery of the connecting conductor and the solder ball, the position of the solder ball is displaced due to vibration of the manufacturing equipment, etc., and the first and second semiconductor packages are mutually connected. There was a case where it was connected in a shifted state. In particular, in the case of multi-layer stacking, the mutual displacement of semiconductor packages has become a problem.

  As described above, when producing PoP, it has been difficult to solve both the problem of poor connection between the connecting conductor and the solder ball and the positional deviation between the upper and lower semiconductor packages.

US Patent Application Publication No. 2010/0283140

  The problem to be solved by the invention is to provide a semiconductor device that can contribute to prevention of poor connection and misalignment between the upper and lower sides when a plurality of layers are stacked.

  The semiconductor device of the embodiment includes a semiconductor chip mounted on a wiring medium, a plurality of connection conductors provided on the wiring medium and used for connection to the outside, the wiring medium, the semiconductor chip, And a covering member provided so as to cover the connecting conductor and having a plurality of recesses exposing the upper portions of the connecting conductors. And the recessed part of the said covering member is a shape which has a part with a short distance from a center to a side wall, and a part with a long distance from a center to a side wall.

FIG. 2 is a plan view and a cross-sectional view showing a schematic configuration of the semiconductor package according to the first embodiment. Sectional drawing which shows the process of manufacturing PoP using the semiconductor package of FIG. The top view which is for demonstrating the modification of 1st Embodiment, and shows the shape of the recessed part for exposing the conductor for a connection. Sectional drawing which is for demonstrating the modification of 1st Embodiment, and shows the shape of the recessed part for exposing the conductor for a connection. The top view and sectional view which show schematic structure of the semiconductor package concerning 2nd Embodiment. Sectional drawing which shows the example which comprised PoP using the semiconductor package of FIG. The top view and sectional view showing the schematic structure of the semiconductor package concerning a 3rd embodiment. Sectional drawing which shows the example which comprised PoP using the semiconductor package of FIG. Sectional drawing which is for demonstrating the modification of 3rd Embodiment, and shows the shape of the recessed part for exposing the conductor for a connection. The top view and sectional drawing which show schematic structure of the semiconductor package concerning 4th Embodiment. Sectional drawing which shows the process of manufacturing PoP using the semiconductor package of FIG. The top view and sectional drawing which show schematic structure of the semiconductor package concerning 5th Embodiment. Sectional drawing which shows the example which comprised PoP using the semiconductor package of FIG. The top view and sectional drawing which show the modification of 5th Embodiment. Sectional drawing which shows the example which comprised PoP using the semiconductor package of FIG. The top view and sectional drawing which show another modification of 5th Embodiment. Sectional drawing which shows the example which comprised PoP using the semiconductor package of FIG. Sectional drawing which is for demonstrating another modification of 5th Embodiment, and shows the shape of the recessed part for exposing the conductor for a connection. The top view and sectional view showing the schematic structure of the semiconductor package concerning a 6th embodiment. FIG. 20 is a cross-sectional view showing a manufacturing process of the semiconductor package of FIG. 19. FIG. 20 is a cross-sectional view illustrating a state where the semiconductor packages of FIG. 19 are stacked. The top view and sectional drawing which show schematic structure of the semiconductor package concerning 7th Embodiment. FIG. 23 is a cross-sectional view showing a process for manufacturing PoP using the semiconductor package of FIG. 22; FIG. 24 is a cross-sectional view illustrating a process of mounting the PoP of FIG. 23 on a mounting substrate. The top view which shows the modification of the semiconductor package of 7th Embodiment. The top view and sectional drawing which show schematic structure of the semiconductor package concerning 8th Embodiment. FIG. 27 is a cross-sectional view showing a process for manufacturing PoP using the semiconductor package of FIG. 26; FIG. 28 is a cross-sectional view illustrating a process of mounting the PoP of FIG. 27 on a mounting substrate.

  Hereinafter, a semiconductor device of an embodiment will be described with reference to the drawings.

(First embodiment)
1A and 1B are diagrams for explaining a schematic configuration of a semiconductor package according to the first embodiment. FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. is there.

  The semiconductor package 10 of the present embodiment includes a wiring medium 11, a connecting conductor 12, a semiconductor chip 13, a wire 14, a sealing material (covering member) 15, a connection terminal 16, and the like.

  A connecting conductor 12 is bonded to the peripheral portion on the wiring medium 11, and one or more semiconductor chips 13 are mounted on the central portion on the wiring medium 11. The wiring medium 11 and the semiconductor chip 13 are connected by a wire 14, and the wiring medium 11, the connecting conductor 12, and the semiconductor chip 13 are electrically connected. As the wiring medium 11, for example, a printed wiring board or a flexible wiring board can be used. The connecting conductor 12 is made of, for example, solder, tin, or copper, and may have any shape such as a spherical shape, a square shape, a columnar shape, a cylindrical shape, a prismatic shape, or a rectangular tube shape.

  One surface of the wiring medium 11, the connecting conductor 12, and the semiconductor chip 13 are sealed with a resin sealing material 15. The connection terminal 16 is joined to the other surface of the wiring medium 11 so that the semiconductor package 10 and an external circuit can be electrically connected. As the connection terminal 16, for example, a solder ball can be used.

  By removing the upper portion of the sealing material 15 where the connecting conductor 12 of the semiconductor package 10 is disposed to form the recess 110, a part or all of the connecting conductor 12 is exposed. As a method for removing the sealing material 15, for example, laser processing, dry etching, wet etching, cutting, or the like may be used.

  On the other hand, another semiconductor package (second semiconductor package) 80 mounted on the semiconductor package (first semiconductor package) 10 of the present embodiment has a configuration of the semiconductor package 10 as shown in FIG. In FIG. 2, the connecting conductor 12 and the recess 110 are not provided, and a connection terminal 86 is formed on the lower surface. The connection terminal 86 is, for example, a solder ball, and is provided so as to be aligned with the connection conductor 12 of the semiconductor package 10.

  As shown in FIG. 2A, the semiconductor package 80 is mounted on the semiconductor package 10 so that the connection conductor 12 of the semiconductor package 10 and the connection terminal 86 of the semiconductor package 80 are aligned, and the connection terminal 86 is inserted into the recess 110. Then, for example, the connection terminal 86 is reflowed by passing through a reflow furnace. As a result, as shown in FIG. 2B, the connecting conductor 12 and the connecting terminal 86 are joined to form an integrated connecting portion 87, the semiconductor package 10 and the semiconductor package 80 are connected, and the PoP structure is completed. become.

  In the present embodiment, since the opening shape of the recess 110 of the semiconductor package 10 is a square (square) as shown in FIG. 1, the length of one side of the square is slightly smaller than the diameter of the connection terminal 86 of the semiconductor package 80. By making it long, the position of the connection terminal 86 can be defined on the side wall surface of the recess 110. For this reason, it is possible to prevent the semiconductor package 10 and the semiconductor package 80 from being displaced from each other.

  Moreover, since the opening shape of the recessed part 110 is a rectangle, the recessed part 110 has a part with a short distance from a center to a side wall, and a part with a long distance from a center to a side wall. That is, even when the connection terminal 86 of the package 80 is inserted into the recess 110, a gap is always formed between the corner of the side wall of the recess 110 and the connection terminal 86. For this reason, when the connection conductor 12 and the connection terminal 86 are melt-bonded at a high temperature, the gas generated from the periphery of the connection conductor 12 and the connection terminal 86 flows from under the connection terminal 86 to the gap between the corners of the side wall of the recess 110. Pass through through. Thereby, it is possible to prevent a bonding failure between the connecting conductor 12 and the connection terminal 86. Since the sealing material 15 is hygroscopic, it is inevitable that gas is generated from the sealing material 15 when the connection terminal 86 is melted at a high temperature.

  The shape of the recess 110 is not limited to a quadrangle, and as shown in FIGS. 3A to 3E, between the sealing material 15 and the connection terminal 86 such as a triangle, a polygon, a cross, a star, and a flower. Any shape may be used as long as a gap is formed to allow gas to escape and the displacement of the connection terminal 86 is suppressed.

  In order to prevent the displacement of the connection terminal 86, the clearance between the side wall of the recess 110 and the connection terminal 86 should be small. However, if the clearance is small, high accuracy is required when the connection terminal 86 is inserted into the recess 110. Insertion is difficult. Therefore, as shown in FIGS. 4A to 4C, the opening size of the recess 110 may be made larger than the outer shape of the connection terminal 86 at the upper part and made smaller according to the shape of the connection terminal 86 at the lower part. In addition, the dimension (mm) shown to Fig.4 (a)-(c) is an example.

  4A and 4B, the side wall surface of the recess 110 is stepped, and in FIG. 4C, the side wall surface of the recess 110 is inclined. In either case, the upper dimension of the concave portion 110 in the upward direction in FIG. 4 is an example in which the upper part is made larger than the outer shape of the connection terminal 86 and the lower part is made smaller in accordance with the shape of the connection terminal 86. Since the dimension of the upper portion of the recess 110 is larger than the outer shape of the connection terminal 86, the connection terminal 86 can be easily inserted into the recess 110. And since the dimension of the lower part of the recessed part 110 is small according to the shape of the connection terminal 86, the position shift of the connection terminal 86 can be prevented.

  The number of stacked layers of the semiconductor package is not limited to two as shown in FIG. 2, but may be stacked in three, four, or more layers. In addition to the semiconductor package, what is stacked may be other than a semiconductor package, or a module component may be configured by stacking a semiconductor package and a package other than the semiconductor package.

  As described above, according to the present embodiment, the opening shape of the recess 110 provided in the sealing material 15 to expose a part of the connecting conductor 12 of the semiconductor package 10 is not a circle but a square or as shown in FIG. It has a simple shape. For this reason, a gap can always be formed between the connection terminal 86 and the side wall surface of the recess 110 without increasing the opening size of the recess 110. Therefore, when a plurality of layers are stacked, it is possible to prevent a connection failure between the upper and lower packages and to prevent a positional shift.

(Second Embodiment)
FIGS. 5A and 5B are diagrams for explaining a schematic configuration of the semiconductor package according to the second embodiment. FIG. 5A is a plan view, and FIG. 5B is an A- It is A 'sectional drawing. In addition, the same code | symbol is attached | subjected to FIG. 1 (a) (b) and an identical part, and the detailed description is abbreviate | omitted.

  The difference between the present embodiment and the first embodiment described above is the shape of the recess provided in the sealing material 15. That is, in the present embodiment, the upper portion of the sealing material 15 where the connection conductor 12 of the semiconductor package 20 is disposed is opened in a groove shape along the arrangement of the connection conductors 12, as shown in FIG. As described above, the recess 120 of the semiconductor package (first semiconductor package) 20 and the connection terminal 86 of another semiconductor package (second semiconductor package) 80 are fitted to each other.

  Since the recess 120 has a continuous groove shape, one direction around the connection terminal 86 is open. Therefore, the gas generated from the periphery of the connection conductor 12 and the connection terminal 86 at the time of reflow escapes from the open portion, so that connection failure between the conductor 12 and the connection terminal 86 can be prevented.

  In addition, since the position of the connection terminal 86 of the semiconductor package 80 is determined by the side wall surface of the recess 120, the mutual displacement between the semiconductor package 20 and the semiconductor package 80 can be prevented. That is, the position of the semiconductor package 80 in the Y direction can be defined by the side wall surface along the X direction of the recess 120, and the position of the semiconductor package 80 in the X direction can be defined by the side wall surface along the Y direction of the recess 120. .

  The cross-sectional shape of the recess 120 (the cross-sectional shape cut in the X direction in the portion along the Y direction and the cross-sectional shape cut in the Y direction in the portion along the X direction) is as described in the first embodiment. The upper part is made larger than the outer shape of the connection terminal 86 so that the connection terminal 86 can be easily inserted into the recess 120, and the lower part is made smaller in accordance with the shape of the connection terminal 86 to prevent displacement of the connection terminal 86. Also good. The number of stacking stages of the semiconductor package is not limited to two but may be stacked in multiple stages. Furthermore, what is laminated | stacked may be other than a semiconductor package as well as a semiconductor package.

  Even in such a configuration, the upper and lower packages can be positioned and degassed by the shape of the recess 120, and the same effect as in the first embodiment can be obtained.

(Third embodiment)
FIGS. 7A and 7B are diagrams for explaining the schematic configuration of the semiconductor package according to the third embodiment. FIG. 7A is a plan view, and FIG. It is A 'sectional drawing. In addition, the same code | symbol is attached | subjected to FIG. 1 (a) (b) and an identical part, and the detailed description is abbreviate | omitted.

  The present embodiment is different from the first embodiment in the shape of the recess provided in the sealing material. That is, in the present embodiment, the upper portion of the sealing material 15 on the outer peripheral portion outside the portion where the connecting conductor 12 of the semiconductor package 30 is disposed is removed, and as shown in FIG. The removal portion 131 of the semiconductor package 30 and the connection terminal 86 of the semiconductor package (second semiconductor package) 80 are fitted.

  Since the removal portion 131 has a structure lowered from the upper surface of the semiconductor package 30, the periphery of the connection terminal 86 (in the package outer direction) is open, and the gas generated from the periphery of the connection conductor 12 and the connection terminal 86. And the connection failure between the conductor 12 and the connection terminal 86 can be prevented.

  Further, since the position of the connection terminal 86 of the semiconductor package 80 is determined by the side surface 132 of the removal portion 131, the mutual displacement of the semiconductor package 30 and the semiconductor package 80 can be prevented.

  Further, as shown in FIGS. 9A to 9C, the removal unit 131 has a shape in which the upper part of the side surface is separated from the connection terminal 86 so that the connection terminal 86 can be easily inserted into the removal unit 131, and the lower part of the side surface is the connection terminal. A shape close to the connection terminal 86 according to the shape of 86 may be used to prevent the displacement of the connection terminal 86. In addition, the dimension shown to Fig.9 (a)-(c) is an example.

  9 (a) and 9 (b), the side surface of the removal portion 131 is stepped, and in FIG. 9 (c), the side surface of the removal portion 131 is inclined so that the upper side surface is separated from the connection terminal 86, and the lower side surface is According to the shape of the connection terminal 86, the connection terminal 86 is approached. Since the upper portion of the removal portion 131 is separated from the connection terminal 86, the connection terminal 86 can be easily inserted into the removal portion 131. And since the lower part of the removal part 131 is made to approach the connection terminal 86 according to the shape of the connection terminal 86, the position shift of the connection terminal 86 can be prevented.

  The number of stacking stages of the semiconductor package is not limited to two but may be stacked in multiple stages. Moreover, what is laminated | stacked may be other than a semiconductor package as well as a semiconductor package.

  Even with such a configuration, the upper and lower packages can be positioned and degassed by forming the removal portion 131, and the same effect as in the first embodiment can be obtained. Further, in the present embodiment, since the removal portion 130 has a shape that communicates with the outer peripheral side surface, there is an advantage that the filler can be filled between the packages 30 and 80 via the removal portion 13 when the filler is applied to the package side surface. is there.

(Fourth embodiment)
FIGS. 10A and 10B are views for explaining a schematic configuration of a semiconductor package according to the fourth embodiment. FIG. 10A is a plan view, and FIG. It is A 'sectional drawing. In addition, the same code | symbol is attached | subjected to FIG. 1 (a) (b) and an identical part, and the detailed description is abbreviate | omitted.

  The difference between the present embodiment and the first embodiment is that the connecting conductor is disposed not in the peripheral portion but in the central portion.

  One or more semiconductor chips 13 are mounted on the wiring medium 11, and a rewiring medium 17 to which the connecting conductor 12 is bonded is mounted on the uppermost semiconductor chip. The wiring medium 11, the semiconductor chip 13, and the rewiring medium 17 are connected by wires 14, and the wiring medium 11, the connecting conductor 12, the semiconductor chip 13, and the rewiring medium 17 are electrically connected. As the wiring medium 11, for example, a printed wiring board or a flexible wiring board can be used. The connecting conductor 12 is made of, for example, solder, tin, or copper, and may have any shape such as a spherical shape, a square shape, a columnar shape, a cylindrical shape, a prismatic shape, or a rectangular tube shape. As the rewiring medium 17, for example, a rewiring layer formed on a printed wiring board or a semiconductor chip can be used.

  One surface of the wiring medium 11, the connecting conductor 12, the rewiring medium 17, and the semiconductor chip 13 are sealed with a sealing material 15. A connection terminal 16 is joined to the lower part of the wiring medium 11 so that the semiconductor package and an external circuit can be electrically connected. For example, solder balls are used as the connection terminals 16.

  The upper portion of the sealing material 15 where the connecting conductor 12 of the semiconductor package 40 is disposed is removed to form a recess 140 to expose part or all of the connecting conductor 12. Examples of the method for removing the sealing material 15 include laser processing, dry etching, wet etching, and cutting.

  On the other hand, another semiconductor package (second semiconductor package) 90 mounted on the semiconductor package (first semiconductor package) 40 of the present embodiment has a configuration of the semiconductor package 40 as shown in FIG. In FIG. 8, the connecting conductor 12, the rewiring medium 17, and the recess 140 are not provided, and a connection terminal 96 is formed on the lower surface. The connection terminal 96 is, for example, a solder ball, and is provided so as to be aligned with the connection conductor 12 of the semiconductor package 40.

  As shown in FIG. 11A, the semiconductor package 90 is mounted on the semiconductor package 40 so that the connection conductor 12 of the semiconductor package 40 and the connection terminal 96 of the semiconductor package 90 are aligned. Thereafter, for example, when it is passed through a reflow furnace, as shown in FIG. 11B, the connecting conductor 12 and the connecting terminal 96 are joined to form an integrated connecting portion 97, and the semiconductor package 40 and the semiconductor package 90 are connected. The PoP structure will be completed.

  In the present embodiment, since the shape of the recess 140 of the semiconductor package 40 is a square as shown in FIG. 10, a gap is formed between the sealing material 15 and the connection terminal 96 at the corner of the recess 140. Therefore, when the connection conductor 12 and the connection terminal 96 are melt-bonded at a high temperature, the gas generated from the periphery of the connection conductor 12 and the connection terminal 96 passes through the gap at the corner of the recess 140 from under the connection terminal 96. Thus, the connection conductor 12 and the connection terminal 96 can be prevented from being defectively bonded.

  In addition, since the position of the connection terminal 96 is determined by the side surface of the recess 140, the semiconductor package 40 and the semiconductor package 90 can be prevented from being displaced from each other.

  The shape of the recess 140 is not limited to a quadrangle, and as shown in FIG. 3, there is a gap through which gas escapes between the sealing material 5 and the connection terminal 66 such as a triangle, a polygon, a cross, a star, and a flower. Any shape that suppresses the displacement of the connection terminal 96 may be used.

  Thus, according to the present embodiment, positioning of the upper and lower packages and degassing can be performed by the shape of the recess 140, and the same effect as in the first embodiment can be obtained.

(Fifth embodiment)
12A and 12B are views for explaining a schematic configuration of a semiconductor package according to the fifth embodiment. FIG. 12A is a plan view, and FIG. 12B is an A- It is A 'sectional drawing. In addition, the same code | symbol is attached | subjected to FIG. 1 (a) (b) and an identical part, and the detailed description is abbreviate | omitted.

  This embodiment is different from the previous four embodiments in that the concave portions are not provided individually but are provided continuously. That is, the recess 150 is opened so as to cover all the connecting conductors 12. As shown in FIG. 13, the recess 150 of the semiconductor package 50 and the connection terminal 96 of the semiconductor package 90 are fitted together.

  In this case, since the periphery of the connection terminal 96 of the semiconductor package 90 is open, the gas generated at the time of reflow can easily escape from the open portion, and connection failure between the conductor 12 and the connection terminal 96 can be prevented. Further, the position of the semiconductor package 90 in the Y direction can be defined by the side wall surface along the X direction of the recess 150, and the position of the semiconductor package 90 in the X direction can be defined by the side wall surface along the Y direction of the recess 150. .

  14 (a) and 14 (b) are examples in which the recess 160 is opened with a certain number of connecting conductors 12, and as shown in FIG. 15, the connection between the recess 160 of the semiconductor package 50 ′ and the semiconductor package 90 is shown. The terminal 96 fits into the structure.

  16 (a) and 16 (b) are examples in which a portion in which the concave portion 170 is opened for each connecting conductor 12 and a portion in which the connecting conductor 12 is opened in every certain number are mixed, as shown in FIG. As described above, the recess 170 of the semiconductor package 50 ″ and the connection terminal 96 are fitted together.

  As described in the first embodiment, in order to facilitate the insertion of the connection terminal 96 into the recesses 150, 160, and 170 and to prevent the displacement of the connection terminal 96, the opening dimensions of the recesses 150, 160, and 170 are set. The upper part may be larger than the outer shape of the connection terminal 96, and the lower part may be made smaller in accordance with the shape of the connection terminal 96. 18 (a) and 18 (b), the side surface of the recess 150 is stepped, and in FIG. 18 (c), the side surface of the recess 150 is inclined so that the opening size of the recess 150 is larger than the outer shape of the connection terminal 96. In this example, the size is increased and the lower portion is reduced in accordance with the shape of the connection terminal 96. Since the opening size of the upper part of the recess 150 is larger than the outer shape of the connection terminal 96, the connection terminal 96 can be easily inserted into the recess 150. And since the lower part of the recessed part 150 is small according to the shape of the connection terminal 96, the position shift of the connection terminal 96 can be prevented.

  The number of stacking stages of the semiconductor package is not limited to two but may be stacked in multiple stages. Moreover, what is laminated | stacked may be other than a semiconductor package as well as a semiconductor package.

  As described above, according to the present embodiment, by devising the shapes of the recesses 150, 160, and 170, the upper and lower packages can be positioned and degassed. Therefore, the same effect as in the first embodiment can be obtained. It is done.

(Sixth embodiment)
FIGS. 19A and 19B are views for explaining a schematic configuration of a semiconductor package according to the sixth embodiment. FIG. 19A is a plan view, and FIG. It is A 'sectional drawing. In addition, the same code | symbol is attached | subjected to FIG. 1 (a) (b) and an identical part, and the detailed description is abbreviate | omitted.

  In the semiconductor package 60 of the present embodiment, the connection terminal 16 of the semiconductor package 40 shown in FIG. 10 is removed, and the connection terminal 26 is formed in the connection conductor 12 portion.

  As shown in FIG. 20A, the upper portion of the sealing material 15 is removed for each connection conductor 12 to form a recess 140. Subsequently, as shown in FIG. 20B, the connecting conductor 22 is mounted on the connecting conductor 12 in the recess 140. For example, a solder ball is used as the connecting conductor 22. Then, for example, through a reflow furnace, the connecting conductor 12 and the connecting conductor 22 are melt-bonded to form the connection terminal 26 as shown in FIG.

  In this embodiment, since the opening shape of the recess 140 of the semiconductor package 60 is a square, a gap is formed between the sealing material 15 and the connecting conductor 26 at the corner of the recess 140. Therefore, when the connecting conductor 12 and the connecting conductor 22 are melt-bonded at a high temperature, the gas generated from the periphery of the connecting conductor 12 and the connecting conductor 22 flows from below the connecting conductor 22 into the recess 140. It is possible to prevent the connection conductor 12 and the connection conductor 22 from being poorly bonded by passing upward through the gaps at the corners.

  Further, since the position of the connecting conductor 22 is determined by the side wall surface of the recess 140, it is possible to prevent the connecting conductor 12 and the connecting conductor 22 from being displaced from each other and joined. Furthermore, the shape of the recess 140 is not limited to a quadrangle, and as shown in FIGS. 3A to 3E, the sealing material 15 and the connecting conductor such as a triangle, a polygon, a cross, a star, and a flower are used. Any shape can be used as long as a gap through which gas can escape is formed between the connecting conductor 22 and the connecting conductor 22 is prevented from being displaced.

  Further, as described in the first embodiment, in order to facilitate the insertion of the connecting conductor 22 into the recess 140 and to prevent the connecting conductor 22 from being displaced, the above-described FIGS. ), The opening size of the recess 140 may be made larger than the outer shape of the connecting conductor 22 in the upper part and may be made smaller together with the connecting conductor 2 in the lower part.

  In addition, the semiconductor package 60 may be used alone or may be stacked as shown in FIGS. FIG. 21A shows an example in which the semiconductor packages 60 of FIG. 19 are stacked. FIG. 21B shows an example in which the semiconductor package 60 of FIG. 19 is turned upside down, the connection terminals 16 are joined on the wiring medium 11, and the semiconductor package 60 ′ of FIG. It is.

  As described above, according to the present embodiment, a semiconductor package having the connection terminal 26 protruding on the upper surface side can be manufactured. In this case, by devising the shape of the recess 140, it is possible to prevent the occurrence of displacement and poor connection when the connection terminal 26 is formed. In addition, there is an advantage that it is easy to produce a stacked package in which these are stacked.

(Seventh embodiment)
FIGS. 22A and 22B are views for explaining a schematic configuration of the semiconductor package according to the seventh embodiment. FIG. 22A is a plan view, and FIG. It is A 'sectional drawing. In addition, the same code | symbol is attached | subjected to FIG. 1 (a) (b) and an identical part, and the detailed description is abbreviate | omitted.

  The difference between the present embodiment and the first embodiment described above is that the recess 110 provided in the sealing material 15 is connected to the side surface of the sealing material 15. That is, the recess 110 is opened on the side surface of the sealing material 15 by the groove 210 having the same depth as the recess 110.

  On the other hand, another semiconductor package (second semiconductor package) 80 mounted on the semiconductor package (first semiconductor package) 10 of the present embodiment is the same as the semiconductor package used in the first embodiment.

  As shown in FIG. 23A, the semiconductor package 80 is mounted on the semiconductor package 10 so that the connection conductors 12 of the semiconductor package 10 and the connection terminals 86 of the semiconductor package 80 are aligned, and the connection terminals 86 is inserted into the recess 110. Then, for example, the connection terminal 86 is reflowed by passing through a reflow furnace. As a result, as shown in FIG. 23B, the connecting conductor 12 and the connection terminal 86 are joined to form an integrated connection portion 87, the semiconductor package 10 and the semiconductor package 80 are connected, and the PoP structure is completed. become. Here, in order to minimize the height dimension in the stacked state in order to reduce the size of parts, there is no gap (or very small, the same applies hereinafter) between the semiconductor package 10 and the semiconductor package 80. Yes.

  Here, in a semiconductor device having a PoP structure, a filler may be filled in a joint portion of the semiconductor device in order to improve reliability against shock, vibration, and thermal cycle stress. In such a case, if there is no gap between the semiconductor packages, there may be a problem that even if the filler is applied around the semiconductor device, the filler is not filled between the packages. On the other hand, in this embodiment, this problem is solved by providing a groove.

  In this embodiment, as shown in FIG. 24A, the PoP structure semiconductor device 100 is mounted on the mounting substrate 200, and as shown in FIG. 24B, the filler 300 is placed around the semiconductor device 100. Apply to. The filler 300 is filled and cured around the connection portion between the semiconductor package 10 and the mounting substrate 200 and the connection portion between the semiconductor package 10 and the semiconductor package 80.

  Here, in this embodiment, since the concave portion 110 of the semiconductor package 10 communicates with the outer peripheral side surface by the groove 210, the filler 300 passes from the outside of the semiconductor package 10 through the groove 210 to the semiconductor package 10 and the semiconductor package 80. Is filled around the connection. Therefore, even if the semiconductor package 10 and the semiconductor package 80 are stacked without a gap, the periphery of the connection portion can be filled with the filler 300, and both the reliability improvement and the thickness reduction of the semiconductor device 100 can be achieved.

  The number of stacked layers of the semiconductor device 100 is not limited to two as shown in FIG. 23, but may be stacked in three, four, or more layers. In addition to the semiconductor package, what is stacked may be other than a semiconductor package, or a module component may be configured by stacking a semiconductor package and a package other than the semiconductor package.

  In addition, in this embodiment, since it has the groove | channel connected to the side surface of the sealing material 15, degassing is possible even if the shape of a recessed part is not square. Therefore, as shown in FIG. 25, a notch structure 180 in which the recess and the groove are integrated may be provided. In this case as well, positioning and degassing can be performed, and it is possible to efficiently fill the filler when mounted on the mounting board.

  As described above, in this embodiment, the effect similar to that of the first embodiment can be obtained, and even if the semiconductor packages are stacked without a gap, the filler 300 forms the groove 210 from the outer peripheral side surface. Through this, the connection portion between the semiconductor packages is filled, and it is possible to achieve both improvement in reliability and thinning of the semiconductor device. Further, since the concave portion 110 is formed so as to communicate with the outer peripheral side surface, the filler 300 can be reliably filled up to the central portion of the semiconductor package, and the restriction on the position of the connection portion between the semiconductor packages is reduced. For this reason, there is also an advantage that the degree of freedom in designing the semiconductor package is improved.

(Eighth embodiment)
FIGS. 26A and 26B are views for explaining a schematic configuration of the semiconductor package according to the eighth embodiment. FIG. 26A is a plan view, and FIG. It is A 'sectional drawing. In addition, the same code | symbol is attached | subjected to the same part as FIG.

  The difference of this embodiment from the fifth embodiment described above is that a part of the recess 150 provided in the sealing material 15 is connected to the side surface of the sealing material 15 by the groove 230. That is, the recess 150 is opened on four side surfaces of the sealing material 15 by four grooves 230 provided in the surface portion of the sealing material 15 at the same depth as the recess 150.

  On the other hand, another semiconductor package (second semiconductor package) 90 mounted on the semiconductor package (first semiconductor package) 50 of the present embodiment is the same as the semiconductor package used in the fourth embodiment.

  As shown in FIG. 27A, the semiconductor package 90 is mounted on the semiconductor package 50 so that the connection conductor 12 of the semiconductor package 50 and the connection terminal 96 of the semiconductor package 90 are aligned. Thereafter, for example, when passed through a reflow furnace, as shown in FIG. 27B, the connecting conductor 12 and the connecting terminal 96 are joined to form an integrated connecting portion 97, and the semiconductor package 40 and the semiconductor package 90 are connected. The PoP structure will be completed. Here, in order to minimize the height dimension in the stacked state, there is no gap between the semiconductor package 50 and the semiconductor package 90.

  Then, as shown in FIG. 28A, the PoP structure semiconductor device 500 is mounted on the mounting substrate 200, and as shown in FIG. 28B, the filler 300 is applied around the semiconductor device 500. . The filler 300 is filled and cured around the connection portion between the semiconductor package 50 and the mounting substrate 200 and the connection portion between the semiconductor cage 50 and the semiconductor package 90.

  Here, in the present embodiment, since the concave portion 150 of the semiconductor package 50 communicates with the outer peripheral side surface by the groove 230, the filler 300 passes from the outside of the semiconductor package 50 through the groove 230 to the semiconductor package 50 and the semiconductor package 90. Is filled around the connection. Therefore, even if the semiconductor package 50 and the semiconductor package 90 are stacked without a gap, the periphery of the connection portion can be filled with the filler 300, and both the reliability of the semiconductor device 500 can be improved and the thickness can be reduced.

  Note that the number of stacking stages of the semiconductor device is not limited to two but may be stacked in multiple stages. Furthermore, what is laminated | stacked may be other than a semiconductor package as well as a semiconductor package. Further, the present embodiment is not limited to the configuration shown in FIG. 12, but can be applied to the configuration shown in FIG. That is, you may make it provide the groove | channel for opening a part of recessed part 120 of FIG.

  As described above, in this embodiment, the effect similar to that of the fifth embodiment can be obtained, and even if the semiconductor packages are stacked without a gap, the filler 300 forms the groove 230 from the outer peripheral side surface. Through this, the connection portion between the semiconductor packages is filled, and it is possible to achieve both improvement in reliability and thinning of the semiconductor device. In addition, since the recess 150 is formed so as to communicate with the outer peripheral side surface, the filler 300 can be reliably filled up to the central portion of the semiconductor package, and the restriction on the position of the connection portion between the semiconductor packages is reduced. For this reason, there is also an advantage that the degree of freedom in designing the semiconductor package is improved.

(Modification)
The present invention is not limited to the above-described embodiments.

  The opening shape of the concave portion for each connection conductor provided on the covering member is not limited to the quadrangle or the shape shown in FIG. 3, but a portion having a short distance from the center to the side wall for positioning, a gas Any structure having a long distance from the center for removal to the side wall may be used.

  Furthermore, as a method for forming the recess, the recess is not formed by removing a part by laser processing or etching after the formation of the covering member, but by filling the covering member in the region excluding the recess when forming the covering member. You may make it form the coating | coated member which has.

  In addition, a plurality of semiconductor packages are not necessarily stacked, and components other than semiconductors can be stacked on the semiconductor package.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 10, 20, 30, 40, 50, 60 ... 1st semiconductor package 80, 90 ... 2nd semiconductor package 11 ... Wiring medium 12, 26 ... Conducting conductor 13 ... Semiconductor chip 14 ... Wire 15 ... Sealing material (Coating member)
DESCRIPTION OF SYMBOLS 16,22 ... Connection terminal 17 ... Rewiring medium 100,500 ... POP structure semiconductor device 110,120,140,150,160,170 ... Recess 131 ... Removal part 132 ... Removal part side surface 180 ... Notch structure 200 ... Mounting Substrate 210, 230 ... groove 300 ... filler

Claims (8)

  1. A semiconductor chip mounted on a wiring medium;
    A plurality of connecting conductors provided on the wiring medium and provided for connection to the outside;
    A covering member that is provided so as to cover the wiring medium, the semiconductor chip, and the connecting conductor, and that has a plurality of recesses that expose the upper portions of the connecting conductors;
    Comprising
    The concave portion of the covering member has a portion having a short distance from the center to the side wall and a portion having a long distance from the center to the side wall,
    The semiconductor device according to claim 1, wherein the concave portion of the covering member has an upper portion formed larger than an outer shape of the connecting conductor, and a lower portion formed smaller in accordance with the shape of the connecting conductor.
  2. A semiconductor chip mounted on a wiring medium;
    A plurality of connecting conductors provided on the wiring medium and provided for connection to the outside;
    A covering member that is provided so as to cover the wiring medium, the semiconductor chip, and the connecting conductor, and that has a plurality of recesses that expose the upper portions of the connecting conductors;
    Comprising
    The recess of the covering member has a shape having a portion having a short distance from the center to the side wall and a portion having a long distance from the center to the side wall.
  3.   3. The semiconductor device according to claim 1, wherein a groove is further formed in the surface portion of the covering member so that the recesses communicate with the side surfaces of the covering member.
  4. A semiconductor chip mounted on a wiring medium;
    A plurality of connecting conductors provided on the wiring medium along the periphery of the medium and provided for connection to the outside;
    Provided so as to cover the wiring medium, the semiconductor chip, and the connecting conductor, and continuously provided along the periphery of the wiring medium so as to expose an upper portion of each connecting conductor. A covering member having a recess;
    A semiconductor device comprising:
  5. A semiconductor chip mounted on a wiring medium;
    A plurality of connecting conductors provided on the wiring medium along the periphery of the medium and provided for connection to the outside;
    A covering member that is provided so as to cover the wiring medium, the semiconductor chip, and the connecting conductor, and that has a stepped portion with a lower peripheral portion so as to expose an upper portion of each connecting conductor;
    A semiconductor device comprising:
  6. A semiconductor chip mounted on a wiring medium;
    A plurality of connecting conductors provided on the semiconductor chip or on the semiconductor chip via another wiring medium and provided for connection to the outside;
    A recess provided to cover the wiring medium, the semiconductor chip, and the connecting conductor, and to be provided across a plurality of connecting conductors so as to expose an upper portion of each connecting conductor. A covering member having,
    A semiconductor device comprising:
  7.   The semiconductor device according to claim 4, wherein a groove is further formed in the surface portion of the covering member so as to communicate a part of the recess with a side surface of the covering member.
  8. A first semiconductor package having the configuration according to claim 3, 5, or 7;
    A second semiconductor package stacked on the first semiconductor package;
    A mounting substrate on which the first semiconductor package on which the second semiconductor package is stacked is mounted;
    A filler formed on a side surface of the first semiconductor package and filled in a connection portion of the first and second semiconductor packages;
    A semiconductor device comprising:
JP2012184085A 2012-03-23 2012-08-23 Semiconductor device Pending JP2013225638A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2012068379 2012-03-23
JP2012068379 2012-03-23
JP2012184085A JP2013225638A (en) 2012-03-23 2012-08-23 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012184085A JP2013225638A (en) 2012-03-23 2012-08-23 Semiconductor device
TW101131621A TWI495053B (en) 2012-03-23 2012-08-30 Semiconductor device
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JP4409455B2 (en) * 2005-01-31 2010-02-03 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
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US9613933B2 (en) 2014-03-05 2017-04-04 Intel Corporation Package structure to enhance yield of TMI interconnections
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US10049971B2 (en) 2014-03-05 2018-08-14 Intel Corporation Package structure to enhance yield of TMI interconnections
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