JP2010212605A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that improves performance reliability, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes: a package substrate 13; a semiconductor memory 16 mounted on one surface of the package substrate 13; an external terminal 11, of the semiconductor memory 16, arranged on the other surface of the package substrate 13; an internal wiring board 19 which is formed on the semiconductor memory 16 via a spacer 18 made of an insulator, and has a plurality of electrode pads 24 on its surface; an internal terminal 21 arranged on each of the electrode pads 24 and electrically connected with the external terminal 11; and an insulating resin 22 covering from the surface of the package substrate 13 to the internal terminal 21. On the upper surface of the internal terminal 21, only the insulating resin 22 is formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Conventionally, a package-on-package (hereinafter referred to as PoP) in which surface-mount semiconductor devices such as a land grid array (hereinafter referred to as LGA) and a ball grid array (hereinafter referred to as BGA) are stacked. ), It is necessary to change the shapes of the lower package and the upper package in order to configure the PoP.

  Therefore, there are problems in that a process for manufacturing each of the lower package and the upper package is generated, and there is a problem of high costs such as capital investment for manufacturing, testing, and evaluating the packages, and time required for development of the packages. (See Patent Document 1).

JP 2008-118140 A

  The present invention seeks to provide a semiconductor device that improves productivity and a method for manufacturing the same.

  A semiconductor device according to an aspect of the present invention includes a package substrate, a semiconductor memory mounted on one surface of the package substrate, an external terminal of the semiconductor memory disposed on the other side of the package substrate, and an insulator An internal wiring substrate formed on the semiconductor memory and having a plurality of electrode pads on the surface thereof, and disposed on each of the electrode pads and electrically connected to the external terminals via spacers made of And an insulating resin that covers from the surface of the package substrate to the internal terminal, and only the insulating resin is formed on the upper surface of the internal terminal.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method in which a first semiconductor memory is mounted on one surface and a first external terminal of the first semiconductor memory is disposed on the other surface. By forming a first insulating resin on the one surface of the package substrate surface, the first substrate is formed on the first semiconductor memory with a spacer made of an insulator as a material, and has a plurality of first electrode pads. A first semiconductor device is manufactured by coating a first internal wiring board having a first internal terminal electrically connected to the first external terminal on the first electrode pad with the first insulating resin. And a step of scraping the first insulating resin until an upper surface of the first internal terminal is exposed.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which improves productivity, and its manufacturing method can be provided.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. Sectional drawing of the X1-X1 direction in FIG. 1 is a cross-sectional view of a semiconductor device adopting a PoP structure according to a first embodiment of the present invention. Sectional drawing which shows the 1st manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the 2nd manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing which shows the 3rd manufacturing process of the semiconductor device which concerns on 1st Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on the modification of 1st Embodiment of this invention. Sectional drawing of the semiconductor device which concerns on 2nd Embodiment of this invention. The top view of the semiconductor device which concerns on 3rd Embodiment of this invention. The top view of the X2-X2 direction in FIG. Sectional drawing of the semiconductor device which employ | adopted the PoP structure based on 3rd Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First embodiment]
1 and 2 show configuration examples of the surface-mount type semiconductor device according to the first embodiment of the present invention. Here, a semiconductor device having a BGA structure will be described as an example. FIG. 1 is a plan view of a semiconductor device having a BGA structure, and is a perspective view showing an internal structure. FIG. 2 shows a cross-sectional view in the X1-X1 direction in FIG.

  As shown in the figure, the semiconductor device 10 includes a base substrate 11, an external connection terminal 12, a semiconductor memory chip 13, a spacer 14, an external connection substrate 15, an internal connection terminal 16, bonding wires 17 and 18, and a mold resin 19. Yes.

  A substrate 11 for external connection (hereinafter referred to as a base substrate 11) is a thin plate 21 (hereinafter referred to as a film 21) made of a polymer material such as a solder resist 20-1, a solder resist 20-2, for example, polyimide, And electrode pads 22 and 23. Further, when the solder resists 20-1 and 20-2 are not distinguished, they are simply referred to as solder resists 20.

  The film 21 is a mounting substrate for the semiconductor memory chip 13 and is formed of a polymer material such as polyimide. Wiring (not shown) is formed on the front surface and the back surface of the film 21 using a copper foil or other metal material.

  The electrode pads 22 and 23 are formed on the back surface and the front surface of the film 21, respectively. The electrode pads 22 are two-dimensionally arranged in the back surface of the film 21 and function as ball lands for joining the external connection terminals 12. On the other hand, the electrode pads 23 are arranged along the edges in the upper surface of the film 21.

  The solder resist 20 is formed on the front surface and the back surface of the film 21, and the solder resist 20 insulates between the wirings and between the electrode pads 22 and 23, and prevents these corrosions.

  The electrode pads 22 and 23 are electrically connected to each other by a wiring (not shown) provided on the surface of the base substrate 11 or inside thereof.

  The external connection terminal 12 is, for example, a solder ball formed on the base substrate 11. The external connection terminal 12 is used for the semiconductor device 10 to be electrically connected to the outside. That is, the external connection terminal 12 transmits / receives a control signal from a control chip (not shown) that controls the semiconductor memory chip 13, and inputs / outputs data to / from the outside based on the control signal. The solder ball is not limited as long as it can be connected to the outside. A plurality of external connection terminals 12 are two-dimensionally arranged in the front surface of the base substrate 11. In addition, the external connection terminal 12 is connected to any one of the electrode pads 22 serving as a ball land by a reflow process.

  The semiconductor memory chip 13 is mounted on the surface of the base substrate 11. The semiconductor memory chip 13 is a memory chip including, for example, a NAND flash memory, and includes an electrode pad 24 on the surface for electrical connection with the outside.

  The bonding wire 17 electrically connects the electrode pad 24 of the semiconductor memory chip 13 and the electrode pad 23 of the base substrate 11. As a result, the semiconductor memory chip 13 is electrically connected to the electrode pads 22 and the external connection terminals 12 through the bonding wires 17, the electrode pads 23, and through holes (not shown) formed in the base substrate 11. The bonding wire 17 formed with the electrode pad 24 as a base point is formed to have a height of “H” from the electrode pad 24.

  The spacer 14 is formed of a polymer material such as glass / epoxy material or polyimide material. The spacer 14 is formed by being bonded to the semiconductor memory chip 13 with an adhesive material (not shown). The height ‘H’ of the spacer 14 is large enough to ensure the height of the bonding wire 17 described above (denoted as H in the figure).

  The internal connection substrate 15 is made of, for example, a polymer material such as glass / epoxy material or polyimide material, or TAB tape. The internal connection substrate 15 is formed on the spacer 14. The spacers 14 are bonded to each other by an adhesive material (not shown).

  The electrode pads 27 are two-dimensionally arranged in the vicinity of the substantially central portion of the internal connection substrate 15 and function as ball lands for joining to the internal connection terminals 16.

  The electrode pads 25 are arranged along the edge of the internal connection substrate 15 so as to surround the periphery of the ball land formed by the electrode pads 27.

  The wiring 26 is formed of, for example, metal on the surface of the internal wiring substrate 15 or inside thereof. The wiring 26 electrically connects the electrode pads 25 and 27.

  The internal connection terminal 16 is, for example, a solder ball formed on the surface of the internal connection substrate 15. Similar to the external connection terminal 12, the internal connection terminal 16 is used for the semiconductor device 10 to be electrically connected to the outside. However, the difference from the external connection terminal 12 is that the internal connection terminal 16 is used between the semiconductor device 10 and another semiconductor device when the semiconductor device 10 forms a PoP together with the other semiconductor device. The internal connection terminals 16 are brought into contact with the electrode pads 27 of the internal connection substrate 15 by a reflow process.

  The bonding wire 18 electrically connects the electrode pad 25 and the electrode pad 23 of the base substrate 11. As a result, the external connection terminals 16 are electrically connected to the electrode pads 22 and the external connection terminals 12 through the bonding wires 18, the electrode pads 23, and through holes (not shown) formed in the base substrate 11.

  Further, a mold resin 19 is laminated on the base substrate 11 so as to cover the upper surface of the internal connection terminal 16.

  Next, the state of PoP formed by stacking a plurality of the semiconductor devices 10 described above will be described with reference to FIG. FIG. 3 is a cross-sectional view of the PoP according to the present embodiment, and shows an example in which two semiconductor devices 10 are stacked as an example. Hereinafter, for convenience of explanation, the lower layer semiconductor device 10 in the stacked structure is referred to as a semiconductor device 10-1, and the upper layer semiconductor device 10 is referred to as a semiconductor device 10-2. That is, since each member constituting the semiconductor devices 10-1 and 10-2 is the same as that of the semiconductor device 10, description thereof is omitted.

  As shown in the drawing, the semiconductor device 10-1 is formed as a lower layer semiconductor device having a PoP structure. The lower layer semiconductor device according to the present embodiment is a semiconductor device 10-1 in which the surface of the mold resin 19 is cut in the semiconductor device 10-1 and a part of the upper surface of the internal connection terminal 16 is exposed.

  The semiconductor device 10-2 is mounted on the semiconductor device 10-1. The external connection terminal 12 included in the semiconductor device 10-2 and the internal connection terminal 16 included in the semiconductor device 10-1 are electrically connected. Thereby, the exchange of data of the semiconductor memory chip 13 in the semiconductor device 10-2 with the outside is performed by the electrode pad 24, the bonding wire 17, the electrode pad 23, the through hole (not shown), and the electrode pad 22 provided in the semiconductor device 10-2. The external connection terminal 12 and the internal connection terminal 16 included in the semiconductor device 10-1 are used.

  Next, a manufacturing process of PoP formed by the semiconductor devices 10-1 and 10-2 will be described with reference to FIGS. As shown in FIG. 4, the semiconductor memory chip 13 is first formed on the base substrate 11. Thereafter, the spacer 14 is mounted on the semiconductor memory chip 13. Then, the bonding wire 17 formed starting from the electrode pad 24 is electrically connected to the electrode pad 23. At this time, since the electrode pad 24 is formed as a starting point, the bonding wire 17 has a bow shape having a height of “H” from the electrode pad 24.

  Subsequently, the internal connection board 15 is mounted on the spacer 14. Thereafter, the internal connection terminals 16 are formed on ball lands (not shown) formed on the internal connection substrate 15. An adhesive material (not shown) is applied between the semiconductor memory chip 13 and the spacer 14, the spacer 14 and the internal connection substrate 15, and the internal connection substrate 15 and the internal connection terminal 16. The materials adhere to each other.

  Then, the electrode pad 25 and the electrode pad 23 are connected by the bonding wire 18.

  Next, as shown in FIG. 5, a mold resin 19 is formed on the base substrate 11 to cover up to the upper surface of the internal connection terminals 16. That is, the semiconductor memory chip 13 is sealed with the mold resin 19.

  Subsequently, the mold resin 19 is shaved until the upper surface of the internal connection terminal 16 is exposed. This is shown in FIG. Thereafter, the semiconductor device 10-2 is stacked on the semiconductor device 10-1, and the internal connection terminal 16 of the semiconductor device 10-1 and the external connection terminal 12 of the semiconductor device 10-2 are joined. Thereby, the PoP shown in FIG. 3 is formed.

<Effects according to this embodiment>
The semiconductor device and the manufacturing method thereof according to the present embodiment can achieve the following effects.

        (1) Production efficiency can be improved.

  That is, it is possible to configure the PoP with the same semiconductor device, solve the cost problem such as capital investment for manufacturing, testing, and evaluating the semiconductor device, and the time required for developing the semiconductor device. Can be shortened.

  This is because, conventionally, in order to form PoP, the external connection terminal of the upper-layer semiconductor device is electrically connected to the lower-layer semiconductor device. Therefore, the mold resin is used until the electrode pad of the lower-layer semiconductor device is exposed. It was necessary to excavate a portion and to provide solder balls to be connected to the upper semiconductor device on the exposed electrode pads. In other words, the manufacturing process has increased due to the necessity of manufacturing semiconductor devices having different shapes. For this reason, it took time to develop the semiconductor device and cost problems such as manufacturing, testing, and capital investment for evaluating the semiconductor device.

  Furthermore, as disclosed in Patent Document 1, there is a structure in which PoP is put in one container and a plurality of such containers are stacked. However, this structure further requires solder balls when the containers are electrically connected. That is, there is a problem that not only a new member is required but also the manufacturing process increases.

  In this regard, in the semiconductor device according to the present embodiment, the semiconductor devices 10-1 and 10-2 themselves include the internal connection terminals 16 that can be directly electrically connected to each other. That is, the number of manufacturing steps can be reduced as compared with the conventional case.

  The semiconductor device 10 is covered with a mold resin 19. For this reason, it is possible to satisfy the demand as a form of a semiconductor device which is insulated from the outside and sent to the market even with the semiconductor device 10 alone. That is, the semiconductor device as shown in FIG. 1 may be used.

  In the present embodiment, the internal connection terminal 16 of the semiconductor device 10-1 and the external connection terminal 12 included in the semiconductor device 10-2 are electrically connected by scraping the mold resin 19 of the semiconductor device 10. Can do. That is, PoP can be easily configured.

  As described above, the configuration of the semiconductor device can be easily changed in accordance with market demand. In addition, it is possible to solve the conventional problems such as manufacturing costs and the time required for the semiconductor device 10 to be finally sent to the market.

<Modification>
Next, a semiconductor device according to a modification of the first embodiment will be described. Explanation of the same members as those of the semiconductor device 10 is omitted.

  A configuration of the semiconductor device 20 according to the modification will be described with reference to FIG. FIG. 7 shows a configuration in which the spacer 14 is eliminated from the semiconductor device 10 described with reference to FIG. That is, the internal connection substrate 15 is directly formed on the semiconductor memory chip 13 via an adhesive material (not shown).

  As shown in the figure, the spacer 14 can be omitted because wire bonding is performed starting from the electrode pad 23 when the bonding wire 17 is formed. That is, if the bonding wire 17 is formed from the electrode pad 23 to the electrode pad 24, the above-described height H becomes substantially zero. At this time, an adhesive material (not shown) for bonding the semiconductor memory chip 13 and the internal connection substrate 15 functions as a spacer. Note that the manufacturing steps of the semiconductor device according to the modification are the same except for the step of forming the spacers 14, and thus the description thereof is omitted.

<Effect according to modification>
In addition to the effect according to the first embodiment, the following effect (2) can be achieved with the semiconductor device according to the modification and the manufacturing method thereof.

        (2) The manufacturing process can be omitted, and the height of PoP itself can be reduced.

  In the semiconductor device according to the modification, the bonding wire 17 that electrically connects the electrode pad 23 and the electrode pad 24 is formed starting from the electrode pad 23. Thereby, the height H of the bonding wire 17 shown in FIG. 2 can be made substantially zero. For this reason, since the spacer 14 for ensuring this height becomes unnecessary, the manufacturing process can be omitted and the PoP can be reduced by the height of the spacer 14.

[Second Embodiment]
Next, FIG. 8 shows a configuration example of a surface-mount type semiconductor device according to the second embodiment of the present invention. In the present embodiment as well, as in the first embodiment, a semiconductor device having a BGA structure will be described as an example. A semiconductor device 30 shown in FIG. 8 has a semiconductor memory chip 13 formed on the base substrate 11 in the semiconductor device 10 described with reference to FIG.

  As shown in the drawing, semiconductor memory chips 13 a, 13 b, and 13 c are sequentially stacked on the base substrate 11. The semiconductor memory chips 13a, 13b, and 13c are bonded to each other with an adhesive material (not shown). When the semiconductor memory chips 13a, 13b, and 13c are not distinguished, they are simply referred to as the semiconductor memory chip 13.

  Electrode pads 24a for exchanging data of the semiconductor memory chip 13a with the outside are formed on the surface edge of the semiconductor memory chip 13a. Electrode pads 24b for exchanging data of the semiconductor memory chip 13b with the outside are formed on the surface edge of the semiconductor memory chip 13b. An electrode pad 24c for exchanging data of the semiconductor memory chip 13c with the outside is formed on the surface edge of the semiconductor memory chip 13c. That is, the electrode pads 24a, 24b, 24c and the electrode pad 23 are electrically connected by the bonding wire 17a, the bonding wire 17b, and the bonding wire 17c, respectively. Since the other configuration is the same as that of FIG.

  Similarly to the modification of the first embodiment, even in the semiconductor device 30 shown in FIG. 8, the spacer 14 is omitted by punching the bonding wire 17a, the bonding wire 17b, and the bonding wire 17c from the electrode pad 23. can do.

  Further, the manufacturing method for forming the PoP using the semiconductor device 30 shown in FIG. 7 is the same except for the step of laminating the semiconductor memory chip 13a, the semiconductor memory chip 13b, and the semiconductor memory chip 13c through an adhesive material (not shown). Therefore, the description is omitted.

<Effects according to this embodiment>
In addition to the effects (1) and (2), the semiconductor device and the manufacturing method thereof according to the present embodiment can provide the following effects.

        (3) The semiconductor device can be thin and have a large capacity.

  In the semiconductor device according to the present embodiment, a plurality of semiconductor memory chips 13 are stacked on the base substrate 11 to obtain a large-capacity semiconductor device. That is, a sufficient memory capacity can be obtained by stacking a plurality of semiconductor memory chips 13 for each semiconductor device 10. Furthermore, it is possible to further increase the capacity of the memory by adopting the PoP structure described in the first embodiment for these semiconductor devices 10.

[Third embodiment]
Next, FIG. 9 and FIG. 10 show a configuration example of the surface mount type semiconductor device according to the third embodiment of the present invention. FIG. 9 is a plan view of the semiconductor device according to the present embodiment, and FIG. 10 is a cross-sectional view in the X2-X2 direction in FIG. In the present embodiment, a case where a lead frame structure is adopted for a lower-layer semiconductor device having a PoP structure will be described as an example. Any of the BGA type semiconductor devices 10-1, 10-2, and 30 described in the first and second embodiments is stacked on a semiconductor device having a lead frame structure.

  As shown in the drawing, the semiconductor device 40 is obtained by replacing the base substrate 11 and the external connection terminals 12 with lead frames 41 in FIG. Other than that, the semiconductor device 10 is the same as the semiconductor device 10 and the description thereof is omitted.

  Of the lead frames 41, a frame covered with the mold resin 19 is called an inner lead 42, and a frame formed outside the semiconductor device 40 is called an outer lead 43. The lead frame 41 exchanges data between the semiconductor memory chip and the outside. In the semiconductor device 40 according to this embodiment, the spacer 14 may be omitted. In addition, a plurality of semiconductor memory chips may be mounted on the lead frame 41 as described in the second embodiment. That is, the semiconductor memory chip formed on the lead frame may be, for example, three layers.

  Next, FIG. 11 shows a state where the PoP structure is formed by the semiconductor device having the BGA structure described in the first and second embodiments and the semiconductor device having the lead frame structure according to the present embodiment.

  As shown in the drawing, the mold resin 19 is cut so that the upper surface of the internal connection terminal 16 of the lead frame structure shown in FIGS. 9 and 10 is exposed. In the PoP structure according to this embodiment, the internal connection terminal 15 and the external connection terminal 12 of the semiconductor device 10, for example, are electrically connected. That is, the mold resin 19 of the semiconductor device 40 is scraped, and the semiconductor device 10 described above is laminated on the semiconductor device 40 to form a PoP structure. Thereby, the data of the semiconductor memory chip 13 in the semiconductor device 10 includes the electrode pad 24, the bonding wire 17, the electrode pad 23, the through hole (not shown), the external connection terminal 12, the internal connection terminal 16 of the semiconductor device 40, and the bonding. Data is exchanged with the outside through the wire 17, the inner lead 42, and the outer lead 43. As shown in FIG. 2, the semiconductor device 10 can be further stacked on the semiconductor device 10 formed on the semiconductor device 40. That is, the semiconductor device 10-1 is used as a lower layer, and the semiconductor device 10-2 is formed as an upper layer. Further, the semiconductor memory chip 13 mounted on the semiconductor devices 10-1 and 10-2 may be, for example, three layers.

<Effects according to this embodiment>
Even in the semiconductor device and the manufacturing method thereof according to the present embodiment, the following effect (4) can be obtained in addition to the effects (1) to (3).

        (4) A configuration with a high degree of freedom can be achieved in the PoP structure.

  That is, in the semiconductor device according to the present embodiment, even if the semiconductor device 40 is obtained by packaging the semiconductor memory chip 13 using the lead frame 41, the semiconductor device adopting another structure such as a BGA structure and the PoP structure. Can be configured.

  Usually, a semiconductor device is applied to the shape of various devices to be mounted as necessary. Therefore, an external connection terminal of the semiconductor device is a solder ball or a lead frame as in this embodiment. In such a situation, the semiconductor device according to the present embodiment can overcome the problems that have conventionally occurred. That is, for example, when there is a device corresponding to the lead frame structure, the semiconductor device 40 is first electrically connected to the device. Here, the PoP structure can be easily formed by stacking the above-described BGA type semiconductor device on the semiconductor device 40. This is because each of the semiconductor devices 10, 20, and 30 has an internal connection terminal. By providing this internal connection terminal, a PoP structure can be formed in multiple layers.

  Note that the above-described embodiment is not the only embodiment for carrying out. That is, the semiconductor memory chip 13 according to the above embodiment is not limited to the NAND flash memory, and may be a semiconductor memory such as a DRAM.

  The signal lines that connect the electrode pads on the surface of the semiconductor memory chip and the electrode pads on the base substrate 11 or the inner leads on the lead frame 41 are not limited to bonding wires.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be extracted as an invention.

  DESCRIPTION OF SYMBOLS 10, 10-1, 10-2, 20, 30, 40 ... Semiconductor device, 11 ... Base substrate, 12 ... External connection terminal, 23, 24, 25 ... Electrode pad, 13 ... Semiconductor memory chip, 21 ... Film, DESCRIPTION OF SYMBOLS 14 ... Spacer, 15 ... Board for internal connection, 16 ... Terminal for internal connection, 17, 18 ... Bonding wire, 19 ... Mold resin

Claims (5)

A package substrate;
A semiconductor memory mounted on one surface of the package substrate;
Disposed on the other side of the package substrate, and external terminals of the semiconductor memory;
An internal wiring board formed on the semiconductor memory via a spacer made of an insulator and having a plurality of electrode pads on the surface;
An internal terminal disposed on each of the electrode pads and electrically connected to the external terminal;
An insulating resin covering from the surface of the package substrate to the internal terminals;
Only the insulating resin is formed on the upper surface of the internal terminal. A plurality of the semiconductor memories are formed on the package substrate, and the plurality of electrode pads and the external terminals formed on the respective surfaces of the semiconductor memories are electrically connected. Item 14. A semiconductor device according to Item 1. A first insulating resin is formed on the one surface of the first package substrate surface on which the first semiconductor memory is mounted on one surface and the first external terminals of the first semiconductor memory are disposed on the other surface By doing so, the first semiconductor memory is formed through a spacer made of an insulator and has a plurality of first electrode pads, and the first electrode pads are electrically formed on the first electrode pads. Manufacturing a first semiconductor device by coating a first internal wiring board having a first internal terminal connected to an external terminal with the first insulating resin;
Cutting the first insulating resin until an upper surface of the first internal terminal is exposed. A method for manufacturing a semiconductor device, comprising: A second insulating resin is formed on the one surface of the second package substrate surface on which the second semiconductor memory is mounted on one surface and the second external terminals of the second semiconductor memory are disposed on the other surface. Accordingly, the second semiconductor memory has a plurality of second electrode pads formed on the second semiconductor memory through spacers made of an insulator, and the second external pads are electrically formed on the second electrode pads. Manufacturing a second semiconductor device by coating a second internal wiring board having a second internal terminal connected to the terminal with the second insulating resin;
4. The method further comprising: electrically connecting the second internal terminal and the first external terminal by laminating the second semiconductor device on the first semiconductor device. The manufacturing method of the semiconductor device of description. A plurality of the first semiconductor memories are formed on the first package substrate, and the plurality of first electrode pads and the first external terminals formed on the respective surfaces of the first semiconductor memory are electrically connected The method for manufacturing a semiconductor device according to claim 3, wherein:

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