JP2005353704A - Multilayered semiconductor device and its manufacturing method - Google Patents

Multilayered semiconductor device and its manufacturing method Download PDF

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JP2005353704A
JP2005353704A JP2004170597A JP2004170597A JP2005353704A JP 2005353704 A JP2005353704 A JP 2005353704A JP 2004170597 A JP2004170597 A JP 2004170597A JP 2004170597 A JP2004170597 A JP 2004170597A JP 2005353704 A JP2005353704 A JP 2005353704A
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semiconductor element
electrodes
electrode
wiring board
semiconductor device
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Fumito Ito
史人 伊藤
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayered semiconductor device which employs a combination of flip chip bonding and a face up method and has a stable wire bondability and a small size while having an overhang structure. <P>SOLUTION: The multilayered semiconductor device comprises a first semiconductor element 2 which is mounted on a wiring board 1 by flip chip bonding with the functional surface facing the wiring board 1; second semiconductor element 4 which is mounted back-to-back with the first semiconductor element 2, with the sides formed with electrodes thereon overhanging the first semiconductor element 2; metal fine wires 6 for electrically connecting second electrodes 1b on the wiring board 1 and the electrodes on the second semiconductor element 4; sealing resin 7 so formed as to protect the structure; and metal bumps 8 for external connection. The arrangement of the electrodes formed on the overhanging sides of the second semiconductor element 4 is such that a plurality of first electrodes 1a near the ends of each side are arranged on the inside of the second electrodes 1b arranged at the center of the overhanging sides. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は複数の半導体素子を積層した形の半導体装置とその製造方法に関し、特に、上に搭載された半導体素子が下に搭載された半導体素子よりも横方向に突出する姿勢で上に搭載された積層型半導体装置とその製造方法に関する。   The present invention relates to a semiconductor device in which a plurality of semiconductor elements are stacked and a method of manufacturing the same, and more particularly, the semiconductor element mounted on the semiconductor device is mounted on the semiconductor device mounted on the semiconductor device mounted on the semiconductor device mounted on the lower side. The present invention relates to a stacked semiconductor device and a method for manufacturing the same.

近年、半導体集積回路装置の高集積化、高機能化に伴って、複数の半導体素子を一つの半導体装置内に搭載した積層型半導体装置が提供されている。
この積層型半導体装置の１つの種類として、下に搭載される半導体素子をフリップチップボンディングによりその半導体素子形成部や電極が設けられた面（機能面と称す）を下側にして配線基板上に搭載するとともに、この半導体素子の背面（天面）上に、上の半導体素子をその電極（機能面）が上に向くように搭載し、上の半導体素子の電極と、回路基板上の接続用電極とをワイヤボンディングにより接続した構造のものがある。この種の積層型半導体装置では、上に搭載される半導体素子のサイズが下に位置する半導体素子のサイズよりも大きく、突出した構成を採用することにより、各半導体素子の電極を支障無く回路基板上の各接続用電極と接続でき、しかもワイヤボンディングの金属細線の長さを短くできるので、搭載する半導体素子のサイズ制限を緩和できて、積層型半導体装置として汎用性を広げることができる。 2. Description of the Related Art In recent years, with the increase in integration and functionality of semiconductor integrated circuit devices, stacked semiconductor devices in which a plurality of semiconductor elements are mounted in one semiconductor device have been provided.
As one type of this stacked semiconductor device, a semiconductor element mounted underneath is placed on a wiring board with a surface (referred to as a functional surface) on which a semiconductor element forming portion and electrodes are provided by flip-chip bonding. In addition to mounting, the upper semiconductor element is mounted on the back surface (top surface) of this semiconductor element so that the electrode (functional surface) faces upward, and the upper semiconductor element electrode is connected to the circuit board. There is a structure in which electrodes are connected by wire bonding. In this type of stacked semiconductor device, the size of the semiconductor element mounted thereon is larger than the size of the semiconductor element located below, and by adopting a protruding configuration, the circuit board can be used without any problem with the electrodes of each semiconductor element. Since it can be connected to each of the above connecting electrodes and the length of the metal wire for wire bonding can be shortened, the size limitation of the semiconductor element to be mounted can be relaxed, and the versatility of the stacked semiconductor device can be expanded.

しかしながら、サイズの小さな下の半導体素子の上に、サイズの大きな上の半導体素子を単に載せただけの構造では、上に搭載された半導体素子における横方向に突出した部分に設けられた電極にワイヤボンドを行う際、片持ち姿勢となった端部を押圧するような状態となって、しっかりと固定されていない状態となりやすいために、接合不良を起こしやすく、歩留りが低下するという短所を有している。   However, in the structure in which the upper semiconductor element having a larger size is simply placed on the lower semiconductor element, the wire provided on the electrode provided in the laterally protruding portion of the semiconductor element mounted thereon When bonding, it becomes a state that presses the end portion in a cantilevered posture, and it tends to be in a state where it is not firmly fixed, so it has a disadvantage that it tends to cause poor bonding and the yield decreases. ing.

そこで、このような不具合を改善するものとして、上に搭載された半導体素子の突出した部分の下にも樹脂等を充填して保持することにより、安定したワイヤボンドを可能にする構造および工法が特許文献１において提案されている。   Therefore, as a means for improving such a problem, there is a structure and a method for enabling stable wire bonding by filling and holding a resin or the like under the protruding portion of the semiconductor element mounted thereon. This is proposed in Patent Document 1.

以下、図５（ａ），（ｂ）を参照しながら、前記特許文献１に示されている積層型半導体装置について説明する。
図５（ａ），（ｂ）に示すように、上面に第１の電極１ａと第２の電極１ａとがそれぞれ複数設けられた配線基板１上に、この配線基板１に対して機能面が対向する形で第１の半導体素子２がフリップチップ搭載され、第１の半導体素子２の電極部に接続されたバンプ３が前記配線基板１の第１の電極１ａと電気的に接続されており、さらに前記第１の半導体素子２と背中合わせになる形で第１の半導体素子２よりも大きいサイズの第２の半導体素子４が第１の半導体素子２上に搭載されている。前記第１の半導体素子２のフリップチップ実装にあたっては、配線基板１との間に絶縁性シート９を使用しており、この絶縁性シート９を、第１の半導体素子２の背面と同じ高さでかつ上に搭載される第２の半導体素子４の突出した部分に対応してはみ出させた形で形成させている。そして、配線基板１上の第２の電極１ｂと前記第２の半導体素子４上の電極４ｆと間の電気的接続を行う金属細線６を有し、第１の半導体素子２と第２の半導体素子４と金属配線６とを覆う形で配線基板１上に封止樹脂７を形成させている。配線基板１の下面には外部接続用の金属バンプ８が設けられている。 The stacked semiconductor device disclosed in Patent Document 1 will be described below with reference to FIGS. 5 (a) and 5 (b).
As shown in FIGS. 5A and 5B, the functional surface of the wiring board 1 is provided on the wiring board 1 provided with a plurality of first electrodes 1a and second electrodes 1a on the upper surface. The first semiconductor element 2 is flip-chip mounted in an opposing manner, and the bump 3 connected to the electrode portion of the first semiconductor element 2 is electrically connected to the first electrode 1a of the wiring board 1. Furthermore, a second semiconductor element 4 having a size larger than that of the first semiconductor element 2 is mounted on the first semiconductor element 2 so as to be back-to-back with the first semiconductor element 2. In flip chip mounting of the first semiconductor element 2, an insulating sheet 9 is used between the first semiconductor element 2 and the wiring board 1, and the insulating sheet 9 has the same height as the back surface of the first semiconductor element 2. In addition, the second semiconductor element 4 mounted thereon is formed so as to protrude from the protruding portion. And it has the metal fine wire 6 which performs the electrical connection between the 2nd electrode 1b on the wiring board 1, and the electrode 4f on the said 2nd semiconductor element 4, and the 1st semiconductor element 2 and the 2nd semiconductor A sealing resin 7 is formed on the wiring substrate 1 so as to cover the element 4 and the metal wiring 6. On the lower surface of the wiring substrate 1, metal bumps 8 for external connection are provided.

本構成の積層型半導体装置によると、第１の半導体素子２より突出した形で搭載された第２の半導体素子４の突出した部分を絶縁性シート９が下方から支持する構造となっていることにより、安定したワイヤボンドを行うことができる。
特開２０００−２９９４３１号公報 According to the stacked semiconductor device of this configuration, the insulating sheet 9 supports the protruding portion of the second semiconductor element 4 mounted so as to protrude from the first semiconductor element 2 from below. Thus, stable wire bonding can be performed.
JP 2000-299431 A

しかしながら、積層型半導体装置の小型化を進めていく中で前述の特開２０００−２９９４３１号公報に示されている構造を採用すると、第１の半導体素子２をフリップチップ実装する際に用いる絶縁性シート９の領域を、この領域の上に突出した形で搭載される第２の半導体素子４に合わせて大きくとる必要があるため、ワイヤボンドに用いる配線基板１上における第２の電極１ｂを配線基板１の中心からかなり離れた位置に配置せざるを得ず、すなわち、配線基板１の中心に近づけることが困難であり、その結果、積層型半導体装置の小型化に制限がかかるという問題を生じていた。   However, if the structure shown in the aforementioned Japanese Patent Application Laid-Open No. 2000-299431 is adopted in the progress of miniaturization of the stacked semiconductor device, the insulating property used when the first semiconductor element 2 is flip-chip mounted. Since it is necessary to make the area of the sheet 9 large in accordance with the second semiconductor element 4 mounted so as to protrude above this area, the second electrode 1b on the wiring substrate 1 used for wire bonding is wired. It must be arranged at a position far from the center of the substrate 1, that is, it is difficult to approach the center of the wiring substrate 1, and as a result, there is a problem that size reduction of the stacked semiconductor device is restricted. It was.

本発明は前記問題に鑑み、第１の半導体素子から突出した形で搭載された第２の半導体素子に対しても安定してワイヤボンドを行うことができながら、積層型半導体装置の小型化も可能となる積層型半導体装置及びその製造方法を提供することを目的とする。   In view of the above problems, the present invention can stably wire bond the second semiconductor element mounted so as to protrude from the first semiconductor element, while reducing the size of the stacked semiconductor device. An object of the present invention is to provide a stacked semiconductor device and a method for manufacturing the same.

前記の目的を達成するために、本発明は請求項１に記載の積層型半導体装置を請求項４に記載の製造方法により製造する。すなわち、第１の半導体素子と背中合わせで、突出した辺を有する第２の半導体素子の、前記第１の半導体素子よりも突出した辺に形成された電極の配列として、前記突出した辺の端部に近い複数の電極は、前記突出した辺の中心寄り部分に配列された電極よりも内側に配列されており、前記突出した辺の端部近くにおいて内側に配列された電極から優先して金属細線による結線を行った後に、中心寄り部分の電極に金属細線による結線を行うことにより積層型半導体装置を形成する。   In order to achieve the above object, the present invention manufactures the stacked semiconductor device according to claim 1 by the manufacturing method according to claim 4. That is, as an array of electrodes formed on the side protruding from the first semiconductor element of the second semiconductor element having the protruding side back to back with the first semiconductor element, an end portion of the protruding side The plurality of electrodes close to is arranged on the inner side of the electrode arranged near the center of the protruding side, and the fine metal wire is preferentially given to the electrode arranged on the inner side near the end of the protruding side. After performing the connection by the above, a stacked semiconductor device is formed by performing the connection by the fine metal wire to the electrode near the center.

また、請求項２に記載の積層型半導体装置を請求項４に記載の製造方法により製造する。すなわち、第２の半導体素子上の電極を千鳥配列にて配置させており、前記第２の半導体素子における第１の半導体素子よりも突出した辺の端部に近い複数の電極は、前記突出した辺の中心寄り部分に配置された千鳥配列の内側の電極と同一ライン上もしくはより内側で部分的にペリフェラルな配置（周辺配置）となっており、前記突出した辺の端部近くにおいて内側に配列された電極から優先して金属細線による結線を行った後に、中心寄り部分の電極に金属細線による結線を行うことにより積層型半導体装置を形成する。   The stacked semiconductor device according to claim 2 is manufactured by the manufacturing method according to claim 4. That is, the electrodes on the second semiconductor element are arranged in a staggered arrangement, and a plurality of electrodes closer to the end of the side projecting than the first semiconductor element in the second semiconductor element are projected. Peripheral arrangement (peripheral arrangement) on the same line as the inner electrode of the staggered arrangement arranged near the center of the side, or on the inner side (peripheral arrangement), arranged inside near the end of the protruding side After performing the connection with the fine metal wire in preference to the formed electrode, the connection with the fine metal wire is performed on the electrode near the center, thereby forming the stacked semiconductor device.

本発明の積層型半導体装置とその製造方法によると、第２の半導体素子の突出した部分に配置された端部近くの電極は、第１の半導体素子からのオーバハング量（突出量）がその辺の中心より部分の電極に対して大きくなることを防ぐため、中心寄り部分の電極に比べて内側に配置されている。これにより、金属配線による結線を行う際の安定性を向上することが可能であると共に、前述の端部近くの電極から金属細線による結線を先に行うことにより、突出した辺の中心寄りの電極に金属細線による結線を行う際には、端部近くの電極になされた金属細線の張力が結線中の半導体素子の挙動を抑制する方向に働き、この結果、安定した金属細線による結線を行うことができる。また、突出した辺を支持する部材が必要でないので、配線基板上に配置する金属細線結線用の電極配置の自由度を上げることができ、積層型半導体装置の小型化を行うことができる。   According to the stacked semiconductor device and the method of manufacturing the same of the present invention, the electrode near the end disposed on the protruding portion of the second semiconductor element has an overhang amount (protruding amount) from the first semiconductor element on its side. In order to prevent the electrode from becoming larger than the center electrode, it is arranged on the inner side compared to the center electrode. As a result, it is possible to improve the stability when performing the connection by the metal wiring, and by performing the connection by the metal fine wire first from the electrode near the aforementioned end, the electrode closer to the center of the protruding side When connecting wires with fine metal wires, the tension of the fine metal wires applied to the electrodes near the edges works in a direction that suppresses the behavior of the semiconductor element during the wire connection. Can do. In addition, since a member that supports the protruding side is not required, the degree of freedom in arranging the electrodes for connecting the fine metal wires arranged on the wiring board can be increased, and the stacked semiconductor device can be miniaturized.

また、請求項３に記載の積層型半導体装置を請求項４に記載の製造方法により製造する。すなわち、第２の半導体素子における第１の半導体素子より突出した辺の端部に、複数のダミー電極を配置しており、前記突出した辺の端部に配列されたダミー電極から優先して金属細線による結線を行った後に、中心寄り部分の電極に金属細線による結線を行うことにより積層型半導体装置を形成する。   A stacked semiconductor device according to claim 3 is manufactured by the manufacturing method according to claim 4. That is, a plurality of dummy electrodes are arranged at the end of the second semiconductor element protruding from the first semiconductor element, and the metal is preferentially disposed over the dummy electrode arranged at the end of the protruding side. After the connection with the fine wire, the stacked semiconductor device is formed by performing the connection with the fine metal wire on the electrode near the center.

この積層型半導体装置とその製造方法によると、端部近くのダミー電極から金属細線による結線を先に行うことにより、第２の半導体素子におけるダミー電極でない電極に金属細線による結線を行う際には、端部近くのダミー電極になされた金属細線の張力が結線中の半導体素子の挙動を抑制する方向に働き、この結果、安定した金属細線による結線を行うことができる。また、突出した辺を支持する部材が必要でないので、配線基板上に配置する金属細線結線用の電極配置の自由度を上げることができ、積層型半導体装置の小型化を行うことができる。   According to the stacked semiconductor device and the manufacturing method thereof, when the connection with the metal thin wire is performed first from the dummy electrode near the end, the connection with the metal thin wire to the electrode that is not the dummy electrode in the second semiconductor element is performed. The tension of the fine metal wire formed on the dummy electrode near the end acts in a direction to suppress the behavior of the semiconductor element during the wire connection, and as a result, stable wire connection can be performed. In addition, since a member that supports the protruding side is not required, the degree of freedom in arranging the electrodes for connecting the fine metal wires arranged on the wiring board can be increased, and the stacked semiconductor device can be miniaturized.

本発明に係る積層型半導体装置及びその製造方法によると、配線基板側に配置された第１の半導体素子よりも突出した辺を有する形で積層された第２の半導体素子に対して、その突出部分を支持する部材を有することなく安定したワイヤボンドを行うことが可能であると共に、支持部材を設けなくても済むことより配線基板上の電極配置の自由度を上げることができ、この結果、積層型半導体装置の外形サイズを小さくすることが可能である。   According to the stacked semiconductor device and the method for manufacturing the same according to the present invention, the protrusion of the second semiconductor element stacked in a form having a side protruding from the first semiconductor element disposed on the wiring board side. It is possible to perform stable wire bonding without having a member that supports the portion, and it is possible to increase the degree of freedom of electrode arrangement on the wiring board by eliminating the need to provide a supporting member. It is possible to reduce the outer size of the stacked semiconductor device.

（第１の実施形態）
以下、本発明の第１の実施形態に係る積層形半導体装置について、図面を参照しながら説明する。 (First embodiment)
Hereinafter, a stacked semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings.

図１（ａ）に示すように、この積層形半導体装置においては、上面に第１の電極１ａと第２の電極１ａとがそれぞれ複数設けられた配線基板１上に、この配線基板１に対して機能面（半導体素子形成部や電極が設けられた面）が対向する形で第１の半導体素子２がフリップチップ搭載され、第１の半導体素子２の電極部に接続されたバンプ３が前記配線基板１の第１の電極１ａと電気的に接続されており、さらに前記第１の半導体素子２と背中合わせになる形で、第１の半導体素子２よりも大きいサイズ（この実施の形態では四辺とも第１の半導体素子２よりも突出している）の第２の半導体素子４が第１の半導体素子２上に搭載されている。そして、配線基板１上の第２の電極１ｂと第２の半導体素子４上の電極４ａ，４ｂとが金属細線６により電気的に接続され、第１の半導体素子２と第２の半導体素子４と金属配線６とを覆う形で配線基板１上に封止樹脂７が形成されている。また、配線基板１の下面には外部接続用の金属バンプ８が設けられている。なお、配線基板１上においては、第１の半導体素子２が接続される第１の電極１ａが、第１の半導体素子２の下方、すなわち、中央部寄り（内側寄り）位置に配置され、第２の半導体素子４が接続される第２の電極２ａが、第１の半導体素子２における辺に近い、外側寄り位置に配置されている。   As shown in FIG. 1A, in this stacked semiconductor device, a wiring substrate 1 having a plurality of first electrodes 1a and a plurality of second electrodes 1a on its upper surface is provided on the wiring substrate 1. The first semiconductor element 2 is flip-chip mounted so that the functional surfaces (surfaces on which the semiconductor element formation portion and the electrodes are provided) face each other, and the bumps 3 connected to the electrode portions of the first semiconductor element 2 are It is electrically connected to the first electrode 1a of the wiring board 1 and is back-to-back with the first semiconductor element 2, and is larger than the first semiconductor element 2 (in this embodiment, four sides). The second semiconductor element 4, which protrudes from the first semiconductor element 2, is mounted on the first semiconductor element 2. Then, the second electrode 1b on the wiring substrate 1 and the electrodes 4a and 4b on the second semiconductor element 4 are electrically connected by the thin metal wire 6, and the first semiconductor element 2 and the second semiconductor element 4 are connected. A sealing resin 7 is formed on the wiring board 1 so as to cover the metal wiring 6. Further, metal bumps 8 for external connection are provided on the lower surface of the wiring board 1. On the wiring board 1, the first electrode 1 a to which the first semiconductor element 2 is connected is disposed below the first semiconductor element 2, that is, at a position closer to the center (inner side) than the first semiconductor element 2. The second electrode 2 a to which the second semiconductor element 4 is connected is disposed at a position closer to the outside, close to the side of the first semiconductor element 2.

ここで特にこの積層形半導体装置においては、この積層型半導体装置の封止樹脂７を形成する前の状態を平面視した図１（ｂ）に示すように、第２の半導体素子４における第１の半導体素子２よりも突出した辺に形成された電極４ａ，４ｂは、その配列が異なるように設けられ、突出した辺の端部（第２の半導体素子４の角部）に近い位置に設けられた複数の第１の電極４ａは、突出した辺の中央寄り位置に設けられた複数の第２の電極４ｂよりも、内側の位置（辺をなす面から内側に寄った位置）に配列されている。   Here, particularly in this stacked semiconductor device, as shown in FIG. 1B in plan view, the first semiconductor element 4 in the first semiconductor element 4 is shown in a state before the sealing resin 7 of the stacked semiconductor device is formed. The electrodes 4a and 4b formed on the side protruding from the semiconductor element 2 are provided so that the arrangement thereof is different, and provided at a position close to the end of the protruding side (corner of the second semiconductor element 4). The plurality of first electrodes 4a thus arranged are arranged at an inner position (position closer to the inner side from the surface forming the side) than the plurality of second electrodes 4b provided near the center of the protruding side. ing.

また、図１（ｂ）に示すように、第２の半導体素子４の電極４ａ，４ｂが金属配線６を介して接続される配線基板１の第２の電極１ｂは、平面視して、第２の半導体素子４の電極４ａ，４ｂに近い位置に配設され、これに応じて、配線基板１も平面視して従来のものよりも小さいサイズのものが用いられている。   Further, as shown in FIG. 1B, the second electrode 1b of the wiring board 1 to which the electrodes 4a and 4b of the second semiconductor element 4 are connected via the metal wiring 6 is shown in plan view. 2 is disposed at a position close to the electrodes 4a and 4b of the semiconductor element 4, and accordingly, the wiring board 1 is also smaller in size than the conventional one in plan view.

次に、本発明の第１の実施形態に係る積層形半導体装置の製造方法について図２を参照しながら説明する。
図２（ａ）に示すように、配線基板１上において、内側寄りに配置されている第１の電極４ａが設けられている領域については覆うが、外側寄りに配置されている第２の電極４ｂが設けられている領域については覆わないように、配線基板１上に絶縁性シート９を貼付ける。 Next, a manufacturing method of the stacked semiconductor device according to the first embodiment of the present invention will be described with reference to FIG.
As shown in FIG. 2 (a), on the wiring substrate 1, the region where the first electrode 4a arranged on the inner side is provided is covered, but the second electrode arranged on the outer side is covered. The insulating sheet 9 is affixed on the wiring board 1 so as not to cover the region where 4b is provided.

次に、図２（ｂ）に示すように、バンプ３が形成された第１の半導体素子２を配線基板上の第１の電極１ａと対向する形で熱圧着する。これにより、絶縁性シート９をバンプ３が突き破り、配線基板１の第１の電極１ａと第１の半導体素子２との導通がとられる。   Next, as shown in FIG. 2B, the first semiconductor element 2 on which the bumps 3 are formed is thermocompression bonded so as to face the first electrode 1a on the wiring board. As a result, the bumps 3 break through the insulating sheet 9, and the first electrode 1a of the wiring board 1 and the first semiconductor element 2 are electrically connected.

ここで用いるフリップチップの方法としては、バンプ３上に導電性ペーストを転写して配線基板１の第１の電極１ａと接続した後、アンダーフィルを充填する方法や、導電性粒子を有するシートを用いて配線基板１の第１の電極１ａとの間の導通をとる方法や、絶縁性ペーストを用いて配線基板１の第１の電極１ａとの導通をとる方法や、金にてなされたバンプ３と金めっき処理が施された配線基板１の第１の電極１ａとを超音波を用いて接合した後にアンダーフィルを充填する方法などが使用可能である。   As a flip-chip method used here, there is a method in which a conductive paste is transferred onto the bump 3 and connected to the first electrode 1a of the wiring substrate 1, and then an underfill is filled, or a sheet having conductive particles is used. A method of using the first paste 1a of the wiring board 1 to make conduction with the first electrode 1a of the wiring board 1 using an insulating paste, or a bump made of gold 3 and the first electrode 1a of the wiring board 1 that has been subjected to the gold plating process can be used after being joined using ultrasonic waves, and a method of filling an underfill can be used.

次に、図２（ｃ）に示すように、第２の半導体素子４を、第１の半導体素子２と背中合わせになる形で接着層５を用いて搭載させる。ここで用いる接着層５は、ペースト状のものやフィルム状のものを使用可能である。   Next, as shown in FIG. 2C, the second semiconductor element 4 is mounted using the adhesive layer 5 so as to be back-to-back with the first semiconductor element 2. The adhesive layer 5 used here can be a paste or film.

次に、図２（ｄ）に示すように、第２の半導体素子４の突出した辺の端部近くに配置された第１の電極４ａと配線基板１の第２の電極１ｂとを金属細線６を用いて結線させる。
次に、図２（ｅ）に示すように、第２の半導体素子４における辺の中央寄り部分に配置された第２の電極４ｂと配線基板１の第２の電極１ｂとを金属配線６を用いて結線させる。 Next, as shown in FIG. 2D, the first electrode 4a disposed near the end of the protruding side of the second semiconductor element 4 and the second electrode 1b of the wiring substrate 1 are connected to a fine metal wire. Use 6 to connect.
Next, as shown in FIG. 2E, the metal wiring 6 is connected to the second electrode 4b disposed near the center of the side of the second semiconductor element 4 and the second electrode 1b of the wiring board 1. Use to connect.

これらの金属細線６による結線の方法としては、金線を用いた超音波併用熱圧着ボンディングなどを用いる。
次に、図２（ｆ）に示すように、配線基板１と第１の半導体素子２と第２の半導体素子４と金属細線６とを覆って保護する形で封止樹脂７を用いて樹脂成形する。ここで用いる方法としては、エポキシ樹脂を用いたトランスファ成形や、印刷封止成形などが使用可能である。 As a method of connection with these fine metal wires 6, ultrasonic combined thermocompression bonding using a gold wire is used.
Next, as shown in FIG. 2 (f), a resin is formed using a sealing resin 7 so as to cover and protect the wiring substrate 1, the first semiconductor element 2, the second semiconductor element 4, and the fine metal wires 6. Mold. As a method used here, transfer molding using an epoxy resin, printing sealing molding, or the like can be used.

次に、図２（ｇ）に示すように、外部接続用の金属バンプ８を搭載することにより積層型半導体装置が形成される。
この積層型半導体装置およびその製造方法によると、第２の半導体素子４の突出した部分に配置された端部近くの第１の電極４ａは、この辺の中央寄りに配置された第２の電極４ｂよりも内側に配置されており、第１の半導体素子２からのオーバハング量が小さくなっているので、前記第１の電極４ａが第２の電極４ｂと同じラインに配設されている場合に比べて、金属配線６による結線を行う際に偏った荷重が第２の半導体素子４に作用し難くなって安定性を向上させることができる。 Next, as shown in FIG. 2G, a stacked semiconductor device is formed by mounting metal bumps 8 for external connection.
According to the stacked semiconductor device and the method of manufacturing the same, the first electrode 4a near the end disposed in the protruding portion of the second semiconductor element 4 is the second electrode 4b disposed near the center of this side. Since the amount of overhang from the first semiconductor element 2 is small, the first electrode 4a is disposed in the same line as the second electrode 4b. Thus, a load that is biased when performing the connection by the metal wiring 6 is less likely to act on the second semiconductor element 4 and the stability can be improved.

また、前述した端部近くの第１の電極４ａを接続した後に、辺の中央寄りに配置された第２の電極４ｂを接続するので、この第２の電極４ｂの金属細線６による結線を行う際には、第１の電極４ａに結線された金属細線６の張力が、第２の電極４ｂの結線中において第２の半導体素子４の突出した部分の挙動を抑制する方向に働き、この結果、安定した金属細線６による結線を行うことができる。   In addition, since the second electrode 4b disposed near the center of the side is connected after connecting the first electrode 4a near the end, the second electrode 4b is connected by the thin metal wire 6. In this case, the tension of the fine metal wire 6 connected to the first electrode 4a acts in a direction to suppress the behavior of the protruding portion of the second semiconductor element 4 during the connection of the second electrode 4b. Thus, it is possible to perform stable connection with the fine metal wires 6.

また、第２の半導体素子４の突出した部分を支持する封止樹脂７などの部材を必要としていないため、配線基板１上の第２の電極１ｂの配置を、配線基板１の中心に近づけて設置することができ、これに応じて、配線基板１も平面視して従来のものよりも小さいサイズのものを用いることができて、積層型半導体装置の小型化を図ることができる。   Further, since a member such as the sealing resin 7 that supports the protruding portion of the second semiconductor element 4 is not required, the arrangement of the second electrode 1b on the wiring board 1 is brought close to the center of the wiring board 1. In accordance with this, the wiring board 1 can also be used in a smaller size than the conventional one in plan view, and the stacked semiconductor device can be miniaturized.

（第２の実施形態）
以下、本発明の第２の実施形態に係る積層型半導体装置について、図面を参照しながら説明する。 (Second Embodiment)
Hereinafter, a stacked semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings.

図３に示すように、この積層型半導体装置においては、第２の半導体素子４上の電極４ａ，４ｂ，４ｃが千鳥配列にて配置されており、第２の半導体素子４の第１の半導体素子２よりも突出した辺の端部に近い複数の第１の電極４ａは、前記突出した辺の中心部分に配置された千鳥配列の内側の第２の電極４ｂと同一ライン上で部分的にペリフェラルな配置（周辺配置）となっている。なお、図３における４ｃは、前記突出した辺の中心部分に配置された千鳥配列の外側の第３の電極である。   As shown in FIG. 3, in this stacked semiconductor device, the electrodes 4 a, 4 b, 4 c on the second semiconductor element 4 are arranged in a staggered arrangement, and the first semiconductor of the second semiconductor element 4 The plurality of first electrodes 4a closer to the end of the protruding side than the element 2 are partially on the same line as the second electrode 4b inside the staggered arrangement arranged at the center of the protruding side. Peripheral arrangement (peripheral arrangement). In addition, 4c in FIG. 3 is the 3rd electrode of the outer side of the staggered arrangement | sequence arrange | positioned in the center part of the said protrusion side.

この積層型半導体装置によると、第２の半導体素子４の突出した辺の端部近くの第１の電極４ａだけでなく、辺の中央寄りに配置された内側の第２の電極４ｂについても、この辺の中央寄りに配置された外側の第３の電極４ｃよりも内側に配置されており、第１の半導体素子２からのオーバハング量が小さくなっているので、第１の電極４ａおよび第２の電極４ｂが第３の電極４ｃと同じラインに配設されている場合に比べて、金属配線６による結線を行う際に偏った荷重が第２の半導体素子４にさらに作用し難くなって安定性を一層向上させることができる。   According to this stacked semiconductor device, not only the first electrode 4a near the end of the protruding side of the second semiconductor element 4, but also the inner second electrode 4b disposed near the center of the side, Since the overhanging amount from the first semiconductor element 2 is smaller than the outer third electrode 4c disposed near the center of the side, the first electrode 4a and the second electrode 4c are reduced. Compared with the case where the electrode 4b is disposed on the same line as the third electrode 4c, the load that is biased when the connection by the metal wiring 6 is performed is less likely to act on the second semiconductor element 4 and is stable. Can be further improved.

また、前述した端部近くの第１の電極４ａを接続した後に、辺の中央寄りに配置された第２の電極４ｂや第３の電極４ｃを接続することにより、これらの第２の電極４ｂや第３の電極４ｃの金属細線６による結線を行う際には、第１の電極４ａに結線された金属細線６の張力が、第２の電極４ｂや第３の電極４ｃの結線中において第２の半導体素子４の突出した部分の挙動を抑制する方向に働き、この結果、安定した金属細線６による結線を行うことができる。   In addition, after connecting the first electrode 4a near the end portion described above, the second electrode 4b and the third electrode 4c arranged near the center of the side are connected, whereby these second electrodes 4b are connected. When the wire of the third electrode 4c is connected with the fine metal wire 6, the tension of the fine metal wire 6 connected to the first electrode 4a is changed during the connection of the second electrode 4b and the third electrode 4c. This works in a direction that suppresses the behavior of the protruding portion of the semiconductor element 4 of the second semiconductor device. As a result, it is possible to perform a stable connection with the fine metal wire 6.

また、第２の半導体素子４の突出した部分を支持する封止樹脂７などの部材を必要としていないため、配線基板１上の第２の電極１ｂの配置を、配線基板１の中心に近づけて設置することができ、これに応じて、配線基板１も平面視して従来のものよりも小さいサイズのものを用いることができて、積層型半導体装置の小型化を図ることができる。   Further, since a member such as the sealing resin 7 that supports the protruding portion of the second semiconductor element 4 is not required, the arrangement of the second electrode 1b on the wiring board 1 is brought close to the center of the wiring board 1. In accordance with this, the wiring board 1 can also be used in a smaller size than the conventional one in plan view, and the stacked semiconductor device can be miniaturized.

（第３の実施形態）
以下、本発明の第３の実施形態に係る積層型半導体装置について、図面を参照しながら説明する。 (Third embodiment)
Hereinafter, a stacked semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings.

図４に示すように、この積層型半導体装置においては、第２の半導体素子４の第１の半導体素子２より突出した辺の端部に近い箇所に、第２の半導体素子４の回路と電気的接合がなされていない複数のダミー電極４ｄが配置された構成となっている。   As shown in FIG. 4, in this stacked semiconductor device, the circuit of the second semiconductor element 4 and the electric circuit are electrically connected to a portion of the second semiconductor element 4 near the end of the side protruding from the first semiconductor element 2. In this configuration, a plurality of dummy electrodes 4d that are not joined to each other are arranged.

この積層型半導体装置によると、第２の半導体素子４の突出した辺の端部近くのダミー電極４ｄは電気的接合がなされておらず、前述のダミー電極４ｄから金属細線６による結線を事前に行うことにより、突出した辺の中心寄りの第２の電極４ｂに金属細線６による結線を行う際には、ダミー電極４ｄになされた金属細線６の張力が結線中の第２の半導体素子４の突出した部分の挙動を抑制する方向に働き、この結果、安定した金属細線６による結線を行うことができる。   According to this stacked type semiconductor device, the dummy electrode 4d near the end of the protruding side of the second semiconductor element 4 is not electrically joined, and the above-described dummy electrode 4d is connected in advance by the metal thin wire 6 in advance. By doing so, when the second electrode 4b near the center of the protruding side is connected by the fine metal wire 6, the tension of the fine metal wire 6 formed on the dummy electrode 4d is applied to the second semiconductor element 4 being connected. This works in a direction to suppress the behavior of the protruding portion, and as a result, stable connection with the fine metal wire 6 can be performed.

また、第２の半導体素子４の突出した部分を支持する封止樹脂７などの部材を必要としていないため、配線基板１上の第２の電極１ｂの配置を、配線基板１の中心に近づけて設置することができ、これに応じて、配線基板１も平面視して従来のものよりも小さいサイズのものを用いることができて、積層型半導体装置の小型化を図ることができる。   Further, since a member such as the sealing resin 7 that supports the protruding portion of the second semiconductor element 4 is not required, the arrangement of the second electrode 1b on the wiring board 1 is brought close to the center of the wiring board 1. In accordance with this, the wiring board 1 can also be used in a smaller size than the conventional one in plan view, and the stacked semiconductor device can be miniaturized.

なお、上記何れの実施の形態でも、第２の半導体素子４の４つの辺の何れもが第１の半導体素子２よりも突出している場合を述べたが、これに限るものではなく、第２の半導体素子４が第１の半導体素子２よりも突出する辺は少なくとも１辺であればよく、突出した辺についてのみ上記構成を用いることによって上記効果を得ることができる。   In any of the above embodiments, the case where any of the four sides of the second semiconductor element 4 protrudes from the first semiconductor element 2 has been described. However, the present invention is not limited to this. The side where the semiconductor element 4 protrudes from the first semiconductor element 2 may be at least one side, and the above-described effect can be obtained by using the above configuration only for the protruding side.

以上説明したように、本発明は、第２の半導体素子が第１の半導体素子より一部突出する形で搭載された積層型半導体装置に適用できるものであり、突出した第２の半導体素子への安定したワイヤボンドを行いつつ、積層型半導体装置の小型化を図る方法として有用である。   As described above, the present invention can be applied to a stacked semiconductor device in which the second semiconductor element is mounted so as to partially protrude from the first semiconductor element. It is useful as a method for reducing the size of a stacked semiconductor device while performing stable wire bonding.

（ａ）は本発明の第１の実施形態に係る積層型半導体装置を示す断面図 （ｂ）は同積層型半導体装置の封止樹脂を設ける前の状態を示す平面図(A) is sectional drawing which shows the laminated semiconductor device which concerns on the 1st Embodiment of this invention (b) is a top view which shows the state before providing sealing resin of the laminated semiconductor device （ａ）〜（ｇ）は、それぞれ第１の実施形態に係る積層型半導体装置の製造方法の各工程を示す断面図(A)-(g) is sectional drawing which shows each process of the manufacturing method of the laminated semiconductor device which concerns on 1st Embodiment, respectively. 本発明の第２の実施形態に係る積層型半導体装置を示す平面図The top view which shows the laminated semiconductor device which concerns on the 2nd Embodiment of this invention 本発明の第３の実施形態に係る積層型半導体装置を示す平面図The top view which shows the laminated semiconductor device which concerns on the 3rd Embodiment of this invention. （ａ）は従来の積層型半導体装置を示す断面図 （ｂ）は同従来の積層型半導体装置の封止樹脂を設ける前の状態を示す平面図(A) is sectional drawing which shows the conventional laminated semiconductor device (b) is a top view which shows the state before providing sealing resin of the conventional laminated semiconductor device

符号の説明Explanation of symbols

１ 配線基板
１ａ 第１の電極
１ｂ 第２の電極
２ 第１の半導体素子
３ バンプ
４ 第２の半導体素子
４ａ 第１の電極
４ｂ 第２の電極
４ｃ 第３の電極
４ｄ ダミー電極
５ 接着層
６ 金属細線
７ 封止樹脂
８ 金属バンプ
９ 絶縁性シート DESCRIPTION OF SYMBOLS 1 Wiring board 1a 1st electrode 1b 2nd electrode 2 1st semiconductor element 3 Bump 4 2nd semiconductor element 4a 1st electrode 4b 2nd electrode 4c 3rd electrode 4d Dummy electrode 5 Adhesive layer 6 Metal Fine wire 7 Sealing resin 8 Metal bump 9 Insulating sheet

Claims (4)

第１の電極と第２の電極とがそれぞれ複数設けられた配線基板と、
前記配線基板に機能面が対向する形でフリップチップ搭載され、前記配線基板上の第１の電極と電気的な接続がなされた第１の半導体素子と、
前記第１の半導体素子と背中合わせになる形で搭載され、この半導体素子上の電極を有する辺の少なくとも１辺が前記第１の半導体素子より突出した第２の半導体素子と、
前記配線基板上の第２の電極と前記第２の半導体素子上の電極との間の電気的接続を行う金属細線と、
前記第１の半導体素子と前記第２の半導体素子と前記金属配線とを覆う形で前記配線基板上に形成された封止樹脂と、
外部接続用の金属バンプと
を有した積層型半導体装置であって、
前記第２の半導体素子における前記第１の半導体素子よりも突出した辺に形成された複数の電極の配列として、前記突出した辺の端部に近い複数の電極は、前記突出した辺の中心寄り部分に配列された電極よりも内側に配列されていることを特徴とする積層型半導体装置。 A wiring board provided with a plurality of first electrodes and a plurality of second electrodes,
A first semiconductor element that is flip-chip mounted with the functional surface facing the wiring board and electrically connected to the first electrode on the wiring board;
A second semiconductor element mounted back-to-back with the first semiconductor element, wherein at least one of the sides having electrodes on the semiconductor element protrudes from the first semiconductor element;
A fine metal wire for electrical connection between the second electrode on the wiring board and the electrode on the second semiconductor element;
A sealing resin formed on the wiring substrate so as to cover the first semiconductor element, the second semiconductor element, and the metal wiring;
A stacked semiconductor device having metal bumps for external connection,
As an arrangement of a plurality of electrodes formed on a side protruding from the first semiconductor element in the second semiconductor element, a plurality of electrodes close to an end of the protruding side are closer to the center of the protruding side. A stacked semiconductor device, wherein the stacked semiconductor device is arranged inside an electrode arranged in a portion. 第２の半導体素子上の電極が千鳥配列にて配置されており、
前記第２の半導体素子における前記第１の半導体素子よりも突出した辺の端部に近い複数の電極は、前記突出した辺の中心寄り部分に配置された千鳥配列の内側の電極と同一ライン上で部分的に周辺配置となっていることを特徴とする請求項１に記載の積層型半導体装置。 The electrodes on the second semiconductor element are arranged in a staggered arrangement,
In the second semiconductor element, the plurality of electrodes near the end of the side protruding from the first semiconductor element are on the same line as the electrode inside the staggered arrangement arranged near the center of the protruding side. 2. The stacked semiconductor device according to claim 1, wherein the stacked semiconductor device is partially peripherally arranged. 第１の電極と第２の電極とがそれぞれ複数設けられた配線基板と、
前記配線基板に機能面が対向する形でフリップチップ搭載され、前記配線基板上の第１の電極と電気的な接続がなされた第１の半導体素子と、
前記第１の半導体素子と背中合わせになる形で搭載され、この半導体素子上の電極を有する辺の少なくとも１辺が前記第１の半導体素子より突出した第２の半導体素子と、
前記配線基板上の第２の電極と前記第２の半導体素子上の電極との間の電気的接続を行う金属細線と、
前記第１の半導体素子と前記第２の半導体素子と前記金属配線とを覆う形で前記配線基板上に形成された封止樹脂と、
外部接続用の金属バンプと
を有した積層型半導体装置であって、
第２の半導体素子における第１の半導体素子よりも突出した辺の端部に近い箇所に、複数のダミー電極を配置していることを特徴とする積層型半導体装置。 A wiring board provided with a plurality of first electrodes and a plurality of second electrodes,
A first semiconductor element that is flip-chip mounted with the functional surface facing the wiring board and electrically connected to the first electrode on the wiring board;
A second semiconductor element mounted back-to-back with the first semiconductor element, wherein at least one of the sides having electrodes on the semiconductor element protrudes from the first semiconductor element;
A fine metal wire for electrical connection between the second electrode on the wiring board and the electrode on the second semiconductor element;
A sealing resin formed on the wiring substrate so as to cover the first semiconductor element, the second semiconductor element, and the metal wiring;
A stacked semiconductor device having metal bumps for external connection,
A stacked semiconductor device, wherein a plurality of dummy electrodes are arranged in a portion of the second semiconductor element that is closer to an end portion of the side protruding than the first semiconductor element. 請求項１〜３の何れか１項に記載の積層型半導体装置を製造する製造方法であって、
配線基板上の第１の電極と対向する形で配置された電極を有する第１の半導体素子をフリップチップにて実装する工程と、
前記第１の半導体素子と背中合わせで、接着材を用いて、前記第１の半導体素子よりも突出した辺を有する第２の半導体素子を搭載する工程と、
前記第２の半導体素子における前記突出した辺の端部近くに配置された複数の電極と前記配線基板上の複数の第２の電極とを金属細線により結線する工程と、
前記突出した辺の端部近くに配置された複数の電極の結線がなされた後に、前記第２の半導体素子の残りの電極と前記配線基板上の残りの第２の電極とを結線する工程と、
前記配線基板において、前記第１の半導体素子と、前記第２の半導体素子と、前記金属細線とを覆う形で樹脂成形する工程と、
前記配線基板における前記第１の半導体素子を搭載する面とは反対の面に、外部接続用の金属バンプを形成する工程と
を有することを特徴とする積層型半導体装置の製造方法。 A manufacturing method for manufacturing the stacked semiconductor device according to claim 1,
Mounting a first semiconductor element having an electrode disposed opposite to the first electrode on the wiring board by flip chip;
Mounting a second semiconductor element having a side protruding from the first semiconductor element by using an adhesive back to back with the first semiconductor element;
Connecting a plurality of electrodes arranged near end portions of the protruding sides in the second semiconductor element and a plurality of second electrodes on the wiring board by metal thin wires;
Connecting the remaining electrodes of the second semiconductor element and the remaining second electrodes on the wiring board after the connection of the plurality of electrodes arranged near the end of the protruding side is made; ,
In the wiring board, a step of resin molding so as to cover the first semiconductor element, the second semiconductor element, and the thin metal wire;
And a step of forming metal bumps for external connection on a surface opposite to the surface on which the first semiconductor element is mounted in the wiring board.
JP2004170597A 2004-06-09 2004-06-09 Multilayered semiconductor device and its manufacturing method Pending JP2005353704A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227596A (en) * 2006-02-23 2007-09-06 Shinko Electric Ind Co Ltd Semiconductor module and its manufacturing method
KR20160059612A (en) * 2014-11-19 2016-05-27 에스케이하이닉스 주식회사 Semiconductor package having overhang part and method for fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227596A (en) * 2006-02-23 2007-09-06 Shinko Electric Ind Co Ltd Semiconductor module and its manufacturing method
KR20160059612A (en) * 2014-11-19 2016-05-27 에스케이하이닉스 주식회사 Semiconductor package having overhang part and method for fabricating the same
KR102276477B1 (en) * 2014-11-19 2021-07-13 에스케이하이닉스 주식회사 Method for fabricating semiconductor package having overhang part

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