JP2008205518A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lower stage semiconductor device and a multilayer type semiconductor device easily manufactured, wherein the lower stage semiconductor device having high contact reliability with an upper stage even when connecting terminal height of a semiconductor device mounted on the upper stage is low in stacking semiconductor devices. <P>SOLUTION: A semiconductor device 20 includes a base substrate 1, a semiconductor chip 3 mounted on the base substrate 1 via an adhesive layer 2, a resin layer 6 covering at least a portion of the semiconductor chip 3, and an outer connecting terminal 8 electrically connected to the base substrate 1 via wiring layer 9. The outer connecting terminal 8 is exposed from the resin layer 6 on the same plane with the surface of the resin layer 6. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device on which a semiconductor chip is mounted, a stacked semiconductor device in which a plurality of semiconductor devices are stacked, and a method for manufacturing the semiconductor device.

In recent years, as electronic devices have been reduced in size, weight, and functionality, there has been a demand for high-density mounting of semiconductor devices. In order to meet this requirement, a method of stacking semiconductor devices to increase the density has been proposed (see, for example, Patent Documents 1 and 2).
JP-A-10-135267 (published May 22, 1998) JP 2004-172157 A (released on June 17, 2004)

  In the conventional configuration, in stacking semiconductor devices, the relationship between the connection terminal height of the upper semiconductor device and the resin sealing height of the lower semiconductor device is important.

  This point will be described with reference to FIGS. FIG. 15 is a cross-sectional view showing a state in which two conventional semiconductor devices are stacked.

  In FIG. 15, the semiconductor device 200 is stacked on the semiconductor device 100. Among these, the semiconductor device 100 is provided on the base substrate 101, the semiconductor chip 103 mounted on the base substrate 101, the external connection terminal 107 provided on the lower surface of the base substrate 101, and the upper surface of the base substrate 101. And an external connection terminal 108. The semiconductor chip 103 and the base substrate 101 are electrically connected by a wire 104. The semiconductor chip 103 and the wire 104 are covered with a resin layer 106. On the other hand, the region where the external connection terminal 108 is provided on the base substrate 101 is not covered with the resin layer 106 and is exposed.

  The semiconductor device 200 is the same as the semiconductor device 100 except that not only the region where the semiconductor chip 103 and the wire 104 are formed, but also the entire region on the base substrate 101 is covered with the resin layer 106. It is configured.

  For example, when the two semiconductor devices 100 and 200 shown in FIG. 15 are stacked, if the height s of the external connection terminal 107 of the semiconductor device 200 is lower than the height t of the resin layer 106 of the semiconductor device 100, the semiconductor device 200. A gap u is generated between the external connection terminal 107 and the external connection terminal 108 of the semiconductor device 100, and the semiconductor device 100 and the semiconductor device 200 are not connected. Therefore, in order to connect the semiconductor device 100 and the semiconductor device 200, a relationship of “height s of the external connection terminals 107 of the semiconductor device 200> height t of the resin layer 106 of the semiconductor device 100” is necessary.

  Therefore, if the height s of the external connection terminal 107 of the semiconductor device 200 is lowered, the height t of the resin layer 106 of the semiconductor device 100 needs to be lowered. However, in order to reduce the height t of the resin layer 106 of the semiconductor device 100, techniques for reducing the thickness of the semiconductor device 100, such as reducing the thickness of the semiconductor chip 103 and lowering the loop of the wire 104, are required. There is a problem that the technical difficulty level in the manufacture of the product increases. Similar problems occur when stacking semiconductor devices as shown in FIG.

  FIG. 16 is a cross-sectional view showing a state in which two conventional semiconductor devices are stacked. In FIG. 16, the semiconductor device 400 is stacked on the semiconductor device 300. In the semiconductor device 300, the external connection terminal 108 is formed on the semiconductor chip 103, and the region where the external connection terminal 108 is formed is not covered with the resin layer 106 and is exposed. Other configurations are the same as those of the semiconductor device 100 described above. The semiconductor device 400 has the same configuration as the semiconductor device 200 described above.

  FIG. 17 is a cross-sectional view showing a resin sealing step in a conventional semiconductor device manufacturing process. When manufacturing the semiconductor device 300 described above, the following problems occur in the resin sealing process. That is, the region of the semiconductor chip 103 where the external connection terminal 108 is formed is not covered with the resin 106, and only the other region is covered. For example, when resin sealing is performed by transfer molding, as shown in FIG. In addition, the mold 50 directly presses the wiring layer 108 formed on the semiconductor chip 103 and composed of the conductive layer x and the insulating layer y. Usually, the wiring layer 108 has a thin thickness of about 50 μm and is hardly deformed. Therefore, the stress applied by the mold 50 cannot be absorbed by the wiring layer 108. For this reason, a strong stress is applied to the semiconductor chip 103, which may damage the semiconductor chip 103.

  The present invention has been made in view of the above problems, and one of its purposes is to stack the semiconductor devices with each other even if the connection terminal height of the semiconductor device mounted on the upper stage is low. It is an object of the present invention to provide a lower semiconductor device and a stacked semiconductor device that have high bonding reliability and can be easily manufactured, and contribute to high-density mounting of the semiconductor device.

  Another object of the present invention is to reduce damage to a semiconductor chip or the like by a simple process in a semiconductor device having a structure in which external connection terminals are exposed from a resin layer.

  In order to solve the above problems, a semiconductor device of the present invention includes a base substrate, a semiconductor chip electrically connected to the base substrate, a resin layer covering at least a part of the semiconductor chip, and the base substrate. And a first external connection terminal electrically connected, wherein the first external connection terminal is exposed from the resin layer on the same plane as the surface of the resin layer.

  According to the above configuration, since the first external connection terminal is exposed from the resin layer in the same plane as the surface of the resin layer, the upper semiconductor device is stacked when the semiconductor device is stacked on the semiconductor device of the present invention. Even if the height of the external connection terminal is low, it is possible to secure the connection between the first external connection terminal and the external connection terminal of the upper semiconductor device. That is, when the external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of the external connection terminals is lowered, but even in this case, the problem is that the resin layer prevents the first external connection terminals from reaching the first external connection terminals. Does not occur. For this reason, since it is not necessary to reduce the height of the resin layer in order to secure the connection, the semiconductor device of the present invention has high bonding reliability with the upper stage, and the semiconductor chip is made thinner and the wire is made less looped. Thus, the semiconductor device can be easily manufactured without requiring a technology for thinning the semiconductor device.

  Further, instead of exposing the wiring layer formed on the surface of the semiconductor chip for connection with the upper semiconductor device, if the first external connection terminal as described above is used, the semiconductor device is made of resin by transfer molding, for example. Even in the case of sealing, damage to the semiconductor chip can be reduced.

  In the semiconductor device of the present invention, the first external connection terminal may be electrically connected to the base substrate via a wiring layer.

  In this manner, by electrically connecting the first external connection terminal to the base substrate via the wiring layer, electrical connection between the semiconductor device of the present invention and the upper semiconductor device can be easily ensured.

  In the semiconductor device of the present invention, the wiring layer may be formed on the surface of the semiconductor chip on the first external connection terminal side.

  By directly forming the wiring layer on the surface of the semiconductor chip on the side of the first external connection terminal, the semiconductor device can be made thinner than a structure having a support and an adhesive layer described later.

  In the semiconductor device of the present invention, the wiring layer may be formed on a support and mounted on the semiconductor chip.

  By forming the wiring layer on the support and mounting it on the semiconductor chip via the adhesive layer, the stress applied to the semiconductor chip is reduced by the support and the adhesive layer, further reducing damage to the semiconductor chip. it can.

  In the semiconductor device of the present invention, the area of the region where the wiring layer is provided may be larger than the area of the semiconductor chip. In other words, the wiring layer may be larger in size than the semiconductor chip.

  By forming the wiring layer over a wider area than the semiconductor chip in this way, the upper and lower semiconductor devices can be stacked even if the external connection terminal array area of the upper semiconductor device is larger than the lower semiconductor chip.

  In the semiconductor device of the present invention, the first external connection terminal may be formed on a base substrate.

  By forming the first external connection terminal on the base substrate instead of above the semiconductor chip, stress applied to the first external connection terminal by the mold during resin sealing is applied to the semiconductor chip. Therefore, damage to the semiconductor chip can be further reduced. Further, there is an advantage that the height of the semiconductor device can be reduced.

  In the semiconductor device of the present invention, the semiconductor chip may be provided in the opening of the base substrate.

  Thus, by providing the semiconductor chip in the opening of the base substrate, the semiconductor chip can be mounted at a higher density than when the semiconductor chip is provided on the base substrate.

  In the semiconductor device of the present invention, the semiconductor chip may be provided in a recess of the base substrate.

  As described above, by providing the semiconductor chip in the concave portion of the base substrate, the semiconductor chip can be mounted at a higher density than when the semiconductor chip is provided on the base substrate.

  In the semiconductor device of the present invention, the surface of the resin layer in the region where the first external connection terminal is provided may be recessed toward the base substrate with respect to the surface of the resin layer in the other region. . In other words, the resin surface in the region where the first external connection terminals are arranged may be lower than the resin surface in other regions.

  As described above, when the surface of the resin layer in the region where the first external connection terminal is provided is recessed, when the semiconductor device is stacked on the semiconductor device of the present invention, the external connection of the upper semiconductor device is performed. A part of the terminal can be accommodated in this recess, and further densification is possible.

  In the semiconductor device of the present invention, the first external connection terminal may be made of solder.

  By forming the first external connection terminal from solder, which is a material that is easily deformed, the first external connection terminal can be easily deformed and more easily exposed from the resin layer on the same surface as the surface of the resin layer. Become.

  In the semiconductor device of the present invention, the melting point temperature of the solder is preferably 200 ° C. or higher.

  Since the mold temperature at the time of resin sealing is generally between 150 to 200 ° C., if the melting point temperature of the solder is 200 ° C. or more, the mold temperature exceeds the melting point of the solder and the solder The risk of melting and flowing can be reduced.

  In the semiconductor device of the present invention, the first external connection terminal may be made of copper.

  By forming the first external connection terminal from copper, which is a material that is easily deformed, the first external connection terminal can be easily deformed and more easily exposed from the resin layer on the same surface as the surface of the resin layer. Become.

  The semiconductor device of the present invention may include a plurality of the semiconductor chips, and each semiconductor chip may be electrically connected to the base substrate.

  By mounting a plurality of semiconductor chips in the resin layer, it is possible to further increase the density.

  Moreover, in order to solve the above-described problem, the stacked semiconductor device according to the present invention includes any one of the above semiconductor devices further including a second external connection terminal. The semiconductor devices are electrically connected to each other by bonding of a first external connection terminal and a second external connection terminal.

  According to the above configuration, the semiconductor devices can be electrically connected to each other by joining the first external connection terminal and the second external connection terminal, thereby further increasing the density.

  Further, in order to solve the above problems, the stacked semiconductor device of the present invention has another semiconductor device provided with a second external connection terminal stacked on any of the above semiconductor devices, The first external connection terminal and the second external connection terminal are electrically connected to each other by bonding.

  According to the above configuration, the semiconductor devices can be electrically connected to each other by joining the first external connection terminal and the second external connection terminal, thereby further increasing the density.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a base substrate; a semiconductor chip electrically connected to the base substrate; and a resin layer covering at least a part of the semiconductor chip. A method of manufacturing a semiconductor device comprising a first external connection terminal electrically connected to the base substrate, wherein the first external connection terminal is exposed from the resin layer on the same plane as the surface of the resin layer. And a sealing step of sealing the resin.

  According to said structure, the semiconductor device which the 1st external connection terminal exposed from the resin layer in the same surface as the surface of the resin layer can be manufactured. Therefore, when the semiconductor device is stacked on the semiconductor device, the connection between the external connection terminals can be ensured even if the height of the external connection terminal of the upper semiconductor device is low. In other words, when the external connection terminals of the upper semiconductor device are arranged at a narrow pitch, the height of the external connection terminals is lowered, but even in this case, it cannot reach the external connection terminals of the semiconductor device obtained by this manufacturing method. There is no problem. Therefore, in the semiconductor device manufacturing method of the present invention, it is not necessary to reduce the height of the resin layer in order to ensure the connection with the upper semiconductor device. It can be easily manufactured without requiring a technique for reducing the thickness of the semiconductor device such as reducing the thickness of the semiconductor device and reducing the loop of the wire.

  In addition, instead of exposing the wiring layer formed on the surface of the semiconductor chip for connection with the upper semiconductor device, as described above, the external connection terminal is formed, and after resin deformation after performing deformation, Damage to the semiconductor chip can be reduced.

  In the method of manufacturing a semiconductor device according to the present invention, in order to solve the above-described problem, the encapsulating step includes the step of pressing a mold to flatten the surface of the first external connection terminal and the flattening. And a step of encapsulating the resin so that the first external connection terminal is exposed from the resin layer on the same surface as the surface of the resin layer.

  According to the above configuration, the external connection terminals can be exposed from the resin layer on the same surface as the surface of the resin layer by a simple process of encapsulating the resin after pressing the mold to deform the external connection terminals. Therefore, the semiconductor device can be easily manufactured.

  The method for manufacturing a semiconductor device of the present invention may further include a step of applying heat below the melting point of the external connection terminal to the mold.

  By setting the heat applied to the mold below the melting point of the external connection terminal, the risk that the mold temperature exceeds the melting point of the solder and the solder melts and flows can be reduced.

  In the semiconductor device of the present invention, as described above, since the first external connection terminal is exposed from the resin layer on the same surface as the surface of the resin layer, the semiconductor device is stacked on the semiconductor device of the present invention. Even when the height of the external connection terminal of the upper semiconductor device is low, the connection between the first external connection terminal and the external connection terminal of the upper semiconductor device can be secured. For this reason, since it is not necessary to reduce the height of the resin layer in order to secure the connection, the semiconductor device of the present invention has high bonding reliability with the upper stage, and the semiconductor chip is made thinner and the wire is made less looped. Thus, there is an effect that the semiconductor device can be easily manufactured without requiring a technology for thinning the semiconductor device.

  In addition, when the first external connection terminal as described above is used instead of exposing the wiring layer formed on the surface of the semiconductor chip for connection with the upper semiconductor device, for example, when resin sealing is performed by transfer molding Even so, there is an effect that damage to the semiconductor chip can be reduced.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 14 as follows. In the following description, the expressions “upper surface”, “lower surface”, “upper”, and “lower” are used with reference to the upper and lower sides in the drawings, but this is for convenience of description, and any surface is upward (or lower). It is not intended to limit the point of whether or not.

  FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device of this embodiment. FIG. 2 is a plan view showing the semiconductor device as viewed from above.

  As shown in FIG. 1, a semiconductor device 20 according to the present embodiment is provided on a base substrate 1, a semiconductor chip 3 mounted on the base substrate 1 via an adhesive layer 2, and a lower surface of the base substrate 1. And external connection terminals (second external connection terminals) 7. The base substrate 1 and the semiconductor chip 3 are electrically connected by wires 4.

  A wiring layer 9 is formed on the upper surface of the semiconductor chip 3, and an external connection terminal (first external connection terminal) 8 that is a conductive protrusion is formed on the wiring layer 9. The external connection terminals 8 are arranged in an area array as shown in FIG. The wiring layer 9 and the base substrate 1 are connected by a wire 4.

  The semiconductor device 20 is sealed with the resin layer 6. Specifically, the resin layer 6 covers the upper surface of the base substrate 1, the adhesive layer 2, the semiconductor chip 3, the wires 4, and the wiring layer 9. As a material of the resin layer 6, for example, an epoxy resin, a silicone resin, or the like is preferably used, but is not particularly limited.

  The semiconductor device 20 according to the present embodiment is characterized in that the external connection terminals 8 are exposed from the resin layer 6 on the same plane as the surface of the resin layer 6. In other words, the surface of the external connection terminal 8 and the surface of the resin layer 6 form the same surface. It can also be said that the surface of the external connection terminal 8 and the surface of the resin layer 6 are at the same height.

  Here, the “same surface” does not have to be exactly the same, and may be substantially the same surface in order to obtain the effects described below.

  By exposing the surface of the external connection terminal 8 from the resin layer 6 as described above, the external connection terminal 8 is formed on the surface of the semiconductor device 20. Therefore, when the semiconductor device is stacked on the semiconductor device 20, even if the height of the external connection terminal of the upper semiconductor device is low, the external connection terminal 8 of the semiconductor device 20 and the external connection terminal of the upper semiconductor device Can be secured. In other words, even if the height of the external connection terminals of the upper semiconductor device is lowered for higher density integration, there is no problem that the resin layer 6 prevents the external connection terminals 8 from reaching the external connection terminals 8. For this reason, since it is not necessary to reduce the height of the resin layer 6 in order to ensure the connection, the semiconductor device 20 of the present embodiment has high bonding reliability with the upper stage, and the semiconductor chip 3 is made thinner. The semiconductor device 20 can be easily manufactured without requiring a technique for reducing the thickness of the semiconductor device 20, such as reducing the loop of the wire 4.

  Further, according to the semiconductor device 20 of the present embodiment, the wiring layer 9 formed on the surface of the semiconductor chip 3 is not exposed from the resin layer 6 (covered by the resin layer 6). For this reason, it is not necessary to block the wiring layer 9 formed on the surface of the semiconductor chip 3 with a mold during resin sealing. Therefore, damage to the semiconductor chip 3 during resin sealing can be reduced.

  Further, in the semiconductor device 20 of the present embodiment, the external connection terminal 8 is electrically connected to the base substrate 1 via the wiring layer 9, and thus the electrical connection between the semiconductor device 20 and the upper semiconductor device. Can be easily secured.

  Further, in the semiconductor device 20 of the present embodiment, since the wiring layer 9 is formed on the upper surface of the semiconductor chip 3, the semiconductor device 20 can be thinned.

  Next, a method for manufacturing the semiconductor device 20 of the present embodiment will be described. FIG. 3A to FIG. 3C are cross-sectional views showing the manufacturing process of the semiconductor device 20 of the present embodiment.

  First, as shown in FIG. 3A, the semiconductor chip 3 in which the wiring layer 9 and the external connection terminals 8 are formed in advance is mounted on the base substrate 1 via the adhesive layer 2. The external connection terminals 8 may be mounted after mounting the semiconductor chip 3 on which the wiring layer 9 has been formed in advance on the base substrate 1. Thereafter, the semiconductor chip 3 and the base substrate 1 are electrically connected by the wire 4, and the wiring layer 9 and the base substrate 1 are also electrically connected by the wire 4.

  Next, the resin is sealed so that the external connection terminals 8 are exposed from the resin layer 6 on the same surface as the surface of the resin layer 6 (encapsulation step). Here, as shown in FIG. 3B, the external connection terminal 8 is deformed by pressing the mold 50. That is, the upper surface of the external connection terminal 8 is flattened by pressing the mold 50 having a flat surface in contact with the external connection terminal 8. In order to perform this process easily, the external connection terminal 8 is preferably made of a material that is easily deformed. Examples of the easily deformable material include solder and copper.

  When solder is used as the material of the external connection terminal 8, if the mold temperature exceeds the melting point of the solder, the solder will melt and flow when encapsulating the resin. The mold temperature during resin sealing is generally between 150 and 200 ° C. Therefore, it is preferable to employ solder having a melting point of 200 ° C. or higher.

  Thereafter, as shown in FIG. 3C, the resin is sealed so that the external connection terminals 8 are exposed from the resin layer 6 on the same surface as the surface of the resin layer 6.

  Finally, external connection terminals 7 are formed on the lower surface of the base substrate 1. Note that the formation of the external connection terminals 7 is not limited to after resin sealing, and may be formed in advance before resin sealing.

  As described above, the manufacturing method of the semiconductor device 20 according to the present embodiment includes the encapsulation step, and this encapsulation step is performed using the mold 50. According to the above manufacturing method, since the external connection terminals 8 of the semiconductor device 20 can be easily exposed from the resin layer on the same surface as the surface of the resin layer 6, the semiconductor device 20 can be easily manufactured. In the above description, the mold 50 is used. However, in the above manufacturing method, if the external connection terminal 8 is exposed from the resin layer 6 (that is, the external connection terminal 8 is on the surface of the semiconductor device 20). It is not limited to using the mold 50 as long as it is formed.

  Below, the modification of the semiconductor device 20 of this Embodiment is shown. In addition, about the member which has the same function as the member mentioned above, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

(Modification 1)
FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device 20a of the first modification. As shown in FIG. 4, in the semiconductor device 20 a, the semiconductor chip 3 and the base substrate 1 are connected by flip chip bonding using bumps 10 instead of using wires 4.

  Except for the above points, the semiconductor device 20a has the same configuration as the semiconductor device 20 described above.

  Thus, in the semiconductor device 20a of the present modification, the semiconductor chip 3 is mounted on the base substrate 1 with higher density by using flip chip bonding.

  The semiconductor device 20a can be manufactured by the same method as that of the semiconductor device 20 described above, except that the semiconductor chip 3 and the base substrate 1 are connected by flip chip bonding.

(Modification 2)
FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device 20b of the second modification. In the semiconductor devices 20 and 20a described above, the wiring layer 9 is formed directly on the semiconductor chip 3, but in the semiconductor device 20b, the wiring layer 9 is formed on the support 11 as shown in FIG. It is mounted on the chip 3 via an adhesive layer 12. Since the wiring layer 9 is formed on the support 11 and mounted on the semiconductor chip 3 via the adhesive layer 12, the stress applied to the semiconductor chip 3 is reduced by the support 11 and the adhesive layer 12. The damage to the chip 3 can be further reduced. The support 11 and the adhesive layer 12 are insulators. If a material having a low elastic modulus is used, the stress can be absorbed and damage to the semiconductor chip 3 can be reduced.

  The support 11 and the formation region of the wiring layer 9 on the support 11 may have a larger area than the semiconductor chip 3. In other words, the wiring layer 9 may be larger than the semiconductor chip 3. If the wiring layer 9 is formed over a wider area than the semiconductor chip 3, the upper and lower semiconductor devices can be stacked even if the external connection terminal array area of the upper semiconductor device is larger than the lower semiconductor chip.

  The semiconductor chip 3 and the base substrate 1 are connected by a wire 4. On the other hand, the wiring layer 9 and the base substrate 1 are connected by a wire 5.

  Since there is not enough space between the semiconductor chip 3 and the adhesive layer 12 to provide the wire 4, the wire 4 is provided so as to pass through the inside of the adhesive layer 12. In other words, the wire 4 is wrapped in the adhesive layer 12. Since the wire 4 is wrapped in the adhesive layer 12, there is an advantage that wire deformation during resin sealing can be suppressed.

  Except for the above points, the semiconductor device 20b has the same configuration as the semiconductor device 20 described above. Therefore, the same method as the method for manufacturing the semiconductor device 20 described above can be used as a method for forming and deforming the external connection terminal 8 and sealing with resin.

(Modification 3)
FIG. 6 is a cross-sectional view illustrating a configuration of a semiconductor device 20c according to the third modification. The configuration of the semiconductor device 20c is almost the same as that of the semiconductor device 20b of the second modification. However, the spacer layer 13 is provided on the semiconductor chip 3 via the adhesive layer 18 as shown in FIG. Different.

  By providing the spacer layer 13, it is possible to secure a sufficient space for providing the wire 4 between the semiconductor chip 3 and the adhesive layer 12. Therefore, in the semiconductor device 20 c of the present modification, the wire 4 is attached to the adhesive layer 12. The reliability of the connection between the semiconductor chip 3 and the wire 4 is improved without passing through the inside. Furthermore, a conductive material can be applied to the support 11 and the spacer layer 13, and heat dissipation is improved.

  Also for the semiconductor device 20c, the same method as the method for manufacturing the semiconductor device 20 described above can be used as a method of forming and deforming the external connection terminal 8 and sealing the resin.

(Modification 4)
FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device 20d of Modification 4. As shown in FIG. 7, unlike the semiconductor device 20 b of Modification 2, in the semiconductor device 20 d, the semiconductor chip 3 and the base substrate 1 are connected by flip chip bonding with bumps 10. Other configurations are the same as those of the semiconductor device 20b of the second modification.

  As described above, in the semiconductor device 20d of this modification, the semiconductor chip 3 is mounted on the base substrate 1 with higher density by using flip chip bonding. That is, it is not necessary to increase the thickness of the adhesive layer 12 as in the second modification, or to provide the spacer layer 13 as in the third modification, so that the semiconductor device is thinned.

  The semiconductor device 20d can also be manufactured by the same method as the semiconductor device 20 described above, except that the semiconductor chip 3 and the base substrate 1 are connected by flip chip bonding.

(Modification 5)
FIG. 8 is a cross-sectional view showing a configuration of a semiconductor device 20e of Modification 5. In the semiconductor devices 20 to 20 d described above, the external connection terminal 8 is provided on the semiconductor chip 3 via the wiring layer 9. On the other hand, in the semiconductor device 20e, as shown in FIG. 8, the external connection terminals 8 are directly provided on the base substrate 1 and are electrically connected.

  Except for the above points, the semiconductor device 20e has the same configuration as the semiconductor device 20 described above.

  As described above, in the semiconductor device 20 d of this modification, the external connection terminal 8 is formed on the base substrate 1 rather than above the semiconductor chip 3. For this reason, since the stress applied to the external connection terminals 8 by the mold during resin sealing is not applied to the semiconductor chip 3, damage to the semiconductor chip 3 can be further reduced. Further, there is an advantage that the height of the semiconductor device can be reduced.

  Also for the semiconductor device 20d, the same method as the method for manufacturing the semiconductor device 20 described above can be used as a method of forming and deforming the external connection terminal 8 and sealing the resin.

(Modification 6)
FIG. 9 is a cross-sectional view illustrating a configuration of a semiconductor device 20f according to Modification 6. Also in the semiconductor device 20f, as in the semiconductor device 20e of the modified example 5, the external connection terminals 8 are provided directly on the base substrate 1 and are electrically connected.

  The difference from the semiconductor device 20e is that, as shown in FIG. 9, (1) the semiconductor chip 3 is provided in the opening 16 of the base substrate 1, and (2) two semiconductor chips 3 are stacked. These are electrically connected to the base substrate 1 through the wires 4 and the wiring layers 9.

  Except for the above points, the semiconductor device 20f has the same configuration as that of the semiconductor device 20e of Modification 5.

  As described above, in the semiconductor device 20f of the present modification, the semiconductor chip 3 is provided in the opening 16 of the base substrate 1, and therefore the semiconductor chip 3 is compared with the case where the semiconductor chip 3 is provided on the base substrate 1. Can be mounted at higher density.

  In this modification, two semiconductor chips 3 are stacked, but the number of semiconductor chips 3 to be mounted is not limited to two. When one semiconductor chip 3 is mounted, the semiconductor device can be made thinner as compared with the case where the semiconductor chip 3 is provided on the base substrate 1, so that high density can be achieved. Also, when three or more semiconductor chips 3 are stacked, the semiconductor chips 3 can be mounted at a higher density than when the same number of semiconductor chips 3 are provided on the base substrate 1.

  Also for the semiconductor device 20f, the same method as the method for manufacturing the semiconductor device 20 described above can be used as a method for forming and deforming the external connection terminal 8 and sealing with resin.

(Modification 7)
FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device 20g according to Modification 7. Also in the semiconductor device 20g, as in the semiconductor device 20e of the modified example 5, the external connection terminals 8 are provided directly on the base substrate 1 and are electrically connected.

  The difference from the semiconductor device 20e is that, as shown in FIG. 10, (1) the semiconductor chip 3 is provided in the recess 17 of the base substrate 1, and (2) two semiconductor chips 3 are stacked. Each of them is electrically connected to the base substrate 1 through the wire 4. In this modification, the lower semiconductor chip 3 and the base substrate 1 are directly electrically connected by the wire 4 without the wiring layer 9, but may be connected through the wiring layer 9. Further, the upper semiconductor chip 3 and the base substrate 1 are electrically connected by the wire 4 via the wiring layer 9, but are directly electrically connected to the base substrate 1 not via the wiring layer 9. Also good.

  Except for the above points, the semiconductor device 20g has the same configuration as the semiconductor device 20e of Modification 5.

  Thus, in the semiconductor device 20f of the present modification, the semiconductor chip 3 is provided in the recess 17 of the base substrate 1, and therefore, compared to the case where the semiconductor chip 3 is provided on the base substrate 1 other than the recess 17, The semiconductor chip 3 can be mounted with higher density.

  In addition, the mechanical strength of the semiconductor device is smaller when the recess 17 is provided in the base substrate 1 than in the configuration of the modification 6 in which the opening 16 is provided in the base substrate 1.

  Also for the semiconductor device 20g, the same method as the method for manufacturing the semiconductor device 20 described above can be used as a method of forming and deforming the external connection terminal 8 and sealing the resin.

(Modification 8)
FIG. 11 is a cross-sectional view illustrating a configuration of a semiconductor device 20h according to Modification 8. As shown in FIG. 11, in the semiconductor device 20 h, the surface of the resin layer 6 is not flat, and the surface of the resin layer 6 in the region 14 where the external connection terminals 8 are provided is the resin layer in the other region 15. 6 is lower than the surface of 6 (that is, recessed toward the base substrate 1 side). Other configurations are the same as those of the semiconductor device 20.

  As described above, when the surface of the resin layer 6 in the region where the external connection terminal 8 is provided is recessed, when the semiconductor device is stacked on the semiconductor device 20h, one of the external connection terminals of the upper semiconductor device is obtained. A part can be accommodated in this hollow, and further densification becomes possible.

  Also for the semiconductor device 20h, the same method as the method for manufacturing the semiconductor device 20 described above can be used as a method of forming and deforming the external connection terminal 8 and sealing the resin. However, as the mold 50, for example, a mold having a shape in which a portion corresponding to a depression on the surface of the resin layer 6 is projected as shown in FIG.

(Modification 9)
FIG. 12 is a cross-sectional view illustrating a configuration of a semiconductor device 20 i of Modification 9. As shown in FIG. 12, also in the semiconductor device 20i, the surface of the resin layer 6 in the region 14 where the external connection terminal 8 is provided is the resin in the other region 15 as in the semiconductor device 20h of the modification 8. It is lower than the surface of the layer 6 (that is, recessed toward the base substrate 1 side).

  In the semiconductor device 20i, the external connection terminals 8 are directly provided on the base substrate 1 and are electrically connected. Therefore, in the semiconductor device 20h, there are other regions 15 on both sides of the region 14 where the external connection terminals 8 are provided. In the semiconductor device 20i, however, the region 14 where the external connection terminals 8 are provided It is on both sides of the region 15 other than.

  Except for the above points, the semiconductor device 20 i has the same configuration as that of the semiconductor device 20 h of the modified example 8.

  Thus, by forming the external connection terminal 8 on the base substrate 1 instead of above the semiconductor chip 3, the stress applied to the external connection terminal 8 by the mold at the time of resin sealing is applied to the semiconductor chip 3. Therefore, damage to the semiconductor chip 3 can be further reduced.

  Further, by recessing the surface of the resin layer 6 in the region where the external connection terminals 8 are provided, when stacking the semiconductor device on the semiconductor device 20i, a part of the external connection terminals of the upper semiconductor device is formed. It can be accommodated in this recess, and further densification is possible.

  Also for the semiconductor device 20i, the same method as the method for manufacturing the semiconductor device 20 described above can be used as a method for forming and deforming the external connection terminal 8 and sealing the resin. However, the mold 50 has a shape in which a portion corresponding to the depression on the surface of the resin layer 6 is projected.

(Modification 10)
FIG. 13 is a cross-sectional view illustrating a configuration of a semiconductor device 20j according to the tenth modification. As shown in FIG. 13, the semiconductor device 20 j includes a base substrate 1, three semiconductor chips 3 a to 3 c stacked on the base substrate 1, and external connection terminals (second terminals provided on the lower surface of the base substrate 1. External connection terminal) 7.

  The lower semiconductor chip 3 a is provided on the base substrate 1 through an adhesive layer, and is electrically connected to the base substrate 1 by flip chip bonding using bumps 10.

  The middle semiconductor chip 3 b is provided on the lower semiconductor chip 3 a through an adhesive layer, and is electrically connected to the base substrate 1 by a wire 4. The wire 4 that connects the middle semiconductor chip 3b and the base substrate 1 passes through the inside of the adhesive layer provided on the middle semiconductor chip 3b.

  The upper semiconductor chip 3 c is provided on the middle semiconductor chip 3 b through an adhesive layer, and is electrically connected to the base substrate 1 by a wire 4. Since the spacer layer 13 is provided on the upper semiconductor chip 3c via an adhesive layer, the wire 4 connecting the upper semiconductor chip 3c and the base substrate 1 does not pass through the adhesive layer.

  A support 11 is provided on the spacer layer 13 via an adhesive layer. An external connection terminal (first external connection) that is a conductive protrusion is provided on the support 11 via a wiring layer 9. Terminal) 8 is formed. The external connection terminals 8 are arranged in an area array like the one shown in FIG. The wiring layer 9 and the base substrate 1 are connected by a wire 5.

  The semiconductor device 20j is sealed with the resin layer 6. Specifically, the resin layer 6 covers all of the members formed on the upper surface side of the base substrate 1 except for the external connection terminals 8.

  Also in the semiconductor device 20j, the external connection terminals 8 are exposed from the resin layer 6 on the same surface as the surface of the resin layer 6, similarly to the semiconductor device 20 described above. In other words, the surface of the external connection terminal 8 and the surface of the resin layer 6 form the same surface. It can also be said that the surface of the external connection terminal 8 and the surface of the resin layer 6 are at the same height. Here, “the same surface as the surface of the resin layer 6” does not have to be exactly the same, but may be substantially the same surface.

  As described above, since the three semiconductor chips 3a to 3c are mounted on the semiconductor device 20j of the present modification example, it is possible to further increase the density.

  In this modification, three semiconductor chips 3 are stacked. However, the number of stacked semiconductor chips 3 is not limited to three, and may be two or four or more. Further, the mounting method of the semiconductor chip 3 is not particularly limited.

  Also for the semiconductor device 20j, the same method as the method of manufacturing the semiconductor device 20 described above can be used as a method of forming and deforming the external connection terminal 8 and sealing the resin.

  Next, a stacked semiconductor device will be described. FIG. 14 is a cross-sectional view showing the configuration of the stacked semiconductor device 40 of the present embodiment.

  As shown in FIG. 14, in the stacked semiconductor device 40, the above-described semiconductor device 20 i is stacked on the above-described semiconductor device 20, and another semiconductor device 30 is further stacked thereon.

  The external connection terminal 8 of the semiconductor device 20 is joined to the external connection terminal 7 of the semiconductor device 20i, whereby the semiconductor device 20 and the semiconductor device 20i are electrically connected.

  The semiconductor device 30 includes an external connection terminal 7 on the lower surface. The external connection terminal 8 of the semiconductor device 20 i is joined to the external connection terminal 7 of the semiconductor device 30, whereby the semiconductor device 20 i and the semiconductor device 30 are electrically connected.

  As described above, the external connection terminal 8 of the semiconductor device 20 is exposed from the resin layer 6 on the same surface as the surface of the resin layer 6. For this reason, even if the height of the external connection terminal 7 of the upper semiconductor device 20i is low, the connection between the external connection terminal 8 of the semiconductor device 20 and the external connection terminal 7 of the semiconductor device 20i can be secured. Similarly, the external connection terminal 8 of the semiconductor device 20 i is also exposed from the resin layer 6 on the same plane as the surface of the resin layer 6. For this reason, even if the height of the external connection terminal 7 of the upper semiconductor device 30 is low, the connection between the external connection terminal 8 of the semiconductor device 20 i and the external connection terminal 7 of the semiconductor device 30 can be secured.

  Therefore, if the semiconductor devices 20, 20i, 30 are stacked as described above and electrically connected to each other to form the stacked semiconductor device 40, the external connection terminal 7 can be lowered without impairing the connection stability. A higher density of the device is achieved.

  In the above description, the number of stacked semiconductor devices is three. However, the number is not limited to this, and may be two or four or more.

  In the above description, the semiconductor devices 20, 20i, and 30 are stacked. However, the semiconductor device 30 may be stacked on one or more semiconductor devices selected from the semiconductor devices 20 to 20j. Alternatively, a plurality of semiconductor devices selected from the semiconductor devices 20 to 20j may be stacked.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be used for manufacturing a semiconductor device.

It is sectional drawing which shows the structure of the semiconductor device concerning embodiment of this invention. FIG. 2 is a plan view showing the semiconductor device of FIG. 1 as viewed from above. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 1 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 2 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 3 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 4 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 5 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 6 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 7 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 8 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 9 concerning embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device of the modification 10 concerning embodiment of this invention. It is sectional drawing which shows the structure of the laminated semiconductor device concerning embodiment of this invention. It is sectional drawing which shows the state by which two conventional semiconductor devices were laminated | stacked. It is sectional drawing which shows the state by which two conventional semiconductor devices were laminated | stacked. It is sectional drawing which shows the resin sealing process in the manufacturing process of the conventional semiconductor device.

Explanation of symbols

1 Base substrate 3 Semiconductor chip 6 Resin layer 7 External connection terminal (second external connection terminal)
8 External connection terminal (first external connection terminal)
DESCRIPTION OF SYMBOLS 9 Wiring layer 11 Support body 12 Adhesive layer 14 Area | region provided with the external connection terminal 15 Area | regions other than the area | region provided with the external connection terminal 20-20j Semiconductor device 30 Semiconductor device 40 Multilayer type semiconductor device 50 Mold

Claims (3)

A base substrate; a semiconductor chip electrically connected to the base substrate; a resin layer covering at least a part of the semiconductor chip; and a first external connection terminal electrically connected to the base substrate. A method for manufacturing a semiconductor device comprising:
A semiconductor device comprising a sealing step of pressing a mold against the first external connection terminal to form a gap between the mold and the periphery of the first external connection terminal, and sealing resin into the gap. Manufacturing method. The encapsulation step is
Pressing the mold to flatten the surface of the first external connection terminal;
2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of encapsulating the resin so that the flattened first external connection terminal is exposed from the resin layer on the same surface as the surface of the resin layer. .   The method of manufacturing a semiconductor device according to claim 2, further comprising a heating step of applying heat below the melting point of the first external connection terminal to the mold.

Images