JP2015032697A - Electronic circuit module, and substrate for electronic circuit module - Google Patents

Electronic circuit module, and substrate for electronic circuit module Download PDF

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JP2015032697A
JP2015032697A JP2013161467A JP2013161467A JP2015032697A JP 2015032697 A JP2015032697 A JP 2015032697A JP 2013161467 A JP2013161467 A JP 2013161467A JP 2013161467 A JP2013161467 A JP 2013161467A JP 2015032697 A JP2015032697 A JP 2015032697A
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semiconductor chip
substrate
underfill material
electronic circuit
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広文 望月
Hirofumi Mochizuki
広文 望月
真吾 木田
Shingo Kida
真吾 木田
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FDK Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

PROBLEM TO BE SOLVED: To suppress generation of voids in an underfill material as much as possible, in a cavity structure electronic circuit module.SOLUTION: A substrate of an electronic component module has a cavity to which a semiconductor chip is attached, and the space between which and the substrate is filled with an underfill material after the semiconductor chip is mounted. The cavity has a region where a plurality of bumps for electrically connecting the semiconductor chip and a wiring pattern provided on the substrate are provided, and a region where the bumps are not provided. A step is provided on the substrate surface in the thickness direction thereof, in the region on the substrate surface constituting the cavity where there is no bump.

Description

本発明は、電子回路モジュール、及び電子回路モジュール用基板に関する。   The present invention relates to an electronic circuit module and an electronic circuit module substrate.

近年、スマートフォンを始めとする各種携帯端末が急速に普及するにつれ、小型化、高性能化への要求がよりいっそう強くなっている。この点から、携帯端末に内蔵されるマザーボード等のプリント配線板に取り付ける電子部品に対しても、高密度実装の観点から高集積化によるいっそうの小型化が求められている。高集積化を実現するために、プリント配線板に取り付ける電子部品はモジュール化されており、例えばＬＧＡ（Land Grid Array）型の基板上にＬＳＩ（Large Scale Integrated circuit）チップ等の半導体チップを実装して構成される電子回路モジュールが採用される。ＬＧＡ型基板の裏面には、マザーボード等の他のプリント配線板へ電気的に接続及び機械的に固着させるための複数の電極パッドが設けられている。   In recent years, as various portable terminals such as smartphones are rapidly spread, demands for miniaturization and high performance are further increased. In view of this, electronic components attached to a printed wiring board such as a mother board built in a portable terminal are required to be further downsized by high integration from the viewpoint of high-density mounting. In order to achieve high integration, the electronic components attached to the printed wiring board are modularized. For example, a semiconductor chip such as an LSI (Large Scale Integrated circuit) chip is mounted on an LGA (Land Grid Array) type substrate. An electronic circuit module configured as described above is employed. A plurality of electrode pads for electrical connection and mechanical fixation to other printed wiring boards such as a mother board are provided on the back surface of the LGA type substrate.

半導体チップは、基板の表面にそのまま平面実装されるか、あるいは基板に設けたキャビティ内に配置するキャビティ構造により実装される。平面実装、キャビティ構造いずれの場合でも、半導体チップと基板との間にはアンダーフィル材が充填される。例えばフリップチップ実装により基板へ一次実装された半導体チップは、外力、内部応力に対して脆弱であり、また周囲の温度、湿度の影響により劣化しがちである。このような問題を解決するために、半導体チップと基板との間の空隙をアンダーフィル材によって充填して補強するとともに、耐環境性を高める。   The semiconductor chip is mounted on the surface of the substrate as it is, or by a cavity structure disposed in a cavity provided on the substrate. In either case of planar mounting or cavity structure, an underfill material is filled between the semiconductor chip and the substrate. For example, a semiconductor chip primarily mounted on a substrate by flip chip mounting is vulnerable to external force and internal stress, and tends to deteriorate due to the influence of ambient temperature and humidity. In order to solve such a problem, the space between the semiconductor chip and the substrate is filled with an underfill material to be reinforced, and the environmental resistance is enhanced.

このアンダーフィル材の充填に関しては、平面実装の場合の例が、例えば特許文献１（特開平９−２８９２２７号公報）に開示されている。特許文献１は、ＩＣチップのパッド電極を回路基板のボンディングパッドにフリップチップボンディングし、封止樹脂で封止する半導体の実装構造に関する。   Regarding the filling of the underfill material, an example in the case of planar mounting is disclosed in, for example, Japanese Patent Application Laid-Open No. 9-289227. Patent Document 1 relates to a semiconductor mounting structure in which a pad electrode of an IC chip is flip-chip bonded to a bonding pad of a circuit board and sealed with a sealing resin.

特開平９−２８９２２７号公報JP-A-9-289227

特許文献１に例示されているような平面実装型の電子回路モジュールでは、半導体チップ下部へ充填したアンダーフィル材が半導体チップの外側へ押し出される様に充填されるため、充填されたアンダーフィル材の内部にボイドが残るリスクはかなり低かった。しかし、キャビティ構造の電子回路モジュールでは、平面実装型電子回路モジュールとの構成の相違に基づく問題がある。   In the electronic circuit module of the surface mounting type as exemplified in Patent Document 1, the underfill material filled in the lower part of the semiconductor chip is filled so as to be pushed out of the semiconductor chip. The risk of voids remaining inside was quite low. However, an electronic circuit module having a cavity structure has a problem based on a difference in configuration from a planar mounting type electronic circuit module.

図５に、キャビティ構造電子回路モジュール１の一般的な構成例を示す模式平面図を示している。電子回路モジュール１の多層基板１０の表面にはほぼ矩形の凹みであるキャビティ５０が設けられており、半導体チップ２０がバンプ７０を介して多層基板１０に取り付けられる際に、半導体チップ２０はキャビティ５０内に収められるようになっている。半導体チップ２０が多層基板１０に取り付けられた後、その取り付け部の補強、及び保護のために、キャビティ５０内にはアンダーフィル材が充填される。   FIG. 5 is a schematic plan view showing a general configuration example of the cavity structure electronic circuit module 1. A cavity 50 that is a substantially rectangular recess is provided on the surface of the multilayer substrate 10 of the electronic circuit module 1. When the semiconductor chip 20 is attached to the multilayer substrate 10 via the bumps 70, the semiconductor chip 20 It is designed to fit inside. After the semiconductor chip 20 is attached to the multilayer substrate 10, the cavity 50 is filled with an underfill material in order to reinforce and protect the attachment portion.

図６Ａ〜図６Ｃに、図５の一般的なキャビティ構造電子回路モジュール１においてアンダーフィル材を充填していく状況を示している。図６Ａにおいて、半導体チップ２０の下方から上方へ向けてアンダーフィル材６０を充填していく場合、アンダーフィル材６０は、バンプ７０が設けられている領域では、毛細管現象によって、半導体チップ２０と多層基板１０との間に迅速に浸透していく。しかし、その一方で、キャビティ５０中央部のバンプ７０が設けられていない領域では、バンプ７０が設けられている周囲の領域よりもアンダーフィル材６０の浸透が遅い。   FIGS. 6A to 6C show a state in which the underfill material is filled in the general cavity structure electronic circuit module 1 of FIG. 6A, when the underfill material 60 is filled from the bottom to the top of the semiconductor chip 20, the underfill material 60 has a multilayer structure with the semiconductor chip 20 due to capillary action in the region where the bumps 70 are provided. It quickly penetrates between the substrate 10. On the other hand, the penetration of the underfill material 60 is slower in the area where the bump 70 is not provided in the central portion of the cavity 50 than in the surrounding area where the bump 70 is provided.

図６Ａに示す状態からさらにアンダーフィル材６０を充填していくと、図６Ｂに例示するように、バンプ７０が設けられていない領域においても、キャビティ５０内の周囲の領域に続いてアンダーフィル材６０が遅れて充填されていく。
この際、図６Ｃに例示するように、キャビティ５０内の周囲部分にキャビティ５０の側壁を伝って先に浸透したアンダーフィル材６０が、中央寄りの充填が遅れている領域に取り残された空気を取り囲んで、ボイドＶがアンダーフィル材６０内に形成されてしまうことがある。言うまでもなく、ボイドＶが特にバンプ７０が配置されている領域に生じた場合には、アンダーフィル材６０による本来の補強、保護機能が発揮されないという不都合が生じる。特に、半導体チップ２０におけるバンプ７０の配置が複雑で、半導体チップ２０と多層基板１０との間で局部的にバンプ７０が設けられない領域が散在するような構成となる場合には、図５〜図６Ｃに例示した場合よりもボイドＶがより生じやすい。 When the underfill material 60 is further filled from the state shown in FIG. 6A, the underfill material continues to the surrounding region in the cavity 50 even in the region where the bump 70 is not provided, as illustrated in FIG. 6B. 60 is filled with a delay.
At this time, as illustrated in FIG. 6C, the underfill material 60 that has penetrated into the peripheral portion of the cavity 50 through the side wall of the cavity 50 first removes the air left in the region where the filling near the center is delayed. The void V may be formed in the underfill material 60 by surrounding. Needless to say, when the void V is generated particularly in the region where the bump 70 is disposed, the original reinforcement and protection functions by the underfill material 60 are not exhibited. In particular, when the arrangement of the bumps 70 in the semiconductor chip 20 is complicated and a region in which the bumps 70 are not locally provided between the semiconductor chip 20 and the multilayer substrate 10 is scattered, FIG. Voids V are more likely to occur than in the case illustrated in FIG. 6C.

本発明は、上記のような問題点を解決するためになされたもので、キャビティ構造モジュールにおいてアンダーフィル材内部にボイドが生じるのを可及的に抑制することを可能とする電子回路モジュール及び電子回路モジュール用基板を提供することを一つの目的としている。   The present invention has been made to solve the above-described problems, and an electronic circuit module and an electronic circuit that can suppress the occurrence of voids in the underfill material in the cavity structure module as much as possible. One object is to provide a circuit module substrate.

前記の、及び他の問題点を解決するために、本発明の一つの態様は、基板に取り付けた半導体チップ及び回路部品をパッケージに収装してなる電子部品モジュールであって、
前記基板は、前記半導体チップが取り付けられるキャビティ部であって、前記半導体チップの取り付け後、前記半導体チップと前記基板との間の空間にアンダーフィル材が充填されるキャビティ部を有し、
前記キャビティ部は、前記半導体チップと前記基板に設けられている配線パターンとを電気的に接続するための複数のバンプが設けられている領域であるバンプ領域と、前記バンプが設けられていない領域である非バンプ領域とを有し、
前記キャビティ部を構成する前記基板表面の、前記非バンプ領域に該当する部分には、前記基板表面にその厚み方向の段差が設けられている。
また、本発明の他の態様は、前記の電子回路モジュールに適用することができる電子回路モジュール用基板である。 In order to solve the above-mentioned and other problems, one aspect of the present invention is an electronic component module formed by housing a semiconductor chip and a circuit component attached to a substrate in a package.
The substrate is a cavity portion to which the semiconductor chip is attached, and has a cavity portion in which a space between the semiconductor chip and the substrate is filled with an underfill material after the semiconductor chip is attached.
The cavity portion includes a bump region which is a region where a plurality of bumps for electrically connecting the semiconductor chip and a wiring pattern provided on the substrate are provided, and a region where the bumps are not provided. And a non-bump area that is
A step corresponding to the non-bump region on the surface of the substrate constituting the cavity portion is provided with a step in the thickness direction on the substrate surface.
Moreover, the other aspect of this invention is a board | substrate for electronic circuit modules which can be applied to the said electronic circuit module.

本発明の一態様によれば、キャビティ構造電子回路モジュールにおいてアンダーフィル材内部にボイドが生じるのを可及的に抑制することを可能とし、また、ボイドが生じたとしても、選択的にバンプが設けられていない領域にボイドを発生させることにより、信頼性に優れた電子回路モジュール及び電子回路モジュール用基板を提供することができる。   According to one aspect of the present invention, it is possible to suppress the occurrence of voids in the underfill material in the cavity structure electronic circuit module as much as possible, and even if voids are generated, bumps are selectively formed. By generating a void in a region where the circuit is not provided, an electronic circuit module and an electronic circuit module substrate having excellent reliability can be provided.

図１は、本発明の一実施形態に係る電子回路モジュール１の構成を例示する模式断面図である。FIG. 1 is a schematic cross-sectional view illustrating the configuration of an electronic circuit module 1 according to an embodiment of the invention. 図２Ａは、図１の電子回路モジュール１の半導体チップ２０取付け側から見た模式平面図である。2A is a schematic plan view of the electronic circuit module 1 of FIG. 1 viewed from the side where the semiconductor chip 20 is attached. 図２Ｂは、図２ＡのIII−III断面で見た電子回路モジュール１の模式断面図である。FIG. 2B is a schematic cross-sectional view of the electronic circuit module 1 as seen in the III-III cross section of FIG. 2A. 図３Ａは、図１の電子回路モジュール１において、半導体チップ２０と多層基板１０との間にアンダーフィル材６０を充填している状態を例示する模式平面図である。FIG. 3A is a schematic plan view illustrating a state in which the underfill material 60 is filled between the semiconductor chip 20 and the multilayer substrate 10 in the electronic circuit module 1 of FIG. 図３Ｂは、図１の電子回路モジュール１において、半導体チップ２０と多層基板１０との間にアンダーフィル材６０を充填している状態を例示する模式平面図である。FIG. 3B is a schematic plan view illustrating a state in which the underfill material 60 is filled between the semiconductor chip 20 and the multilayer substrate 10 in the electronic circuit module 1 of FIG. 1. 図３Ｃは、図１の電子回路モジュール１において、半導体チップ２０と多層基板１０との間にアンダーフィル材６０を充填し終わった状態を例示する模式平面図である。3C is a schematic plan view illustrating a state in which the underfill material 60 has been filled between the semiconductor chip 20 and the multilayer substrate 10 in the electronic circuit module 1 of FIG. 図４Ａは、図１の電子回路モジュール１の変形例において、半導体チップ２０と基板１０との間にアンダーフィル材６０を充填している状態を例示する模式説明図である。FIG. 4A is a schematic explanatory view illustrating a state in which the underfill material 60 is filled between the semiconductor chip 20 and the substrate 10 in the modification of the electronic circuit module 1 of FIG. 図４Ｂは、図４Ａの電子回路モジュール１の模式断面図である。4B is a schematic cross-sectional view of the electronic circuit module 1 of FIG. 4A. 図５は、一般的なキャビティ構造電子回路モジュール１の半導体チップ２０取付け側から見た模式平面図である。FIG. 5 is a schematic plan view of a general cavity structure electronic circuit module 1 as viewed from the semiconductor chip 20 mounting side. 図６Ａは、図５の電子回路モジュール１において、半導体チップ２０と多層基板１０との間にアンダーフィル材６０を充填している状態を例示する模式平面図である。FIG. 6A is a schematic plan view illustrating a state in which the underfill material 60 is filled between the semiconductor chip 20 and the multilayer substrate 10 in the electronic circuit module 1 of FIG. 図６Ｂは、図５の電子回路モジュール１において、半導体チップ２０と多層基板１０との間にアンダーフィル材６０を充填している状態を例示する模式平面図である。FIG. 6B is a schematic plan view illustrating a state in which the underfill material 60 is filled between the semiconductor chip 20 and the multilayer substrate 10 in the electronic circuit module 1 of FIG. 図６Ｃは、図５の電子回路モジュール１において、半導体チップ２０と多層基板１０との間にアンダーフィル材６０を充填し終わった状態を例示する模式平面図である。6C is a schematic plan view illustrating a state in which the underfill material 60 has been filled between the semiconductor chip 20 and the multilayer substrate 10 in the electronic circuit module 1 of FIG.

次に、本発明の一実施形態について、添付図面を参照して説明する。図１に、本発明の一実施形態に係る電子回路モジュール１の模式断面図を示している。電子回路モジュール１は、ガラスエポキシ樹脂等の材料で形成されている多層基板１０を備える。多層基板１０の一方の表面には種々の電子部品３０が回路パターン４０に面付けされるとともに、パッケージ１５によって封止されている。多層基板１０の他方の表面にはキャビティ５０（キャビティ部）が設けられるとともに、そのキャビティ５０内に配置された半導体チップ２０がハンダボール等のバンプ７０によって多層基板１０に機械的に取り付けられるとともに、回路パターン４０と電気的に接続されている。キャビティ５０内において、半導体チップ２０と多層基板１０との間には、アンダーフィル材６０が充填されている。なお、図１に示す電子回路モジュール１の構成は例示であって、本発明がこのような特定の構成に限定され得ることを意図していない。   Next, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional view of an electronic circuit module 1 according to an embodiment of the present invention. The electronic circuit module 1 includes a multilayer substrate 10 formed of a material such as glass epoxy resin. Various electronic components 30 are applied to the circuit pattern 40 on one surface of the multilayer substrate 10 and are sealed by the package 15. A cavity 50 (cavity portion) is provided on the other surface of the multilayer substrate 10, and the semiconductor chip 20 disposed in the cavity 50 is mechanically attached to the multilayer substrate 10 by bumps 70 such as solder balls, The circuit pattern 40 is electrically connected. In the cavity 50, an underfill material 60 is filled between the semiconductor chip 20 and the multilayer substrate 10. The configuration of the electronic circuit module 1 shown in FIG. 1 is an exemplification, and it is not intended that the present invention be limited to such a specific configuration.

図２Ａに、図１の電子回路モジュール１を半導体チップ２０の取付け側から見た模式平面図を、図２Ｂに、図２Ａの電子回路モジュール１のIII−III矢視模式断面図を示している。図２Ａ、図２Ｂに例示している電子回路モジュール１は、基本的に図５に関して説明した一般的なキャビティ構造電子回路モジュール１と同様の構成を有しているが、バンプ７０が設けられていない領域（非バンプ領域）であるキャビティ５０の中央付近に、ほぼ矩形の輪郭を有する凹部５５が設けられている構成が異なる。   2A is a schematic plan view of the electronic circuit module 1 of FIG. 1 viewed from the mounting side of the semiconductor chip 20, and FIG. 2B is a schematic cross-sectional view of the electronic circuit module 1 of FIG. . The electronic circuit module 1 illustrated in FIGS. 2A and 2B basically has the same configuration as the general cavity structure electronic circuit module 1 described with reference to FIG. 5, but is provided with bumps 70. The configuration is different in that a recess 55 having a substantially rectangular outline is provided in the vicinity of the center of the cavity 50 which is a non-bumped region (non-bump region).

既存の一般的なキャビティ構造電子回路モジュール１に関して前記したように、アンダーフィル材６０が毛細管現象で半導体チップ２０と多層基板１０との間に浸透していくことは一般的に知られており、アンダーフィル材６０は、半導体チップ２０のバンプ７０などを伝って半導体チップ２０と多層基板１０との間に浸透していく。しかし、前記のように、半導体チップ２０の回路設計によっては、半導体チップ２０の裏面側のバンプ７０の配置が変則的になる場合があり、バンプ７０のある領域（バンプ領域）ではアンダーフィル材６０が速く浸透していくが、バンプ７０のない領域ではこれに比較してアンダーフィル材６０の浸透が遅れる現象を生じる。そして、その浸透速度差によって浸透が遅い領域にある空気がアンダーフィル材６０によって取り囲まれてボイドＶとなる。   As described above with respect to the existing general cavity structure electronic circuit module 1, it is generally known that the underfill material 60 penetrates between the semiconductor chip 20 and the multilayer substrate 10 by capillary action. The underfill material 60 penetrates between the semiconductor chip 20 and the multilayer substrate 10 through the bumps 70 and the like of the semiconductor chip 20. However, as described above, depending on the circuit design of the semiconductor chip 20, the arrangement of the bumps 70 on the back surface side of the semiconductor chip 20 may become irregular, and the underfill material 60 is present in a region where the bumps 70 are present (bump region). However, in the region where there is no bump 70, the penetration of the underfill material 60 is delayed as compared with this. Then, air in a region where the permeation is slow due to the permeation speed difference is surrounded by the underfill material 60 and becomes a void V.

キャビティ５０の底面に設けられている凹部５５は、半導体チップ２０と多層基板１０との間を浸透していくアンダーフィル材６０に対して、バンプ７０と同様の、毛細管現象を促す段差を有する部分として作用する。キャビティ５０の底面部に凹部５５による段差を設けることで、凹部５５の縁を廻り込む様にアンダーフィル材６０が浸透し、バンプ７０が配置されている領域との充填状態の差が抑制される。   The concave portion 55 provided on the bottom surface of the cavity 50 is a portion having a step for promoting capillary action similar to the bump 70 with respect to the underfill material 60 penetrating between the semiconductor chip 20 and the multilayer substrate 10. Acts as By providing a step due to the recess 55 on the bottom surface of the cavity 50, the underfill material 60 penetrates so as to go around the edge of the recess 55, and the difference in filling state from the region where the bump 70 is disposed is suppressed. .

図３Ａ〜図３Ｃに、図２Ａ、図２Ｂに例示する本実施形態の電子回路モジュール１において、アンダーフィル材６０を充填していく模様を模式的に示している。各図において、アンダーフィル材６０は、半導体チップ２０の下方から充填されるものとする。まず、図３Ａに示すように、半導体チップ２０と多層基板１０との間に充填されるアンダーフィル材６０は、毛細管現象によって、バンプ７０が設けられている領域において、もっとも早く浸透する。次いで、図３Ｂに示すように、アンダーフィル材６０が凹部５５の下端に到達すると、アンダーフィル材６０は、凹部５５の両下端から上方へ延びる段差に沿って速度を速めつつ浸透していき、バンプ７０が設けられている領域との浸透速度差が縮小されるとともに、バンプ７０設置領域とそうでない領域（凹部５５が設けられている領域）との間でのアンダーフィル材６０の浸透状態の差が軽減される。その結果、バンプ７０の設置領域からのアンダーフォル材６０の廻り込みによるボイドＶの発生が抑制される（図３Ｃ）。   3A to 3C schematically show a pattern in which the underfill material 60 is filled in the electronic circuit module 1 of this embodiment illustrated in FIGS. 2A and 2B. In each drawing, the underfill material 60 is filled from below the semiconductor chip 20. First, as shown in FIG. 3A, the underfill material 60 filled between the semiconductor chip 20 and the multilayer substrate 10 penetrates the earliest in the region where the bumps 70 are provided by capillary action. Next, as shown in FIG. 3B, when the underfill material 60 reaches the lower end of the recess 55, the underfill material 60 penetrates while increasing the speed along the steps extending upward from both lower ends of the recess 55, The difference in permeation speed between the region where the bump 70 is provided is reduced, and the state of penetration of the underfill material 60 between the region where the bump 70 is installed and the region where the bump 70 is not provided (the region where the recess 55 is provided). The difference is reduced. As a result, the generation of the void V due to the under-forming material 60 wrapping around from the installation area of the bump 70 is suppressed (FIG. 3C).

なお、多層基板１０のキャビティ５０の底面部に凹部５５による段差を設けることで、凹部５５の縁を廻り込みつつアンダーフィル材６０が浸透するように構成しているため、凹部５５の周囲の段差にボイドＶが形成されるおそれはあるが、半導体チップ２０のバンプ７０設置領域におけるボイドＶの発生は防止することが可能であるので、電子回路モジュール製品としての信頼性に影響を及ぼすことはない。   In addition, since the underfill material 60 permeates around the edge of the recess 55 by providing a step due to the recess 55 on the bottom surface of the cavity 50 of the multilayer substrate 10, the step around the recess 55. However, since it is possible to prevent the generation of the void V in the bump 70 installation region of the semiconductor chip 20, the reliability as an electronic circuit module product is not affected. .

以上説明した本実施形態によれば、多層基板１０のキャビティ５０に設けられた凹部５５による段差により、半導体チップ２０と多層基板１０との間におけるアンダーフィル材６０の浸透速度差を抑制し、バンプ７０の領域においてボイドＶのないアンダーフィル材６０の充填が可能となる。また、半導体チップ２０のバンプ７０の配置に、アンダーフィル材６０の浸透の影響を考慮する必要がなくなるため、半導体チップ２０の設計の自由度が向上することにもつながる。   According to the present embodiment described above, the difference in the penetration rate of the underfill material 60 between the semiconductor chip 20 and the multilayer substrate 10 is suppressed by the step due to the concave portion 55 provided in the cavity 50 of the multilayer substrate 10, and the bump It is possible to fill the underfill material 60 without the void V in the area 70. In addition, since it is not necessary to consider the influence of penetration of the underfill material 60 in the arrangement of the bumps 70 of the semiconductor chip 20, the degree of freedom in designing the semiconductor chip 20 is also improved.

次に、以上説明した本実施形態の変形例について説明する。図４Ａ、図４Ｂに、当該変形例に係る電子回路モジュールのキャビティ５０の周辺を模式的に示す平面図、及び断面図をそれぞれ示している。前記の実施形態と同様に、図４Ａ、図４Ｂの変形例においても、キャビティ５０の底面に凹部５５が設けられているが、凹部５５の形状が矩形の平坦な凹みではなく、矩形を形成する細幅の溝として形成されている点が異なる。図４Ａに模式的に矢印で示しているように、半導体チップ２０の上方から浸透していくアンダーフィル材６０は、凹部５５の縁に沿ってバンプ７０設置領域と同等の速度で浸透していくため、バンプ７０の設置領域におけるボイドＶの発生はやはり効果的に抑制される。   Next, a modified example of the present embodiment described above will be described. 4A and 4B are respectively a plan view and a cross-sectional view schematically showing the periphery of the cavity 50 of the electronic circuit module according to the modification. 4A and 4B, the recesses 55 are provided on the bottom surface of the cavity 50, but the shape of the recesses 55 is not a rectangular flat recess but a rectangle. The difference is that it is formed as a narrow groove. As schematically indicated by arrows in FIG. 4A, the underfill material 60 that permeates from above the semiconductor chip 20 permeates along the edge of the recess 55 at the same speed as the bump 70 installation region. Therefore, the generation of the void V in the installation area of the bump 70 is also effectively suppressed.

なお、以上説明したアンダーフィル材６０の浸透を促進する段差部は、凹部５５としての構成に限定されるものではない。例えば、アンダーフィル材６０の浸透方向に沿った一ないし複数の筋状の溝を設けてもよいし、あるいはそれを溝でなく一ないし複数の凸条として形成してもよい。要するに、キャビティ５０に、バンプ７０が設置されない領域においてアンダーフィル材６０の浸透を促進する効果を発揮する構成の段差を設ければよく、このような段差の構成は、以上例示した構成以外にも、実験等を通じて種々考えられるものである。   Note that the stepped portion that promotes the penetration of the underfill material 60 described above is not limited to the configuration as the recessed portion 55. For example, one or a plurality of streak-like grooves along the penetration direction of the underfill material 60 may be provided, or it may be formed as one or a plurality of ridges instead of a groove. In short, it is only necessary to provide the cavity 50 with a step having a configuration that exhibits the effect of promoting the penetration of the underfill material 60 in a region where the bump 70 is not installed. The configuration of such a step is not limited to the configuration exemplified above. Various things can be considered through experiments.

１ 電子回路モジュール １０ 多層基板 １５ パッケージ
２０ 半導体チップ ３０ 電子部品 ４０ 回路パターン
５０ キャビティ ５５ 凹部 ６０ アンダーフィル材
７０ バンプ Ｖ ボイド DESCRIPTION OF SYMBOLS 1 Electronic circuit module 10 Multilayer substrate 15 Package 20 Semiconductor chip 30 Electronic component 40 Circuit pattern 50 Cavity 55 Recessed part 60 Underfill material 70 Bump V Void

Claims (4)

基板に取り付けた半導体チップ及び回路部品をパッケージに収装してなる電子部品モジュールであって、
前記基板は、前記半導体チップが取り付けられるキャビティ部であって、前記半導体チップの取り付け後、前記半導体チップと前記基板との間の空間にアンダーフィル材が充填されるキャビティ部を有し、
前記キャビティ部は、前記半導体チップと前記基板に設けられている配線パターンとを電気的に接続するための複数のバンプが設けられている領域であるバンプ領域と、前記バンプが設けられていない領域である非バンプ領域とを有し、
前記キャビティ部を構成する前記基板表面の、前記非バンプ領域に該当する部分には、前記基板表面にその厚み方向の段差が設けられている、
電子部品モジュール。 An electronic component module in which a semiconductor chip and a circuit component attached to a substrate are accommodated in a package,
The substrate is a cavity portion to which the semiconductor chip is attached, and has a cavity portion in which a space between the semiconductor chip and the substrate is filled with an underfill material after the semiconductor chip is attached.
The cavity portion includes a bump region which is a region where a plurality of bumps for electrically connecting the semiconductor chip and a wiring pattern provided on the substrate are provided, and a region where the bumps are not provided. And a non-bump area that is
A step corresponding to the non-bump region of the substrate surface constituting the cavity portion is provided with a step in the thickness direction on the substrate surface.
Electronic component module. 請求項１に記載の電子部品モジュールであって、前記段差は、前記基板表面に設けられる凸部又は凹部によって形成される、電子部品モジュール。   The electronic component module according to claim 1, wherein the step is formed by a convex portion or a concave portion provided on the surface of the substrate. 請求項１に記載の電子部品モジュールであって、前記段差は、前記アンダーフィル材の充填方向と並行に設けられる少なくとも１本の溝又は凸条で構成されている、電子部品モジュール。   2. The electronic component module according to claim 1, wherein the step is configured by at least one groove or protrusion provided in parallel with the filling direction of the underfill material. 請求項１に記載の電子部品モジュールに用いられる電子部品モジュール用基板であって、
半導体チップが取り付けられるキャビティ部であって、前記半導体チップの取り付け後、前記半導体チップと前記電子部品モジュール用基板との間の空間にアンダーフィル材が充填されるキャビティ部を有し、
前記キャビティ部は、前記半導体チップと前記電子部品モジュール用基板に設けられている配線パターンとを電気的に接続するための複数のバンプが設けられている領域であるバンプ領域と、前記バンプが設けられていない領域である非バンプ領域とを有し、
前記キャビティ部を構成する前記電子部品モジュール用基板表面の、前記非バンプ領域に該当する部分には、前記電子部品モジュール用基板表面にその厚み方向の段差が設けられている、電子部品モジュール用基板。 An electronic component module substrate used in the electronic component module according to claim 1,
A cavity part to which a semiconductor chip is attached, the cavity part being filled with an underfill material in a space between the semiconductor chip and the electronic component module substrate after the semiconductor chip is attached;
The cavity portion includes a bump region which is a region where a plurality of bumps for electrically connecting the semiconductor chip and a wiring pattern provided on the electronic component module substrate are provided, and the bump is provided. A non-bump area that is an unfinished area,
The electronic component module substrate, wherein a step corresponding to the non-bump region of the electronic component module substrate surface constituting the cavity portion is provided with a step in the thickness direction on the electronic component module substrate surface. .
JP2013161467A 2013-08-02 2013-08-02 Electronic circuit module, and substrate for electronic circuit module Pending JP2015032697A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109416839A (en) * 2016-07-04 2019-03-01 富士胶片株式会社 Image processing apparatus, image processing method, program and recording medium
WO2021192715A1 (en) * 2020-03-23 2021-09-30 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device, and manufacturing method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109416839A (en) * 2016-07-04 2019-03-01 富士胶片株式会社 Image processing apparatus, image processing method, program and recording medium
CN109416839B (en) * 2016-07-04 2023-06-16 富士胶片株式会社 Image processing apparatus, image processing method, and recording medium
WO2021192715A1 (en) * 2020-03-23 2021-09-30 ソニーセミコンダクタソリューションズ株式会社 Semiconductor device, and manufacturing method therefor

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