JP2005235997A - Printed board, electronic circuit substrate, and its manufacturing method - Google Patents

Printed board, electronic circuit substrate, and its manufacturing method Download PDF

Info

Publication number
JP2005235997A
JP2005235997A JP2004042791A JP2004042791A JP2005235997A JP 2005235997 A JP2005235997 A JP 2005235997A JP 2004042791 A JP2004042791 A JP 2004042791A JP 2004042791 A JP2004042791 A JP 2004042791A JP 2005235997 A JP2005235997 A JP 2005235997A
Authority
JP
Japan
Prior art keywords
circuit board
printed circuit
semiconductor element
wiring pattern
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004042791A
Other languages
Japanese (ja)
Inventor
Toshihiro Matsunaga
俊宏 松永
Yasumi Kamigai
康己 上貝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2004042791A priority Critical patent/JP2005235997A/en
Publication of JP2005235997A publication Critical patent/JP2005235997A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed board and an electronic circuit board having electronic components mounted thereon which relaxes stresses caused in the electronic components or connecting points when a bending stress is applied to the printed board. <P>SOLUTION: The electronic circuit board mounts a semiconductor element 2 on a printed board 1 having a specified wiring pattern not shown. The semiconductor element 2 is electrically connected to the specified region of the wiring pattern with a solder connection part 3. The printed board 1 has recessed trenches 4 opened on the surface having the wiring pattern formed thereon in the vicinity of a wiring pattern region connectable with the semiconductor element 2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、プリント基板、電子回路基板及びその製造方法に係る発明であって、特に、実装される電子部品及びその接続部に加わる応力を緩和することができるプリント基板、電子回路基板及びその製造方法に関するものである。   The present invention relates to a printed circuit board, an electronic circuit board, and a manufacturing method thereof, and in particular, a printed circuit board, an electronic circuit board, and a manufacturing method thereof that can relieve stress applied to an electronic component to be mounted and its connecting portion. It is about the method.

近年、半導体装置などの電子回路基板の小型化及び軽量化への要求が高まるにつれて、半導体素子等の電子部品が実装されるプリント基板も小型化及び軽量化の要求が高まっている。特に、プリント基板全体の薄板化が進んでいる。   In recent years, as the demand for miniaturization and weight reduction of electronic circuit boards such as semiconductor devices has increased, the demand for miniaturization and weight reduction of printed boards on which electronic components such as semiconductor elements are mounted has also increased. In particular, the entire printed circuit board is being made thinner.

また、小型化及び軽量化した電子回路基板は、様々な状況で使用される用途が増えるため、従来の電子回路基板に比べ耐久性等が要求されることになる。例えば、ＩＣカードやＩＣタグのように厚みの薄い携帯用の電子回路基板は、ポケットに収納される等の際に折り曲げ力が働くことにより、内蔵されるプリント基板が折り曲げられることになる。   Moreover, since the electronic circuit board reduced in size and weight is used in various situations, durability and the like are required as compared with the conventional electronic circuit board. For example, a portable electronic circuit board having a small thickness, such as an IC card or an IC tag, is bent by a bending force when it is stored in a pocket.

このようにプリント基板が折り曲げられると、半田付け部分や、実装されている半導体素子等の電子部品に曲げ応力が作用する。実装されている半導体素子は、樹脂パッケージに封入されていても外部からの応力に弱く、折り曲げられることにより半導体素子の割れや接続部の断線といった事態を発生し、回路不良となることがあった。   When the printed circuit board is bent in this way, bending stress acts on the soldered portion and the electronic components such as the mounted semiconductor element. Even if the mounted semiconductor element is sealed in a resin package, it is vulnerable to external stress, and when it is bent, the semiconductor element may be broken or the connection part may be broken, resulting in a circuit failure. .

そこで、特許文献１に記載されている電子回路基板には、配線パターンが設けられたプリント基板上の半導体素子が搭載される領域の外側に、複数個の貫通孔を設けている。この貫通孔によってプリント基板の剛性が低下することになり、プリント基板に加えられた曲げ応力によって発生する半導体素子や接続部に生じる応力を緩和することができる。その結果、特許文献１に記載の電子回路基板においては、半導体素子の割れや接続部の断線の発生を低減することができる。   Therefore, in the electronic circuit board described in Patent Document 1, a plurality of through holes are provided outside a region on which a semiconductor element is mounted on a printed board on which a wiring pattern is provided. This through-hole reduces the rigidity of the printed circuit board, and can relieve the stress generated in the semiconductor elements and connection portions generated by the bending stress applied to the printed circuit board. As a result, in the electronic circuit board described in Patent Document 1, it is possible to reduce the occurrence of cracking of the semiconductor element and disconnection of the connection portion.

特開２０００−８２８６８号公報（第３−４頁、第１−３図）JP 2000-82868 (page 3-4, Fig. 1-3)

しかし、電子回路基板の小型化及び軽量化に伴い、プリント基板全体の薄板化も進んでいるため、プリント基板の強度は低下している。また、特許文献１ではプリント基板に複数の貫通孔を設けることにより、半導体素子や接続部に生じる応力を緩和することはできるが、貫通孔を設けたことにより、プリント基板の強度をさらに低下させることになる。プリント基板の強度が低下することにより、外力がプリント基板に加わると、プリント基板上の配線パターンが断線したり、プリント基板自体が破損したりする可能性が高まる問題があった。   However, as the electronic circuit board becomes smaller and lighter, the entire printed board is also made thinner, and the strength of the printed board is reduced. Further, in Patent Document 1, by providing a plurality of through holes in the printed circuit board, it is possible to relieve stress generated in the semiconductor element and the connection portion, but by providing the through holes, the strength of the printed circuit board is further reduced. It will be. When the strength of the printed circuit board is reduced, when an external force is applied to the printed circuit board, the wiring pattern on the printed circuit board may be disconnected or the printed circuit board itself may be damaged.

そこで、本発明は、プリント基板に曲げ応力が加わった場合に、電子部品や接続部に生じる応力を緩和するプリント基板や、これに電子部品を載置した電子回路基板を提供することを第１の目的とする。また、本発明は、電子部品や接続部に生じる応力を緩和しつつ、十分な強度を維持することができるプリント基板、電子回路基板及びその製造方法を提供することを第２の目的とする。   SUMMARY OF THE INVENTION Accordingly, the present invention provides a printed circuit board that relieves stress generated in an electronic component and a connection portion when bending stress is applied to the printed circuit board, and an electronic circuit board on which the electronic component is mounted. The purpose. A second object of the present invention is to provide a printed circuit board, an electronic circuit board, and a manufacturing method thereof that can maintain sufficient strength while relieving stress generated in electronic components and connection parts.

本発明に係る解決手段は、電子部品を載置可能であって、電子部品と接続可能な領域を含む配線パターンと、領域の近傍で、配線パターンが設けられた面に開口する凹形状の第１の溝とを備える。   According to the present invention, there is provided a wiring pattern including a region on which an electronic component can be placed and which can be connected to the electronic component, and a concave shape that opens in the vicinity of the region on the surface on which the wiring pattern is provided. 1 groove.

本発明に記載のプリント基板は、電子部品を載置可能であって、電子部品と接続可能な領域を含む配線パターンと、領域の近傍で、配線パターンが設けられた面に開口する凹形状の第１の溝とを備えるので、電子部品や接続部で発生する応力を緩和することができる効果がある。   The printed circuit board according to the present invention is capable of mounting electronic components, and includes a wiring pattern including a region connectable to the electronic component, and a concave shape opening in a surface provided with the wiring pattern in the vicinity of the region. Since the first groove is provided, there is an effect that stress generated in the electronic component or the connection portion can be relaxed.

（実施の形態１）
図１に、本実施の形態に係る電子回路基板の断面図を示す。図１に示す電子回路基板では、所定の配線パターンが形成されたプリント基板１上に電子部品である半導体素子２が搭載されている。配線パターンは図示しないが、半導体素子２は、配線パターンの所定の領域でこれと電気的に接続されている。図１に示す電子回路基板では、半導体素子２が小さく丸めた半田材料である半田接続部３により配線パターンと接続している（以下、この接続をＢＧＡ（Ball Grid Array）接続ともいう）。なお、半導体素子２と配線パターンとの接続はＢＧＡ接続に限られず、他の接続方式であっても良い。また、図１に示す電子回路基板では、プリント基板１上に半導体素子２を搭載しているが、半導体素子２に代えて受動部品等の電子部品をプリント基板１上に搭載しても良い。以下の他の実施の形態であっても同じである。 (Embodiment 1)
FIG. 1 shows a cross-sectional view of an electronic circuit board according to the present embodiment. In the electronic circuit board shown in FIG. 1, a semiconductor element 2 as an electronic component is mounted on a printed board 1 on which a predetermined wiring pattern is formed. Although a wiring pattern is not shown, the semiconductor element 2 is electrically connected to a predetermined region of the wiring pattern. In the electronic circuit board shown in FIG. 1, the semiconductor element 2 is connected to the wiring pattern by a solder connection portion 3 which is a small round solder material (hereinafter, this connection is also referred to as BGA (Ball Grid Array) connection). The connection between the semiconductor element 2 and the wiring pattern is not limited to the BGA connection, and other connection methods may be used. In the electronic circuit board shown in FIG. 1, the semiconductor element 2 is mounted on the printed board 1, but an electronic component such as a passive component may be mounted on the printed board 1 instead of the semiconductor element 2. The same applies to other embodiments described below.

本実施の形態に係る電子回路基板では、半導体素子２と接続可能な配線パターンの領域の近傍で、配線パターンが設けられた面に開口する凹形状の溝４が形成されている。図１に示す電子回路基板では、半導体素子２の左右に溝４が形成されている様子が図示されている。溝４が設けられる位置は、半導体素子２が搭載される側のプリント基板１の面であって、半導体素子２が搭載される領域より外側の所定の位置となる。このような溝４が設けられることで、図１に示すような外力Ｆ１が、プリント基板１に加えられた場合でも、半導体素子２や半田接続部３に生じる応力を緩和することができる。   In the electronic circuit board according to the present embodiment, in the vicinity of the area of the wiring pattern that can be connected to the semiconductor element 2, the concave groove 4 that is opened on the surface provided with the wiring pattern is formed. In the electronic circuit board shown in FIG. 1, a state in which grooves 4 are formed on the left and right sides of the semiconductor element 2 is illustrated. The position where the groove 4 is provided is the surface of the printed circuit board 1 on the side where the semiconductor element 2 is mounted, and is a predetermined position outside the region where the semiconductor element 2 is mounted. By providing such a groove 4, even when an external force F <b> 1 as shown in FIG. 1 is applied to the printed circuit board 1, stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed.

より詳しく説明すると、電子回路基板を曲げたり、落としたりすることで、プリント基板１に図１に示すような外力Ｆ１が加わることがある。溝４が設けられていない場合、外力Ｆ１がプリント基板１に加えられると、半導体素子２の直下のプリント基板１も湾曲し、半導体素子２や半田接続部３に応力が発生することになる。半導体素子２や半田接続部３に発生する応力により、半導体素子２が破損したり、半田接続部３に断線が生じたりする場合があった。   More specifically, an external force F1 as shown in FIG. 1 may be applied to the printed circuit board 1 by bending or dropping the electronic circuit board. When the groove 4 is not provided, when the external force F1 is applied to the printed circuit board 1, the printed circuit board 1 immediately below the semiconductor element 2 is also curved, and stress is generated in the semiconductor element 2 and the solder connection portion 3. In some cases, the semiconductor element 2 may be damaged or the solder connection part 3 may be disconnected due to the stress generated in the semiconductor element 2 or the solder connection part 3.

本実施の形態では、溝４をプリント基板１上に設けることで、半導体素子２や半田接続部３に生じる応力を緩和している。この溝４の形状は、緩和させる応力の大きさ、プリント基板の強度、プリント基板上の配線パターン等を考慮して個別に決定される。また、溝４のプリント基板上の位置も、半導体素子２と接続可能な配線パターンの領域の近傍で、配線パターンが設けられた面に開口する条件を満たす範囲内であれば、緩和させる応力の大きさ等の条件を考慮して個別に決定される。   In the present embodiment, by providing the groove 4 on the printed circuit board 1, stress generated in the semiconductor element 2 and the solder connection portion 3 is relaxed. The shape of the groove 4 is individually determined in consideration of the magnitude of stress to be relaxed, the strength of the printed board, the wiring pattern on the printed board, and the like. Further, if the position of the groove 4 on the printed circuit board is within the range of the area of the wiring pattern that can be connected to the semiconductor element 2 and satisfies the condition for opening on the surface on which the wiring pattern is provided, the stress to be relieved is reduced. It is determined individually in consideration of conditions such as size.

以上のように、本実施の形態に係るプリント基板１は、電子部品である半導体素子２を載置可能であって、半導体素子２と接続可能な領域を含む配線パターンと、領域の近傍で、配線パターンが設けられた面に開口する凹形状の溝４とを備えるので、電子部品である半導体素子２や半田接続部３で発生する応力を緩和することができる。また、本実施の形態に係る電子回路基板は、本実施の形態に係るプリント基板１と、領域に接続された電子部品である半導体素子２とを備えるので、電子部品である半導体素子２や半田接続部３で発生する応力を緩和することができる。   As described above, the printed circuit board 1 according to the present embodiment is capable of mounting the semiconductor element 2 that is an electronic component and includes a wiring pattern including a region connectable to the semiconductor element 2 and the vicinity of the region. Since the concave groove 4 opened on the surface on which the wiring pattern is provided is provided, stress generated in the semiconductor element 2 and the solder connection portion 3 which are electronic components can be relieved. Moreover, since the electronic circuit board according to the present embodiment includes the printed circuit board 1 according to the present embodiment and the semiconductor element 2 that is an electronic component connected to the region, the semiconductor element 2 that is an electronic component or solder The stress generated at the connection part 3 can be relaxed.

（変形例）
図１に示すようにプリント基板１上に溝４を設けることで、溝４を設けない場合に比べて、プリント基板の強度は低下することになる。プリント基板の強度が低下すると、プリント基板１上の配線パターンが断線したり、プリント基板１自体が破損したりする可能性が高くなる。そこで、本変形例では、図１に示すプリント基板１の溝４に封止材５を詰め込むことで、プリント基板１の強度を補強する。図２に、溝４に封止材５を詰め込んだ本変形例に係る電子回路基板の断面図を示す。なお、図２では、溝４の全てに封止材５が充填されているが、本発明では、プリント基板１の強度を補強することができる程度に、封止材５が溝４に詰め込まれてさえすれば良い。 (Modification)
As shown in FIG. 1, by providing the groove 4 on the printed circuit board 1, the strength of the printed circuit board is reduced as compared with the case where the groove 4 is not provided. When the strength of the printed circuit board decreases, there is a high possibility that the wiring pattern on the printed circuit board 1 is disconnected or the printed circuit board 1 itself is damaged. Therefore, in this modification, the strength of the printed circuit board 1 is reinforced by filling the sealing material 5 in the groove 4 of the printed circuit board 1 shown in FIG. FIG. 2 shows a cross-sectional view of an electronic circuit board according to this modification in which the sealing material 5 is packed in the groove 4. In FIG. 2, all of the grooves 4 are filled with the sealing material 5, but in the present invention, the sealing materials 5 are packed into the grooves 4 to such an extent that the strength of the printed circuit board 1 can be reinforced. All you need to do is

溝４に詰め込む封止材５は、プリント基板１の曲げ弾性率より低い樹脂を使用する。例えば、ポリアミド、ＡＢＳ樹脂、ポリスチレン等が封止材５に用いられる。溝４に封止材５を詰め込んだ場合であっても、半導体素子２や半田接続部３に生じる応力を緩和することができる。つまり、図１に示すような外力Ｆ１が図２に示すプリント基板１に加えられても、プリント基板１の曲げに封止材５が追従するため、半導体素子２の直下のプリント基板１は湾曲しない。よって、図２に示す電子回路基板であっても、半導体素子２や半田接続部３で発生する応力を緩和することができる。   As the sealing material 5 packed in the groove 4, a resin having a lower bending elastic modulus than that of the printed circuit board 1 is used. For example, polyamide, ABS resin, polystyrene, or the like is used for the sealing material 5. Even when the sealing material 5 is packed in the groove 4, the stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed. That is, even when an external force F1 as shown in FIG. 1 is applied to the printed circuit board 1 shown in FIG. 2, the sealing material 5 follows the bending of the printed circuit board 1, so that the printed circuit board 1 immediately below the semiconductor element 2 is curved. do not do. Therefore, even in the electronic circuit board shown in FIG. 2, the stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed.

一方、溝４に封止材５を詰め込んだ場合、封止材５を詰め込まない場合に比べてプリント基板１自体の強度は向上する。プリント基板１自体の強度が向上することにより、プリント基板１上の配線パターンが断線したり、プリント基板１自体が破損したりする可能性を低減することができる。   On the other hand, when the sealing material 5 is packed in the groove 4, the strength of the printed circuit board 1 itself is improved as compared with the case where the sealing material 5 is not packed. By improving the strength of the printed circuit board 1 itself, the possibility that the wiring pattern on the printed circuit board 1 is disconnected or the printed circuit board 1 itself is damaged can be reduced.

以上のように、本変形例に係るプリント基板１は、溝４にプリント基板１より曲げ弾性率が低い封止材５が詰め込まれているので、半導体素子２や半田接続部３で発生する応力を緩和するとともに、プリント基板１の強度の低下を抑えることができ、プリント基板１上の配線パターンが断線したり、プリント基板１自体が破損したりする可能性を低減することができる。   As described above, since the printed board 1 according to this modification is filled with the sealing material 5 having a lower bending elastic modulus than the printed board 1 in the groove 4, the stress generated in the semiconductor element 2 and the solder connection portion 3. Can be mitigated, and a decrease in strength of the printed circuit board 1 can be suppressed, and the possibility that the wiring pattern on the printed circuit board 1 is broken or the printed circuit board 1 itself is damaged can be reduced.

（実施の形態２）
図３に、本実施の形態に係る電子回路基板の断面図を示す。図３に示す電子回路基板は、図１に示す電子回路基板と同様、所定の配線パターンが形成されたプリント基板１上に電子部品である半導体素子２が搭載されている。配線パターンは図示しないが、半導体素子２は、半田接続部３により、配線パターンの所定の領域でこれとＢＧＡ接続されている。 (Embodiment 2)
FIG. 3 shows a cross-sectional view of the electronic circuit board according to the present embodiment. In the electronic circuit board shown in FIG. 3, a semiconductor element 2 as an electronic component is mounted on a printed board 1 on which a predetermined wiring pattern is formed, like the electronic circuit board shown in FIG. Although a wiring pattern is not shown, the semiconductor element 2 is BGA-connected to a predetermined region of the wiring pattern by a solder connection portion 3.

また、図３に示す電子回路基板にも、半導体素子２と接続可能な配線パターンの領域の近傍で、配線パターンが設けられた面に開口する凹形状の溝４が形成されている。さらに、図３に示す電子回路基板では、半導体素子２が実装される面と反対側の面上に凹形状の溝６が形成されている。図３に示す電子回路基板では、半導体素子２の左右に溝４が形成され、さらに溝４の外側の位置で、半導体素子２が実装される面と反対側の面上に溝６が形成されている。   Also, in the electronic circuit board shown in FIG. 3, a concave groove 4 is formed in the vicinity of the area of the wiring pattern that can be connected to the semiconductor element 2 and opens on the surface provided with the wiring pattern. Further, in the electronic circuit board shown in FIG. 3, a concave groove 6 is formed on the surface opposite to the surface on which the semiconductor element 2 is mounted. In the electronic circuit board shown in FIG. 3, grooves 4 are formed on the left and right sides of the semiconductor element 2, and grooves 6 are formed on the surface opposite to the surface on which the semiconductor element 2 is mounted at a position outside the grooves 4. ing.

溝６が設けられる位置は、半導体素子２が実装される面と反対側の面上であって、半導体素子２が搭載される領域より外側の所定の位置となる。なお、本発明に係る電子回路基板では、図３に示すような溝４が内側、溝６が外側に形成される場合に限られず、溝６が内側、溝４が外側に形成される場合であっても良い。つまり、プリント基板１に形成される溝４と溝６とが繋がり貫通孔を形成しなければ良い。   The position where the groove 6 is provided is a predetermined position on the surface opposite to the surface on which the semiconductor element 2 is mounted and outside the region where the semiconductor element 2 is mounted. Note that the electronic circuit board according to the present invention is not limited to the case where the groove 4 is formed on the inner side and the groove 6 is formed on the outer side as shown in FIG. 3, but the case where the groove 6 is formed on the inner side and the groove 4 is formed on the outer side. There may be. That is, the groove 4 and the groove 6 formed in the printed circuit board 1 are not connected to form a through hole.

また、図３に示す電子回路基板では、溝４，６にプリント基板１の曲げ弾性率より低い封止材５が詰め込まれている。このように溝４，６に封止材５を詰め込んだ場合、封止材５を詰め込まない場合に比べてプリント基板１の強度が向上する。なお、溝４，６をプリント基板１に設けても十分なプリント基板１の強度が得られるのであれば、封止材５を溝４，６に詰め込まない構成であっても良い。   Further, in the electronic circuit board shown in FIG. 3, the grooves 4 and 6 are filled with a sealing material 5 lower than the bending elastic modulus of the printed board 1. As described above, when the sealing material 5 is packed in the grooves 4 and 6, the strength of the printed circuit board 1 is improved as compared with the case where the sealing material 5 is not packed. If sufficient strength of the printed circuit board 1 can be obtained even if the grooves 4 and 6 are provided in the printed circuit board 1, a configuration in which the sealing material 5 is not packed in the grooves 4 and 6 may be used.

本実施の形態に係る電子回路基板において、図１に示すような外力Ｆ１がプリント基板１に加えられた場合、溝４が設けられているため半導体素子２や半田接続部３に生じる応力を緩和することができる。さらに、本実施の形態に係る電子回路基板では、外力Ｆ２（半導体素子２が実装されているプリント基板１の面に加えられる外力）がプリント基板１に加えられた場合にも、溝６が設けられているため半導体素子２や半田接続部３に生じる応力を緩和することができる。   In the electronic circuit board according to the present embodiment, when an external force F1 as shown in FIG. 1 is applied to the printed circuit board 1, since the grooves 4 are provided, the stress generated in the semiconductor element 2 and the solder connection portion 3 is relieved. can do. Furthermore, in the electronic circuit board according to the present embodiment, the groove 6 is also provided when an external force F2 (an external force applied to the surface of the printed circuit board 1 on which the semiconductor element 2 is mounted) is applied to the printed circuit board 1. Therefore, stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed.

つまり、本実施の形態に係るプリント基板１では、半導体素子２が搭載される面と反対側の面上に凹形状の溝６が形成されているので、二方向の外力に対して半導体素子２や半田接続部３に生じる応力を緩和することができる。なお、溝４，６の形状は、緩和させる応力の大きさ、プリント基板１の強度、プリント基板１上の配線パターン等を考慮して個別に決定される。また、プリント基板１上の溝４，６の位置も、半導体素子２と接続可能な配線パターンの領域の近傍で、配線パターンが設けられた面に開口する条件を満たす範囲で、緩和させる応力の大きさ等の条件を考慮して個別に決定される。   That is, in the printed circuit board 1 according to the present embodiment, since the concave groove 6 is formed on the surface opposite to the surface on which the semiconductor element 2 is mounted, the semiconductor element 2 against external forces in two directions. In addition, the stress generated in the solder connection portion 3 can be relaxed. The shapes of the grooves 4 and 6 are individually determined in consideration of the magnitude of stress to be relaxed, the strength of the printed circuit board 1, the wiring pattern on the printed circuit board 1, and the like. Further, the positions of the grooves 4 and 6 on the printed circuit board 1 are also in the vicinity of the area of the wiring pattern that can be connected to the semiconductor element 2 and within the range that satisfies the condition for opening the surface on which the wiring pattern is provided. It is determined individually in consideration of conditions such as size.

さらに、プリント基板１に貫通孔を設けるには、プリント基板１上の配線パターンを回避して設けなければならないが、本実施の形態で示した溝６であれば、配線パターンが形成される面の反対側に形成されるため、プリント基板１上の配線パターンを考慮せずに設けることができる。もちろん、溝６を設けた側のプリント基板１の面において、配線パターンを形成しても構わない。   Further, in order to provide a through-hole in the printed circuit board 1, it is necessary to avoid the wiring pattern on the printed circuit board 1, but the groove 6 shown in the present embodiment is a surface on which the wiring pattern is formed. Therefore, it can be provided without considering the wiring pattern on the printed circuit board 1. Of course, a wiring pattern may be formed on the surface of the printed circuit board 1 on the side where the grooves 6 are provided.

（実施の形態３）
図４（ａ）に、本実施の形態に係る電子回路基板の平面図を示す。図４（ａ）に示す破線部の断面図を図４（ｂ）に示す。図４（ａ）に示す電子回路基板では、プリント基板１上に電子部品である半導体素子２が搭載されている。そして、プリント基板１上の半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４が形成されている。半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４を設けることにより、半導体素子２が実装される面内のどの方向に外力が加えられても、半導体素子２や半田接続部３に生じる応力を緩和することができる。 (Embodiment 3)
FIG. 4A shows a plan view of the electronic circuit board according to the present embodiment. A cross-sectional view of the broken line portion shown in FIG. 4A is shown in FIG. In the electronic circuit board shown in FIG. 4A, a semiconductor element 2 that is an electronic component is mounted on a printed board 1. Grooves 4 are formed all around the area of the wiring pattern that can be connected to the semiconductor element 2 on the printed circuit board 1. By providing the groove 4 around the entire area of the wiring pattern that can be connected to the semiconductor element 2, the semiconductor element 2 and the solder connection portion 3 can be applied regardless of the direction in which the semiconductor element 2 is mounted. It is possible to relieve the stress generated in.

さらに、溝４には、プリント基板１の曲げ弾性率より低い封止材５が詰め込まれている。なお、溝４をプリント基板１に設けても十分な強度が得られるのであれば、封止材５を溝４に詰め込まない構成であっても良い。   Further, the groove 4 is filled with a sealing material 5 lower than the bending elastic modulus of the printed circuit board 1. In addition, the structure which does not stuff the sealing material 5 in the groove | channel 4 may be sufficient if sufficient intensity | strength is acquired even if it provides the groove | channel 4 in the printed circuit board 1. FIG.

図４（ａ）に示すように半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４を形成する場合、半導体素子２に接続される配線パターンは、プリント基板１の中又は半導体素子２が実装される面の反対側の面に形成しても良い。図４（ｂ）に、配線パターンがプリント基板１の中に形成される場合が示されている。図４（ｂ）に示す半導体素子２は、半田接続部３によりプリント基板１上の配線パターン７とＢＧＡ接続している。そして、半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４が形成されている。   As shown in FIG. 4A, when the groove 4 is formed all around the area of the wiring pattern connectable to the semiconductor element 2, the wiring pattern connected to the semiconductor element 2 is in the printed circuit board 1 or the semiconductor element. You may form in the surface on the opposite side to the surface where 2 is mounted. FIG. 4B shows a case where a wiring pattern is formed in the printed circuit board 1. The semiconductor element 2 shown in FIG. 4B is BGA-connected to the wiring pattern 7 on the printed circuit board 1 by the solder connection portion 3. Grooves 4 are formed all around the area of the wiring pattern that can be connected to the semiconductor element 2.

半導体素子２と接続された配線パターン７は、プリント基板１中の溝４の下側を通り外部へと配線されている。図４（ｂ）では半導体素子２の外側に位置する半田接続部３と接続された配線パターン７のみが図示されているが、他の半田接続部３も同様に配線パターン７と接続されている。なお、本発明に係る電子回路基板では、プリント基板１中を通って、半導体素子２が実装される面の反対側のプリント基板１面に配線パターン７を形成しても良い（図４（ｃ））。   The wiring pattern 7 connected to the semiconductor element 2 is wired to the outside through the lower side of the groove 4 in the printed board 1. 4B shows only the wiring pattern 7 connected to the solder connection portion 3 located outside the semiconductor element 2, the other solder connection portions 3 are also connected to the wiring pattern 7 in the same manner. . In the electronic circuit board according to the present invention, the wiring pattern 7 may be formed on the surface of the printed circuit board 1 opposite to the surface on which the semiconductor element 2 is mounted through the printed circuit board 1 (FIG. 4C). )).

以上のように、本実施の形態に係るプリント基板１は、半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４が形成されるので、半導体素子２が実装される面内のどの方向に外力が加えられても、半導体素子２や半田接続部３に生じる応力を緩和することができる。   As described above, the printed circuit board 1 according to the present embodiment has the grooves 4 formed all around the area of the wiring pattern that can be connected to the semiconductor element 2. Even if an external force is applied in the direction, the stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed.

なお、図４（ａ）に示す電子回路基板では、溝４が隙間なく設けられ正方形の溝４が形成されている。しかし、本発明は、半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４を設ければ良く、溝４を隙間なく設ける必要はない。そこで、図５に示すように、半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４を設けるが、各辺の溝４の間に隙間を設けている。図５に示すように、各辺の溝４の間に隙間を設けることで、図４（ｂ）で示したように配線パターン７をプリント基板１の中を通す必要がなくなる。つまり、図５に示す電子回路基板では、各辺の溝４の隙間に配線パターン７を設けている。   In the electronic circuit board shown in FIG. 4A, the grooves 4 are provided without gaps, and the square grooves 4 are formed. However, according to the present invention, the groove 4 may be provided around the entire area of the wiring pattern connectable to the semiconductor element 2, and the groove 4 does not need to be provided without any gap. Therefore, as shown in FIG. 5, the grooves 4 are provided all around the area of the wiring pattern connectable to the semiconductor element 2, but a gap is provided between the grooves 4 on each side. As shown in FIG. 5, by providing a gap between the grooves 4 on each side, it is not necessary to pass the wiring pattern 7 through the printed board 1 as shown in FIG. That is, in the electronic circuit board shown in FIG. 5, the wiring pattern 7 is provided in the gap between the grooves 4 on each side.

また、図４（ａ）や図５に示した電子回路基板において、半導体素子２が搭載される面と反対側の面上に、実施の形態２で示した溝６を設けても良い。さらに、溝４の形状は、図４（ａ）に示すように四角形である必要はなく、多角形や円形であっても良い。   Further, in the electronic circuit board shown in FIG. 4A or 5, the groove 6 shown in the second embodiment may be provided on the surface opposite to the surface on which the semiconductor element 2 is mounted. Furthermore, the shape of the groove 4 does not have to be a square as shown in FIG. 4A, and may be a polygon or a circle.

（実施の形態４）
図６に、本実施の形態に係る電子回路基板の断面図を示す。図６に示す電子回路基板では、図１に示す電子回路基板と同様、所定の配線パターンが形成されたプリント基板１上に電子部品である半導体素子２が搭載されている。配線パターンは図示しないが、半導体素子２は、半田接続部３により、配線パターンの所定の領域でこれとＢＧＡ接続している。 (Embodiment 4)
FIG. 6 shows a cross-sectional view of the electronic circuit board according to the present embodiment. In the electronic circuit board shown in FIG. 6, similarly to the electronic circuit board shown in FIG. 1, a semiconductor element 2 as an electronic component is mounted on a printed board 1 on which a predetermined wiring pattern is formed. Although a wiring pattern is not shown, the semiconductor element 2 is BGA-connected to a predetermined region of the wiring pattern by a solder connection portion 3.

そして、図６に示す電子回路基板では、溝に代えて、半導体素子２と接続可能な配線パターンの領域の近傍で、プリント基板１を貫通する貫通孔８を形成する。貫通孔８には、プリント基板１の曲げ弾性率より低い封止材５が詰め込まれている。なお、貫通孔８の形状については、図６に示す円形のみに限られず、四角形等の他の形状であっても良い。   In the electronic circuit board shown in FIG. 6, a through hole 8 penetrating the printed circuit board 1 is formed in the vicinity of the area of the wiring pattern connectable to the semiconductor element 2 instead of the groove. The through hole 8 is filled with a sealing material 5 lower than the bending elastic modulus of the printed circuit board 1. In addition, about the shape of the through-hole 8, it is not restricted only to the circle shown in FIG. 6, Other shapes, such as a rectangle, may be sufficient.

背景技術でも説明したように、半導体素子２と接続可能な配線パターンの領域の近傍で、プリント基板１を貫通する貫通孔８を設けることにより、半導体素子２や半田接続部３に生じる応力を緩和することができる。しかし、貫通孔８を設けることにより、プリント基板１の強度が低下する問題があった。そこで、本実施の形態では、貫通孔８にプリント基板１の曲げ弾性率より低い封止材５が詰め込まれている。例えば、ポリアミド、ＡＢＳ樹脂、ポリスチレン等が封止材５に用いられる。これにより、本実施の形態に係るプリント基板１は、封止材５を詰め込まない場合に比べ、プリント基板１の強度が向上する。プリント基板１の強度が向上することにより、プリント基板１上の配線パターンが断線したり、プリント基板１自体が破損したりする可能性を低減することができる。   As described in the background art, by providing the through hole 8 that penetrates the printed circuit board 1 in the vicinity of the area of the wiring pattern that can be connected to the semiconductor element 2, the stress generated in the semiconductor element 2 and the solder connection portion 3 is relieved. can do. However, there is a problem that the strength of the printed circuit board 1 is reduced by providing the through holes 8. Therefore, in the present embodiment, the sealing material 5 lower than the bending elastic modulus of the printed circuit board 1 is packed in the through hole 8. For example, polyamide, ABS resin, polystyrene, or the like is used for the sealing material 5. Thereby, compared with the case where the sealing material 5 is not packed, the printed circuit board 1 which concerns on this Embodiment improves the intensity | strength of the printed circuit board 1. FIG. By improving the strength of the printed circuit board 1, the possibility that the wiring pattern on the printed circuit board 1 is disconnected or the printed circuit board 1 itself is damaged can be reduced.

なお、貫通孔８に封止材５を詰め込んだ場合であっても、プリント基板１の曲げに封止材５が追従するため、半導体素子２や半田接続部３に生じる応力を緩和することができる。   Even when the sealing material 5 is packed in the through-hole 8, the sealing material 5 follows the bending of the printed circuit board 1, so that the stress generated in the semiconductor element 2 and the solder connection portion 3 can be relieved. it can.

以上のように、本実施の形態に係るプリント基板１は、電子部品である半導体素子２が載置されるプリント基板１であって、半導体素子２と接続可能な領域を含む配線パターンと、領域の近傍で、プリント基板１を貫通する貫通孔８とを備え、貫通孔８が、プリント基板１より曲げ弾性率が低い樹脂を詰め込まれているので、プリント基板１の強度を維持しつつ、半導体素子２や半田接続部３で発生する応力を緩和することができる。   As described above, the printed circuit board 1 according to the present embodiment is a printed circuit board 1 on which a semiconductor element 2 that is an electronic component is placed, and includes a wiring pattern including a region connectable to the semiconductor element 2 and a region. And the through hole 8 penetrating the printed circuit board 1, and the through hole 8 is filled with a resin having a lower bending elastic modulus than the printed circuit board 1. The stress generated in the element 2 and the solder connection portion 3 can be relaxed.

（変形例）
図６に示した電子回路基板では、全ての溝４を貫通孔８に代えてプリント基板１に形成している。しかし、本発明では、プリント基板１上に溝４か貫通孔８かのどちらか一方のみを形成するように制限する必要はなく、必要に応じて溝４と貫通孔８とを組み合わせても良い。図７に、溝４と貫通孔８とを組み合わせて形成した電子回路基板の平面図を示す。図７に示す電子回路基板では、プリント基板１上に、半導体素子２が搭載されている。そして、半導体素子２を囲む所定の位置で、且つプリント基板１上に溝４や貫通孔８が形成されている。図７では、半導体素子２の左右に各２個（計４個）の貫通孔８が設けられ、半導体素子２の下側に溝４が設けられている。 (Modification)
In the electronic circuit board shown in FIG. 6, all the grooves 4 are formed on the printed board 1 instead of the through holes 8. However, in the present invention, it is not necessary to limit only one of the groove 4 and the through hole 8 to be formed on the printed circuit board 1, and the groove 4 and the through hole 8 may be combined as necessary. . FIG. 7 shows a plan view of an electronic circuit board formed by combining the groove 4 and the through hole 8. In the electronic circuit board shown in FIG. 7, the semiconductor element 2 is mounted on the printed board 1. A groove 4 and a through hole 8 are formed on the printed board 1 at a predetermined position surrounding the semiconductor element 2. In FIG. 7, two (four in total) through holes 8 are provided on the left and right sides of the semiconductor element 2, and the groove 4 is provided on the lower side of the semiconductor element 2.

図７のように溝４や貫通孔８を組み合わせることにより、プリント基板１上に配線パターン７の領域を確保することができる。図７に示す電子回路基板では、貫通孔８の間に配線パターン７を設けつつ、半導体素子２や半田接続部３に生じる応力を緩和することができる。つまり、図４で示したように、半導体素子２と接続可能な配線パターンの領域の周囲全てに溝４を形成すると、半導体素子２と接続される配線パターン７をプリント基板１中に設けるなどの処置が必要となるが、図７のように一部の溝４に代えて貫通孔８を設けることで、プリント基板１上に配線パターン７を設ける領域を確保することができる。   By combining the grooves 4 and the through holes 8 as shown in FIG. 7, the area of the wiring pattern 7 can be secured on the printed circuit board 1. In the electronic circuit board shown in FIG. 7, the stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed while providing the wiring pattern 7 between the through holes 8. That is, as shown in FIG. 4, when the groove 4 is formed all around the area of the wiring pattern connectable to the semiconductor element 2, the wiring pattern 7 connected to the semiconductor element 2 is provided in the printed circuit board 1. Although treatment is required, by providing the through holes 8 in place of some of the grooves 4 as shown in FIG. 7, it is possible to secure an area for providing the wiring pattern 7 on the printed circuit board 1.

以上のように、本変形例に係るプリント基板１では、プリント基板１に溝４と、貫通孔８とを備えるので、配線パターン７の領域を確保しつつ、半導体素子２や半田接続部３に生じる応力を緩和することができる。   As described above, the printed circuit board 1 according to this modification includes the groove 4 and the through hole 8 in the printed circuit board 1, so that the area of the wiring pattern 7 can be secured and the semiconductor element 2 and the solder connection portion 3 can be secured. The generated stress can be relaxed.

（実施の形態５）
図８に、本実施の形態に係る電子回路基板の断面図を示す。図８に示す電子回路基板では、プリント基板１上に配線パターン７が設けられ、当該配線パターン７上に電子部品である半導体素子２が搭載されている。半導体素子２は、半田接続部３により、配線パターン７の所定の領域でこれとＢＧＡ接続している。 (Embodiment 5)
FIG. 8 shows a cross-sectional view of the electronic circuit board according to the present embodiment. In the electronic circuit board shown in FIG. 8, a wiring pattern 7 is provided on a printed board 1, and a semiconductor element 2 that is an electronic component is mounted on the wiring pattern 7. The semiconductor element 2 is BGA-connected to a predetermined region of the wiring pattern 7 by a solder connection portion 3.

本実施の形態に係る電子回路基板では、さらにプリント基板１に空洞９が埋設されている。この空洞９は、半導体素子２と接続可能な配線パターンの領域の近傍で、プリント基板１に埋設されている。図８では、半導体素子２の左右の位置に空洞９が設けられている。本実施の形態に係る電子回路基板では、プリント基板１の中に空洞９が形成されるので、プリント基板１上に配線パターン７を自由に形成することができる。つまり、プリント基板１上に溝や貫通孔を形成する場合のように、配線パターン７を設ける領域を確保することについて考慮する必要がなくなる。   In the electronic circuit board according to the present embodiment, a cavity 9 is further embedded in the printed board 1. The cavity 9 is embedded in the printed circuit board 1 in the vicinity of the area of the wiring pattern that can be connected to the semiconductor element 2. In FIG. 8, cavities 9 are provided at the left and right positions of the semiconductor element 2. In the electronic circuit board according to the present embodiment, since the cavity 9 is formed in the printed board 1, the wiring pattern 7 can be freely formed on the printed board 1. That is, it is not necessary to consider securing a region for providing the wiring pattern 7 as in the case of forming a groove or a through hole on the printed circuit board 1.

図８に示す電子回路基板のように、プリント基板１の中に空洞９を設けた場合であっても、プリント基板１上に溝や貫通孔を設けた場合と同様、半導体素子２や半田接続部３に生じる応力を緩和することができる。つまり、外力がプリント基板１に加えられた場合、空洞９の存在により半導体素子２の直下に位置するプリント基板１の湾曲が軽減される。これにより、本実施の形態であっても半導体素子２や半田接続部３に生じる応力を緩和することができる。   Even when the cavity 9 is provided in the printed circuit board 1 as in the electronic circuit board shown in FIG. 8, the semiconductor element 2 and the solder connection are the same as the case where the groove and the through hole are provided on the printed circuit board 1. The stress generated in the portion 3 can be relaxed. That is, when an external force is applied to the printed circuit board 1, the curvature of the printed circuit board 1 located immediately below the semiconductor element 2 is reduced due to the presence of the cavity 9. Thereby, even in the present embodiment, the stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed.

なお、空洞９の形状は、緩和させる応力の大きさ、プリント基板の強度、プリント基板上の配線パターン等を考慮して個別に決定される。また、プリント基板中の空洞９の位置も、半導体素子２と接続可能な配線パターンの領域の近傍である条件を満たす範囲で、緩和させる応力の大きさ等の条件を考慮して個別に決定される。   The shape of the cavity 9 is individually determined in consideration of the magnitude of stress to be relaxed, the strength of the printed board, the wiring pattern on the printed board, and the like. In addition, the position of the cavity 9 in the printed circuit board is also individually determined in consideration of conditions such as the magnitude of stress to be relaxed within a range that satisfies the conditions in the vicinity of the area of the wiring pattern that can be connected to the semiconductor element 2. The

また、図８に示すプリント基板１では、空洞９にプリント基板１の曲げ弾性率より低い封止材５が詰め込まれている。このように空洞９に封止材５を詰め込んだ場合、封止材５を詰め込まない場合に比べてプリント基板１自体の強度が向上する。なお、空洞９をプリント基板１に設けても十分な強度が得られるのであれば、封止材５を空洞９に詰め込まない構成であっても良い。   Further, in the printed board 1 shown in FIG. 8, the cavity 9 is filled with a sealing material 5 lower than the bending elastic modulus of the printed board 1. Thus, when the sealing material 5 is packed in the cavity 9, the strength of the printed circuit board 1 itself is improved as compared with the case where the sealing material 5 is not packed. Note that the sealing material 5 may not be packed into the cavity 9 as long as sufficient strength is obtained even if the cavity 9 is provided in the printed circuit board 1.

なお、封止材５を空洞９に詰め込む方法として、次に述べるような方法がある。例えば、プリント基板１が２枚の基板をプレスすることにより形成される場合、プレス前のそれぞれの基板に所定の溝を形成しておき、２枚の基板をプレスする際、溝に封止材５を詰め込んで貼り合わせる。これにより、封止材５が空洞９に詰め込まれたプリント基板１を形成することができる。   As a method for packing the sealing material 5 into the cavity 9, there is a method as described below. For example, when the printed circuit board 1 is formed by pressing two substrates, a predetermined groove is formed in each substrate before pressing, and when the two substrates are pressed, a sealing material is formed in the groove. Pack 5 and paste together. Thereby, the printed circuit board 1 in which the sealing material 5 is packed in the cavity 9 can be formed.

以上のように、本実施の形態に係るプリント基板１では、電子部品である半導体素子２を載置可能であって、半導体素子２と接続可能な領域を含む配線パターンと、領域の近傍で、埋設された空洞とを備えるので、プリント基板１上に形成される配線パターン７に何らの制限を与えることなく、半導体素子２や半田接続部３で発生する応力を緩和することができる。また、本実施の形態に係る電子回路基板は、本実施の形態に係るプリント基板１と、領域に接続された電子部品である半導体素子２とを備えるので、プリント基板１上に形成される配線パターン７に何らの制限を与えることなく、半導体素子２や半田接続部３で発生する応力を緩和することができる。   As described above, in the printed circuit board 1 according to the present embodiment, the semiconductor element 2 which is an electronic component can be placed, and the wiring pattern including the region connectable to the semiconductor element 2 and the vicinity of the region are Since the embedded cavity is provided, the stress generated in the semiconductor element 2 and the solder connection portion 3 can be alleviated without giving any restriction to the wiring pattern 7 formed on the printed circuit board 1. In addition, since the electronic circuit board according to the present embodiment includes the printed board 1 according to the present embodiment and the semiconductor element 2 that is an electronic component connected to the region, the wiring formed on the printed board 1 The stress generated in the semiconductor element 2 and the solder connection portion 3 can be relaxed without giving any restriction to the pattern 7.

また、本実施の形態に係るプリント基板１では、空洞９にプリント基板１より曲げ弾性率が低い樹脂が詰め込まれるので、プリント基板１の強度を維持しつつ、半導体素子２や半田接続部３で発生する応力を緩和することができる。   Further, in the printed circuit board 1 according to the present embodiment, the cavity 9 is filled with a resin having a lower bending elastic modulus than the printed circuit board 1, so that the strength of the printed circuit board 1 is maintained and the semiconductor element 2 and the solder connection portion 3 are used. The generated stress can be relaxed.

（実施の形態６）
次に、本実施の形態では、図１に示したような電子回路基板のプリント基板１を製造する方法について説明する。まず、図１に示すプリント基板１を設計する段階で、実装する半導体素子２や半田接続部３などに発生する応力を緩和できるように、プリント基板１上には必要な溝４を設けておく。そして、設計する段階で、プリント基板１の強度も計算し、補強が必要な溝４に封止材５を詰め込む。その後、封止材５が詰め込まれたプリント基板１上に、半導体素子２を実装することで、図１に示す電子回路基板を形成することができる。 (Embodiment 6)
Next, in the present embodiment, a method for manufacturing the printed circuit board 1 of the electronic circuit board as shown in FIG. 1 will be described. First, at the stage of designing the printed circuit board 1 shown in FIG. 1, a necessary groove 4 is provided on the printed circuit board 1 so that stress generated in the semiconductor element 2 to be mounted, the solder connection portion 3 and the like can be relieved. . Then, at the design stage, the strength of the printed circuit board 1 is also calculated, and the sealing material 5 is packed into the grooves 4 that need to be reinforced. Then, the electronic circuit board shown in FIG. 1 can be formed by mounting the semiconductor element 2 on the printed board 1 filled with the sealing material 5.

又は、図１に示す電子回路基板を設計する段階で、実装する半導体素子２や半田接続部３などに発生する応力を緩和できるように、プリント基板１上には必要な溝４を設けておく。そして、溝４が形成されたプリント基板１上に、半導体素子２を実装する。その後に、プリント基板１の強度を測定し、補強が必要と判断される溝４に封止材５を詰め込むことで、図１に示す電子回路基板を形成することができる。   Alternatively, a necessary groove 4 is provided on the printed circuit board 1 so as to relieve stress generated in the semiconductor element 2 to be mounted, the solder connection portion 3 and the like at the stage of designing the electronic circuit board shown in FIG. . And the semiconductor element 2 is mounted on the printed circuit board 1 in which the groove | channel 4 was formed. Then, the electronic circuit board shown in FIG. 1 can be formed by measuring the strength of the printed circuit board 1 and filling the sealing material 5 in the groove 4 that is determined to be reinforced.

以上のように、本実施の形態で説明した製造方法では、溝４に封止材５を詰め込むことにより、プリント基板１の強度を自由に補強することができる。特に、半導体素子２をプリント基板１上に実装した後、プリント基板１の強度を測定し、封止材５を詰め込む製造方法の場合、プリント基板１の強度を測定して弱い箇所を選択的に補強することができるため、封止材５のコストを低減しつつ、適切な強度を有するプリント基板１を得ることが可能となる。   As described above, in the manufacturing method described in the present embodiment, the strength of the printed circuit board 1 can be freely reinforced by filling the sealing material 5 in the groove 4. In particular, after mounting the semiconductor element 2 on the printed circuit board 1, the strength of the printed circuit board 1 is measured, and in the case of the manufacturing method in which the sealing material 5 is packed, the strength of the printed circuit board 1 is measured to selectively select weak portions. Since it can reinforce, it becomes possible to obtain the printed circuit board 1 having appropriate strength while reducing the cost of the sealing material 5.

なお、図６に示すような貫通孔８を設けるような電子回路基板についても、本実施の形態で説明した製造方法は適用することができる。   Note that the manufacturing method described in the present embodiment can also be applied to an electronic circuit board in which a through hole 8 as shown in FIG. 6 is provided.

（実施の形態７）
図９に、本実施の形態に係る電子回路基板の断面図を示す。図９に示す電子回路基板は、プリント基板１上に配線パターンが設けられ、当該配線パターン上に半導体素子２が搭載されている。配線パターンは図示しないが、半導体素子２は、半田接続部３により、配線パターンの所定の領域でこれとＢＧＡ接続されている。そして、図９に示す電子回路基板は、半導体素子２と接続可能な配線パターンの領域の近傍で、配線パターンが設けられた面に凹形状の溝４が形成されている。 (Embodiment 7)
FIG. 9 shows a cross-sectional view of the electronic circuit board according to the present embodiment. In the electronic circuit board shown in FIG. 9, a wiring pattern is provided on a printed circuit board 1, and a semiconductor element 2 is mounted on the wiring pattern. Although a wiring pattern is not shown, the semiconductor element 2 is BGA-connected to a predetermined region of the wiring pattern by a solder connection portion 3. In the electronic circuit board shown in FIG. 9, a concave groove 4 is formed on the surface provided with the wiring pattern in the vicinity of the area of the wiring pattern that can be connected to the semiconductor element 2.

さらに、図９に示す電子回路基板は、半田接続部３を補強するために注入される樹脂（以下、アンダーフィル樹脂１０という）で封止される。アンダーフィル樹脂１０を半導体素子２とプリント基板１との間に注入して、半導体素子２を封止する。図９に示す電子回路基板では、アンダーフィル樹脂１０の一部が溝４に詰め込まれている。   Further, the electronic circuit board shown in FIG. 9 is sealed with a resin (hereinafter referred to as an underfill resin 10) injected to reinforce the solder connection portion 3. Underfill resin 10 is injected between semiconductor element 2 and printed circuit board 1 to seal semiconductor element 2. In the electronic circuit board shown in FIG. 9, a part of the underfill resin 10 is packed in the groove 4.

つまり、本実施の形態に係る電子回路基板を製造する場合、アンダーフィル樹脂１０を半導体素子２とプリント基板１との間に注入する際に、補強が必要な溝４にも選択的にアンダーフィル樹脂１０を注入する。これにより、別途溝４に封止材を詰め込む工程を設ける必要がなくなり、工程を簡略化することができる。なお、アンダーフィル樹脂１０は、プリント基板１より曲げ弾性率が低い樹脂を用いる。   That is, when the electronic circuit board according to the present embodiment is manufactured, when the underfill resin 10 is injected between the semiconductor element 2 and the printed board 1, the underfill is selectively applied to the grooves 4 that need to be reinforced. Resin 10 is injected. Thereby, it is not necessary to provide a process of separately filling the sealing material in the groove 4, and the process can be simplified. The underfill resin 10 is a resin having a lower bending elastic modulus than the printed board 1.

以上のように、本実施の形態に係る電子回路基板の製造方法は、プリント基板１より曲げ弾性率が低い樹脂を用いて、プリント基板１上に搭載された半導体素子２を封止する際に、溝４を選択的に樹脂で詰め込むので、溝４に封止材を別途詰め込む工程が不要になり、製造コストを低減することができる。   As described above, the manufacturing method of the electronic circuit board according to the present embodiment uses the resin whose bending elastic modulus is lower than that of the printed board 1 to seal the semiconductor element 2 mounted on the printed board 1. Since the grooves 4 are selectively packed with resin, a process of separately packing the sealing material into the grooves 4 becomes unnecessary, and the manufacturing cost can be reduced.

なお、図６に示すような貫通孔８を設けるような電子回路基板についても、本実施の形態で説明した製造方法は適用することができる。   Note that the manufacturing method described in the present embodiment can also be applied to an electronic circuit board in which a through hole 8 as shown in FIG. 6 is provided.

本発明の実施の形態１に係る電子回路基板の断面図である。It is sectional drawing of the electronic circuit board which concerns on Embodiment 1 of this invention. 本発明の実施の形態１の変形例に係る電子回路基板の断面図である。It is sectional drawing of the electronic circuit board which concerns on the modification of Embodiment 1 of this invention. 本発明の実施の形態２に係る電子回路基板の断面図である。It is sectional drawing of the electronic circuit board which concerns on Embodiment 2 of this invention. 本発明の実施の形態３に係る電子回路基板の平面図である。It is a top view of the electronic circuit board which concerns on Embodiment 3 of this invention. 本発明の実施の形態３に係る電子回路基板の平面図である。It is a top view of the electronic circuit board which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る電子回路基板の断面図である。It is sectional drawing of the electronic circuit board which concerns on Embodiment 4 of this invention. 本発明の実施の形態４に係る電子回路基板の平面図である。It is a top view of the electronic circuit board which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る電子回路基板の断面図である。It is sectional drawing of the electronic circuit board which concerns on Embodiment 5 of this invention. 本発明の実施の形態７に係る電子回路基板の断面図である。It is sectional drawing of the electronic circuit board which concerns on Embodiment 7 of this invention.

符号の説明Explanation of symbols

１ プリント基板、２ 半導体素子、３ 半田接続部、４，６ 溝、５ 封止材、７ 配線パターン、８ 貫通孔、９ 空洞、１０ アンダーフィル樹脂。
DESCRIPTION OF SYMBOLS 1 Printed circuit board, 2 Semiconductor element, 3 Solder connection part, 4,6 groove | channel, 5 Sealing material, 7 Wiring pattern, 8 Through-hole, 9 Cavity, 10 Underfill resin.

Claims (12)

電子部品を載置可能であって、
前記電子部品と接続可能な領域を含む配線パターンと、
前記領域の近傍で、前記配線パターンが設けられた面に開口する凹形状の第１の溝とを備える、プリント基板。 Electronic components can be placed,
A wiring pattern including a region connectable with the electronic component;
A printed circuit board comprising: a first groove having a concave shape that opens in the vicinity of the region and on the surface on which the wiring pattern is provided. 請求項１記載のプリント基板であって、
前記第１の溝は、前記領域の周囲全てに形成されていることを特徴とする、プリント基板。 The printed circuit board according to claim 1,
The printed circuit board, wherein the first groove is formed all around the region. 請求項１又は請求項２に記載のプリント基板であって、
前記電子部品が載置される面と反対側の面上に形成される凹形状の第２の溝をさらに備えることを特徴とする、プリント基板。 The printed circuit board according to claim 1 or 2,
The printed circuit board further comprising a concave second groove formed on a surface opposite to a surface on which the electronic component is placed. 請求項１乃至請求項３のいずれかに記載のプリント基板であって、
前記第１の溝及び前記第２の溝は、前記プリント基板より曲げ弾性率が低い樹脂が詰め込まれていることを特徴とする、プリント基板。 The printed circuit board according to any one of claims 1 to 3,
The printed circuit board, wherein the first groove and the second groove are filled with a resin having a lower bending elastic modulus than the printed circuit board. 電子部品を載置可能なプリント基板であって、
前記電子部品と接続可能な領域を含む配線パターンと、
前記領域の近傍で、前記プリント基板を貫通する貫通孔とを備え、
前記貫通孔は、前記プリント基板より曲げ弾性率が低い樹脂が詰め込まれていることを特徴とする、プリント基板。 A printed circuit board on which electronic components can be placed,
A wiring pattern including a region connectable with the electronic component;
A through hole penetrating the printed circuit board in the vicinity of the region;
The printed circuit board, wherein the through hole is filled with a resin having a lower bending elastic modulus than the printed circuit board. 請求項１に記載の前記第１の溝と、
請求項５に記載の前記貫通孔とを備えた、プリント基板。 The first groove of claim 1;
A printed circuit board comprising the through hole according to claim 5. 請求項１乃至請求項６のいずれか一つに記載のプリント基板と、
前記領域に接続された前記電子部品とを備えた、電子回路基板。 The printed circuit board according to any one of claims 1 to 6,
An electronic circuit board comprising the electronic component connected to the region. 請求項４乃至請求項６のいずれかに記載のプリント基板を製造する方法であって、
前記領域の近傍に前記第１の溝又は前記貫通孔を形成し、
前記プリント基板の強度を測定して、所定の強度よりも低い部分の前記第１の溝又は前記貫通孔に、前記プリント基板より曲げ弾性率が低い樹脂を選択的に詰め込むことを特徴とする、プリント基板の製造方法。 A method for producing a printed circuit board according to any one of claims 4 to 6,
Forming the first groove or the through hole in the vicinity of the region;
The strength of the printed board is measured, and the resin having a lower bending elastic modulus than the printed board is selectively packed in the first groove or the through hole in a portion lower than a predetermined strength, A method for manufacturing a printed circuit board. 請求項７に記載の電子回路基板を製造する方法であって、
前記プリント基板より曲げ弾性率が低い樹脂を用いて、前記プリント基板上に搭載された前記電子部品を封止する際に、前記第１の溝又は前記複数の貫通孔に前記樹脂を選択的に詰め込むことを特徴とする、電子回路基板の製造方法。 A method for manufacturing an electronic circuit board according to claim 7, comprising:
When sealing the electronic component mounted on the printed circuit board using a resin having a lower bending elastic modulus than the printed circuit board, the resin is selectively used in the first groove or the plurality of through holes. A method of manufacturing an electronic circuit board, comprising packing. 電子部品を載置可能であって、
前記電子部品と接続可能な領域を含む配線パターンと、
前記領域の近傍で、埋設された空洞とを備える、プリント基板。 Electronic components can be placed,
A wiring pattern including a region connectable with the electronic component;
A printed circuit board comprising an embedded cavity in the vicinity of the region. 請求項１０記載のプリント基板であって、
前記空洞は、前記プリント基板より曲げ弾性率が低い樹脂が詰め込まれていることを特徴とする、プリント基板。 The printed circuit board according to claim 10,
The printed circuit board, wherein the cavity is filled with a resin having a lower bending elastic modulus than the printed circuit board. 請求項１０又は請求項１１に記載のプリント基板と、
前記領域に接続された前記電子部品とを備えた、電子回路基板。
A printed circuit board according to claim 10 or claim 11,
An electronic circuit board comprising the electronic component connected to the region.
JP2004042791A 2004-02-19 2004-02-19 Printed board, electronic circuit substrate, and its manufacturing method Pending JP2005235997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004042791A JP2005235997A (en) 2004-02-19 2004-02-19 Printed board, electronic circuit substrate, and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004042791A JP2005235997A (en) 2004-02-19 2004-02-19 Printed board, electronic circuit substrate, and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2005235997A true JP2005235997A (en) 2005-09-02

Family

ID=35018637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004042791A Pending JP2005235997A (en) 2004-02-19 2004-02-19 Printed board, electronic circuit substrate, and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2005235997A (en)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158571A (en) * 2007-12-25 2009-07-16 Fujitsu Ltd Wiring board and method for manufacturing wiring board
JP2009194284A (en) * 2008-02-18 2009-08-27 Eito Kogyo:Kk Heat-dissipating printed circuit board
JP2009206195A (en) * 2008-02-26 2009-09-10 Hitachi Ltd Wiring board
JP2009302343A (en) * 2008-06-13 2009-12-24 Denso Corp Multilayer substrate, and method of manufacturing the same
JP2011014648A (en) * 2009-06-30 2011-01-20 Toshiba Corp Electronic device
JP2013138157A (en) * 2011-12-28 2013-07-11 Kyocer Slc Technologies Corp Wiring board and probe card using the same
CN103430303A (en) * 2011-03-07 2013-12-04 奥斯兰姆奥普托半导体有限责任公司 Lead frame for optoelectronic components and method for producing optoelectronic components
US8687377B2 (en) 2011-03-31 2014-04-01 Kabushiki Kaisha Toshiba Storage device, electronic device, and circuit board assembly
JP2014241338A (en) * 2013-06-11 2014-12-25 富士通株式会社 Semiconductor device
GB2524327A (en) * 2014-03-21 2015-09-23 Nokia Technologies Oy Flexible electronics apparatus and associated methods
JP2016032102A (en) * 2014-07-25 2016-03-07 ダイ−チュン フＤｙｉ−Ｃｈｕｎｇ ＨＵ Package substrate
WO2016199219A1 (en) * 2015-06-09 2016-12-15 日産自動車株式会社 Mechanically and electrically integrated rotating electric machine device
JP2018006724A (en) * 2016-06-23 2018-01-11 京セラ株式会社 Wiring board
WO2019013028A1 (en) * 2017-07-13 2019-01-17 株式会社村田製作所 Semiconductor device and piezoelectric oscillator
CN109451650A (en) * 2018-08-07 2019-03-08 苏州霞光电子科技有限公司 A kind of low stress printed circuit that can improve surface mount device welding spot reliability
US10321563B2 (en) 2014-08-29 2019-06-11 Nokia Technologies Oy Apparatus and associated methods for deformable electronics
US10393599B2 (en) 2014-10-16 2019-08-27 Nokia Technologies Oy Deformable apparatus and method
US10435289B2 (en) 2014-10-16 2019-10-08 Nokia Technoloiges Oy Deformable apparatus and method
WO2019216244A1 (en) * 2018-05-07 2019-11-14 株式会社村田製作所 Multilayer board and connection structure therefor
US10531559B2 (en) 2017-06-09 2020-01-07 Kabushiki Kaisha Toshiba Electronic device

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158571A (en) * 2007-12-25 2009-07-16 Fujitsu Ltd Wiring board and method for manufacturing wiring board
JP2009194284A (en) * 2008-02-18 2009-08-27 Eito Kogyo:Kk Heat-dissipating printed circuit board
JP2009206195A (en) * 2008-02-26 2009-09-10 Hitachi Ltd Wiring board
JP2009302343A (en) * 2008-06-13 2009-12-24 Denso Corp Multilayer substrate, and method of manufacturing the same
JP2011014648A (en) * 2009-06-30 2011-01-20 Toshiba Corp Electronic device
JP4676013B2 (en) * 2009-06-30 2011-04-27 株式会社東芝 Electronics
US8068345B2 (en) 2009-06-30 2011-11-29 Kabushiki Kaisha Toshiba Electronic device
US9130136B2 (en) 2011-03-07 2015-09-08 Osram Opto Semiconductors Gmbh Leadframe for optoelectronic components and method for producing optoelectronic components
CN103430303A (en) * 2011-03-07 2013-12-04 奥斯兰姆奥普托半导体有限责任公司 Lead frame for optoelectronic components and method for producing optoelectronic components
JP2014506398A (en) * 2011-03-07 2014-03-13 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Optoelectronic component leadframe and optoelectronic component manufacturing method
US8687377B2 (en) 2011-03-31 2014-04-01 Kabushiki Kaisha Toshiba Storage device, electronic device, and circuit board assembly
US9157932B2 (en) 2011-12-28 2015-10-13 KYOCERA Circuit Solutions, Inc. Wiring board and probe card using the same
JP2013138157A (en) * 2011-12-28 2013-07-11 Kyocer Slc Technologies Corp Wiring board and probe card using the same
JP2014241338A (en) * 2013-06-11 2014-12-25 富士通株式会社 Semiconductor device
GB2524327A (en) * 2014-03-21 2015-09-23 Nokia Technologies Oy Flexible electronics apparatus and associated methods
JP2016032102A (en) * 2014-07-25 2016-03-07 ダイ−チュン フＤｙｉ−Ｃｈｕｎｇ ＨＵ Package substrate
US10373918B2 (en) 2014-07-25 2019-08-06 Dyi-chung Hu Package substrate
US10321563B2 (en) 2014-08-29 2019-06-11 Nokia Technologies Oy Apparatus and associated methods for deformable electronics
US10435289B2 (en) 2014-10-16 2019-10-08 Nokia Technoloiges Oy Deformable apparatus and method
US10393599B2 (en) 2014-10-16 2019-08-27 Nokia Technologies Oy Deformable apparatus and method
WO2016199219A1 (en) * 2015-06-09 2016-12-15 日産自動車株式会社 Mechanically and electrically integrated rotating electric machine device
JPWO2016199219A1 (en) * 2015-06-09 2018-03-15 日産自動車株式会社 Mechanical and electric integrated rotating electrical machine
JP2018006724A (en) * 2016-06-23 2018-01-11 京セラ株式会社 Wiring board
US10531559B2 (en) 2017-06-09 2020-01-07 Kabushiki Kaisha Toshiba Electronic device
WO2019013028A1 (en) * 2017-07-13 2019-01-17 株式会社村田製作所 Semiconductor device and piezoelectric oscillator
WO2019216244A1 (en) * 2018-05-07 2019-11-14 株式会社村田製作所 Multilayer board and connection structure therefor
JPWO2019216244A1 (en) * 2018-05-07 2021-03-11 株式会社村田製作所 Multilayer board and its connection structure
US11470728B2 (en) 2018-05-07 2022-10-11 Murata Manufacturing Co., Ltd. Multilayer board and connecting structure of the same
CN109451650A (en) * 2018-08-07 2019-03-08 苏州霞光电子科技有限公司 A kind of low stress printed circuit that can improve surface mount device welding spot reliability

Similar Documents

Publication Publication Date Title
JP2005235997A (en) Printed board, electronic circuit substrate, and its manufacturing method
US7554191B2 (en) Semiconductor device having a heatsink plate with bored portions
US9508789B2 (en) Electronic components on trenched substrates and method of forming same
US7247945B2 (en) Semiconductor apparatus
JP2007281129A (en) Stacked semiconductor device
TW200605739A (en) Printed circuit board having structure for relieving stress concentration, and semiconductor chip package equipped with the same
JP2009252894A (en) Semiconductor device
JP2006245076A (en) Semiconductor device
JP2007157958A (en) Electronic device
JP2007149829A (en) Electronic component mounting substrate
JP2006278771A (en) Semiconductor device and manufacturing method thereof
JP2015032697A (en) Electronic circuit module, and substrate for electronic circuit module
KR100713930B1 (en) Chip stack package
KR20060044387A (en) Semiconductor device
JP5078631B2 (en) Semiconductor device
US20100147558A1 (en) Anchor pin lead frame
WO2012070168A1 (en) Semiconductor chip and semiconductor device
JP2005101053A (en) Connection member of module component and component connection structure thereof
JP2008210985A (en) Semiconductor device
JP2005268241A (en) Semiconductor package and system module
JP2005129570A (en) Wiring board and semiconductor device
JP2019508908A (en) Packaging structure with solder balls and method of manufacturing the packaging structure
JP2008218935A (en) Circuit board fitted with semiconductor integrated circuit package and semiconductor integrated circuit package
JP2008085228A (en) Printed circuit board, electronic device with printed circuit board, and method of producing printed circuit board
JP2007005559A (en) Electronic circuit module