JP2006128441A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be increased in bonding reliability by reducing thermal stress at ball electrodes of semiconductor elements mounted on both faces of a circuit board. <P>SOLUTION: The semiconductor device includes the semiconductor elements arranged on both faces of the circuit board. At a position corresponding to the ball electrode arranged in the most outer part of the first semiconductor element, a projection is formed on the top face of the package of the second semiconductor element located on the opposite side of the circuit board. The projection on the package of the second semiconductor element is rectangularly parallelepiped, and formed of a member same as or different from that of the package. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor element mounting structure in which a plurality of ball electrodes are arranged.

  Conventionally, in order to improve the reliability of a solder joint between a package of a semiconductor element in which a plurality of ball electrodes are arranged in an array and a circuit board on which the semiconductor element is mounted, the stress at the solder joint is reduced. A method has been adopted.

  This is because the coefficient of linear expansion differs among semiconductor elements, packages, ball electrodes, and circuit boards, so when heat is applied, the coefficients of expansion differ, and a large stress is applied to the ball electrode that is the joint, resulting in the life of the joint. May be shortened.

  Therefore, as a conventional method for reducing the thermal stress applied to the ball electrode, for example, a method described in Patent Document 1 in which the thickness of a part of the package is reduced to minimize warpage due to the heat of the package is known. ing.

  Further, as a method for reducing the thermal stress at the solder joint in the form in which the semiconductor element is mounted on both sides of the circuit board, for example, the solder joint of the semiconductor element mounted on the front and back of the circuit board described in Patent Document 2 is provided. There are known ones that are arranged so as not to be in the same position on the front and back of the circuit board.

Japanese Patent Laid-Open No. 11-289031 Japanese Patent No. 2634351

  As the mounting density increases, the number of semiconductor elements mounted on both sides of a circuit board is increasing. When a semiconductor element is mounted on both sides, deformation is restrained by the semiconductor element on the other side, and the circuit board cannot be bent freely. Therefore, the reliability of the solder joint is more reliable than when the semiconductor element is mounted only on one side of the circuit board. Therefore, it is necessary to improve the reliability of the solder joint.

  Among the above conventional examples, the method of reducing the thickness of a portion inside the pad electrode of the package described in Patent Document 1 (Japanese Patent Laid-Open No. 11-289031) is a case where a semiconductor element is mounted on one side of a circuit board. This is to improve the reliability of the solder joint.

  Further, the method of arranging the semiconductor elements described in Patent Document 2 (Japanese Patent No. 2634351) on both sides of the circuit board is a form in which the semiconductor elements are joined by leads, and the plurality of ball electrodes of the present invention are arranged in an array. It is different from the shape formed in the above.

  When the semiconductor elements in which the plurality of ball electrodes are formed in an array are arranged on both sides of the circuit board at positions where they do not interfere with the mating joint as described in Patent Document 2, in reality, Mounting is not possible unless the semiconductor element is completely displaced.

  The present invention has been made in view of the above problems, and the object of the present invention is to reduce the thermal stress of the ball electrode portions of the semiconductor element mounted on both sides of the circuit board and to improve the bonding reliability. An object of the present invention is to provide a semiconductor device that can be used.

  In order to achieve the above object, the present invention provides a semiconductor device including semiconductor elements disposed on both sides of a circuit board, at a position corresponding to the outermost ball electrode portion of the first semiconductor element through the circuit board. A protrusion is provided on the upper surface of the package of the second semiconductor element located on the side.

  ADVANTAGE OF THE INVENTION According to this invention, the thermal stress of the ball | bowl electrode part of the semiconductor element mounted on both surfaces of the circuit board can be reduced, and improvement of joining reliability can be aimed at.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. The embodiments described below are preferred specific examples of the present invention, and various technically preferable limitations are given. However, unless otherwise stated, the present invention is limited to these embodiments. It is not limited.

<Embodiment 1>
FIG. 1 is a perspective view of a semiconductor device of the present invention as viewed from the upper surface side of a package.

  The semiconductor element 10 in the semiconductor device of the present invention includes an IC chip 13, a package 11, a package protrusion 12, a semiconductor element connection part 14, and a plurality of ball electrodes 16.

  The semiconductor element connection portion is composed of an interposer and an electrode pad. The material of the interposer is, for example, an epoxy resin or a polyimide resin.

  Although not shown in the drawing, the semiconductor element connection portion is configured with a wiring for appropriately connecting the semiconductor element 10 and the plurality of ball electrodes 16.

  The IC chip 13 is connected to the semiconductor element junction through a plurality of electrodes (not shown) provided on the back surface thereof. The material is silicon. The IC chip 13 is packaged so as to protect it by a package. The material is, for example, an epoxy resin.

  On the upper surface of the package 11, a package protrusion 12 having a substantially rectangular parallelepiped shape is provided. The material of the package 11 is, for example, the same epoxy resin as the package material.

  The package protrusion 12 is integrally formed with the same resin as the package 11 or is formed of a separate member having high rigidity, and is bonded to the upper surface of the package 11 with an adhesive or the like.

  The plurality of ball electrodes 16 are arranged in an approximate array on the back surface of the package 11. The material of the plurality of ball electrodes 16 is, for example, lead-free solder.

  2A is a perspective view in which the semiconductor device of the present invention is mounted on both sides of the circuit board, FIG. 2B is a plan view, and FIG. 2C is a side view.

  The circuit board 100 on which the semiconductor element is mounted is provided with terminals in an array (not shown) at positions corresponding to the plurality of ball electrodes of the package, and the package is as shown in FIG. The plurality of ball electrodes are joined with solder. The material is, for example, glass epoxy resin.

  The suffixes of the mounted semiconductor elements are 10a, 11a, 12a... For the first semiconductor mounted on the front surface side, and 10b, 11b, 12b... For the second semiconductor mounted on the back surface side.

  As shown in FIG. 2B, the first semiconductor and the second semiconductor mounted on the front and back of the circuit board are mounted in a state shifted from each other in the horizontal direction.

  A rectangular parallelepiped package protrusion is provided on the upper surface of the semiconductor element mounted on the back side of the circuit board corresponding to the position of the outermost ball electrode of the semiconductor element mounted on the front side of the circuit board.

  On the other hand, a rectangular parallelepiped package protrusion is provided on the upper surface of the semiconductor element mounted on the front surface side of the circuit board corresponding to the position of the outermost ball electrode of the semiconductor element mounted on the back surface side of the circuit board.

  FIG. 11A is a plan view of a conventional semiconductor device viewed from the package side, and FIG. 11B is a side view of the conventional semiconductor device. The configuration of the semiconductor device will be described with reference to these drawings.

  The semiconductor element 70 in the semiconductor device according to the present invention includes an IC chip 73, a package 71, a semiconductor element connection portion 74, and a plurality of ball electrodes 76.

  The semiconductor element connecting portion 74 is composed of an interposer and electrode pads. The material of the interposer is, for example, an epoxy resin or a polyimide resin.

  The semiconductor element connection portion 74 is configured with wiring (not shown) for appropriately connecting the semiconductor element 70 and the plurality of ball electrodes 76.

  The IC chip 73 is connected to the semiconductor element junction 74 through a plurality of electrodes 8 (not shown) provided on the back surface thereof. The material is silicon.

  The IC chip 73 is packaged by a package 71 so as to protect it. The material is, for example, an epoxy resin.

  Next, the phenomenon that the package is deformed by heat will be described.

  FIG. 12 is a side view showing a state in which a conventional semiconductor element mounted on one side of a circuit board is thermally deformed.

  Consider a conventional semiconductor device 70 mounted on a circuit board as shown in FIG.

  The number of the plurality of ball electrodes is described as an arbitrary number.

  The linear expansion coefficients of circuit boards on which IC chips, packages, and semiconductor elements are mounted are compared. If the physical properties of the semiconductor element are silicon, the package is epoxy resin, and the physical properties of the circuit board on which the semiconductor element is mounted are glass epoxy resin, the linear expansion coefficient of silicon is about the linear expansion coefficient of epoxy resin or glass epoxy resin. An order of magnitude smaller. Moreover, the linear expansion coefficient of an epoxy resin and a glass epoxy resin is not necessarily the same.

  For this reason, when the temperature of the package rises due to heat generation of the semiconductor element or the like, the elongation of the circuit board becomes larger than the elongation of the package including the IC chip having a small linear expansion coefficient, and the warp as shown in FIG. Produce. When the power is turned off and the semiconductor element or the like no longer generates heat, the warp disappears. As a result, a shear stress is repeatedly applied to the ball electrode portion connecting the package and the circuit board, and strain accumulates in the ball electrode portion, leading to breakage.

  At this time, among the plurality of ball electrode portions, the stress applied to the ball electrodes disposed at the four corners of the package and the ball electrodes disposed at the boundary between the IC chip and the package tends to be large and the life tends to be short.

  The stress of the ball electrodes arranged at the four corners is high because the thermal expansion increases in proportion to the length, and therefore the linear expansion difference on the diagonal line of the package is the largest.

  In addition, the stress of the ball electrode arranged at the boundary between the IC chip and the package is high because the package is restrained by the IC chip having a small coefficient of thermal expansion near the IC chip, and the thermal expansion difference from the circuit board is large. It is to become.

  FIG. 13 is a side view showing a state in which a semiconductor element mounted on both sides of a circuit board is thermally deformed.

  As shown in FIG. 13, when a conventional semiconductor element having the same shape is mounted with 100% overlapping on both sides of the circuit board, it is as if only one side of the circuit board is mounted due to mutual interference of the semiconductor elements. Since it cannot be warped, the thermal stress applied to the ball electrode cannot be relaxed, and the life is shorter than when it is mounted only on one side.

  FIG. 14 is a side view showing a state where a semiconductor element mounted on both sides of a circuit board is thermally deformed.

  FIG. 14 shows a case in which the semiconductor elements on the front and back sides overlap with each other in a state of being shifted by approximately 25% in the horizontal direction. Unlike the case where the semiconductor elements overlap each other by 100%, complicated thermal deformation occurs.

  In the portion where the semiconductor element on the other side is present across the circuit board, warpage is unlikely to occur due to mutual interference. However, in a portion where the counterpart semiconductor element does not exist, warpage occurs because there is no interference.

  This will be described in more detail in the left part of FIG.

  As shown in FIG. 13, when the first semiconductor element 71a mounted on the circuit board surface side moves from the state where it is 100% overlapped on both sides of the circuit board to the left side of the drawing, the first semiconductor element 71a When the ball electrode comes outside the outermost ball electrode of the second semiconductor element 71b mounted on the lower surface side of the circuit board, the package starts to warp sequentially.

  That is, the first semiconductor element 71a has no interference with the second semiconductor element 71b mounted on the opposite side via the circuit board.

  As a result, a large shear stress is applied to the ball electrode, which is the outermost part of the second semiconductor element mounted on the lower surface side of the circuit board, due to the influence of the warp of the first semiconductor element.

  Further, when the edge portion of the IC chip is in a portion where the warpage of the package occurs, the difference in linear expansion coefficient from the package is large, and the influence thereof is taken into consideration and the warpage amount tends to be further increased.

  The same phenomenon occurs in the right portion of FIG.

  Next, thermal deformation due to the shape of the semiconductor element according to the present embodiment will be described.

  FIG. 3 is a side view showing a state in which a semiconductor element mounted on both sides of a circuit board is thermally deformed. A first semiconductor element is mounted on the front surface of the circuit board, and a second semiconductor element is mounted on the rear surface of the circuit board.

  FIG. 3 shows a case in which the first and second semiconductor elements are overlapped with each other while being shifted by about 25% in the horizontal direction, as shown in the plan view of FIG.

  In the portion where the semiconductor element on the other side is present across the circuit board, warpage is unlikely to occur due to mutual interference. However, in a portion where the counterpart semiconductor element does not exist, warpage occurs because there is no interference.

  Referring to the left side of FIG. 3, unlike the conventional example, by providing the package protrusion provided on the upper surface of the package, the rigidity of the portion is increased and the warpage of the package is suppressed.

  The first semiconductor element mounted on the surface side of the circuit board is smoothly deformed without abrupt warping of the package even when the interference of the counterpart second semiconductor element is eliminated.

  Thereby, the ball electrode which hits the outermost part of the 2nd semiconductor element mounted in the circuit board lower surface side does not apply a shear stress as big as the conventional example.

  The same phenomenon occurs in the right portion of FIG. 3 just by reversing the vertical relationship, and the shear stress is not as great as in the conventional example.

<Embodiment 2>
FIG. 4 is a perspective view of the semiconductor device according to the second embodiment of the present invention as viewed from the upper surface side of the package.

  The semiconductor element 20 in the semiconductor device according to the present embodiment includes an IC chip 23, a package 21, a package protrusion 22, a semiconductor element connection part 24, and a plurality of ball electrodes 26.

  A wiring for connecting the semiconductor element 20 and the plurality of ball electrodes 26 as appropriate is formed in the semiconductor element connection portion 24 in the package 21 (not shown).

  The IC chip 23 is connected to the semiconductor element junction 24 through a plurality of electrodes (not shown) provided on the back surface thereof. The material is silicon.

  The IC chip 23 is packaged by a package 21 so as to protect it. The material is, for example, an epoxy resin.

  A substantially L-shaped package protrusion 22 is provided on the upper surface of the package 21. The material is, for example, the same epoxy resin as the package material.

  The package protrusion 22 is integrally formed of the same resin as the package 21 or is formed of a separate member having high rigidity, and is bonded to the upper surface of the package 21 with an adhesive or the like.

  5A is a perspective view of the semiconductor device according to the present embodiment mounted on both sides of the circuit board, and FIG. 5B is a plan view of the semiconductor device mounted on both sides of the circuit board. FIG. 5C is a side view of the semiconductor device mounted on both sides of the circuit board.

  On the circuit circuit board 100 on which the semiconductor element 20 is mounted, terminals are provided in an array (not shown) at positions corresponding to the plurality of ball electrodes 26 and the plurality of auxiliary ball electrodes 26 of the package 21. As shown in FIG. 5C, 21 is joined to the plurality of ball electrodes 26 with solder. The material is, for example, glass epoxy resin.

  The suffix of the semiconductor element 20 in the mounted state is 20a, 21a, 22a... For the first semiconductor mounted on the front surface side, and 20b, 21b, 22b.

  As shown in FIG. 5B, the first semiconductor and the second semiconductor mounted on the front and back of the circuit board are mounted in a state where they are shifted in an oblique direction.

  An L-shaped package protrusion is provided on the surface of the package of the semiconductor element mounted on the back side of the circuit board corresponding to the position of the outermost ball electrode of the semiconductor element mounted on the front side of the circuit board.

  Also, an L-shaped package protrusion is provided on the surface of the package of the semiconductor element mounted on the front side of the circuit board corresponding to the position of the outermost ball electrode of the semiconductor element mounted on the back side of the circuit board. Yes.

  The principle of thermal deformation and the suppression of warpage by the package protrusion are the same as those described in the first embodiment.

<Embodiment 3>
6A and 6B are diagrams showing a semiconductor device according to the third embodiment of the present invention. FIG. 6A is a plan view and FIG. 6B is a side view.

  The semiconductor element 30 in the semiconductor device according to the present embodiment includes an IC chip 33, a package 31, a semiconductor element connection portion 34, and a plurality of ball electrodes 36.

  In the semiconductor element connecting portion 34 in the package 31, wiring for appropriately connecting the semiconductor element 30 and the plurality of ball electrodes 36 is configured (not shown).

  The IC chip 33 is connected to the semiconductor element junction 34 through a plurality of electrodes (not shown) provided on the back surface thereof. The material is silicon.

  The IC chip 33 is disposed at a position offset from the central portion in the package 31. The IC chip 33 is packaged by a package 31 so as to protect it. The material is, for example, an epoxy resin.

  FIG. 7A is a plan view of the semiconductor device according to the present embodiment mounted on both sides of the circuit board, and FIG. 7B is a side view of the semiconductor device mounted on both sides of the circuit board.

  The circuit circuit board 100 on which the semiconductor element 30 is mounted is provided with terminals in an array (not shown) at positions corresponding to the plurality of ball electrodes 36 and the plurality of auxiliary ball electrodes 36 of the package 31. As shown in FIG. 6B, 31 is joined to the plurality of ball electrodes 36 by solder. The material is, for example, glass epoxy resin.

  The suffixes of the semiconductor element 30 in the mounted state are 30a, 31a, 32a... For the first semiconductor mounted on the front surface side, and 30b, 31b, 32b.

  As shown in FIG. 7B, the first semiconductor and the second semiconductor mounted on the front and back of the circuit board are mounted in a state shifted from each other in the horizontal direction. The first semiconductor element mounted on the front surface of the circuit board and the IC chip of the second semiconductor element mounted on the rear surface side of the circuit board are respectively arranged at positions where they do not overlap each other.

  The principle of deformation of the semiconductor elements mounted on the front and back of the circuit board by heat is the same as described in the first embodiment. In the part where the semiconductor element on the other side exists with the circuit board in between, mutual interference is present. It is difficult for warp to occur. However, in a portion where the counterpart semiconductor element does not exist, warpage occurs because there is no interference. This becomes conspicuous in a state where IC chips having higher rigidity are overlapped.

  Furthermore, since there is a difference in the coefficient of linear expansion at the boundary between the IC chip and the package, the warpage of the package tends to increase. As shown in the conventional example of FIG. 13, if the outermost solder bumps of the second semiconductor element are present at the edge part of the IC chip of the first semiconductor element and the part that hits the opposite side through the circuit board, A large shear stress is applied to the outermost solder bump.

  Next, thermal deformation of the semiconductor element in this embodiment will be described.

  FIG. 8 is a side view showing a state where a semiconductor element mounted on both sides of a circuit board is thermally deformed. A first semiconductor element 30a is mounted on the surface of the circuit board, and a second semiconductor element 30b is mounted on the back surface of the circuit board.

  FIG. 8 shows a case where the first and second semiconductor elements overlap with each other in a state of being shifted by approximately 25% in the horizontal direction, as shown in the plan view of FIG.

  Unlike the conventional example, since there is no overlapping portion between the high-rigidity IC chips, the first semiconductor element and the second semiconductor element can warp relatively freely in the part where the own IC chip exists. .

  Further, since the package tries to follow the warp of the other IC chip portion having a high rigidity, there is little phenomenon of restraining the warpage of the package.

  As a result, the ball electrode mounted on the lower surface side of the circuit board on the left side of FIG. 8 is not subjected to a shear stress as great as that of the conventional example.

  The same phenomenon occurs in the right portion of FIG. 8 just by reversing the vertical relationship, and the shear stress is not as great as in the conventional example.

<Embodiment 4>
9A and 9B are diagrams showing a semiconductor device according to the fourth embodiment of the present invention. FIG. 9A is a plan view and FIG. 9B is a side view.

  The semiconductor element 40 in the semiconductor device according to the present embodiment includes an IC chip 43, a package 41, a semiconductor element connection portion 44, and a plurality of ball electrodes 46.

  In the semiconductor element connecting portion 44 in the package 41, wirings for appropriately connecting the semiconductor element 40 and the plurality of ball electrodes 46 are configured (not shown).

  The IC chip 43 is connected to the semiconductor element junction 44 through a plurality of electrodes (not shown) provided on the back surface thereof. The material is silicon. The IC chip 43 is disposed at a position offset from the central portion in the package 41.

  The IC chip 43 is packaged by a package 41 so as to protect it. The material is, for example, an epoxy resin.

  FIG. 10A is a plan view showing a state in which the semiconductor device according to the present embodiment is mounted on both sides of the circuit board, and FIG. 10B is a side view of the state in which the semiconductor device is mounted on both sides of the circuit board.

  On the circuit circuit board 100 on which the semiconductor element 40 is mounted, terminals are provided in an array (not shown) at positions corresponding to the plurality of ball electrodes 46 and the plurality of auxiliary ball electrodes 46 of the package 41, and the package 41, as shown in FIG. 10B, the plurality of ball electrodes 46 are joined by solder. The material is, for example, glass epoxy resin.

  The suffix of the semiconductor element 40 in the mounted state is 40a, 41a, 42a ... for the first semiconductor mounted on the front surface side, and 40b, 41b, 42b ... for the second semiconductor mounted on the back surface side. .

  As shown in FIG. 10B, the first semiconductor and the second semiconductor mounted on the front and back of the circuit board are mounted in a state where they are shifted in an oblique direction. The first semiconductor element mounted on the front surface of the circuit board and the second semiconductor element mounted on the rear surface side of the circuit board are arranged at positions where the IC chips do not overlap each other.

  In the present embodiment, the first and second semiconductor elements mounted on the front and back of the circuit board have been described as having substantially the same shape, but they may have different shapes.

It is the perspective view which looked at the semiconductor device which concerns on Embodiment 1 of this invention from diagonally upward. (A) is a perspective view of a state in which the semiconductor device according to the first embodiment of the present invention is mounted on both sides of the circuit board, (b) a plan view of the state in which the semiconductor device is mounted on both sides of the circuit board, c) is a side view of the semiconductor device mounted on both sides of the circuit board. It is sectional drawing which shows the state which what thermally mounted the thing which mounted the semiconductor element on both surfaces of the circuit board. It is the perspective view which looked at the semiconductor device which concerns on Embodiment 2 of this invention from diagonally upward. (A) is a perspective view of the state which mounted the semiconductor device based on Embodiment 2 of this invention on both surfaces of a circuit board, (b) is a top view of the state which mounted the semiconductor device on both surfaces of the circuit board, (c) FIG. 3 is a side view of the semiconductor device mounted on both sides of the circuit board. (A) is the top view which looked at the semiconductor device based on Embodiment 3 of this invention from the package upper surface, (b) is the side view of the semiconductor device. (A) is a top view of the state which mounted the semiconductor device based on Embodiment 3 of this invention in the circuit board, (b) is a side view of the state which mounted the semiconductor device in the circuit board. It is sectional drawing which shows the state which what mounted the semiconductor device which concerns on Embodiment 3 of this invention on both surfaces of the circuit board was thermally deformed. (A) is the top view which looked at the semiconductor device based on Embodiment 4 of this invention from the package upper surface, (b) is the side view of the semiconductor device. (A) is a top view of the state which mounted the semiconductor device based on Embodiment 4 of this invention in the circuit board, (b) is a side view of the state which mounted the semiconductor device in the circuit board. (A) is a top view of the state which mounted the semiconductor device of the prior art example on both surfaces of the circuit board, (b) is a side view of the state which mounted the semiconductor device on both surfaces of the circuit board. It is a side view which shows the state which what thermally mounted the thing which mounted the conventional semiconductor element on the single side | surface of a circuit board. It is a side view which shows the state which what thermally mounted the thing which mounted the semiconductor element on both surfaces of the circuit board. It is sectional drawing which shows the state which what thermally mounted the thing which mounted the semiconductor element on both surfaces of the circuit board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor element 11 Package 12 Package protrusion part 13 IC chip 14 Semiconductor element connection part 16 Ball electrode 20 Semiconductor device 30 Semiconductor device 40 Semiconductor device 100 Circuit board

Claims (7)

  Semiconductor elements arranged on both sides of the circuit board, and protruding on the upper surface of the package of the second semiconductor element located on the opposite side at a position corresponding to the outermost ball electrode portion of the first semiconductor element via the circuit board A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the protrusion on the package of the second semiconductor element is a rectangular parallelepiped.   2. The semiconductor device according to claim 1, wherein the protrusion on the upper surface of the package of the second semiconductor element is made of the same member as the package.   2. The semiconductor device according to claim 1, wherein the protrusion on the upper surface of the package of the second semiconductor element is made of a member different from the package.   The semiconductor element is arranged horizontally shifted on both sides of the circuit board, and corresponds to the outermost ball electrode part of the first semiconductor element and the outermost ball electrode part of the second semiconductor element through the circuit board, respectively. A protrusion is provided on the upper surface of the package of each of the first semiconductor element and the second semiconductor element located on opposite sides of the semiconductor device.   The semiconductor device includes semiconductor elements arranged obliquely on both sides of the circuit board, and each corresponds to the outermost ball electrode part of the first semiconductor element and the outermost ball electrode part of the second semiconductor element via the circuit board. A semiconductor device characterized in that an L-shaped protrusion is provided on the upper surface of the package of the first semiconductor element and the second semiconductor element located on the opposite sides.   A semiconductor element is disposed on both sides of the circuit board so that a part of the circuit board overlaps, and the IC chip of the first semiconductor element and the IC chip of the second semiconductor element are arranged at positions that do not overlap each other via the circuit board. A semiconductor device characterized by the above.

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