CN110211946A - A kind of chip-packaging structure and its manufacturing method - Google Patents
A kind of chip-packaging structure and its manufacturing method Download PDFInfo
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- CN110211946A CN110211946A CN201910520072.1A CN201910520072A CN110211946A CN 110211946 A CN110211946 A CN 110211946A CN 201910520072 A CN201910520072 A CN 201910520072A CN 110211946 A CN110211946 A CN 110211946A
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- chip
- pinboard
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- hole
- conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The invention discloses a kind of chip-packaging structures, comprising: plastic packaging layer；First chip, first chip are coated in the plastic packaging layer, and first chip has the first chip bonding pad；Pinboard, the first face of the pinboard are connected with the plastic packaging layer, the first chip back, and the pinboard has chip embedded groove and conductive through hole；Lead, the lead are electrically connected first chip bonding pad to the conductive through hole；Second chip, second chip are arranged in the chip embedded groove of the pinboard, and second chip and first chip are back-to-back；Filler layer, the filler layer fills the gap between second chip and the chip embedded groove, and covers second chip in addition to the second chip bonding pad position；Again the second face of the pinboard is arranged in placement-and-routing's layer, and the placement-and-routing again layer is electrically connected with the conductive through hole, second chip bonding pad；The second face of the pinboard is arranged in dielectric layer, the dielectric layer, interlayer and the intermetallic insulation protection of same layer for the layer of placement-and-routing again；And external soldered ball, the external soldered ball are electrically connected with the layer of placement-and-routing again.
Description
Technical field
The present invention relates to chip encapsulation technology field more particularly to a kind of chip-packaging structure and its manufacturing methods.
Background technique
The development miniaturised with electronic product, multi-chip realize the scheme of interconnection many by PCB substrate
In the case of gradually by multi-chip module (MCM) replace.Multi-chip module (MCM) refers to that multiple IC chips are electrically connected to altogether
It on circuit substrate, and realizes using it the component of inter-chip interconnection, is a kind of typical highly integrated component.In these components
Each chip generally use wire bonding, carrier band bonding or flip-chip mode unsealing be assembled in the substrate of multilayer interconnection
On, then encapsulating structure is formed by plastic packaging.It is directly installed on PCB compared with by chip, MCM has certain advantage.Such as:
(1) chip chamber transmission path is shortened, performance is improved, while there is low power supply self-induction, low capacitor, low crosstalk and low driving
The advantages that voltage；(2) has the advantages that miniaturization and multi-functional, and the I/O number of system circuit board is reduced；It (3) can be extensive
Applied to specific integrated circuit, product especially with short production cycle.(4) mixed type encapsulating structure can be achieved, form functional group
Part module.(5) product reliability is improved.
Although multi-chip module has many advantages, such as, existing multichip packaging structure is still based on substrate, lead key
The technologies such as conjunction realize that the interconnection distance between encapsulation volume, multi-chip is also relatively large.
There is smaller encapsulation volume, smaller signal delay after multi-chip is integrated in order to realize, the present invention proposes one kind
It is integrated to realize multi-chip, and further reduces the volume of multichip packaging structure for chip-packaging structure and its manufacturing method, subtract
Small multichip interconnection distance, reduces signal delay.
Summary of the invention
For existing multi-chip module there is also encapsulation volume it is also larger, inter-chip interconnection distance also longer, multicore
The problems such as signal delay between piece, according to an aspect of the present invention, provide a kind of chip-packaging structure, comprising:
Plastic packaging layer；
First chip, first chip are coated in the plastic packaging layer, and first chip is welded with the first chip
Disk；
Pinboard, the first face of the pinboard are connected with the plastic packaging layer, the first chip back, and the pinboard has
Chip embedded groove and conductive through hole；
Lead, the lead are electrically connected first chip bonding pad to the conductive through hole；
Second chip, second chip are arranged in the chip embedded groove of the pinboard, and second core
Piece and first chip are back-to-back；
Filler layer, the filler layer fills the gap between second chip and the chip embedded groove, and covers and remove
Second chip outside second chip bonding pad position；
Again the second face of the pinboard is arranged in placement-and-routing's layer, and the placement-and-routing again layer is led with described
Electric through-hole, second chip bonding pad electrical connection；
The second face of the pinboard is arranged in dielectric layer, the dielectric layer, the layer for the layer of placement-and-routing again
Between and the intermetallic insulation protection of same layer；And
External soldered ball, the external soldered ball are electrically connected with the layer of placement-and-routing again.
In one embodiment of the invention, the material of the plastic packaging layer is epoxy resin or solidification glue or EMC.
In one embodiment of the invention, there are M the first chips, wherein M >=2.
In one embodiment of the invention, the pinboard is silicon substrate pinboard.
In one embodiment of the invention, the conductive through hole of the pinboard is conduction copper column.
In one embodiment of the invention, the material of the lead is gold, copper, aluminium or combinations thereof.
In one embodiment of the invention, the filler layer covers entire second face of the pinboard.
In one embodiment of the invention, the layer of placement-and-routing again has N layers, wherein N >=2.
According to another aspect of the present invention, a kind of manufacturing method of chip-packaging structure is provided, comprising:
Pinboard is provided, the pinboard has chip embedded groove and conductive through hole, wherein the conductive through hole is blind hole；
By the first chip patch to the pinboard, and the chip bonding pad of the first core described in wire bonding is to the pinboard
Conductive through hole；
Plastic packaging is carried out to the first chip, forms plastic packaging layer；
The back side for carrying out pinboard carries out processing of appearing, and realizes the back side leakage of the conductive through hole and chip embedded groove of pinboard
Out；
The patch of the second chip, the second chip and first after patch are carried out in the chip embedded groove that switching back leaks out
The back-to-back fitting of chip；
The second chip filler is carried out, filler layer is formed, completes the wafer reconstruct of pinboard；
The bonding pad opening of the second chip is formed in filler layer；And
The leakage face of pinboard after reconstitution forms again placement-and-routing's layer, dielectric layer and external soldered ball.
In another embodiment of the present invention, it while forming the bonding pad opening of the second chip in filler layer, is formed
The opening of pinboard conductive through hole.
The present invention provides a kind of chip-packaging structure and its manufacturing method, is embedded in groove and conductive through hole using with chip
Pinboard, the first chip patch is connected to pinboard, followed by leading for wire bonding interconnection die pad to pinboard
Electric through-hole and plastic packaging；Then it carries out the back side to pinboard to appear, to leak out the chip embedded groove and conductive through hole of pinboard；It connects
Get off to carry out the second chip patch and filler plastic packaging in chip embedded groove；Then again by placement-and-routing again, by multi-chip
On small salient point be fanned out to, and be converted into big salient point.Had such as based on this kind of chip-packaging structure of the invention and its manufacturing method
Lower advantage: 1) it is integrated that multi-chip can be achieved；2) substrate is substituted using the pinboard of microarray strip insertion groove, production capacity is higher；3) it seals
The encapsulation volume of assembling structure is smaller；4) interconnection line between multi-chip is apart from shorter, signal delay is smaller.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, identical or corresponding component will use identical or class
As mark indicate.
Fig. 1 shows a kind of diagrammatic cross-section of the chip-packaging structure 100 formed according to one embodiment of present invention.
Fig. 2A to Fig. 2 H shows the process section for forming this kind of chip-packaging structure 100 according to one embodiment of present invention
Schematic diagram.
Fig. 3 shows the flow chart 300 for forming this kind of chip-packaging structure 100 according to one embodiment of present invention.
Fig. 4 shows a kind of diagrammatic cross-section of the chip-packaging structure 400 formed according to still another embodiment of the invention.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In the present specification, the reference of " one embodiment " or " embodiment " is meaned to combine embodiment description
A particular feature, structure, or characteristic is included at least one embodiment of the invention.Occur in everywhere in this specification short
Language " in one embodiment " is not necessarily all referring to the same embodiment.
It should be noted that the embodiment of the present invention is described processing step with particular order, however this is only
Facilitate and distinguish each step, and is not the sequencing for limiting each step, it in different embodiments of the invention, can be according to work
Skill is adjusted to adjust the sequencing of each step.
The present invention provides a kind of chip-packaging structure and its manufacturing method, is embedded in groove and conductive through hole using with chip
Pinboard, the first chip patch is connected to pinboard, followed by leading for wire bonding interconnection die pad to pinboard
Electric through-hole and plastic packaging；Then it carries out the back side to pinboard to appear, to leak out the chip embedded groove and conductive through hole of pinboard；It connects
Get off to carry out the second chip patch and filler plastic packaging in chip embedded groove；Then again by placement-and-routing again, by multi-chip
On small salient point be fanned out to, and be converted into big salient point.Had such as based on this kind of chip-packaging structure of the invention and its manufacturing method
Lower advantage: 1) it is integrated that multi-chip can be achieved；2) substrate is substituted using the pinboard of microarray strip insertion groove, production capacity is higher；3) it seals
The encapsulation volume of assembling structure is smaller；4) interconnection line between multi-chip is apart from shorter, signal delay is smaller.
A kind of chip-packaging structure according to an embodiment of the invention is discussed in detail below with reference to Fig. 1.Fig. 1 is shown
A kind of diagrammatic cross-section of the chip-packaging structure 100 formed according to one embodiment of present invention.As shown in Figure 1, the chip
Encapsulating structure 100 further comprises plastic packaging layer 110, the first chip 120, lead 130, pinboard 140, the second chip 150, filler
Layer 160, again placement-and-routing's layer 170, dielectric layer 180 and external soldered ball 190.
The first face of the chip-packaging structure 100 is arranged in plastic packaging layer 110.In one embodiment of the invention, plastic packaging
The material of layer 110 can be the materials such as epoxy resin, solidification glue, EMC.
First chip 120 is coated by plastic packaging layer 110, and the first chip 120 further comprises the first chip bonding pad 121.At this
In one embodiment of invention, the first chip 120 can be the logical operations chips such as processor, DSP, FPGA, AI chip, can also
To be the special chips such as memory, sensor.In one particular embodiment of the present invention, the first chip 120 can be one
Or it is multiple, when being multiple first chips 120, these first chips 120 can be similar chip (as being all logical operation chip),
It may be non-similar chip.
Lead 130 is for being electrically interconnected the first chip 120 to pinboard 130.Particularly by wire bonding, formed from the
First chip bonding pad 121 of one chip 120 arrives the conductive through hole 142 of pinboard 140.In one embodiment of the invention, draw
Line 130 can be gold thread, copper wire or alloy wire.
The top of plastic packaging layer 110 is arranged in pinboard 140, and the first face of pinboard 140 is adjacent with plastic packaging layer 110, switching
Plate 140 further has chip insertion groove 141 and conductive through hole 142；Wherein the of conductive through hole 142 and the first chip 120
The electrical connection of one chip bonding pad 121.In one embodiment of the invention, pinboard 140 is silicon substrate pinboard.In its of the invention
In his embodiment, the pinboard of the other materials such as pinboard 140 or glass.In a specific embodiment of the invention
In, can also have multiple chip insertion grooves 141 and multiple groups conductive through hole 142.
Second chip 150 is arranged in the chip embedded groove 141 of pinboard 140, the second chip bonding pad of the second chip 150
151 upward, to form the second chip 150 and the back-to-back mounting structure of the first chip 120.It is similar with preceding description, it can be with
Multiple second chips 150 are set in the chip embedded groove 141 of pinboard 140.Under normal conditions, second chip 150 is set
Set in a corresponding chip embedded groove 141, but can also by the way that the chip embedded groove 141 of larger size is arranged, so as to
Multiple second chips 150 are embedded into same chip embedded groove 141.In another embodiment of the present invention, the second chip 150
By the back side of first chip 120 of the Heraeus patch into chip embedded groove 141, therefore in the second chip 150 and the first core
There is a glue-line between piece 120.
Filler layer 160 is disposed over the gap between the chip embedded groove 141 of pinboard 140 and the second chip 150, from
And keep the second face of pinboard 140 smooth, realize wafer quality reconstruction.The material of filler layer 160 can for resin, EMC or
Bottom filler material.
Again placement-and-routing's layer 170 is arranged on the second face of pinboard 140, again placement-and-routing's layer 170 and pinboard
Second chip bonding pad 151 of conductive through hole 142 and the second chip 150 in 140 is electrically connected, and further passes through conductive through hole
142 realize the electricity and/or signal interconnection with the first chip 120.In one embodiment of the invention, again placement-and-routing layer 170
It can be one or more layers, wherein first layer wiring layer has the mutual of the second chip soldered ball 151 for being electrically connected to the second chip 150
Link structure 171；External pad (not indicating in figure) is provided in outermost wiring layer.
Dielectric layer 180 is arranged on the second face of pinboard 140, the interlayer and same layer for the layer of placement-and-routing again 170
Insulation protection and mechanical support between metal wire.
External soldered ball 190 be arranged in outermost layer again placement-and-routing layer 170 external pad on.External soldered ball 190 can be with
It is formed by planting the techniques such as ball, plating.In one embodiment of the invention, external soldered ball 190 can for lead-free solder ball or
Copper post.
The process to form this kind of chip-packaging structure 100 is described in detail below with reference to Fig. 2A to Fig. 2 H and Fig. 3.Fig. 2A
The process diagrammatic cross-section for forming this kind of chip-packaging structure 100 according to one embodiment of present invention is shown to Fig. 2 H；Fig. 3 shows
Out be the flow chart 300 for forming this kind of chip-packaging structure 100 according to one embodiment of present invention.
Firstly, as shown in Figure 2 A, providing pinboard 210 in step 310.Pinboard 210 has 211 He of chip embedded groove
Conductive through hole 212, wherein conductive through hole 212 is blind hole, and open end is in the 211 place face of chip embedded groove of pinboard 210.?
In a specific embodiment of the invention, chip embedded groove 211, core are formed in pinboard 210 by image conversion etching technics
Piece embedded groove 211 can be one or more, and specific size and position determine according to the design needs.In another reality of the invention
It applies in example, conductive through hole 212 is formed by through-hole, conductive fill, and concrete technology can be selected from photoetching, etching/laser via, plating
The techniques such as seed layer deposition, plating, removal seed layer are formed.
Next, in step 320, as shown in Figure 2 B, by 220 patch of the first chip to pinboard 210, and wire bonding
One chip 220 to pinboard 210 conductive through hole.First chip 220 has the first chip bonding pad 221, wherein the first chip welds
Disk 221 is electrically connected by lead 230 with the conductive through hole 212 of pinboard 210.In one embodiment of the invention, lead key
The material for closing the lead 230 that technique uses can be selected from gold, copper, aluminium or combinations thereof etc., 220 patch of the first chip to pinboard
210 can be realized by Heraeus (not shown).In another embodiment of the present invention, the first chip 220 can be place
The logical operations chips such as device, DSP, FPGA, AI chip are managed, the special chips such as memory, sensor are also possible to, can also be one
A or multiple chips can be same type chip or different type chip when not multiple chips.
Then, in step 330, as shown in Figure 2 C, plastic packaging is carried out to the first chip 220, forms plastic packaging layer 240.Plastic packaging layer
240 material can be the materials such as epoxy resin, solidification glue, EMC.
Next, in step 340, as shown in Figure 2 D, the back side for carrying out pinboard 210 is appeared processing, realization pinboard 210
Conductive through hole 212 and chip embedded groove 211 leakage.The works such as etching, CMP can be passed through in one embodiment of the invention
Skill realizes that the back side of pinboard 210 is appeared processing.
Then, in step 350, as shown in Figure 2 E, the second chip 250 is carried out in the chip embedded groove 211 of pinboard 210
Patch, the second chip 250 forms back-to-back be bonded with the first chip 220 after patch.In one embodiment of the invention,
Two chips 250 pass through Heraeus patch to the back side of the first chip 220.
Next, as shown in Figure 2 F, carrying out 250 filler of the second chip in step 360, forming filler layer 260.Filler layer
Gap between the chip embedded groove 211 and the second chip 250 of 260 filling pinboards 210, to make the exposed of pinboard 210
Face is smooth, realizes wafer quality reconstruction.The material of filler layer 260 can be resin, EMC or other bottom filler materials.
Then, in step 370, as shown in Figure 2 G, the bonding pad opening 261 of the second chip 250 is formed in filler layer 260.
Specific hatch method can be formed by modes such as etching, mechanical through hole, laser vias.
Finally, as illustrated in figure 2h, the leakage face of pinboard 210 after reconstitution forms placement-and-routing again in step 380
Layer 270, dielectric layer 280 and external soldered ball 290.Again placement-and-routing's layer 270 and the conductive through hole 212 of pinboard 210 and
Second chip soldered ball 251 (being realized by through-hole interconnection 271) of the second chip 250 is electrically connected；Further pass through conductive through hole 212
And realize the electricity and/or signal interconnection with the first chip 220；The external setting of soldered ball 280 is in outermost layer again placement-and-routing layer 270
Pad (not shown) on；Dielectric layer 280 for the insulation protection between placement-and-routing's interlayer or the conducting wire of same layer again and
Mechanical support effect.Again placement-and-routing's layer 270 realizes the first chip 220 and the IO of the second chip 250 is fanned out to.In the present invention
One embodiment in, placement-and-routing's layer 270 can be one or more layers again.Specific formation process can be electroplating technology.
A kind of chip-packaging structure according to still another embodiment of the invention is discussed in detail in conjunction with Fig. 4 below.Fig. 4 shows
A kind of diagrammatic cross-section of the chip-packaging structure 400 formed according to still another embodiment of the invention out.As shown in figure 4, the core
Chip package 400 further comprises plastic packaging layer 410, the first chip 420, lead 430, pinboard 440, the second chip 450, fills out
Glue-line 460, again placement-and-routing's layer 470, dielectric layer 480 and external soldered ball 490.Itself and chip-packaging structure shown in FIG. 1
100, which do not exist together, is only that the surface of entire pinboard 440 is completely covered in its filler layer 460, and coats the second chip 450, realizes
Wafer reconstruct.
Based on this kind of chip-packaging structure provided by the invention and its manufacturing method, it is embedded in groove using with chip and leads
First chip patch is connected to pinboard by the pinboard of electric through-hole, followed by wire bonding interconnection die pad to switching
The conductive through hole and plastic packaging of plate；Then it carries out the back side to pinboard to appear, to leak out the chip embedded groove and conduction of pinboard
Through-hole；Next the second chip patch and filler plastic packaging are carried out in chip embedded groove；It then, will again by placement-and-routing again
Small salient point in multi-chip is fanned out to, and is converted into big salient point.Based on this kind of chip-packaging structure of the invention and its manufacturing method
Have the advantages that multi-chip, which 1) can be achieved, to be integrated；2) substrate is substituted using the pinboard of microarray strip insertion groove, production capacity is more
It is high；3) encapsulation volume of encapsulating structure is smaller；4) interconnection line between multi-chip is apart from shorter, signal delay is smaller.
Although described above is various embodiments of the present invention, however, it is to be understood that they are intended only as example to present
, and without limitation.For those skilled in the relevant art it is readily apparent that various combinations, modification can be made to it
Without departing from the spirit and scope of the invention with change.Therefore, the width of the invention disclosed herein and range should not be upper
It states disclosed exemplary embodiment to be limited, and should be defined according only to the appended claims and its equivalent replacement.
Claims (10)
1. a kind of chip-packaging structure, comprising:
Plastic packaging layer；
First chip, first chip are coated in the plastic packaging layer, and first chip has the first chip bonding pad；
Pinboard, the first face of the pinboard are connected with the plastic packaging layer, the first chip back, and the pinboard has chip
Embedded groove and conductive through hole；
Lead, the lead are electrically connected first chip bonding pad to the conductive through hole；
Second chip, second chip are arranged in the chip embedded groove of the pinboard, and second chip with
First chip is back-to-back；
Filler layer, the filler layer fills the gap between second chip and the chip embedded groove, and covers and remove second
Second chip outside chip bonding pad position；
Again the second face of the pinboard is arranged in placement-and-routing's layer, and the placement-and-routing again layer and the conduction are logical
Hole, second chip bonding pad electrical connection；
The second face of the pinboard is arranged in dielectric layer, the dielectric layer, for the placement-and-routing again layer interlayer and
The intermetallic insulation protection of same layer；And
External soldered ball, the external soldered ball are electrically connected with the layer of placement-and-routing again.
2. chip-packaging structure as described in claim 1, which is characterized in that the material of the plastic packaging layer is for epoxy resin or admittedly
Change glue or EMC.
3. chip-packaging structure as described in claim 1, which is characterized in that there are M the first chips, wherein M >=2.
4. chip-packaging structure as described in claim 1, which is characterized in that the pinboard is silicon substrate pinboard.
5. chip-packaging structure as described in claim 1, which is characterized in that the conductive through hole of the pinboard is conductive copper
Column.
6. chip-packaging structure as described in claim 1, which is characterized in that the material of the lead is gold, copper, aluminium or its group
It closes.
7. chip-packaging structure as described in claim 1, which is characterized in that the filler layer covers the entire of the pinboard
Second face.
8. chip-packaging structure as described in claim 1, which is characterized in that the layer of placement-and-routing again has N layers, wherein
N≥2。
9. a kind of manufacturing method of chip-packaging structure, comprising:
Pinboard is provided, the pinboard has chip embedded groove and conductive through hole, wherein the conductive through hole is blind hole；
By the first chip patch to the pinboard, and chip bonding pad the leading to the pinboard of the first core described in wire bonding
Electric through-hole；
Plastic packaging is carried out to the first chip, forms plastic packaging layer；
The back side for carrying out pinboard carries out processing of appearing, and the back side of the conductive through hole and chip embedded groove of realizing pinboard leaks out；
The patch of the second chip, the second chip and the first chip after patch are carried out in the chip embedded groove that switching back leaks out
Back-to-back fitting；
The second chip filler is carried out, filler layer is formed, completes the wafer reconstruct of pinboard；
The bonding pad opening of the second chip is formed in filler layer；And
The leakage face of pinboard after reconstitution forms again placement-and-routing's layer, dielectric layer and external soldered ball.
10. the manufacturing method of chip-packaging structure as claimed in claim 9, which is characterized in that form second in filler layer
While the bonding pad opening of chip, the opening of pinboard conductive through hole is formed.
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| CN201910520072.1A CN110211946A (en) | 2019-06-17 | 2019-06-17 | A kind of chip-packaging structure and its manufacturing method |
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| CN110783327A (en) * | 2019-10-24 | 2020-02-11 | 中芯集成电路（宁波）有限公司 | Wafer level system packaging method and packaging structure |
| CN111613585A (en) * | 2020-05-28 | 2020-09-01 | 华进半导体封装先导技术研发中心有限公司 | Chip packaging structure and method |
| WO2021115377A1 (en) * | 2019-12-13 | 2021-06-17 | 中兴通讯股份有限公司 | Packaging method, packaging structure and packaging module |
| CN116190349A (en) * | 2023-04-25 | 2023-05-30 | 甬矽电子(宁波)股份有限公司 | Semiconductor packaging structure and preparation method thereof |
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