CN104851816A - Method for packaging multiple chips in high density - Google Patents

Method for packaging multiple chips in high density Download PDF

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Publication number
CN104851816A
CN104851816A CN201510173636.0A CN201510173636A CN104851816A CN 104851816 A CN104851816 A CN 104851816A CN 201510173636 A CN201510173636 A CN 201510173636A CN 104851816 A CN104851816 A CN 104851816A
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China
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wafer
chip
multi
metal
high
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CN201510173636.0A
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Chinese (zh)
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宋崇申
张文奇
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华进半导体封装先导技术研发中心有限公司
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Priority to CN201510173636.0A priority Critical patent/CN104851816A/en
Publication of CN104851816A publication Critical patent/CN104851816A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

The invention discloses a method for packaging multiple chips in a high density. The method comprises the following steps of: 1) using a silicon wafer as a substrate material and processing multilayer metal interconnection, metallic bonding pads, and an insulated layer on the surface of the silicon wafer; 2) mounting the multiple chip in a wafer-level way and in a surface-mounting manner and performing wafer-level plastic packaging on the mounting surface of the silicon wafer equipped with the chips; 3) removing the substrate material of the silicon wafer until the insulated layer under the multilayer metal interconnection is exposed; 4) performing graphical treatment on the insulated layer under the multilayer metal interconnection in order to expose the bottom metal of the multilayer metal interconnection; 5) processing metallic solder balls on a back surface of the silicon wafer, wherein the metallic solder balls are electrically connected with the bottom metal of the multilayer metal interconnection; and 6) cutting the silicon wafer which has been subjected to the wafer-level process in order to obtain discrete packaging bodies or integrated devices. The method has advantages of high integration density, convenient processing, low cost, and low high-frequency loss.

Description

一种多芯片高密度封装方法 A multi-chip high-density packaging method

技术领域 FIELD

[0001] 本发明属于电子封装技术领域,尤其涉及一种多芯片高密度封装方法。 [0001] The present invention belongs to the technical field of electronic packages, particularly to a high density multi-chip packaging method.

背景技术 Background technique

[0002]目前,现有的多芯片高密度封装方法均存在一些限制或问题: [0002] Currently, conventional multi-chip high-density packaging methods have problems or limitations:

[0003] I)倒装封装(Flip chip),要实现高密度需要加工高密度封装基板,一方面细线宽细间距加工困难,另一方面封装基板容易翘曲,高密度组装困难; [0003] I) flip-chip package (Flip chip), the processing required to achieve high-density high-density package board, on the one hand a thin line width of fine pitch processing difficulties, the package substrate is likely to warp on the other hand, difficult to assemble a high density;

[0004] 2)扇出型晶圆级封装(Fan-out),塑封后在芯片正面进行布线加工,由于衬底翘曲及对位偏差,细线宽,多层再布线层(RDL)加工困难; [0004] 2) fan-out type wafer level package (Fan-out), after wiring processing in plastic chip front side, and the warping of the substrate due to the alignment deviation, a thin line width, the multilayer rewiring layer (RDL) processing difficult;

[0005] 3)2.封装,需使用TSV(Through Silicon Vias,硅通孔),工艺复杂,成本高,且TSV在硅衬底内传输,存在衬底损耗,不利于高频应用。 [0005] 3) 2. Package, use TSV (Through Silicon Vias, TSV), process complexity, high cost, and TSV transmission loss of the substrate is present in the silicon substrate, is not conducive to high frequency applications.

发明内容 SUMMARY

[0006] 本发明的目的在于提供一种多芯片高密度封装方法,其具有集成密度高、加工方便、成本低和高频损耗小的特点,以解决现有技术中多芯片高密度封装存在的上述问题。 [0006] The object of the present invention is to provide a high density multi-chip packaging method, which has a high integration density, easy processing, low cost and small high-frequency loss characteristics, in order to solve the prior art high-density multi-chip package of the present the above-mentioned problems.

[0007] 为达此目的,本发明采用以下技术方案: [0007] To achieve this object, the present invention employs the following technical solution:

[0008] 一种多芯片高密度封装方法,其包括以下步骤: [0008] A high density multi-chip packaging method, comprising the steps of:

[0009] I)以娃晶圆作为衬底材料,在娃晶圆表面加工多层金属互连及金属焊盘,在所述多层金属与硅衬底之间包含一层绝缘材料; [0009] I) In Wa of the wafer as the substrate material, and metal interconnect processing of multi-layer metal pad baby wafer surface between the multilayer metal and silicon substrate comprising a layer of insulating material;

[0010] 2)将多芯片以晶圆级的形式进行贴装,每个集成区域至少贴装2颗芯片,并对贴有芯片的硅晶圆的贴装面进行晶圆级塑封处理,将所贴装芯片均包覆在注塑材料中; [0010] 2) The multi-chip wafer level form placement, each of at least two integrated chip mounting region, and wafer level processing plastic affixed silicon chip mounting surface, the the coated chips are mounted in an injection molding material;

[0011] 3)将所述硅晶圆的衬底材料全部去除,直至暴露多层金属互连下面的绝缘材料; [0011] 3) The substrate material of the silicon wafer is completely removed until a multilayer metal interconnects exposed underlying insulating material;

[0012] 4)对多层金属互连下面的绝缘材料进行图形化处理,形成绝缘层窗口,在窗口内暴露所述多层金属互连的最底层金属; [0012] 4) The multilayer metal interconnects on an insulating material following patterning process, the insulating layer is formed a window, the window is exposed in the multi-layer metal interconnection metal bottom;

[0013] 5)在背面加工金属焊球,所述金属焊球经由绝缘层窗口与所述多层金属互连的最底层金属形成电连接; [0013] 5) a metal ball at the rear face, electrically connected to the metal ball formation via the bottom of the window and the metal insulating layer of the multilayer metal interconnect;

[0014] 6)对完成晶圆级工艺的晶圆进行切割,获得分立的封装体或集成器件。 [0014] 6) of the wafer-level processing is completed wafer is cut to obtain a discrete device or integrated package.

[0015] 特别地,所述步骤6)中的对晶圆切割完成后获得分立的集成器件,将所述分立的集成器件以倒装的形式进一步在有机基板上组装,最终形成封装体。 [0015] Specifically, the step 6) is obtained on the wafer after completion of cutting discrete integrated device, said device further separate integrated on the organic substrate in a flip-chip assembled, eventually forming the package.

[0016] 特别地,所述步骤2)中将多芯片以晶圆级的形式进行贴装的方式采用基于焊料凸点的热压键合方式或金属直接键合方式的任一种。 [0016] In particular, the step 2) in the multi-chip mounting manner of wafer level using any of a form of embodiment of a direct bond or a thermocompression bonding method of a metal based solder bumps.

[0017] 特别地,所述步骤2)中多芯片以晶圆级的形式采用热压键合方式进行贴装,在多芯片热压键合之后,于焊点之外的区域填充底填树脂并固化,以提高焊点的可靠性。 [0017] In particular, the step 2) in a multi-chip mounting manner thermocompression bonding to form a wafer-level, multi-chip after the thermocompression bonding, the region outside the solder joint underfill resin filling and cured to improve the reliability of solder joints.

[0018] 特别地,所述步骤2)中在硅晶圆的贴装面进行晶圆级塑封处理后,还包括对塑封材料表面进行平整化处理,以形成平坦的上表面。 After [0018] In particular, said step is carried out at wafer level processing plastic mounting surface of the silicon wafer 2), the process further comprising planarizing the surface of plastic material to form a flat upper surface.

[0019] 特别地,所述步骤3)中将所述硅晶圆的衬底材料全部去除,具体的去除方法为:用研磨的方式将衬底硅厚度减少到50um以下,然后进行表面抛光处理,抛光方式可以是干法抛光或化学机械研磨的任一种,之后采用湿法腐蚀或干法刻蚀的方式,将剩余薄层硅全部去除。 [0019] In particular, the substrate material of the step) in the complete removal of said silicon wafer 3, concrete removal method: trituration manner to reduce the thickness of 50um or less the silicon substrate, and then subjected to surface polishing treatment polishing manner may be either a dry polishing or chemical mechanical polishing, wet etching using the following etching or dry manner, all of the remaining thin layer of silicon is removed.

[0020] 特别地,所述步骤4)中对多层金属互连下面的绝缘材料进行图形化处理,绝缘材料为氧化硅材料,采用光刻胶作为掩膜,使用干法刻蚀或湿法腐蚀的方式对氧化硅进行图形化处理。 [0020] In particular, said step 4), patterning the multilayer metal interconnects processing following an insulating material, the insulating material is a silicon oxide material, using the resist as a mask, dry etching or wet etching the silicon oxide manner patterning process.

[0021] 特别地,所述步骤5)中在背面加工金属焊球采用电镀、植球或印刷的任一种进行。 [0021] In particular, said step 5) in the rear face by plating a metal ball, or any bumping for performing printing.

[0022] 本发明的有益效果为,与现有技术相比所述多芯片高密度封装方法基于硅基工艺,进行多层布线加工,提高集成密度;而且不使用TSV工艺,成本有很大优势,且高频损耗更小。 [0022] Advantageous effects of the present invention as compared to the prior art the high density multi-chip packaging method is based on silicon technology, multilayer wiring process, improve the integration density; and do not use TSV technology, a great cost advantage , and less high-frequency loss.

附图说明 BRIEF DESCRIPTION

[0023] 图1是本发明具体实施方式I提供的多芯片高密度封装方法的于硅基上加工多层高密度布线及焊盘的剖面图; [0023] FIG. 1 is a specific embodiment of the present invention is a high density multi-chip on a silicon encapsulation method embodiment I provide high density wiring and a sectional view of a multilayer pad processing;

[0024] 图2是本发明具体实施方式I提供的多芯片高密度封装方法的于待封装芯片上加工微凸点的剖面图; [0024] FIG 2 is a specific embodiment of the present invention, sectional view of the high density multi-chip packaging method I to be supplied to the micro-chip package point;

[0025] 图3是本发明具体实施方式I提供的多芯片高密度封装方法的晶圆级芯片贴装的示意图; [0025] FIG. 3 is a schematic view of wafer-level chip-mount high-density packaging methods of multi-chip I provides specific embodiments of the present invention;

[0026] 图4是本发明具体实施方式I提供的多芯片高密度封装方法的单个集成区域芯片贴装后的剖面图; [0026] FIG. 4 is a specific embodiment of the present invention is a cross-sectional view of a single integrated chip mount region of high density multi-chip packaging method provides a way of I;

[0027] 图5是本发明具体实施方式I提供的多芯片高密度封装方法的单个集成区域芯片贴装后注塑包封后的剖面图; [0027] FIG. 5 is a specific embodiment of the present invention is a cross-sectional view of a molded rear region of a single integrated chip a high density multi-chip packaging method of embodiment I provide a mount;

[0028] 图6是本发明具体实施方式I提供的多芯片高密度封装方法的硅衬底全部去除后的剖面图; [0028] FIG 6 is a specific embodiment of the present invention is a cross-sectional view of a silicon substrate, a high density multi-chip packaging method provides a way to remove all I;

[0029] 图7是本发明具体实施方式I提供的多芯片高密度封装方法的对绝缘材料进行图形化处理后的剖面图; [0029] FIG. 7 is a specific embodiment of the present invention is a cross-sectional view of the insulating material pattern-processing method for high-density multi-chip package provided in I;

[0030] 图8是本发明具体实施方式I提供的多芯片高密度封装方法的加工金属焊球并使金属焊球与所述多层金互连的最底层金属形成电连接后的剖面图。 [0030] FIG 8 is a processing according to the present invention, a metal ball high density multi-chip packaging method DETAILED DESCRIPTION I provide a metal bottom and a metal ball and metal interconnections of the multilayer is formed is electrically connected to a cross-sectional view of.

具体实施方式 Detailed ways

[0031] 下面结合附图并通过具体实施方式来进一步说明本发明的技术方案。 [0031] below with reference to specific embodiments and further technical solutions of the present invention.

[0032] 请参阅图1至图8所示,本实施例中,一种多芯片高密度封装方法,其包括以下步骤: [0032] Please refer to FIG. 1 to FIG. 8, the present embodiment, a high density multi-chip packaging method embodiment, which comprises the steps of:

[0033] I)以娃晶圆作为衬底材料,在娃晶圆表面加工多层金属互连及金属焊盘,在所述多层金属与硅衬底之间包含一层绝缘材料;由于采用硅基工艺,可以有多种选择,可以采用晶圆制造厂(foundry)的后端(BEOL)工艺,实现高密度互连加工,也可采用封装厂的晶圆级互连工艺,即半加成电镀工艺,实现中密度互连加工。 [0033] I) In Wa of the wafer as the substrate material, machining the wafer surface Wa and the multilayer metal interconnect metal pad between the metal and the silicon substrate, the multilayer comprising a layer of insulating material; Thanks silicon-based processes, there are many options, may be employed fabs (Foundry) the rear end (the BEOL) process, high density interconnect processing, a wafer-level interconnection process may also be employed in the packaging factory, i.e., half plus electroplating process to achieve density interconnect processing. 如图1所示,在硅衬底10表面制作绝缘层11并进行多层金属布线12加工,所述多层金属布线12之间设置金属层间介质层13,并加工用于芯片微凸点焊接的焊盘14。 As shown, the surface 10 of the silicon substrate 1 the insulating layer 11 and the multilayer metal wiring process 12, the plurality of metallic wires are provided between the metal layer 13 between the dielectric layer 12, and a chip micro machining point welding pad 14. 更为具体的,所述绝缘层11采用氧化硅,厚度为200nm〜2um,优选的使用Ium的氧化硅层。 More specifically, the silicon oxide insulating layer 11, a thickness of 200nm~2um, preferably using a silicon oxide layer Ium. 在一个具体实施例中,所述多层金属布线12采用大马士革型铜制程获得,所述金属层间介质层13为氧化硅、氮化硅、氮氧化硅的组合。 In one particular embodiment, the multilayer metal wirings 12 using the copper damascene type process is obtained, the intermetallic dielectric layer 13 is silicon oxide, silicon nitride, silicon oxynitride composition. 在另一个具体实施例中,所述多层金属布线12采用晶圆级封装互连工艺,即半加成电镀方式加工,所述金属层间介质层13为聚合物层。 In another particular embodiment, the multilayer metal wirings 12 interconnect process using wafer-level package, i.e., a semi-additive electroplating process, the intermetallic dielectric layer 13 is a polymer layer. 所述焊盘14采用多种金属堆叠的结构,在一个典型实施例中,焊盘14采用铜/镍/金堆叠,一个典型厚度组合为铜5um,镍lum,金0.5um,在另一个典型实施例中,14采用铜/锡组合,一个典型厚度组合为铜10um,锡5um。 The pad 14 employs a stacked structure of a plurality of metals, for example, the pad 14 using a copper / nickel / gold stacked in one exemplary embodiment, a combination of typical thickness 5um copper, nickel-Lum, gold 0.5um, in another exemplary Example 14 copper / tin combination, a typical composition of a copper thickness 10um, tin 5um.

[0034] 2)将多芯片以晶圆级的形式进行贴装,每个集成区域至少贴装2颗芯片,并对贴有芯片的硅晶圆的贴装面进行晶圆级塑封处理,将所贴装芯片均包覆在注塑材料16中;如图2至图5所示,本实施例中每个集成区域内放置2颗芯片,分别是第一芯片100和第二芯片200。 [0034] 2) The multi-chip wafer level form placement, each of at least two integrated chip mounting region, and wafer level processing plastic affixed silicon chip mounting surface, the the coated chips are mounted in an injection molding material 16; FIG. 2 to FIG. 5, in the present embodiment, the chip 2 is placed within each integrated region, respectively a first chip 100 and the second chip 200. 第一芯片100包含衬底101,器件及内部互连层102,表面钝化层103,表面微凸点104。 The first die 100 includes a substrate 101, and device interconnection layer 102, surface passivation layer 103, 104 asperity points. 所述衬底101为硅、砷化镓、氮化镓、锗硅等适于加工电子集成电路的材料,所述表面微凸点104典型的是采用铜/镍/锡材料组合,典型厚度为铜lOum,镍lum,锡15um。 The substrate 101 is silicon, gallium arsenide, gallium nitride, silicon germanium material suitable for the processing of electronic integrated circuit, the typical surface micro bump 104 is made of copper / nickel / tin composite material, a typical thickness of copper lOum, Ni lum, tin 15um. 所述第二芯片200包含衬底201,器件及内部互连层202,表面钝化层203,表面微凸点204。 The second chip 200 comprises a substrate 201, and device interconnection layer 202, surface passivation layer 203, point 204 asperity. 所述衬底201为硅、砷化镓、氮化镓、锗硅等适于加工电子集成电路的材料,所述表面微凸点204典型的是采用铜/镍/锡材料组合,典型厚度为铜10um,镍lum,锡15um。 The substrate 201 is a material suitable for processing electronic integrated circuits of silicon, gallium arsenide, gallium nitride, silicon germanium, the asperity point 204 is typically copper / nickel / tin material composition, typically having a thickness of copper 10um, Ni lum, tin 15um. 在焊接之后,第一芯片100和第二芯片200表面的微凸点与硅衬底10表面的焊盘结合,形成焊接界面15,在焊接之后,为提高焊点可靠性,在焊点之外区域填充底填树脂(图中未示出)。 After welding, the first chip 100 and the surface of the pad 10 surface of the second micro bump 200 and the silicon substrate chip bonding, welding interface 15 is formed, after welding, in order to improve the reliability of solder joints, solder joints outside area fill underfill resin (not shown). 使用晶圆级塑封的方式,将所贴装的第一芯片100和第二芯片200均包覆在注塑材料16中,所述第一芯片100和第二芯片200固定在硅衬底10上,并经由平坦化处理,形成平坦的上表面。 Plastic manner using wafer level, chip The first mount 100 and the second chip 200 are coated on the injection molding material 16, the first chip 100 and the chip 200 is fixed to the second silicon substrate 10, via planarization, to form a flat upper surface.

[0035] 3)将硅衬底10全部去除,直至暴露多层金属互连下面的绝缘层11 ;如图6所示,以塑封面为支撑,进行硅衬底10去除,典型的去除流程是:先用研磨的方式将硅衬底10厚度减少到50um以下,然后进行表面抛光处理,抛光方式可以是干法抛光或化学机械研磨(CMP),之后采用湿法腐蚀或干法刻蚀的方式,将剩余薄层硅全部去除。 [0035] 3) The silicon substrate 10 is completely removed until a multilayer metal interconnect below the exposed insulating layer 11; shown in Figure 6, to cover plastic support, removing the silicon substrate 10, the process is typically removed : first way to reduce polishing of the silicon substrate 10 to a thickness of 50um or less, then surface polished, polishing manner may be a dry polishing or chemical mechanical polishing (the CMP), wet etching using the following etching or dry manner , all of the remaining thin layer of silicon is removed. 绝缘层11在衬底的湿法腐蚀或干法刻蚀过程中可以作为停止层,可以确保即使存在腐蚀或刻蚀的片内分布差异,衬底硅也能够经由过刻蚀全部去除。 Insulating layer 11 in a wet etching process or dry etching of the substrate can be used as a stop layer, the sheet can be ensured even if there are differences in the distribution of corrosion or etching, the silicon substrate can be completely removed by overetching.

[0036] 4)对多层金属互连下面的绝缘层11进行图形化处理,形成绝缘层窗口,在窗口内暴露所述多层金属互连的最底层金属;如图7所示,采用光刻胶作为掩膜,使用干法刻蚀或湿法腐蚀的方式对绝缘层11进行图形化处理。 [0036] 4) a multilayer metal interconnect below the insulating layer 11 is pattern-processed, an insulating layer window, the window in the bottom of the metal multilayer metal interconnect said exposed; shown in FIG. 7, by light engraved rubber as a mask, dry etching or wet etching of the insulating layer 11 on the way of patterning process. 典型的,干法刻蚀采用氟基气体,如四氟化碳,六氟化硫等,湿法腐蚀采用氢氟酸缓蚀液(BHF)进行。 Typically, dry etching using fluorine-based gas, such as carbon tetrafluoride, sulfur hexafluoride, wet etching using hydrofluoric acid corrosion solution (BHF) performed.

[0037] 5)在背面加工金属焊球17,所述金属焊球17经由绝缘层11窗口与所述多层金属互连的最底层金属形成电连接;对完成晶圆级工艺的晶圆进行切割,获得分立的封装体或集成器件。 [0037] 5) a metal ball attached to the rear face 17, the metal ball 17 with the multilayered metal interconnect via the insulating layer 11 formed of a metal window bottom electrically; the completion of wafer level processing of the wafer cutting, to obtain a discrete device or integrated package. 如图8所示,在背面加工金属焊球17,加工方式可以是电镀的方式,也可是植球或印刷的方式。 8, the metal ball 17 at the rear face, the processing mode may be a plating manner, but also bumping or printing method. 在一个实施例中,金属焊球17的典型直径为200〜300um,典型节距为0.35〜0.5mm,金属焊球17可以用于直接面向PCB板的表面贴装(SMT),至此完成晶圆级封装,经切割,即获得封装产品。 In one embodiment, the typical diameter of the metal ball 17 is 200~300um, typical pitch 0.35~0.5mm, the metal balls 17 may be used directly facing the surface mount PCB board (the SMT), thereby completing the wafer level package, the cut, i.e., to obtain packages. 在另一个实施例中,金属焊球17的典型直径为60〜lOOum,典型节距在100〜200um,金属焊球17用于向有机基板的焊接,将集成器件以倒装(FlipChip)的形式进行二次组装,最终形成封装产品。 In another embodiment, the typical diameter of the metal ball 17 is 60~lOOum, typical pitch 100~200um, the solder balls 17 for welding metal to the organic substrate, the integrated device will flip (FlipChip) form secondary assembly, forming packages.

[0038] 以上实施例只是阐述了本发明的基本原理和特性,本发明不受上述事例限制,在不脱离本发明精神和范围的前提下,本发明还有各种变化和改变,这些变化和改变都落入要求保护的本发明范围内。 [0038] The above embodiments are merely set forth the basic principles and features of the present invention, the present invention is not restricted the above examples, without departing from the spirit and scope of the present invention, the present invention and various changes and modifications, and variations of these changes fall within the scope of the claimed invention. 本发明要求保护范围由所附的权利要求书及其等效物界定。 The scope of the invention as claimed by the appended claims and their equivalents.

Claims (8)

1.一种多芯片高密度封装方法,其特征在于,其包括以下步骤: 1)以硅晶圆作为衬底材料,在硅晶圆表面加工多层金属互连及金属焊盘,在所述多层金属与硅衬底之间包含一层绝缘材料; 2)将多芯片以晶圆级的形式进行贴装,每个集成区域至少贴装2颗芯片,并对贴有芯片的硅晶圆的贴装面进行晶圆级塑封处理,将所贴装芯片均包覆在注塑材料中; 3)将所述硅晶圆的衬底材料全部去除,直至暴露多层金属互连下面的绝缘材料; 4)对多层金属互连下面的绝缘材料进行图形化处理,形成绝缘层窗口,在窗口内暴露所述多层金属互连的最底层金属; 5)在背面加工金属焊球,所述金属焊球经由绝缘层窗口与所述多层金属互连的最底层金属形成电连接; 6)对完成晶圆级工艺的晶圆进行切割,获得分立的封装体或集成器件。 A high density multi-chip packaging method, which is characterized in that it comprises the following steps: 1) a silicon wafer as the substrate material, the surface of the silicon wafer and metal interconnect processing of multi-layer metal pad, the comprising a multilayer metal between the layer of insulating material and the silicon substrate; 2) for mounting the multi-chip wafer level form, each of the at least two integrated chip mounting region, and a silicon wafer chip affixed the surface mount plastic wafer level process, the chips are mounted the covering material in an injection molding; 3) the substrate material of the silicon wafer is completely removed until a multilayer metal interconnects exposed the underlying insulating material ; 4) multilayer metal interconnects on an insulating material following patterning process, the insulating layer is formed a window, the window is exposed in the bottom of the multilayer metal interconnect metal; 5) in the rear face of the metal ball, the a metal ball is formed are electrically connected via the metal bottom window and the insulating layer of the multilayer metal interconnection; 6) of the wafer-level processing is completed wafer is cut to obtain a discrete device or integrated package.
2.根据权利要求1所述的多芯片高密度封装方法,其特征在于,所述步骤6)中的对晶圆切割完成后获得分立的集成器件,将所述分立的集成器件以倒装的形式进一步在有机基板上组装,最终形成封装体。 The high-density multi-chip packaging method according to claim 1, wherein said step 6) obtained in the discrete integrated device after the completion of dicing, the discrete integrated devices in a flip-chip form that are further assembled on an organic substrate, eventually forming the package.
3.根据权利要求1或2所述的多芯片高密度封装方法,其特征在于,所述步骤2)中将多芯片以晶圆级的形式进行贴装的方式采用基于焊料凸点的热压键合方式或金属直接键合方式的任一种。 The high-density multi-chip packaging method as claimed in claim 1 or claim 2, wherein said step 2) in the multi-chip mounting manner of wafer level based hot form solder bumps metal bonding method or a direct bond bonding any way.
4.根据权利要求3所述的多芯片高密度封装方法,其特征在于,所述步骤2)中多芯片以晶圆级的形式采用热压键合方式进行贴装,在多芯片热压键合之后,于焊点之外的区域填充底填树脂并固化,以提高焊点的可靠性。 The high-density multi-chip packaging method according to claim 3, wherein said step 2) is a multi-chip mounting manner thermocompression bonding to form a wafer-level, multi-chip thermocompression bond after bonding, the region outside the solder joint underfill resin is filled and cured to improve the reliability of solder joints.
5.根据权利要求1或2所述的多芯片高密度封装方法,其特征在于,所述步骤2)中在硅晶圆的贴装面进行晶圆级塑封处理后,还包括对塑封材料表面进行平整化处理,以形成平坦的上表面。 The high-density multi-chip packaging method as claimed in claim 1 or claim 2, characterized in that, after mounting the wafer-level molding process at the surface of the silicon wafer in step 2), also of plastic material having a surface comprising be planarized to form a flat upper surface.
6.根据权利要求1或2所述的多芯片高密度封装方法,其特征在于,所述步骤3)中将所述硅晶圆的衬底材料全部去除,具体的去除方法为:用研磨的方式将衬底硅厚度减少到50um以下,然后进行表面抛光处理,抛光方式可以是干法抛光或化学机械研磨的任一种,之后采用湿法腐蚀或干法刻蚀的方式,将剩余薄层硅全部去除。 The high-density multi-chip packaging method according to claim 1, characterized in that the material of the substrate 3) in the said step of removing all of the silicon wafer, removing specific method: trituration of reducing the thickness of the silicon substrate manner to 50um or less, then surface polished, polishing manner may be any of a dry polishing or chemical mechanical polishing, after wet etching or dry etching manner, the remaining thin layer removing all silicon.
7.根据权利要求1或2所述的多芯片高密度封装方法,其特征在于,所述步骤4)中对多层金属互连下面的绝缘材料进行图形化处理,绝缘材料为氧化硅材料,采用光刻胶作为掩膜,使用干法刻蚀或湿法腐蚀的方式对氧化硅进行图形化处理。 The high-density multi-chip packaging method of claim 1 or claim 2, wherein,) in step 4 for the multi-layered metal interconnection insulating material following patterning process, the insulating material is a silicon oxide material, using the resist as a mask, dry etching or wet etching of the silicon oxide manner patterning process.
8.根据权利要求1或2所述的多芯片高密度封装方法,其特征在于,所述步骤5)中在背面加工金属焊球采用电镀、植球或印刷的任一种进行。 The high-density multi-chip packaging method of claim 1 or claim 2, wherein said step 5) in the rear face using any of the metal solder plating, or printing a bumping performed.
CN201510173636.0A 2015-04-13 2015-04-13 Method for packaging multiple chips in high density CN104851816A (en)

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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050230797A1 (en) * 2002-11-07 2005-10-20 Kwun-Yo Ho Chip packaging structure
CN103000593A (en) * 2011-09-09 2013-03-27 台湾积体电路制造股份有限公司 Packaging methods and structures for semiconductor devices
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