TWI419272B - Semiconductor chip assembly with post/base heat spreader and signal post - Google Patents

Description

Semiconductor wafer package with bump/base heat sink and signal bump

The present invention relates to a semiconductor wafer package, and more particularly to a semiconductor wafer package comprising a semiconductor component, a wire, an adhesive layer, and a heat sink, and a method of fabricating the same.

[Reciprocal reference of related applications]

This application is a continuation-in-part of U.S. Patent Application Serial No. 12/616,773, filed on Nov. 11, 2009, the content of which is hereby incorporated by reference. This application is also a continuation of the U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, the content of which is hereby incorporated by reference. The present application claims priority to U.S. Provisional Patent Application Serial No. 61/257,830, filed on Jan. 3, 2009, the content of which is hereby incorporated by reference.

U.S. Patent Application No. 12/616,773, filed on November 11, 2009, and U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, filed on Sep. 11, 2009 Part of the continuation of U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009.

U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009, and filed No. 12/557,541, filed on Sep. 11, 2009, filed on March 18, 2009 Partial continuation of U.S. Patent Application Serial No. 12/406,510. U.S. Patent Application Serial No. 61/071,588, filed on May 7, 2008, and U.S. Provisional Patent Application No. 61/071,588, filed on May 7, 2008. Priority of US Provisional Patent Application No. 61/071,072, filed on Apr. 11, 2008, and U.S. Provisional Patent Application No. 61/064,748, filed on March 25, 2008, the content of each of This is incorporated herein by reference. U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009, and filed on Sep. 11, 2009, filed on Sep. 11, 2009. Priority is claimed in US Provisional Patent Application Serial No. 61/150,980, the disclosure of which is incorporated herein by reference.

Semiconductor components such as packaged and unpackaged semiconductor wafers can provide high voltage, high frequency, and high performance applications; these applications require a very high amount of power to perform a particular function, but the higher the power, the higher the semiconductor component More heat. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is reduced, which further increases heat generation.

Semiconductor components are prone to performance degradation and shortened service life under high temperature operation, and may even malfunction immediately. High heat not only affects wafer performance, but may also cause thermal stress on the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be quickly and efficiently dissipated to ensure the efficiency and reliability of its operation. A high thermal conductivity path typically conducts and dissipates thermal energy to a region of greater surface area than the die pad in which the wafer or wafer is located.

Light-emitting diodes (LEDs) have recently become an alternative source of incandescent, fluorescent, and halogen sources. LEDs provide high energy efficiency and low cost long-term illumination for medical, military, signage, signal, aerospace, marine, vehicle, portable, commercial and residential lighting applications. For example, LEDs can provide light sources for fixtures, flashlights, headlights, searchlights, traffic lights, and displays.

The high power chips in the LEDs also produce a large amount of thermal energy while providing high brightness output. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened service life, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. Therefore, LEDs highlight the market's need for high-power chips with good heat dissipation.

The LED package typically includes an LED chip, a pedestal, electrical contacts, and a thermal contact. The pedestal is thermally coupled to the LED wafer and used to support the LED wafer. The electrical contacts are electrically connected to the anode and cathode of the LED chip. The thermal contacts are thermally coupled to the LED wafer via the pedestal, and the underlying carrier is sufficiently thermally dissipated to prevent overheating of the LED wafer.

The industry is actively investing in the development of high-power chip packages and thermal boards with various design and manufacturing technologies in order to meet performance requirements in this extremely cost-competitive environment.

A plastic ball grid array (PBGA) package encloses a wafer and a laminate substrate in a plastic case and then adheres to a printed circuit board (PCB) with solder balls. The laminate substrate comprises a dielectric layer typically composed of glass fibers. The heat generated by the wafer can be transferred to the solder ball via the plastic and dielectric layers and transferred to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the PBGA has a poor heat dissipation effect.

A quad flat no-lead (QFN) package places the wafer on a copper die pad that is soldered to a printed circuit board. The thermal energy generated by the wafer can be transferred to the printed circuit board via the die pad. However, due to the limited routing capabilities of its leadframe interposer, QFN packages are not suitable for high input/output (I/O) chips or passive components.

The heat conducting plate provides electrical routing, thermal management, and mechanical support for the semiconductor components. The heat conducting board usually comprises a substrate for signal routing, a heat sink or heat sink for providing heat removal function, a solder pad electrically connectable to the semiconductor component, and a terminal electrically connectable to the next layer assembly. The substrate can be a laminate structure having a single or multi-layer routing circuitry and one or more dielectric layers. The heat sink can be a metal base, a metal block or a buried metal layer.

The heat conducting plate engages the next layer of the body. For example, the next layer of the body can be a lamp holder having a printed circuit board and a heat sink. In this example, an LED package system is disposed on the heat conducting plate, and the heat conducting plate is disposed on the heat dissipating device, and the heat conducting plate/heat dissipating device sub-group and the printed circuit board are further disposed in the lamp holder. In addition, the heat conducting plate is electrically connected to the printed circuit board via wires. The substrate directs the electrical signal from the printed circuit board to the LED package, and the heat sink scatters and transfers the thermal energy of the LED package to the heat sink. Therefore, the heat conducting plate can provide an important thermal path for the LED wafer.

U.S. Patent No. 6,507,102 to the disclosure of U.S. Pat. A heat dissipating block having a square or rectangular shape similar to the central opening is adhered to the central opening side wall and thus joined to the substrate. The upper and lower conductive layers are respectively adhered to the top and bottom of the substrate, and are electrically connected to each other through the plating vias penetrating the substrate. A wafer is disposed on the heat dissipation block and wire bonded to the upper conductive layer, a package material is molded on the wafer, and a lower conductive layer is provided with a solder ball.

When manufactured, the substrate was originally a B-stage resin film placed on the lower conductive layer. The heat dissipating block is inserted in the central opening so as to be located on the lower conductive layer and separated from the substrate by a gap. The upper conductive layer is disposed on the substrate. After the upper and lower conductive layers are heated and pressed together, the resin is melted and flows into the gap to be solidified. The upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate and exposing the resin flash to the heat sink. The resin flash is then removed to expose the heat sink. Finally, the wafer is placed on the heat sink block and bonded and packaged.

Therefore, the thermal energy generated by the wafer can be transferred to the printed circuit board via the heat slug. However, in mass production, the manual placement of the heat sink in the central opening is labor intensive and costly. Moreover, since the mounting tolerance of the lateral direction is small, the heat dissipating block is not easily positioned in the central opening, which may cause a gap between the substrate and the heat dissipating block and uneven wiring. As a result, the substrate is only partially adhered to the heat dissipation block, and sufficient support force cannot be obtained from the heat dissipation block, and the layer is easily delaminated. In addition, the chemical etching solution for removing part of the conductive layer to expose the resin flash will also remove some of the heat-dissipating block which is not covered by the resin flash, so that the heat-dissipating block is not flat and difficult to combine, and finally the yield of the group is lowered, Insufficient reliability and high cost.

US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package having a substrate comprising a metal core layer and a wafer disposed in a die pad region on the top surface of the metal core layer. An insulating layer is formed on the bottom surface of the metal core layer. The blind hole penetrates the insulating layer through the metal core layer, and the hole is filled with the heat-dissipating solder ball, and the solder ball corresponding to the heat-dissipating solder ball is further disposed on the substrate. The thermal energy generated by the wafer can flow through the metal core to the heat sink balls and then to the printed circuit board. However, the insulating layer sandwiched between the metal core layer and the printed circuit board limits the heat flow to the printed circuit board.

U.S. Patent No. 6,670,219 to Lee et al., the disclosure of which is incorporated herein by reference. A substrate having a central opening is disposed on the ground plate through an adhesive layer having a central opening. A chip is mounted on the heat sink in a recess formed by the central opening of the ground plate, and the substrate is provided with a solder ball. However, since the solder ball is located on the substrate, the heat sink cannot contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection instead of heat conduction, thereby greatly reducing the heat dissipation effect.

U.S. Patent No. 7,038,311 to Woodall et al. provides a high-heat-dissipating BGA package having a heat sink that is inverted T-shaped and includes a post portion and a wide base. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate. A wafer system is disposed on the pillar portion and wire bonded to the substrate, and a packaging material is molded on the wafer, and the substrate is provided with a solder ball. A post extends through the window opening and supports the substrate by a wide substrate, with the solder ball being between the wide substrate and the periphery of the substrate. The thermal energy generated by the wafer can be transferred to the wide substrate via the post and then to the printed circuit board. However, since a space for accommodating the solder balls must be left on the wide substrate, the wide substrate protrudes below the substrate only at a position corresponding to the central window and the innermost tin ball. As a result, the substrate is unbalanced during the manufacturing process, and is easily shaken and bent, thereby causing difficulty in mounting, wire bonding, and molding of the package material. In addition, the wide substrate may be bent due to the molding of the encapsulating material, and once the solder ball collapses, the package may not be soldered to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high.

U.S. Patent Application Publication No. 2007/0267642 to Erchak et al., which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire contents There are electrical contacts. A packaging system having a through hole and a transparent upper cover is disposed on the electrical contact. An LED chip is disposed on the protruding portion and connected to the substrate by wire bonding. The protrusion is adjacent to the substrate and extends through the insulating layer and the through hole on the package to enter the package. An insulating layer is disposed on the substrate, and an electrical contact is disposed on the insulating layer. The packaging system is disposed on the electrical contacts and spaced apart from the insulating layer. The heat generated by the wafer can be transferred to the substrate via the protrusions to reach a heat sink. However, the electrical contacts are not easily disposed on the insulating layer, and are difficult to electrically connect with the next layer of the assembly, and cannot provide multilayer routing.

Conventional packages and thermally conductive plates have major drawbacks. For example, an electrically insulating material having a low thermal conductivity such as an epoxy resin limits the heat dissipation effect, however, an electrically insulating material having a high thermal conductivity such as an epoxy resin filled with ceramic or tantalum carbide has low adhesion. The disadvantage of high production cost. The electrically insulating material may be delaminated by heat during the manufacturing process or at the beginning of the operation. If the substrate is a single-layer circuit system, the routing capability is limited. However, if the substrate is a multi-layer circuit system, the excessively thick dielectric layer will reduce the heat dissipation effect. In addition, the previous case technology still has problems such as insufficient heat sink performance, excessive volume or difficulty in thermally connecting to the next layer. The manufacturing process of the prior art is also not suitable for low-cost mass production operations.

In view of the various developments and related limitations of the existing high-power semiconductor device packages and heat-conducting plates, the industry needs a cost-effective, reliable, mass-produced, multi-functional, flexible signal routing and excellent heat dissipation. Semiconductor wafer assembly.

The invention provides a semiconductor wafer package comprising at least a semiconductor component, a heat sink, a wire and an adhesive layer. The semiconductor component is electrically connected to the wire and thermally coupled to the heat sink. The heat sink includes at least a heat conducting stud and a base. The thermally conductive stud extends upwardly from the base and into a first opening of the adhesive layer, the base extending laterally from the thermally conductive stud. The wire includes at least one pad, a terminal and a signal stud. The signal stud extends upward from the terminal and enters a second opening of the adhesive layer.

According to one aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink and a wire. The adhesive layer has at least first and second openings. The heat sink includes at least a heat conducting stud and a base, wherein the heat conducting stud is adjacent to the base and extends upwardly in the upward direction of the base, the base is opposite to the upward direction The direction extends below the thermally conductive stud and extends laterally from the thermally conductive stud in a direction perpendicular to the upward and downward directions. The wire is at least The device includes a solder pad, a terminal and a signal stud, wherein the signal stud extends below the solder pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud.

The semiconductor component is located above the thermally conductive stud and overlaps the thermally conductive stud. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal; and thermally coupled to the thermally conductive stud to be thermally coupled to the susceptor. The adhesive layer is disposed on the base, extends above the base, and extends laterally from the thermally conductive stud to the terminal or over the terminal. The pad extends over the adhesive layer and the terminal extends below the adhesive layer. The thermally conductive stud extends into the first opening, and the signal stud extends into the second opening. In addition, the thermally conductive stud and the signal stud have the same thickness and are coplanar with each other, and the base and the terminal also have the same thickness and are coplanar with each other.

The wire can include the pad, the terminal, the signal stud, and a routing wire. The routing line can abut the pad. The signal stud may abut the routing line and the terminal, extend below the solder pad and the routing line, and extend above the terminal. The pad and the routing line may overlap the adhesive layer. The terminal can be overlapped by the adhesive layer. The signal studs extend through the adhesive layer. The solder pad, the terminal, the signal stud and the routing line can contact the adhesive layer. A conductive path between the pad and the terminal can include the signal stud and the routing line.

According to another aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink, a substrate and a wire. The adhesive layer has at least first and second openings. The heat sink includes at least one a thermally conductive stud and a base, wherein the thermally conductive stud is adjacent to the base and extends above the base in an upward direction, the base extending in the downward direction opposite the upward direction to the thermally conductive convex Below the column, and extending laterally from the thermally conductive stud in a direction perpendicular to the upward and downward directions. The substrate includes at least one pad and a dielectric layer, and the first and second vias extend through the substrate. The wire includes at least the pad, a terminal and a signal stud, wherein the signal stud extends below the solder pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud .

The semiconductor component is located above the thermally conductive stud and overlaps the thermally conductive stud. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal; and thermally coupled to the thermally conductive stud to be thermally coupled to the susceptor. The adhesive layer is disposed on the pedestal and extends over the pedestal and extends into the first through hole, a first gap between the heat conducting stud and the substrate, and extends into the second through hole The second gap between the signal stud and the substrate and extends across the dielectric layer in the gaps. The adhesive layer extends laterally from the thermally conductive stud to the terminal or over the terminal, between the thermally conductive stud and the dielectric layer, between the signal stud and the dielectric layer, and the pedestal Between the dielectric layer and the dielectric layer. The substrate is disposed on the adhesive layer and extends above the base. The heat conducting stud extends into the first opening and the first through hole, and the signal stud extends into the second opening and the second through hole. In addition, the thermally conductive stud and the signal stud have the same thickness and are coplanar with each other, and the base and the terminal also have the same thickness and are coplanar with each other.

The heat sink can include a cover body, and the cover system is located at the heat conducting stud The top of the top portion abuts the top of the thermally conductive stud while covering the top of the thermally conductive stud from above and extending laterally from the top of the thermally conductive stud in the lateral direction. For example, the cover may be rectangular or square, and the top of the thermally conductive stud may be circular. In this case, the cover may be sized and shaped to match the thermal contact surface of the semiconductor component, and the top and bottom of the thermally conductive stud are not designed according to the thermal contact surface of the semiconductor component. The cover may also contact and cover the adhesive layer, a portion adjacent to the thermally conductive stud and coplanar with the thermally conductive stud. The cover may also be coplanar with the pad above the dielectric layer. In addition, the thermally conductive stud can thermally join the base and the cover. The heat sink can be composed of the heat conducting stud and the base, or the heat conducting stud, the base and the cover. The heat sink can also be composed of copper, aluminum or copper/nickel/aluminum alloy. Regardless of any composition, the heat sink can provide heat dissipation to diffuse the thermal energy of the semiconductor component to the next layer.

The semiconductor component can be disposed on the heat sink. For example, the semiconductor device can be disposed on the heat sink and the substrate, and is superposed on the heat conducting stud and the solder pad, electrically connected to the solder pad through a first solder, and thermally coupled to the solder via a second solder. Heat sink. Alternatively, the semiconductor device may be disposed on the heat sink instead of the substrate, and overlap the heat conducting stud instead of the substrate, electrically connected to the pad through a wire, and thermally coupled to the heat through a die bonding material. seat.

The semiconductor component can be a packaged or unpackaged semiconductor wafer. For example, the semiconductor component can be an LED package including an LED chip disposed on the heat sink and the substrate, overlapping the thermally conductive stud and The pad is electrically connected to the pad via a first solder and thermally coupled to the heat sink via a second solder. Alternatively, the semiconductor device can be a semiconductor wafer disposed on the heat sink instead of the substrate, overlapping the heat conducting stud instead of the substrate, electrically connected to the pad via a wire, and via a solid The crystalline material is thermally coupled to the heat sink.

The adhesive layer contacts the thermal conductive stud and the dielectric layer in the first notch, and contacts the signal stud and the dielectric layer in the second notch, and contacts the pedestal outside the notches The terminal and the dielectric layer. The adhesive layer can also cover and surround the heat conducting stud and the signal stud in the lateral direction, and is similarly coated on the sidewall of the heat conducting stud and the signal stud. The adhesive layer is still coplanar with the heat conducting stud and the top and bottom of the signal stud.

The adhesive layer may extend laterally from the thermally conductive stud to the terminal or across the terminal. For example, the adhesive layer and the terminal can extend to the peripheral edge of the assembly; in this example, the adhesive layer extends laterally from the thermally conductive stud to the terminal. Alternatively, the adhesive layer may extend to a peripheral edge of the set, and the terminal is spaced from a peripheral edge of the set; in this case, the adhesive layer extends laterally from the thermally conductive stud and over the terminal .

The thermally conductive stud can be integrally formed with the base. For example, the thermally conductive stud and the pedestal may be a single metal body or comprise a single metal body in its interface, wherein the single metal body may be copper. The thermally conductive stud can also extend through the first port. The thermally conductive stud may also be coplanar with the adhesive layer above the dielectric layer. The thermally conductive stud may also be a flat-topped tapered cylinder having a diameter that decreases upwardly from the base toward its flat top adjacent the cover.

The signal stud can be integrally formed with the terminal. For example, the signal stud The terminal may be a single metal body or comprise a single metal body in its interface, wherein the single metal body may be copper. The signal stud can also extend through the second port. The signal studs may also be coplanar with the adhesive layer above the dielectric layer. The signal stud may also be a flat-topped tapered cylinder having a diameter that decreases upwardly from the terminal toward its flat top adjacent the routing line.

The pedestal can cover the thermally conductive stud from below while supporting the substrate and maintaining a distance from the peripheral edge of the group.

The substrate can be spaced from the thermally conductive stud and the base. The substrate can also be a laminated structure.

The wire can be spaced from the heat sink. The pad can contact the dielectric layer, the terminal can contact the adhesive layer, and the signal stud can contact the adhesive layer and the dielectric layer. In addition, the terminal is adjacent to the signal stud, extends below the signal stud, and extends laterally from the signal stud.

The pad can serve as an electrical contact of the semiconductor component, the terminal can serve as an electrical contact of the next layer, and the pad and the terminal can provide a vertical between the semiconductor component and the next layer Signal routing.

The group can be a first or second stage single crystal or polycrystalline device. For example, the group can be a first level package containing a single wafer or multiple wafers. Alternatively, the group may be a second-level module comprising a single LED package or a plurality of LED packages, wherein each of the LED packages may comprise a single LED chip or a plurality of LED chips.

The present invention provides a method of fabricating a semiconductor wafer package, comprising: providing a thermal conductive stud, a signal stud and a pedestal; and providing an adhesive layer on the pedestal, the step comprising inserting the thermally conductive stud Adhesive layer a first opening, and inserting the signal stud into a second opening of the adhesive layer; and providing a conductive layer on the adhesive layer, the step comprising aligning the thermally conductive stud with the first through hole of the conductive layer Aligning the signal stud with a second through hole of the conductive layer; causing the adhesive layer to flow upward into the first through hole, a first gap between the heat conducting stud and the conductive layer, and the second pass a second gap between the signal stud and the conductive layer; curing the adhesive layer; providing a wire comprising at least a pad, a terminal, the signal stud and a selected portion of the conductive layer; A semiconductor device is disposed on a heat sink, wherein the heat sink includes at least the heat conductive stud and the base; electrically connecting the semiconductor component to the wire; and thermally bonding the semiconductor component to the heat sink.

According to one aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, a pedestal, an adhesive layer, and a conductive layer, wherein (a) the thermal conduction a stud is adjacent to the pedestal, extends upwardly above the pedestal in an upward direction, extends into a first opening of the adhesive layer, and is aligned with a first through hole of the conductive layer, and (b) the signal stud Adjoining the susceptor, extending in the upward direction above the pedestal, extending into a second opening of the adhesive layer, and aligning with a second through hole of the conductive layer, (c) the pedestal is along a a downward direction opposite to the upward direction extending below the heat conducting stud and the signal stud, and extending laterally from the heat conducting stud and the signal stud in a direction perpendicular to the upward and downward directions (d) the adhesive layer is disposed on the pedestal, extends over the pedestal, and is located between the pedestal and the conductive layer, and is not cured. Further, (e) the conductive layer is disposed on the pedestal Adhesive layer and extending over the adhesive layer; (2) making the adhesion The layer flows upward into the first through hole, a first gap between the heat conducting stud and the conductive layer, and a second gap between the signal stud and the conductive layer in the second through hole; (3) curing the layer (4) providing a wire, the wire comprising at least a pad, a terminal, the signal stud and a selected portion of the conductive layer; (5) providing a semiconductor component at least comprising the thermally conductive stud and a heat sink of the pedestal, wherein the semiconductor component is overlapped with the heat conducting stud; (6) electrically connecting the semiconductor component to the solder pad, thereby electrically connecting the semiconductor component to the terminal, wherein the solder pad One of the conductive paths between the terminals includes the signal stud; and (7) thermally bonding the semiconductor component to the thermally conductive stud, thereby thermally bonding the semiconductor component to the pedestal.

According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, and a pedestal, wherein the thermally conductive stud is adjacent and integrally formed on the base And extending in an upward direction above the base, the signal studs are adjacent and integrally formed on the base, and extend upward in the upward direction on the base, and the base is along the upward direction The opposite direction extends downwardly from the heat conducting stud and the signal stud, and extends laterally from the heat conducting stud and the signal stud in a direction perpendicular to the upward and downward directions; (2 Providing an adhesive layer, wherein the first and second openings extend through the adhesive layer; (3) providing a conductive layer, wherein the first and second through holes extend through the conductive layer; (4) the adhesive layer is disposed thereon The step of inserting the thermal conductive stud into the first opening and inserting the signal stud into the second opening, wherein the adhesive layer extends over the base, the thermally conductive stud extending into the first An opening, and the signal stud extends into A second opening; (5) disposed on the conductive layer On the adhesive layer, the step of aligning the thermal conductive post to the first through hole and aligning the signal stud to the second through hole, wherein the conductive layer extends over the adhesive layer, the adhesive layer Between the susceptor and the conductive layer and uncured; (6) heating and melting the adhesive layer; (7) causing the pedestal and the conductive layer to abut each other, thereby making the thermally conductive stud at the first The inside of the through hole moves upward, and the signal stud is moved upward in the second through hole, and a pressure is applied to the molten adhesive layer between the base and the conductive layer, and the pressure forces the molten adhesive layer to flow upward into the first a first gap between the heat conducting stud and the conductive layer and a second gap between the signal stud and the conductive layer in the through hole; (8) heat curing the molten adhesive layer, The conductive post and the signal stud and the base are mechanically adhered to the conductive layer; (9) providing a wire, the wire comprising at least a pad, a terminal, a routing line and the signal stud, Wherein the wire comprises a selected portion of the conductive layer, and one of the pads is located The conductive path between the terminals includes the routing line and the signal stud; (10) a semiconductor component is disposed on a heat sink, the heat sink includes at least the heat conducting stud and the base, wherein the semiconductor component overlaps the heat conducting a bump; (11) electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and (12) thermally bonding the semiconductor device to the thermally conductive stud, thereby thermally bonding the semiconductor Components to the base.

The conductive layer may include: the conductive layer is separately disposed on the adhesive layer, or the conductive layer is first adhered to a carrier, and the conductive layer is disposed on the adhesive layer together with the carrier, so that the conductive layer The carrier is overlapped with the conductive layer, and the conductive layer contacts the adhesive layer and is interposed between the adhesive layer and the carrier, and then after the adhesive layer is cured, the carrier is first removed and then provided The wire.

According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, a pedestal, an adhesive layer, and a substrate, wherein (a) the substrate Having at least a conductive layer and a dielectric layer, (b) the thermally conductive stud is adjacent to the pedestal, extends upwardly above the pedestal in an upward direction, extends through a first opening of the adhesive layer, and extends into a first through hole of the substrate, (c) the signal stud is adjacent to the base, extends upward in the upward direction above the base, extends through a second opening of the adhesive layer, and extends into the substrate a second through hole, (d) the base extends in a downward direction opposite to the upward direction below the thermally conductive stud and the signal stud, and along a side perpendicular to the upward and downward directions The direction extends laterally from the heat conducting stud and the signal stud, and (e) the adhesive layer is disposed on the base, extends above the base, and is located between the base and the substrate, and Uncured, (f) the substrate is disposed on the adhesive layer and extends over the adhesive layer, and The conductive layer extends over the dielectric layer, and (g) a first gap is located in the first via hole and between the heat conductive stud and the substrate, and (h) a second gap system Located in the second through hole and between the signal stud and the substrate; (2) causing the adhesive layer to flow upward into the gap; (3) curing the adhesive layer; (4) providing a semiconductor component a heat sink having at least the heat conducting stud and the base, wherein the semiconductor component is overlapped with the heat conducting stud, and a wire includes at least a solder pad, a terminal, the signal stud, and a selected portion of the conductive layer And the conductive path between the pad and the terminal includes the signal stud; (5) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the terminal; (6) thermally bonding the semiconductor component to the thermally conductive stud, thereby thermally bonding the semiconductor component to the pedestal.

According to still another aspect of the present invention, a method for fabricating a semiconductor wafer package includes: (1) providing a thermally conductive stud, a signal stud, and a pedestal, wherein the thermally conductive stud is adjacent and integrally formed on the base And extending in an upward direction above the base, the signal studs are adjacent and integrally formed on the base, and extend in the upward direction above the base, the base is along an upward direction The opposite direction extends downwardly from the heat conducting stud and the signal stud, and extends laterally from the heat conducting stud and the signal stud in a direction perpendicular to the upward and downward directions; (2) Providing an adhesive layer, wherein the first and second openings extend through the adhesive layer; (3) providing a substrate including at least one conductive layer and a dielectric layer, wherein the first and second through holes extend through the substrate; 4) disposing the adhesive layer on the pedestal, the step of passing the thermal conductive stud through the first opening, and passing the signal stud through the second opening, wherein the adhesive layer extends over the pedestal Above, the heat conducting stud extends through the first opening, The signal stud extends through the second opening; (5) the substrate is disposed on the adhesive layer, the step of inserting the thermal conductive post into the first through hole, and inserting the signal stud into the second through hole The substrate extends above the adhesive layer, and the conductive layer extends above the dielectric layer, the heat conductive protrusion extends through the first opening and enters the first through hole, and the signal protrusion extends through the second opening And entering the second through hole, the adhesive layer is between the pedestal and the substrate and is not cured, a first notch is located in the first through hole and between the thermal conductive stud and the substrate In addition, a second gap is located in the second through hole and is between the signal protrusion and the (6) heating and melting the adhesive layer; (7) causing the base and the substrate to abut each other, thereby moving the thermally conductive stud upward in the first through hole, and causing the signal stud Moving upward in the second through hole while applying pressure to the molten adhesive layer between the base and the substrate, wherein the pressure forces the molten adhesive layer to flow upward into the gap, and the thermally conductive stud and the signal stud And the molten adhesive layer extends over the dielectric layer; (8) heat curing the molten adhesive layer, thereby mechanically adhering the thermally conductive stud and the signal stud and the base to the substrate; (9) A semiconductor device is disposed on a heat sink, the heat sink includes at least the heat conducting stud and the base, wherein the semiconductor component is overlapped with the stud, and a wire includes at least a solder pad, a terminal, the signal stud and a selected portion of the conductive layer, and a conductive path between the pad and the terminal includes the signal stud; (10) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the a terminal; and (11) thermally bonding the semiconductor component to Thermally conductive boss, whereby the semiconductor element is thermally coupled to the base.

Providing the thermal conductive stud, the signal stud and the base may include: providing a metal plate; forming a patterned etch stop layer on the metal plate, selectively exposing the metal plate; etching the metal plate to Forming a pattern defined by the patterned etch stop layer, thereby forming a recess on the metal plate that extends into but not through the metal plate; and then removes the patterned etch stop layer, wherein the thermal conductive convex The pillar includes a first unetched portion of the metal plate, the first unetched portion protrudes above the pedestal and is laterally surrounded by the groove, and the signal stud includes one of the metal plates a second unetched portion protruding above the pedestal and being The recess is laterally surrounded, and the base is also an unetched portion of the metal plate. The unetched portion is located under the thermally conductive stud and the signal stud and the recess.

Providing the adhesive layer can comprise: providing a film of uncured epoxy. Flowing the adhesive layer can include: melting the uncured epoxy resin; and pressing the uncured epoxy resin between the susceptor and the substrate. Curing the adhesive layer can include curing the melted uncured epoxy resin.

Providing the heat sink can include: providing a cover on the heat conducting stud after curing the adhesive layer and before disposing the semiconductor component, the cover being located above a top of one of the heat conducting studs, adjacent to the heat conducting stud The top portion covers the top of the thermally conductive stud from above and extends laterally from the top of the thermally conductive stud in the lateral direction.

Providing the bond pad can include removing selected portions of the conductive layer after curing the adhesive layer.

The bonding pad may further include: after curing the adhesive layer, grinding the thermal conductive stud, the signal stud, the adhesive layer and the conductive layer to make the thermal conductive stud, the signal stud, the adhesive layer and The conductive layers are laterally flush with each other on a side surface facing the upward direction; and then selected portions of the conductive layer are removed such that the pads comprise selected portions of the conductive layer. The polishing may include: grinding the adhesive layer without grinding the thermal conductive stud and the signal stud; and then grinding the thermally conductive stud, the signal stud, the adhesive layer and the conductive layer. The removing may include: wet chemical etching the conductive layer with a patterned etch stop layer defining the pad.

Providing the bonding pad may also include: after the polishing is completed, the thermal conductive stud Depositing a conductive metal on the conductive pillar, the adhesive layer and the conductive layer to form a second conductive layer; then removing the conductive layer and selected portions of the second conductive layer, so that the solder pad comprises the conductive layer and a selected portion of the second conductive layer. Depositing the conductive metal to form the second conductive layer may include: disposing a first coating layer on the thermally conductive stud, the signal stud, the adhesive layer and the conductive layer in an electroless plating manner; The second coating layer is electroplated on the first coating layer. The removing may include: performing wet chemical etching on the conductive layer and the second conductive layer by using a patterned etch stop layer defining the pad.

Providing the terminal can include removing a selected portion of the susceptor after curing the adhesive layer. The removing may include wet chemical etching the susceptor with a patterned etch stop layer defining the terminal such that the terminal includes an unetched portion of the pedestal, the unetched portion abutting the signal The studs are separated from the base and spaced apart from each other and are therefore not part of the base. In this way, the pad and the terminal can be simultaneously formed by using different patterned etching resist layers in the same wet chemical etching step.

Providing the cover can include removing selected portions of the second conductive layer. Providing the cover may further comprise: first performing the grinding, and then removing a selected portion of the second conductive layer by using a patterned etch stop layer defining the cover such that the cover includes a selected portion of the second conductive layer . In this way, the pad and the cover can pass through the same polishing process and are simultaneously formed by the same patterned etching resist in the same wet chemical etching step.

Flowing the adhesive layer can include filling the gaps with the adhesive layer. Flowing the adhesive layer may also include: pressing the adhesive layer to pass the same The notch reaches the heat conducting stud, the signal stud and the upper portion of the substrate, and the heat conducting stud and the top surface of the signal stud are adjacent to the top surface of the substrate.

Curing the adhesive layer can include mechanically bonding the thermally conductive stud, the signal stud, and the base to the substrate.

Providing the semiconductor device may include disposing the semiconductor element on the cover. The semiconductor device may further include: the semiconductor device is disposed on the heat conducting stud, the cover, the first opening and the first through hole, and the semiconductor element is overlapped with the heat conducting stud, the cover The first opening and the first through hole do not overlap the signal post, the second opening and the second through hole.

The disposing the semiconductor device may include: providing a first solder and a second solder, wherein the first solder is located between an LED package including an LED chip and the bonding pad, and the second solder is located in the LED package Between the covers. Electrically connecting the semiconductor component can include providing the first solder between the LED package and the pad. Thermally bonding the semiconductor component can include providing the second solder between the LED package and the cover.

Providing the semiconductor device can include providing a die bond material between a semiconductor wafer and the cover. Electrically bonding the semiconductor component can include providing a wire between the wafer and the pad. Thermally bonding the semiconductor component can include providing the die attach material between the wafer and the cover.

The adhesive layer can contact the heat conducting stud, the signal stud, the base, the cover and the dielectric layer, covering the substrate from below, covering and surrounding the heat conducting stud and the signal convex in the side directions Column and extend to the group system After the completion of the fabrication, the peripheral edges formed by separation from other groups produced in the same batch are formed.

After the assembly is manufactured and separated from other groups of the same batch, the pedestal can cover the semiconductor element, the thermally conductive stud and the cover from below, while supporting the substrate and surrounding the group Keep the distance at the edge.

The invention has several advantages. The heat sink provides excellent heat dissipation and allows thermal energy to flow through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not easily delaminated. The thermally conductive stud can be integrally formed with the base to improve reliability. The cover body can be tailored to the semiconductor component to enhance the effect of thermal bonding. The adhesive layer can be interposed between the heat conducting stud and the signal stud and the substrate and between the base and the substrate, thereby providing a strong mechanical connection between the heat sink and the substrate. The wires can form a simple circuit pattern to provide signal routing or to form complex circuit patterns for flexible multilayer signal routing. The wire can also provide a vertical signal routing between the pad above the dielectric layer and the terminal below the adhesive layer. The pedestal provides mechanical support for the substrate to prevent it from bending and deforming. The assembly can be manufactured by a low temperature process, which not only reduces stress but also improves reliability. The assembly can also be fabricated using high control procedures that can be easily implemented by circuit boards, lead frames, and tape and roll substrate manufacturers.

The above and other features and advantages of the present invention will be further described hereinafter by way of various embodiments.

1A to 1D are cross-sectional views showing a method of fabricating a thermally conductive stud 22, a signal stud 24 and a pedestal 26 in accordance with an embodiment of the present invention, and FIGS. 1E and 1F are top views of FIG. 1D, respectively. Bottom view.

1A is a cross-sectional view of a metal plate 10 that includes opposing major surfaces 12 and 14. The illustrated metal plate 10 is a copper plate having a thickness of 330 microns. Copper has the advantages of high thermal conductivity, good bonding and low cost. The metal plate 10 can be made of a variety of metals such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold, mixtures thereof, and alloys thereof.

1B is a cross-sectional view showing a patterned etch stop layer 16 and a etch stop layer 18 overlying the metal plate 10. The patterned etch stop layer 16 and the over-etched etch stop layer 18 are deposited on the metal plate 10 in a photoresist layer. The photoresist layer is used to simultaneously press the photoresist layer with a hot roller. Surfaces 12 and 14. Wet spin coating and curtain coating are also suitable photoresist forming techniques. A reticle (not shown) is placed on the photoresist layer, and then light is selectively passed through the reticle to make the light-receiving portion of the light-receivable portion insoluble according to conventional techniques; The photoresist portion, which is still soluble, forms a pattern of the photoresist layer. Thus, the patterned etch stop layer 16 has a pattern of selectively exposed surface 12, while the overlying etch stop layer 18 is unpatterned and covers the surface 14.

1C is a cross-sectional view showing the metal plate 10 formed with a recess 20 which is dug but does not penetrate the metal plate 10. The recess 20 is formed by etching the metal plate 10 such that the metal plate 10 forms a pattern defined by the patterned etch stop layer 16. The etching method shown is a front wet chemical etching. For example, the structure can be reversed such that the patterned etch stop layer 16 faces downward, while the overlying etch stop layer 18 faces upward, and then a bottom nozzle (not shown) that faces the patterned etch stop layer 16 The chemical etching solution is sprayed upward on the metal plate 10 and the patterned etching resist layer 16, while at the same time, an etching is provided for the full coverage. The top nozzle (not shown) of the resist layer 18 is not activated, so that the by-product of the etching can be removed by gravity. Alternatively, the backside protection can be provided by a fully covered etch stop layer 18, and the structure can also be immersed in a chemical etchant to form the recess 20. The chemical etchant is highly targeted to copper and can be engraved into the metal sheet 10 up to 300 microns. Thus, the recess 20 extends from the surface 12 but does not penetrate the metal sheet 10, 30 microns from the surface 14, and 300 microns deep. The chemical etchant also causes lateral etch in the metal plate 10 beneath the patterned etch stop layer 16. Suitable chemical etching solutions can be alkaline ammonia-containing solutions or diluted mixtures of nitric acid and hydrochloric acid. In other words, the chemical etching solution can be acidic or alkaline. The ideal etching time sufficient to form the recess 20 without causing the metal plate 10 to be excessively exposed to the chemical etchant can be determined by trial and error.

1D, FIG. 1E, and FIG. 1F are respectively a cross-sectional view, a top view, and a bottom view of the metal plate 10 after the patterned etch stop layer 16 and the etch stop layer 18 are completely covered, wherein the etched resist layer 16 and the full cover are respectively covered. The etch stop layer 18 has been removed by solvent treatment. For example, the solvent used may be a strong alkaline potassium hydroxide solution having a pH of 14.

The etched metal plate 10 thus includes a thermally conductive stud 22, a signal stud 24, and a pedestal 26.

The thermally conductive studs 22 are one of the first unetched portions of the metal plate 10 protected by the patterned etch stop layer 16. The thermally conductive stud 22 is adjacent to the base 26 and is integral with the base 26 and projects above the base 26 and is laterally surrounded by the recess 20. The thermally conductive stud 22 is 300 microns high (equal to the depth of the groove 20), the top surface (the circular portion of the surface 12) having a diameter of 1000 microns, and the bottom portion (the circular portion adjacent the pedestal 26) having a diameter of 1100. Micron. Therefore, heat conduction The stud 22 has a flat-topped tapered cylindrical shape (like a frustum) with its side walls tapered and the diameter decreasing from the base 26 toward its flat circular top surface. The tapered sidewalls are formed by lateral etching of the chemical etchant into the patterned etch stop layer 16. The top surface is concentric with the circumference of the bottom (as shown in Figure 1E).

The signal studs 24 are one of the second unetched portions of the metal plate 10 protected by the patterned etch stop layer 16. The signal stud 24 is adjacent to the base 26 and is integral with the base 26 and projects above the base 26 and is laterally surrounded by the recess 20. The signal stud 24 is 300 microns high (equal to the depth of the groove 20), the top surface (the circular portion of the surface 12) has a diameter of 300 microns, and the bottom portion (the circular portion adjacent the pedestal 26) has a diameter of 400. Micron. Thus, the signal studs 24 are in the form of a flat-topped conical cylinder (like a frustum) with the side walls tapered and the diameter decreasing from the base 26 toward its flat circular top surface. The tapered sidewalls are formed by lateral etching of the chemical etchant into the patterned etch stop layer 16. The top surface is concentric with the circumference of the bottom (as shown in Figure 1E).

The pedestal 26 is an unetched portion of the metal plate 10 below the heat conducting stud 22 and the signal stud 24, and is laterally oriented from the heat conducting stud 22 and the signal stud 24 (such as the left and right sides). Laterally extending, the thickness is 30 microns (ie 330 microns minus 300 microns).

The thermally conductive studs 22, signal posts 24 and pedestal 26 can be treated to enhance bonding to epoxy and solder. For example, the thermally conductive studs 22, the signal studs 24, and the pedestal 26 can be chemically oxidized or microetched to create a rougher surface.

The thermally conductive studs 22, the signal studs 24 and the pedestal 26 are in the form of a single metal (copper) body formed by a reduction process. In addition, you can also use a contact to punch Pressing the metal plate 10, wherein the contact member has a first groove or hole defining a heat conducting stud 22 and a second groove or hole defining the signal stud 24, so that the heat conducting stud 22 and the signal stud 24 are The susceptor 26 is a single metal body that is stamped and formed. Alternatively, the thermally conductive studs 22 and the signal studs 24 may be formed by an additive method, and the thermally conductive studs 22 and the signal studs may be passed through electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. 24 is deposited on the susceptor 26. For example, the solder thermally conductive studs 22 and the solder signal studs 24 can be plated on the copper pedestal 26; in this case, the thermally conductive studs 22 and the pedestal 26 are joined by a metallurgical interface, adjacent to each other but not integrally formed. The signal studs 24 and the pedestal 26 are joined by a metallurgical interface, adjacent to each other but not integrally formed. Alternatively, the thermally conductive studs 22 and the signal studs 24 can be formed by a semi-additive method. For example, the thermally conductive studs 22 and the upper portions of the signal studs 24 can be respectively deposited on the lower portions of the thermally conductive studs 22 and the signal studs 24. In addition, the heat conducting studs 22, the signal studs 24 and the pedestal 26 can also be formed by a semi-additive method. For example, thermal conductive bumps can be respectively deposited on the lower portions of the thermally conductive studs 22, the signal studs 24 and the pedestals 26. The column 22, the signal stud 24 and the base 26 have the same upper portion. The thermally conductive studs 22 and the signal studs 24 can also be sintered to the pedestal 26.

2A and 2B are cross-sectional views illustrating a method of making an adhesive layer 28 in accordance with one embodiment of the present invention. 2C and 2D are a plan view and a bottom view, respectively, according to FIG. 2B.

2A is a cross-sectional view of the adhesive layer 28 in which the adhesive layer 28 is a B-stage uncured epoxy film which is an uncured and unpatterned sheet having a thickness of 180 microns.

Adhesive layer 28 can be a variety of dielectric films or films made from a variety of organic or inorganic electrical insulators. For example, the adhesive layer 28 may initially be a film in which the resin-type thermosetting epoxy resin is partially cured to a medium stage after being immersed in a reinforcing material. The epoxy resin may be FR-4, but other epoxy resins such as polyfunctional and bismaleimide-triazabenzene (BT) resins may also be used. Cyanate esters, polyimine and polytetrafluoroethylene (PTFE) are also useful epoxy resins in certain applications. The reinforcing material may be an electronic grade glass, or may be other reinforcing materials such as high-strength glass, low-induced glass, quartz, kevlar aramid, and paper. The reinforcing material may also be a woven fabric, a non-woven fabric or a non-directional microfiber. Fillers such as enamel (melt fused silica) can be added to the film to improve thermal conductivity, thermal shock resistance and thermal expansion matching. Commercially available prepregs can be utilized, such as the SPEEDBOARD C film from W. L. Gore & Associates of Oakley, Wisconsin, USA.

2B, 2C, and 2D are cross-sectional, top, and bottom views, respectively, of the adhesive layer 28 having openings 30,32. The opening 30 extends through the adhesive layer 28 and has a diameter of 1150 microns. Opening 32 extends through adhesive layer 28 and has a diameter of 450 microns. The openings 30, 32 are formed by mechanically drilling through the film, but may be fabricated by other techniques, such as stamping and stamping.

3A and 3B are cross-sectional views illustrating a method of fabricating a substrate 34 in accordance with an embodiment of the present invention, and FIGS. 3C and 3D are a plan view and a bottom view, respectively, according to FIG. 3B.

3A is a cross-sectional view of the substrate 34. The substrate 34 includes a conductive layer 36 and a dielectric layer 38. Conductive layer 36 is an electrical conductor that contacts dielectric layer 38 and extends over dielectric layer 38. Dielectric layer 38 is an electrical insulator. E.g, The conductive layer 36 is a copper plate having a pattern of 30 micrometers in thickness, and the dielectric layer 38 is an epoxy resin having a thickness of 150 micrometers.

3B, 3C, and 3D are a cross-sectional view, a plan view, and a bottom view, respectively, of the substrate 34 having the through holes 40, 42. The through hole 40 penetrates the substrate 34 and has a diameter of 1150 μm. The through hole 42 penetrates the substrate 34 and has a diameter of 450 μm. The through holes 40, 42 are formed by mechanically drilling through the conductive layer 36 and the dielectric layer 38, but may be fabricated by other techniques such as punching and stamping. Preferably, the opening 30 has the same diameter as the through hole 40 and is formed in the same manner on the same drill floor by the same drill bit; and the opening 32 and the through hole 42 also have the same diameter and are the same drill bit in the same The drill floor is formed in the same way.

The substrate 34 is illustrated as a laminate structure, but the substrate 34 can also be other electrically connected bodies, such as ceramic plates or printed circuit boards. Similarly, the substrate 34 can further comprise a plurality of layers of embedded circuits.

4A-4L are cross-sectional views illustrating a method of fabricating a thermally conductive plate 74 that includes a thermally conductive stud 22, a signal stud 24, a pedestal 26, an adhesive layer 28, and a substrate 34, in accordance with an embodiment of the present invention. 4M and 4N are a plan view and a bottom view, respectively, of FIG. 4L.

4A is a cross-sectional view showing the adhesive layer 28 disposed on the susceptor 26. The adhesive layer 28 is lowered onto the base 26 such that the thermally conductive studs 22 are inserted upwardly through the opening 30, and the signal studs 24 are inserted upwardly through the opening 32, and finally the adhesive layer 28 is contacted and positioned on the base 26. Preferably, the thermally conductive stud 22 is aligned with the opening 30 after being inserted into and through the opening 30 and is located at a central position within the opening 30 but does not contact the adhesive layer 28; and the signal stud 24 is inserted and penetrated The opening 32 is also aligned with the opening 32 and is located centrally within the opening 32 but does not contact the adhesive layer 28.

In the structure shown in FIG. 4B, the substrate 34 is disposed on the adhesive layer 28. The substrate 34 is lowered onto the adhesive layer 28 such that the thermally conductive studs 22 are inserted upwardly into the through holes 40, and the signal studs 24 are inserted upwardly into the through holes 42 to ultimately contact and position the substrate 34 to the adhesive layer 28.

The thermally conductive stud 22 is aligned with the through hole 40 after being inserted (but not penetrating) through the through hole 40 and located at a central position within the through hole 40 without contacting the substrate 34. Therefore, the notch 44 is located in the through hole 40 and between the thermally conductive stud 22 and the substrate 34. The notch 44 laterally surrounds the thermally conductive stud 22 while being laterally surrounded by the substrate 34. Further, the opening 30 and the through hole 40 are aligned with each other and have the same diameter.

The signal stud 24 is aligned with the through hole 42 after insertion (but not through) the through hole 42 and is located at a central position within the through hole 42 without contacting the substrate 34. Therefore, the notch 46 is located in the through hole 42 and between the signal stud 24 and the substrate 34. The notch 46 laterally surrounds the signal stud 24 while being laterally surrounded by the substrate 34. Further, the opening 32 and the through hole 42 are aligned with each other and have the same diameter.

At this time, the substrate 34 is disposed on and in contact with the adhesive layer 28 and extends over the adhesive layer 28. After extending through the opening 30, the thermally conductive studs 22 enter the vias 40 and reach the dielectric layer 38. The thermally conductive studs 22 are 60 microns lower than the top surface of the conductive layer 36 and are exposed in an upward direction via the vias 40. After the signal studs 24 extend through the openings 32, they enter the vias 42 and reach the dielectric layer 38. The signal stud 24 is 60 microns lower than the top surface of the conductive layer 36 and passes through the through hole 42 is exposed in the upward direction. Adhesive layer 28 contacts pedestal 26 and substrate 34 and is interposed therebetween. Adhesive layer 28 contacts dielectric layer 38 but is at a distance from conductive layer 36. At this stage, the adhesive layer 28 is still a film of B-stage uncured epoxy, while the gaps 44, 46 are air.

4C illustrates the adhesive layer 28 flowing into the gaps 44, 46 after being heated and pressurized. In this figure, the method of forcing the adhesive layer 28 into the gaps 44, 46 is to apply downward pressure to the conductive layer 36 and/or apply upward pressure to the susceptor 26, that is, to press the susceptor 26 against the substrate 34, Thereby, the adhesive layer 28 is pressed; at the same time, the adhesive layer 28 is also heated. The heated adhesive layer 28 can be arbitrarily shaped under pressure. Therefore, after the adhesive layer 28 between the susceptor 26 and the substrate 34 is pressed, its original shape is changed and flows upward into the notches 44, 46. The susceptor 26 and the substrate 34 are continuously pressed against each other until the adhesive layer 28 fills the notches 44, 46. In addition, after the gap between the susceptor 26 and the substrate 34 is reduced, the adhesive layer 28 still fills the reduced gap.

For example, the susceptor 26 and the conductive layer 36 can be disposed between a press machine and a lower pressing table (not shown). In addition, an upper baffle and an upper buffer paper (not shown) may be interposed between the conductive layer 36 and the upper pressing table, and the lower baffle and the lower cushioning paper (not shown) are placed on the base 26 . Between the lower pressing table. The stacked body thus constructed is, in order from top to bottom, an upper pressing table, an upper baffle plate, an upper baffle paper, a substrate 34, an adhesive layer 28, a susceptor 26, a lower cushioning paper, a lower baffle plate, and a lower pressing table. In addition, the stacking body can be positioned on the lower pressing table by means of a tool pin (not shown) extending upward from the lower pressing table and passing through a counter hole (not shown) of the base 26.

The upper and lower press tables are then heated and pushed into each other, whereby the adhesive layer 28 is heated and pressed. The baffle can disperse the heat of the pressing table to uniformly apply heat to the base. The holder 26 and the substrate 34 are as an adhesive layer 28. The cushioning paper disperses the pressure of the platen so that the pressure is uniformly applied to the susceptor 26 and the substrate 34 or even the adhesive layer 28. Initially, the dielectric layer 38 contacts and is pressed against the adhesive layer 28. As the platen continues to operate and continues to heat, the adhesive layer 28 between the susceptor 26 and the substrate 34 is squeezed and begins to melt, thereby flowing upward into the notches 44, 46 and after reaching the conductive layer 36 after passing through the dielectric layer 38. For example, the uncured epoxy resin is melted into the gaps 44, 46 after being melted by heat, but the reinforcing material and the filler remain between the susceptor 26 and the substrate 34. The adhesive layer 28 rises faster in the through hole 40 than the thermally conductive stud 22, and finally fills the notch 44. The adhesive layer 28 also rises faster in the through hole 42 than the signal stud 24, and finally fills the notch 46. The adhesive layer 28 also rises slightly above the notches 44, 46 and overflows to the top surface of the thermally conductive stud 22 and the top surface of the conductive layer 36 adjacent the notch 44 and the top of the signal stud 24 before the platen stops operating. The top surface of the surface and conductive layer 36 abuts the notch 46. This can happen if the film thickness is slightly larger than actually needed. As a result, the adhesive layer 28 forms a thin layer of cover on the top surface of the heat conducting stud 22 and the top surface of the signal stud 24 . The platen stops after touching the thermally conductive studs 22 and the signal studs 24, but continues to heat the adhesive layer 28.

The direction in which the adhesive layer 28 flows upward in the notches 44, 46 is as shown by the upward bold arrow in the figure, and the thermal conductive post 22, the signal stud 24 and the pedestal 26 move upward relative to the substrate 34 as indicated by the upward arrow. The downward movement of the substrate 34 relative to the thermally conductive studs 22, the signal studs 24 and the pedestal 26 is as indicated by the downwardly thin arrows.

The adhesive layer 28 in Figure 4D has cured.

For example, after the platen stops moving, the heat conducting stud 22 and the signal are continuously clamped. The studs 24 are heated with the susceptor 26, thereby converting the melted B-stage epoxy to a C-stage cured or hardened epoxy. Therefore, the epoxy resin is cured in a manner similar to conventional lamination. After the epoxy resin is cured, the platen is separated to remove the structure from the press.

The cured adhesive layer 28 provides a secure mechanical bond between the thermally conductive stud 22 and the substrate 34, between the signal studs 24 and the substrate 34, and between the pedestal 26 and the substrate 34. The adhesive layer 28 can withstand normal operating pressure without deformation and damage, and is only temporarily distorted when excessive pressure is applied. Furthermore, the adhesive layer 28 can absorb the thermal expansion mismatch between the thermally conductive studs 22 and the substrate 34, between the signal studs 24 and the substrate 34, and between the pedestal 26 and the substrate 34.

At this stage, the thermally conductive studs 22, signal posts 24 and the conductive layer 36 are substantially coplanar, and the adhesive layer 28 and the conductive layer 36 extend to a top surface of the upward direction. For example, the adhesive layer 28 between the pedestal 26 and the dielectric layer 38 is 120 microns thicker, and is 60 microns smaller than its initial thickness of 180 microns; that is, the thermally conductive stud 22 is raised 60 microns in the through hole 40, and the signal studs 24 are The via 42 is raised by 60 microns, and the substrate 34 is lowered by 60 microns with respect to the thermally conductive stud 22 and the signal stud 24. The height of the thermally conductive studs 22 and the signal studs 24 is substantially equal to the combined height of the conductive layer 36 (30 microns), the dielectric layer 38 (150 microns) and the underlying adhesive layer 28 (120 microns). In addition, the heat conducting stud 22 is still located at a central position in the opening 30 and the through hole 40 and is spaced apart from the substrate 34. The signal stud 24 is still located at a central position in the opening 32 and the through hole 42 and is spaced apart from the substrate 34, and adhered. Layer 28 fills the space between pedestal 26 and substrate 34 and fills gaps 44,46. For example, the notch 44 (and the adhesive layer 28 between the thermally conductive stud 22 and the substrate 34) is on the top surface of the thermally conductive stud 22 At a width of 75 microns (i.e., 1150 microns minus 1000 microns divided by 2), the notch 46 (and the adhesion layer 28 between the signal studs 24 and the substrate 34) is 75 microns wider at the top surface of the signal studs 24 (450 300 )/2). Adhesive layer 28 extends across dielectric layer 38 within indentations 44,46. In other words, the adhesive layer 28 in the notch 44 extends along the upward direction and a downward direction and across the thickness of the dielectric layer 38 of the outer sidewall of the notch 44, and the adhesive layer 28 in the notch 46 is along the upward direction and the downward direction. The thickness of the dielectric layer 38 extends and spans the outer sidewall of the notch 46. The adhesive layer 28 also includes a thin top portion above the notches 44, 46 that contacts the top surface of the thermally conductive stud 22, the signal post 24 and the top surface of the conductive layer 36 and extends over the thermally conductive stud 22 and the signal studs 24 Micron.

In the structure shown in FIG. 4E, the tops of the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36 have been removed.

The tops of the thermally conductive studs 22, signal posts 24, adhesive layer 28, and conductive layer 36 are removed by grinding, such as by rotating the diamond wheel and the top of the structured water. Initially, the diamond wheel only scratches the adhesive layer 28. With continuous grinding, the adhesive layer 28 becomes thinner as the surface to be worn is moved downward. The diamond wheel will eventually contact the thermally conductive stud 22, the signal stud 24 and the conductive layer 36 (not necessarily simultaneously), thus beginning to polish the thermally conductive stud 22, the signal stud 24 and the conductive layer 36. After continuous grinding, the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36 are all thinned by the worn surface being moved down. The grinding continues until the desired thickness is removed. Thereafter, the structure was rinsed with distilled water to remove dirt.

The grinding step removes the top of the adhesive layer 28 by 25 microns, the top of the thermally conductive stud 22 by 15 microns, the top of the signal stud 24 by 15 microns, and the top of the conductive layer 36 by 15 microns. Thickness reduction The thermally conductive studs 22, the signal studs 24, or the adhesive layer 28 have no significant effect, but the thickness of the conductive layer 36 is greatly reduced from 30 microns to 15 microns.

At this point, the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36 are collectively located above the dielectric layer 38 toward the smooth splicing side top surface of the upward direction. Similarly, the thermally conductive studs 22, signal posts 24, and adhesive layer 28 are coplanar with each other at the pedestal 26.

The structure shown in FIG. 4F has a conductive layer 50 deposited on the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36.

The conductive layer 50 contacts the thermally conductive studs 22, the signal studs 24, the adhesive layer 28, and the conductive layer 36, and covers the four from above. For example, the structure can be immersed in an activator solution, so that the adhesive layer 28 can react with the electroless copper to generate a catalyst, and then a first copper layer is provided on the thermally conductive stud 22 and the signal convex in an electroless plating manner. On the pillar 24, the adhesive layer 28 and the conductive layer 36, a second copper layer is then electroplated on the first copper layer. The first copper layer is about 2 microns thick and the second copper layer is about 13 microns thick, so the total thickness of the conductive layer 50 is about 15 microns. As a result, the thickness of the conductive layer 36 is increased to about 30 microns (15 + 15). The conductive layer 50 serves as a thickening layer of the thermal conductive stud 22 and the signal bump 24 and the conductive layer 36. For convenience of description, the thermal conductive studs 22, the signal studs 24 and the conductive layer 50, and the conductive layers 36 and 50 are all shown in a single layer. Since the copper is a homogeneous coating, the boundary between the heat conducting stud 22 and the conductive layer 50, the boundary between the signal stud 24 and the conductive layer 50, and the boundary between the conductive layers 36 and 50 (both shown by dashed lines) may be difficult to detect or even aware. However, the boundary between the adhesive layer 28 and the conductive layer 50 is clearly visible.

A patterned etching is provided on the upper surface and the lower surface of the structure shown in FIG. 4G. The resist layer 52 and the patterned etch stop layer 54. The illustrated patterned etch stop layers 52, 54 are all photoresist layers similar to the patterned etch stop layer 16. The patterned etch stop layer 52 is provided with a pattern that selectively exposes the conductive layer 50, and the patterned etch stop layer 54 is provided with a pattern that selectively exposes the pedestal 26.

In the structure shown in FIG. 4H, the conductive layers 36, 50 have been removed by etching to select portions thereof to form a pattern defined by the patterned etch stop layer 52, and the pedestal 26 has also been removed by etching to select selected portions thereof. A pattern defined by the patterned etch stop layer 54. The etching is a two-sided wet chemical etching similar to that applied to the metal plate 10. For example, a top nozzle (not shown) and a bottom nozzle (not shown) are used to spray the chemical etching solution on the top and bottom surfaces of the structure, respectively, or to immerse the structure in the chemical etching solution. The chemical etchant etches through the conductive layers 36, 50 to expose the adhesive layer 28 and the dielectric layer 38, thereby converting the originally unpatterned conductive layers 36, 50 into a patterned layer. The chemical etchant also erodes the susceptor 26 to expose the adhesive layer 28.

In Figure 4I, the patterned etch stop layers 52, 54 on the structure have been removed. The manner in which the patterned etch stop layers 52, 54 are removed may be the same as the manner in which the patterned etch stop layer 16 is removed and the etch stop layer 18 is completely covered.

The etched conductive layers 36, 50 include pads 56 and routing lines 58, and the etched conductive layer 50 includes a cover 60. The pad 56 and the routing line 58 are electrically protected layers 36, 50 protected by the patterned etch stop layer 52, and the cover 60 is protected by the patterned etch stop layer 52. Part of it. As such, the conductive layers 36, 50 become patterned layers that include the pads 56 and routing lines 58 but do not include the cover 60. In addition, routing line 58 is a copper wire that contacts dielectric layer 38 and extends above it. At the same time, the signal bumps 24 and the pads 56 are electrically connected adjacent to each other.

The etched susceptor 26 includes a pedestal 26 (only the central portion remains) and a terminal 62. The pedestal 26 is the portion of the original pedestal 26 that is protected by the patterned etch stop layer 54 and that is not etched, extending laterally and 1000 microns beyond the thermally conductive studs 22 in the lateral direction. The terminal 62 is a portion of the original pedestal 26 that is protected by the patterned etch stop layer 54 and is not etched. The adjacent signal post 24 extends below the signal stud 24 and extends laterally from the signal stud 24 . At the same time, the adhesive layer 28 is contacted and extends below the adhesive layer 28. The pedestal 26 is still a non-patterned layer, but a patterned layer comprising terminals 62 and laterally spaced from the pedestal 26 is formed outside the periphery of the pedestal 26. Therefore, the terminal 62 and the base 26 are separated from each other, and the terminal 62 is not part of the base 26. In addition, the signal studs 24 abut the routing line 58 and the terminal 62 and form an electrical connection between the routing line 58 and the terminal 62.

Signal bumps 24, pads 56, routing lines 58, and terminals 62 collectively form wires 64. The signal studs 24 and routing lines 58 are one of the conductive paths between the pads 56 and the terminals 62. Wire 64 provides a vertical (top to bottom) routing from pad 56 to terminal 62. The wire 64 is not limited to this configuration. For example, the conductive path may further include conductive vias through the dielectric layer 38, additional routing lines (which are above and/or below the dielectric layer 38), and passive components (such as resistors disposed on other pads). capacitance).

The heat sink 66 includes a heat conductive stud 22, a base 26 and a cover 60. The thermally conductive stud 22 is integrally formed with the base 26. The cover 60 is located above the top of the thermally conductive stud 22 adjacent to the top of the thermally conductive stud 22 while covering the top of the thermally conductive stud 22 from above and extending laterally from the top of the thermally conductive stud 22. After the cover 60 is disposed, the thermally conductive studs 22 are located in a central region within the circumference of the cover 60. The cover 60 also contacts and covers a portion of the adhesive layer 28 therebelow from above. The portion of the adhesive layer 28 is coplanar with the thermally conductive studs 22, abuts the thermally conductive studs 22, and laterally surrounds the thermally conductive studs 22.

The heat sink 66 is substantially an inverted T-shaped heat sink block including a post portion (thermal conductive stud 22), a wing portion (a portion of the base 26 extending laterally from the post portion), and a thermal pad (cover 60).

The structure of FIG. 4J is provided with a solder resist green paint 68 on the adhesive layer 28, the dielectric layer 38, the conductive layer 50 and the cover 60, and the solder resist green paint is provided on the base 26, the adhesive layer 28 and the terminal 62. 70.

The solder resist green paint 68 is an electrical insulating layer which can be patterned to expose the solder pad 56 and the cover 60, and covers the routing line 58, the exposed portion of the adhesive layer 28 and the dielectric layer 38 from above. Exposed part. The solder resist green lacquer 68 has a thickness of 25 microns above the pad 56 and the cover 60, and the solder resist green lacquer 68 extends 55 microns (30+25) above the dielectric layer 38.

The solder resist green paint 70 is an electrically insulating layer that can be patterned to expose the pedestal 26 and the terminal 62 and to cover the exposed portion of the adhesive layer 28 from below. The solder resist green lacquer 70 has a thickness of 25 microns below the pedestal 26 and the terminal 62, and the solder resist green lacquer 70 extends 55 microns (30+25) below the adhesive layer 28.

The solder resist green paints 68 and 70 were originally coated with a light-developing liquid resin on the structure. Then, a pattern is formed on the solder resist green paints 68 and 70. The method is to selectively pass light through the mask (not shown), so that the portion of the light-shielded green paint becomes insoluble, and then removes the solution by using a developing solution. Light and still soluble Part of the anti-weld green paint is solved, and finally hard baking is performed. The above steps are known techniques.

The base 26, the pad 56, the cover 60, and the terminal 62 of the structure shown in Fig. 4K are provided with covered contacts 72.

The coated contact 72 is a multi-layer metal coating that contacts the pedestal 26 and the terminal 62 and covers the exposed portion thereof from below while contacting the pad 56 and the cover 60 and covering the exposed portion thereof from above. For example, a nickel layer is provided on the susceptor 26, the pad 56, the cover 60 and the terminal 62 in an electroless plating manner, and then a gold layer is provided on the nickel layer in an electroless plating manner, wherein The inner nickel layer is about 3 microns thick and the surface gold layer is about 0.5 microns thick, so the thickness of the coated contact 72 is about 3.5 microns.

The surface treatment with the covered contacts 72 as the pedestal 26, the pads 56, the cover 60 and the terminals 62 has several advantages. The inner nickel layer provides primary mechanical and electrical bonding and/or thermal bonding, while the surface gold layer provides a wettable surface for solder reflow. The covered contacts 72 also protect the susceptor 26, the pads 56, the cover 60 and the terminals 62 from corrosion. The coated contacts 72 can contain a variety of metals to meet the needs of externally coupled media. For example, a layer of silver coated on a nickel layer can be soldered or wired.

For convenience of explanation, the susceptor 26 provided with the covered contacts 72, the pads 56, the cover 60 and the terminals 62 are all displayed in a single layer. The boundary (not shown) between the covered contact 72 and the susceptor 26, the pad 56, the cover 60 and the terminal 62 is a copper/nickel interface.

The fabrication of the heat conducting plate 74 is thus completed.

4L, 4M, and 4N are cross-sectional views of the heat conducting plate 74, respectively. View and bottom view, the edges of the heat conducting plate 74 in the figure have been separated along the cutting line from the support frame and/or the adjacent heat transfer plates produced in the same batch.

The heat conducting plate 74 includes an adhesive layer 28, a substrate 34, a wire 64, a heat sink 66, and solder resist green paints 68, 70. Substrate 34 includes a dielectric layer 38. Wire 64 includes signal studs 24, pads 56, routing lines 58, and terminals 62. The heat sink 66 includes a heat conductive stud 22, a base 26 and a cover 60.

After the heat conducting stud 22 extends through the opening 30 and enters the through hole 40, it is still located at a central position within the opening 30 and the through hole 40. The top of the thermally conductive stud 22 is coplanar with an adjacent portion of the adhesive layer 28 above the dielectric layer 38, and the bottom of the thermally conductive stud 22 is coplanar with an adjacent portion of the adhesive layer 28 that contacts the pedestal 26. The thermally conductive studs 22 maintain a flat-topped tapered cylindrical shape with tapered side walls that decrease in diameter from the base 26 toward the flattened dome of the thermally conductive stud 22 adjacent the cover 60.

After the signal stud 24 extends through the opening 32 and enters the through hole 42, it is still located at a central position within the opening 32 and the through hole 42. The top of the signal stud 24 is coplanar with an adjacent portion of the adhesive layer 28 above the dielectric layer 38, and the bottom of the signal stud 24 is coplanar with an adjacent portion of the adhesive layer 28 that contacts the terminal 62. The signal studs 24 maintain a flat-topped tapered cylindrical shape with tapered side walls that decrease in diameter from the terminal 62 toward the flat dome of the signal post 24 adjacent the routing line 58.

The pedestal 26 covers the thermally conductive stud 22 and the cover 60 from below and is spaced from the peripheral edge of the thermally conductive plate 74.

The cover 60 is located above the thermally conductive stud 22 adjacent thereto and is thermally coupled. The cover body 60 simultaneously covers the top of the heat conducting stud 22 from above and is self-conducting The top of the stud 22 extends laterally. The cover 60 also contacts and covers a portion of the adhesive layer 28 from above, the portion of the adhesive layer 28 abutting the thermally conductive studs 22, coplanar with the thermally conductive studs 22, and laterally surrounding the thermally conductive studs 22. The cover 60 is also coplanar with the pads 56.

The adhesive layer 28 is disposed on the base 26 and extends above it. The adhesive layer 28 contacts the gap between the thermally conductive studs 22 and the dielectric layer 38 and fills the space between the thermally conductive studs 22 and the dielectric layer 38. The adhesive layer 28 contacts the gap 46 between the signal stud 24 and the dielectric layer 38 and fills the space between the signal studs 24 and the dielectric layer 38. Adhesive layer 28 contacts outside of gaps 44, 46 and is interposed between susceptor 26 and dielectric layer 38 and fills the space between pedestal 26 and dielectric layer 38. The adhesive layer 28 extends laterally from the thermally conductive stud 22 and over the terminal 62, overlying the terminal 62, and covers the pedestal 26 from above with a portion outside the periphery of the thermally conductive stud 22 while covering in the lateral direction and surrounding the thermally conductive stud 22 And the signal studs 24. Adhesive layer 28 also fills most of the space between substrate 34 and heat sink 66. At this point the adhesive layer 28 has cured.

The substrate 34 is disposed on and in contact with the adhesive layer 28. In addition, the substrate 34 extends above the underlying adhesive layer 28 and over the susceptor 26. Conductive layer 36 (and pad 56 and routing line 58) contact dielectric layer 38 and extend thereover, while dielectric layer 38 contacts and is between adhesive layer 28 and conductive layer 36.

The thermally conductive studs 22 have the same thickness as the signal studs 24 and are coplanar with each other. The pedestal 26 has the same thickness as the terminals 62 and is coplanar with each other. In addition, the thermal conductive studs 22, the top and bottom of the signal studs 24 and the adhesive layer 28 Coplanar.

The thermally conductive studs 22, the signal studs 24, the pedestal 26, the cover 60, and the terminals 62 are all spaced from the substrate 34. Therefore, the substrate 34 is mechanically coupled to the heat sink 66 and electrically isolated from each other.

After the same batch of thermally conductive plates 74 are cut, the adhesive layer 28, the dielectric layer 38 and the solder resist green paints 68, 70 extend to the cut vertical edges.

The pad 56 is an electrical interface tailored to a semiconductor component such as an LED package or a semiconductor wafer, and the semiconductor component is disposed on the cover 60 in a subsequent process. Terminal 62 is an electrical interface tailored to the next layer of components (e.g., solderable wires from a printed circuit board). The cover 60 is a thermal interface tailored to the semiconductor component. The pedestal 26 is a thermal interface tailored to the next layer of components, such as the aforementioned printed circuit board or a heat sink for an electronic device. Further, the cover 60 is thermally coupled to the susceptor 26 via the thermally conductive studs 22 .

The pad 56 and the terminal 62 are offset from each other in the vertical direction, and are respectively exposed on the top surface and the bottom surface of the heat conducting plate 74, thereby providing a vertical route between the semiconductor element and the next layer assembly.

The top surface of both the pad 56 and the cover 60 is coplanar above the dielectric layer 38, and the bottom surfaces of both the pedestal 26 and the terminal 62 are coplanar below the adhesive layer 28.

For ease of illustration, the wire 64 is depicted as a continuous circuit trace in cross-sectional view. However, the wires 64 typically provide horizontal signal routing in the X and Y directions, i.e., the pads 56 and the terminals 62 are laterally offset from each other in the X and Y directions, and the routing lines 58 form the path in the X and Y directions.

The heat sink 66 can diffuse the thermal energy generated by the semiconductor component subsequently disposed on the cover 60 to a lower group to which the heat conducting plate 74 is connected. The thermal energy generated by the semiconductor component flows into the cover 60, enters the thermally conductive stud 22 from the cover 60, and enters the susceptor 26 via the thermally conductive stud 22. Thermal energy is dissipated from the susceptor 26 in the downward direction, for example, to a lower heat sink.

The heat conducting studs 22, the signal studs 24 and the routing wires 58 of the heat conducting plate 74 are not exposed, wherein the heat conducting studs 22 are covered by the cover 60, and the signal studs 24 and the routing wires 58 are covered by the solder resist green paint 68. The adhesive layer 28 is simultaneously covered by the solder resist green paints 68, 70. For convenience of description, FIG. 4M shows the heat conducting stud 22, the signal stud 24, the adhesive layer 28 and the routing line 58 in broken lines.

The heat conducting plate 74 also includes other wires 64 that are substantially comprised of signal posts 24, pads 56, routing lines 58, and terminals 62. For ease of explanation, only a single wire 64 is illustrated and illustrated herein. In the wire 64, the signal posts 24, pads 56 and terminals 62 generally have the same shape and size, while the routing wires 58 are typically of a different routing configuration. For example, portions of the wires 64 are spaced apart from each other and electrically isolated, and the partial wires 64 are staggered or directed to the same pad 56, routing line 58 or terminal 62 and electrically coupled to each other. Similarly, a portion of the pads 56 can be used to receive independent signals, while a portion of the pads 56 share a signal, power supply, or ground.

The heat conducting plate 74 can be applied to an LED package having blue, green, and red LED chips, wherein each LED chip includes an anode and a cathode, and each LED package includes a corresponding anode terminal and cathode terminal. In this example, the thermally conductive plate 74 can include six pads 56 and four terminals 62 to direct each anode from a separate pad 56 to a separate terminal 62, and each cathode is A separate pad 56 is directed to a common ground terminal 62.

A simple cleaning step can be used at each stage of manufacture to remove oxides and residues from the exposed metal. For example, a short oxygen plasma cleaning step can be applied to the structure of the present invention. Alternatively, the structure of the present invention can be subjected to a brief wet chemical cleaning step using a potassium permanganate solution. Similarly, the structure can be rinsed with distilled water to remove dirt. This cleaning step cleans the desired surface without causing significant damage or damage to the structure.

The advantage of this case is that there is no need to separate or separate the confluence points or associated circuitry from the wires 64 after they are formed. The sink point can be separated during the wet chemical etching step of forming pad 56, routing line 58, cover 60 and terminal 62.

The heat conducting plate 74 may include a counter hole (not shown) formed by drilling or cutting through the adhesive layer 28, the substrate 34 and the solder resist green paint 68, 70. In this way, when the heat conducting plate 74 needs to be disposed on a lower carrier in a subsequent process, the tool pin can be inserted into the alignment hole to position the heat conducting plate 74.

The cover 60 can be omitted from the heat conducting plate 74. To achieve this, the patterned etch stop layer 52 can be adjusted such that the conductive layer 50 over the entire via 40 is exposed to the chemical etchant used to form the pads 56 and routing lines 58. Another method of omitting the cover 60 is to provide no conductive layer 50.

The heat conducting plate 74 can accommodate a plurality of semiconductor components instead of only a single semiconductor component. To achieve this, the patterned etch stop layer 16 can be modified to define more thermally conductive posts 22 and signal posts 24, the adhesive layer 28 can be adjusted to include more openings 30, 32, and the substrate 34 can be adjusted to include more passes. The holes 40, 42 are patterned to etch the etch stop layer 52 to define more pads 56, routing lines 58 and cover 60, and to adjust the solder resist green lacquer 68 to include more openings. Terminal 62 Components other than the ones can change the lateral position to provide a 2x2 array for the four semiconductor components. In addition, the cross-sectional shape and height (ie, side shape) of some but not all components may be adjusted. For example, pad 56, cover 60 and terminal 62 may maintain the same side shape, while routing line 58 has a different routing configuration.

5A, 5B, and 5C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate 76 according to an embodiment of the present invention. The heat conducting plate 76 is provided with a wire 64 on the adhesive layer 28.

In this embodiment, the dielectric layer 38 is omitted and the wires 64 are in contact with the adhesive layer 28. For the sake of brevity, the description of the heat conducting plate 74 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate 76 of this embodiment are similar to those of the heat conducting plate 74, and corresponding reference numerals are used.

The thermally conductive plate 76 includes an adhesive layer 28, wires 64, heat sinks 66 and solder resist green paints 68,70. Wire 64 includes signal studs 24, pads 56, routing lines 58, and terminals 62. The heat sink 66 includes a heat conductive stud 22, a base 26 and a cover 60.

The conductive layer 36 of this embodiment is thicker than the previous embodiment. For example, the thickness of the conductive layer 36 is increased from 30 micrometers to 130 micrometers in the previous embodiment, so that the conductive layer 36 does not bend and sway during handling. The thickness of pad 56 and routing line 58 is also increased, and pad 56 and routing line 58 both contact and overlap the adhesive layer 28. Thermally conductive plate 76 does not have a dielectric layer corresponding to dielectric layer 38.

The heat conducting plate 76 is fabricated in a manner similar to the heat conducting plate 74, but must be a guide The heat studs 22, the signal studs 24 and the conductive layer 36 are appropriately adjusted. For example, the thickness of the metal plate 10 is changed from 330 micrometers to 280 micrometers, so that the height of the heat conducting studs 22 and the signal studs 24 is reduced from 300 micrometers to 250 micrometers. This can be achieved by shortening the etching time. Then, the adhesive layer 28 is disposed on the susceptor 26 in the manner described above, and the conductive layer 36 is separately disposed on the adhesive layer 28; the adhesive layer 28 is heated and pressurized to cause the adhesive layer 28 to flow and solidify; The top surface of the structure is planarized by grinding, and the conductive layer 50 is deposited on the top surface. The conductive layers 36, 50 are then etched to form the pads 56 and routing lines 58, the conductive layer 50 is etched to form the cover 60, the pedestal 26 is etched to form the terminals 62, and the solder resist green lacquer 68 is placed over the top surface to select The pad 56 and the cover 60 are exposed, and the solder resist green paint 70 is disposed on the bottom surface of the structure to selectively expose the pedestal 26 and the terminal 62. Finally, the lap joint 72 is used as the pedestal 26 and the pad 56. The cover 60 and the terminal 62 are surface-treated.

6A, FIG. 6B and FIG. 6C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer package 100 according to an embodiment of the present invention. The semiconductor wafer package 100 includes a heat conducting plate 74 and an LED package having a back contact. Body 102.

The semiconductor wafer package 100 includes a heat conductive plate 74, an LED package 102, and solders 104 and 106. The LED package 102 includes an LED wafer 108, a pedestal 110, a wire 112, electrical contacts 114, thermal contacts 116, and a transparent encapsulation material 118. An electrode (not shown) of the LED chip 108 is electrically connected to one of the conductive holes (not shown) of the susceptor 110 via the wire 112 to electrically connect the LED chip 108 to the electrical contact 114. LED chip 108 is transmitted through a solid crystal A material (not shown) is disposed on the susceptor 110 to thermally bond and mechanically adhere the LED wafer 108 to the susceptor 110, thereby thermally bonding the LED wafer 108 to the thermal junction 116. The susceptor 110 is a ceramic block having low conductivity and high thermal conductivity. The electrical contact 114 and the thermal contact 116 are covered on the back of the pedestal 110 and protrude downward from the back of the pedestal 110.

The LED package 102 is disposed on the substrate 34 and the heat sink 66 , electrically connected to the substrate 34 , and thermally coupled to the heat sink 66 . In detail, the LED package 102 is disposed on the pad 56 and the lid 60 , overlaps the heat conducting stud 22 , is electrically connected to the substrate 34 via the solder 104 , and is thermally coupled to the heat sink 66 via the solder 106 . For example, the solder 104 contacts and is located between the pad 56 and the electrical contact 114 , and electrically and mechanically bonds the pad 56 and the electrical contact 114 , thereby electrically connecting the LED chip 108 to the terminal 62 . Similarly, the solder 106 contacts and is located between the cover 60 and the thermal contact 116 while thermally bonding and mechanically bonding the cover 60 to the thermal contact 116, thereby thermally bonding the LED wafer 108 to the pedestal 26. The pad 56 is provided with a nickel/gold coated metal pad for stable bonding with the solder 104, and the pad 56 is shaped and sized to match the electrical contact 114, thereby improving the signal from the substrate 34 to the LED package 102. Conduction. Similarly, the cover 60 is provided with a nickel/gold coated metal pad for stable bonding with the solder 106, and the shape and size of the cover 60 are matched with the thermal contact 116, thereby improving the self-LED package 102 to heat dissipation. Heat transfer from seat 66. The shape and size of the thermally conductive studs 22 are not and do not need to be designed in conjunction with the thermal contacts 116.

The transparent encapsulating material 118 is a solid electrically insulating protective plastic covering, which can provide anti-moisture and anti-micro for the LED chip 108 and the wire 112. Environmental protection such as grain. The LED chip 108 and the wire 112 are embedded in the transparent encapsulation material 118.

If the semiconductor wafer package 100 is to be fabricated, a solder may be deposited on the pad 56 and the cover 60, and then the contacts 114 and 116 are placed on the pads 56 and the solder over the cover 60, respectively. Reflow is performed to form subsequent solders 104,106.

For example, the solder paste is selectively printed on the pad 56 and the cover 60 by screen printing, and then the LED package 102 is placed in a step-and-repeat manner by using a grab head and an automated pattern recognition system. On the heat conducting plate 74. The grabbing head of the reflow machine places the electric contact 114 and the hot contact 116 on the solder paste 56 and the solder paste above the cover 60, respectively. The solder paste is then heated to reflow at a relatively low temperature (e.g., 190oC), then the heat source is removed, and the solder paste is allowed to cool and solidify to form hardened solders 104,106. Alternatively, a solder ball may be placed on the pad 56 and the cover 60, and then the electrical contact 114 and the hot contact 116 are respectively placed on the solder ball 56 and the solder ball above the cover 60, and then the solder ball is heated to be returned. Soldering to form subsequent solders 104,106.

The solder may initially be deposited on the thermally conductive plate 74 or the LED package 102 via coating or printing or placement techniques between the thermally conductive plate 74 and the LED package 102 and reflowed. Solder can also be placed on terminal 62 for use by the next layer of the assembly. In addition, the solder may be replaced by a conductive adhesive (for example, a silver-filled epoxy) or other bonding medium, and the bonding pads 56, the cover 60 and the connecting medium on the terminal 62 are not necessarily the same.

The semiconductor wafer package 100 is a second-level single crystal module.

7A, 7B and 7C are respectively a half guide according to an embodiment of the present invention. The semiconductor wafer package 200 includes a heat conducting plate 74 and an LED package 202 having side pins.

In this embodiment, the LED package 202 has side pins and no back contacts. For the sake of brevity, the description of the semiconductor wafer package 100 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the assembly of this embodiment are similar to those of the component 100, and the corresponding reference numerals are used, but the base number of the coding is changed from 100 to 200. For example, LED die 208 corresponds to LED die 108, while pedestal 210 corresponds to pedestal 110, and so on.

The semiconductor wafer package 200 includes a heat conductive plate 74, an LED package 202, and solders 204, 206. The LED package 202 includes an LED wafer 208, a pedestal 210, a wire 212, a pin 214, and a transparent encapsulation material 218. The LED chip 208 is electrically coupled to the pin 214 via the wire 212. The back side of the susceptor 210 includes a thermal contact surface 216. Further, the pedestal 210 is narrower than the pedestal 110 and has the same lateral dimensions and shape as the thermal junction 116. The LED chip 208 is disposed on the susceptor 210 via a die bonding material (not shown) to thermally bond and mechanically adhere the LED chip 208 to the susceptor 210, thereby thermally bonding the LED chip 208 to the thermal contact surface 216. . Pin 214 extends laterally from pedestal 210 while thermal contact surface 216 faces downward.

The LED package 202 is disposed on the substrate 34 and the heat sink 66 , electrically connected to the substrate 34 , and thermally coupled to the heat sink 66 . In detail, the LED package 202 is disposed on the pad 56 and the cover 60, overlaps the heat conducting stud 22, and is electrically connected to the substrate 34 via the solder 204, and is soldered via the solder. 206 is thermally coupled to the heat sink 66. For example, the solder 204 contacts and is located between the pad 56 and the pin 214 , and electrically and mechanically bonds the pad 56 and the pin 214 , thereby electrically connecting the LED chip 208 to the terminal 62 . Similarly, the solder 206 contacts and is positioned between the cover 60 and the thermal contact surface 216 while thermally bonding and mechanically bonding the cover 60 to the thermal contact surface 216, thereby thermally bonding the LED wafer 208 to the pedestal 26.

If the semiconductor wafer package 200 is to be fabricated, a solder may be placed on the pad 56 and the cover 60, and then the pins 214 and the thermal contact surface 216 are placed on the solder over the pads 56 and the cover 60, respectively. The solder is reflowed to form the next solder 204, 206.

The semiconductor wafer package 200 is a second-level single crystal module.

8A, 8B, and 8C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer assembly 300 in accordance with an embodiment of the present invention, wherein the semiconductor wafer assembly 300 includes a thermally conductive plate 74 and a semiconductor wafer 302.

In this embodiment, the semiconductor component is a wafer instead of a package, and the wafer 302 is disposed on the heat sink 66 instead of the substrate 34. In addition, the wafer 302 is superposed on the heat conducting stud 22 instead of the substrate 34, and the wafer 302 is electrically connected to the pad 56 via a wire and thermally bonded to the cover 60 by a die bonding material 306. .

The semiconductor wafer package 300 includes a heat conducting plate 74, a wafer 302, a wire bonding 304, a die bonding material 306, and an encapsulating material 308. The wafer 302 includes a top surface 310, a bottom surface 312, and a wire bonding pad 314. The top surface 310 is an active surface and includes a wire bond pad 314, while the bottom surface 312 is a thermal contact surface.

The chip 302 is disposed on the heat sink 66 and electrically connected to the substrate 34. And thermally coupled to the heat sink 66. In detail, the wafer 302 is disposed on the cover 60 and is located in the periphery of the cover 60 and overlaps the thermally conductive stud 22 but does not overlap the substrate 34. In addition, the wafer 302 is electrically connected to the substrate 34 via the bonding wires 304 while being thermally coupled via the die bonding material 306 and mechanically adhered to the heat sink 66. For example, the wire 304 is connected to the electrically conductive pad 56 and the wire bonding pad 314, thereby electrically connecting the wafer 302 to the terminal 62. Similarly, the die bond material 306 contacts and is positioned between the cover 60 and the thermal contact surface 312 while thermally bonding and mechanically bonding the cover 60 to the thermal contact surface 312, thereby thermally bonding the wafer 302 to the pedestal 26. The pad 56 is provided with a nickel/silver coated metal pad for secure bonding with the wire 304, thereby improving signal transmission from the substrate 34 to the wafer 302. In addition, the shape and size of the cover 60 is adapted to the thermal contact surface 312, thereby improving heat transfer from the wafer 302 to the heat sink 66. The shape and size of the thermally conductive studs 22 are not and do not need to be designed in conjunction with the thermal contact surface 312.

The encapsulating material 308 is a solid electrically insulating protective plastic covering body, which can provide environmental protection against moisture and anti-particles for the wafer 302 and the wire bonding 304. The wafer 302 and the wire 304 are embedded in the encapsulation material 308. Additionally, if wafer 302 is an optical wafer such as an LED, encapsulation material 308 can be transparent. The encapsulating material 308 is transparent in FIG. 8B for ease of illustration.

If the semiconductor wafer assembly 300 is to be fabricated, the wafer 302 can be placed on the cover 60 by using the die bonding material 306, and then the bonding pads 56 and the bonding pads 314 are bonded by wire bonding, and then the sealing material 308 is formed.

For example, the solid crystal material 306 is originally a silver-containing epoxy having high thermal conductivity. The resin paste is selectively printed on the cover 60 by screen printing. The wafer 302 is then placed on the epoxy silver paste in a step-and-repeat manner using a pick-up head and an automated pattern recognition system. The epoxy silver paste is then heated and allowed to harden at a relatively low temperature (e.g., 190 ° C) to complete the solid crystal. The wire 304 is a gold wire which is then connected to the bonding pad 56 and the wire bonding pad 314 by thermal ultrasonic waves. Finally, the encapsulation material 308 is transferred onto the structure.

The wafer 302 can be electrically connected to the bonding pad 56 through a plurality of bonding media, thermally bonded by a plurality of thermal adhesives and mechanically adhered to the heat sink 66, and packaged in a plurality of packaging materials.

The semiconductor wafer package 300 is a first-level single crystal package.

The semiconductor wafer package and the heat conductive plate described above are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with other embodiments or in combination with other embodiments in consideration of design and reliability. For example, the substrate can comprise a complex array of single layer conductors and a complex array of multilayer conductors. The heat conducting plate may comprise a plurality of studs, and the studs are arranged in an array for use by a plurality of semiconductor components. Further, the heat conducting plate may be configured to accommodate additional semiconductor components and may include more wires. Similarly, the semiconductor component can be an LED package having a plurality of LED chips, and the thermally conductive plate can include more wires to accommodate additional LED chips. The semiconductor element and the cover may overlap the substrate and cover the thermally conductive stud from above.

The semiconductor element can use the heat sink alone or share the heat sink with other semiconductor elements. For example, a single semiconductor component can be disposed on the heat sink or a plurality of semiconductor components can be disposed on the heat sink. For example That is, four small wafers arranged in a 2x2 array can be attached to the thermally conductive studs, and the substrate can include additional wires to match the electrical connections of the wafers. This practice is far more economical than setting a tiny thermally conductive stud on each wafer.

The semiconductor wafer can be optical or non-optical. For example, the wafer can be an LED, a solar cell, a microprocessor, a controller, or a radio frequency (RF) power amplifier. Similarly, the semiconductor package can be an LED package or a radio frequency module. Thus, the semiconductor component can be a packaged or unpackaged optical or non-optical wafer. In addition, the semiconductor element can be mechanically, electrically and thermally bonded to the heat conducting plate by a plurality of connecting media, including by soldering and using an electrically conductive and/or thermally conductive adhesive.

The heat sink can quickly, efficiently and uniformly dissipate the thermal energy generated by the semiconductor component to the next layer assembly without passing heat through the adhesive layer, the substrate or the heat conducting plate elsewhere. In this way, an adhesive layer having a lower thermal conductivity can be used, thereby greatly reducing the cost. The heat sink can include an integrally formed thermally conductive stud and a base, and a cover body that is metallurgically bonded and thermally coupled to the thermally conductive stud, thereby improving reliability and reducing cost. The cover can be coplanar with the pad to form electrical, thermal, and mechanical bonds with the semiconductor component. In addition, the cover may be tailored to the semiconductor component, and the pedestal may be tailored to the next layer of the body to enhance thermal bonding from the semiconductor component to the next layer. For example, the thermally conductive stud may be circular in a lateral plane, the cover may be square or rectangular in a lateral plane, and the side shape of the cover may be opposite to the side shape of the thermal junction of the semiconductor component. Same or similar.

The heat sink can be electrically or electrically isolated from the semiconductor component and the substrate. For example, the second conductive layer on the polished surface may include a routing line extending between the substrate and the cover through the adhesive layer, thereby electrically connecting the semiconductor element to the heat dissipation. seat. Thereafter, the heat sink can be electrically grounded to electrically ground the semiconductor component.

The heat sink can be copper, aluminum, copper/nickel/aluminum alloy or other thermally conductive metal structure.

The thermally conductive stud can be deposited on the base or integrally formed with the base. The thermally conductive stud can be integrally formed with the base and thus become a single metal body (such as copper or aluminum). The thermally conductive stud can also be integrally formed with the base such that the interface between the two comprises a single metal body (for example, copper), and other portions include other metals (for example, the upper portion of the stud is solder, the lower portion of the stud and the base) The seat is made of copper). The thermally conductive stud can also be integrally formed with the base such that the interface between the two comprises a plurality of layers of a single metal body (eg, a nickel buffer layer on an aluminum core peripheral and a copper layer on the nickel buffer layer).

The signal stud can be deposited on the terminal or integrally formed with the terminal. The signal stud can be integrally formed with the terminal and thus becomes a single metal body (such as copper or aluminum). The signal stud can also be integrally formed with the terminal such that the interface between the two comprises a single metal body (for example, copper), and other portions include other metals (for example, the upper portion of the stud is solder, the lower portion of the stud and the terminal For copper). The signal stud can also be integrally formed with the terminal such that the interface between the two comprises a plurality of single metal bodies (for example, a nickel buffer layer is disposed on an aluminum core peripheral, and the nickel A buffer layer is provided on the buffer layer).

The thermally conductive stud may include a flat top surface and the top surface is coplanar with the adhesive layer. For example, the thermally conductive stud may be coplanar with the adhesive layer, or the thermally conductive stud may be etched after the adhesive layer is cured, such that the adhesive layer over the thermally conductive stud forms a recess. The thermally conductive stud can also be selectively etched to form a recess extending into the thermally conductive stud below its top surface. In any of the above cases, the semiconductor component may be disposed on the thermally conductive stud and located in the recess, and the bonding wire may extend from the semiconductor component in the recess to the pad outside the recess . In this case, the semiconductor component can be an LED wafer and the LED light is focused by the recess toward the upward direction.

The pedestal provides mechanical support for the substrate. For example, the susceptor can prevent the substrate from being bent and deformed during metal grinding, wafer placement, wire bonding, and molding of the packaging material. Additionally, the back of the base may include fins that project in the downward direction. For example, a rig can be used to cut the bottom surface of the pedestal to form lateral grooves, and the lateral grooves are fins. In this case, the pedestal may have a thickness of 500 microns, and the depth of the grooves may be 300 microns, that is, the height of the fins may be 300 microns. The fins may increase the surface area of the susceptor, and if the fins are exposed to the air rather than being disposed on a heat sink, the thermal conductivity of the susceptor via thermal convection may be enhanced.

The cover may be formed by various deposition techniques, including electroplating, electroless plating, evaporation, and sputtering, before, during, or after the bonding of the bonding layer, including forming a single layer by electroplating, electroless plating, evaporation, and sputtering. Or multilayer structure. The cover It can be made of the same metal material as the thermal conductive stud or the same metal material as the top of the thermal conductive stud adjacent to the cover. In addition, the cover may span the through hole and extend to the substrate or be located within the periphery of the through hole. Thus, the cover can contact or be spaced from the substrate. In either case, the cover extends laterally from the top of the thermally conductive stud in the lateral direction.

The adhesive layer provides a strong mechanical bond between the heat sink and the substrate. For example, the adhesive layer may extend laterally from the heat conducting stud and pass the wire to the peripheral edge of the group. The adhesive layer may fill the space between the heat sink and the substrate, and the adhesive layer may have A non-porous structure of a uniformly distributed bond line. The adhesive layer can also absorb the mismatch caused by thermal expansion between the heat sink and the substrate. In addition, the adhesive layer can be a low cost dielectric and does not require high thermal conductivity. Furthermore, the adhesive layer is not easily delaminated.

We can adjust the thickness of the adhesive layer so that the adhesive layer substantially fills the gaps and allows almost all of the adhesive to be located within the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error. Similarly, we can also adjust the thickness of the dielectric layer to achieve this effect.

The substrate can be a low cost laminate structure and does not require high thermal conductivity. Additionally, the substrate can comprise a single conductive layer or a plurality of conductive layers. Furthermore, the substrate may comprise or consist of the conductive layer.

The conductive layer can be separately disposed on the adhesive layer. For example, the through holes may be formed on the conductive layer, and then the conductive layer is disposed on the adhesive layer, so that the conductive layer contacts the adhesive layer and is exposed in the upward direction. At the same time, the heat conducting stud and the signal stud extend into the through holes and are exposed through the through holes in the upward direction. In this case, the conductive layer may have a thickness of 100 to 200 micrometers, for example, 125 micrometers. The thickness is thick enough on the one hand, so that it does not bend when transported, and is thin enough on the one hand, so that the pattern can be formed without excessive etching. .

The conductive layer may also be disposed on the adhesive layer together with the dielectric layer. For example, the conductive layer may be disposed on the dielectric layer, and then the via holes are formed on the conductive layer and the dielectric layer, and then the conductive layer and the dielectric layer are disposed on the adhesive layer. Exposing the conductive layer toward the upward direction and contacting the dielectric layer between the conductive layer and the adhesive layer, thereby separating the conductive layer from the adhesive layer, and at the same time, the thermally conductive stud And the signal studs extend into the through holes and are exposed through the through holes in the upward direction. In this case, the conductive layer may have a thickness of 10 to 50 microns, such as 30 microns, which is thick enough on the one hand to provide reliable signal transmission and, on the other hand, thin enough to reduce weight and cost. Furthermore, the dielectric layer is always part of the heat conducting plate.

The conductive layer may also be disposed on the adhesive layer simultaneously with a carrier. For example, the conductive layer may be adhered to a carrier such as a bi-directional polyethylene terephthalate film (Mylar) by using a film, and then the via holes are formed only on the conductive layer instead of the carrier. And then the conductive layer and the carrier are disposed on the adhesive layer, the carrier covers the conductive layer, and is exposed in the upward direction, and the film is contacted and interposed between the carrier and the conductive layer, as for the conductive The layer is in contact with and between the film and the adhesive layer, and at the same time, the heat conducting stud and the signal stud are aligned with the through holes, and the load is The body is covered from above. After the adhesive layer is cured, the film may be decomposed by ultraviolet light to strip the carrier from the conductive layer, thereby exposing the conductive layer toward the upward direction, and then the conductive layer may be ground and patterned to form the conductive layer. wire. In this case, the conductive layer may have a thickness of 10 to 50 micrometers, for example 30 micrometers, which is thick enough on the one hand to provide reliable signal transmission, and on the other hand thin enough to reduce weight and cost; The thickness can be 300 to 500 micrometers, and the thickness is thick enough on the one hand, so that it does not bend and shake when transported, and is thin enough on the one hand to help reduce weight and cost. The carrier is only a temporary fixture and is not permanently part of the heat conducting plate.

The pad and the terminal can be in various package forms depending on the needs of the semiconductor component and the next layer assembly.

The top surface of the solder pad and the top surface of the cover may be coplanar, so that the soldering between the semiconductor component and the heat conducting plate can be strengthened by controlling the degree of collapse of the solder ball.

The pad and the routing line on the dielectric layer can be fabricated by various deposition techniques, including electroplating, electroless plating, evaporation, and sputtering, when the substrate is not yet or already disposed on the adhesive layer. A single layer or a multilayer structure is formed. For example, the conductive layer may be formed on the substrate when the substrate is not disposed on the adhesive layer, or after the substrate has been adhered to the heat conductive stud and the signal stud and the base by the adhesive layer. The pattern of the layers.

The step of surface treatment with the covered contacts may be performed before or after the formation of the pads and the terminals. For example, the coating layer may be deposited on the pedestal and the second conductive layer, and then the patterned etch stop layer is used to define the The pad is etched with the terminal to have a pattern of the cover layer.

The wire may include additional pads, terminals, conductive vias, signal posts, routing wires, and passive components, and may be of different configurations. The wire can be used as a signal layer, a power layer or a ground layer depending on the purpose of the corresponding semiconductor component pads. The wire may also comprise various conductive metals such as copper, gold, nickel, silver, palladium, tin, mixtures thereof, and alloys thereof. The ideal composition depends both on the nature of the externally connected medium and on the design and reliability considerations. In addition, those skilled in the art will appreciate that the copper used in the semiconductor wafer package may be pure copper, but is typically a copper-based alloy such as copper-zirconium (99.9% copper), copper-silver- Phosphorus-magnesium (99.7% copper) and copper-tin-iron-phosphorus (99.7% copper) to improve mechanical properties such as tensile strength and ductility.

In general, it is preferable to provide the cover, the dielectric layer, the solder resist green lacquer, the coated contact and the second conductive layer on the surface after the grinding, but in some embodiments, it may be omitted. For example, if the opening and the through hole are formed by punching instead of drilling, so that the shape and size of the top of the heat conducting stud are matched with the thermal contact surface of the semiconductor element, the cover and the cover may be omitted. The second conductive layer reduces cost. As such, the dielectric layer can be omitted to reduce cost.

The heat conducting plate may include a heat conducting hole, the heat conducting hole is spaced apart from the heat conducting stud and the signal stud, and extends through the dielectric layer and the adhesive layer outside the openings and the through holes. The base and the cover are adjacently and thermally coupled, thereby enhancing the heat dissipation effect from the cover to the base and promoting thermal energy diffusion in the base.

The group of this case can provide single or multi-layer signal routing horizontally or vertically. .

U.S. Patent Application Serial No. 12/616,773, filed on Jan. The structure of the pad, the terminal and the routing line are all located above the dielectric layer, the contents of which are incorporated herein by reference.

U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, the disclosure of which is incorporated herein in The structure of the routing in which the pads, terminals and routing wires are located above the adhesive layer, and the structure is not provided with a dielectric layer, the contents of which are incorporated herein by reference.

U.S. Patent Application Serial No. 12/557,540, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire content a routing structure in which pads and terminals above the dielectric layer are electrically connected by using first and second conductive vias through the dielectric layer and routing lines under the dielectric layer. US Patent Application The content is hereby incorporated by reference.

U.S. Patent Application Serial No. 12/557,541, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire content The structure of the signal routing, wherein the pads above the dielectric layer and the terminals under the adhesive layer utilize a first conductive via that passes through the dielectric layer, below the dielectric layer The routing line and the second conductive via through the adhesive layer are electrically connected. The contents of this U.S. Patent Application is incorporated herein by reference.

The heat shield can be operated in a single or multiple heat shield depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a plurality of thermally conductive plates can be fabricated in batches using a single metal sheet, a single adhesive layer, a single substrate, a single top solder mask green paint, and a single bottom solder resist green paint, and then separated. Similarly, for each thermal plate in the same batch, we can also use a single metal plate, a single adhesive layer, a single substrate, a single top anti-weld green paint and a single bottom anti-weld green paint to simultaneously manufacture multiple groups for a single batch. The heat sink and the wire used in the semiconductor component.

For example, a plurality of grooves may be etched on a metal plate to form the pedestal, the plurality of thermally conductive studs and the plurality of signal studs; and then an opening having a corresponding thermally conductive stud and the signal studs An uncured adhesive layer is disposed on the pedestal such that each of the thermal conductive posts and the signal studs extend through a corresponding opening; and then a substrate (having a single conductive layer, a single dielectric layer, and corresponding heat conduction) The through holes of the studs and the signal studs are disposed on the adhesive layer, so that each of the studs extends through a corresponding opening and enters a corresponding through hole; and then the base and the substrate are mutually connected by the pressing table Relying the adhesive layer into the through holes, the gap between the heat conducting studs and the signal studs and the substrate; then curing the adhesive layer, and then grinding the thermally conductive studs, the signals a pillar, the adhesive layer and the first conductive layer to form a top surface; and then a second conductive layer is disposed on the heat conducting studs, the signal bumps, the adhesive layer and the first conductive layer; Then etching the first and second conductive layers to form Group respectively correspond to the signal pads and the like of the boss and Routing a second conductive layer to form a plurality of caps respectively corresponding to the thermally conductive studs, and etching the pedestal to form a plurality of pedestals corresponding to the thermally conductive studs and a plurality of corresponding signal bumps a terminal of the column; and then the top solder resist green paint is disposed on the structure, and the top solder resist green paint is patterned to expose the solder pads and the cover body, and the bottom solder resist green paint is disposed on the bottom Structurally, the bottom solder resist green lacquer is patterned to expose the pedestals and the terminals; and then the pedestals, the pads, the terminals, and the covers are covered by the covered contacts Surface treatment; finally cutting or cleaving the substrate, the adhesive layer and the solder resist green paint at appropriate positions on the peripheral edge of the heat conducting plates to separate the individual heat conducting plates from each other.

The operational format of the semiconductor wafer package can be a single group or a plurality of groups, depending on the manufacturing design. For example, a single set can be manufactured separately. Alternatively, a plurality of groups can be manufactured in batches at the same time, and then the heat conducting plates are separated one by one. Similarly, a plurality of semiconductor elements may be electrically connected, thermally coupled, and mechanically coupled to each of the heat conducting plates in mass production.

For example, a plurality of solder paste portions may be separately deposited on the plurality of pads and the cover, and then the plurality of LED packages are respectively placed on the solder paste portions, and then the solder paste portions are simultaneously heated to be returned. Welding, hardening and forming a plurality of solder joints, and then separating the heat conducting plates one by one.

In another example, a plurality of solid crystal materials are separately deposited on a plurality of covers, and then a plurality of wafers are respectively placed on the solid crystal materials, and then the solid crystal materials are simultaneously heated to harden them. A plurality of solid crystals are formed, and then the wafers are wire bonded to the corresponding pads, and then corresponding packaging materials are formed on the wafers and the wires, and finally the heat conducting plates are separated one by one.

We can separate the heat conducting plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements are disposed on the flat plate, and then the plurality of semiconductor wafer assemblies formed by the flat plates are separated one by one. Alternatively, a plurality of heat conducting plates can be batched into a flat plate, and then the plurality of heat conducting plates formed by the flat plate are slit into a plurality of heat conducting strips, and then a plurality of semiconductor elements are respectively disposed on the heat conducting strips. Finally, the plurality of semiconductor wafer assemblies formed by the heat conducting strips are separated into individual parts. In addition, mechanical cutting, laser cutting, bifurcation or other suitable techniques may be utilized in splitting the thermally conductive plates.

As used herein, the term "adjacent" means that the elements are integrally formed (forming a single individual) or in contact with one another (with or without separation from one another). For example, the thermally conductive stud is adjacent to the pedestal, which is independent of the addition or reduction method when forming the thermally conductive stud.

The term "overlapping" means located above and extending within the perimeter of a lower element. "Overlap" includes extending within, outside of, or within the circumference of the circumference. For example, the semiconductor component is overlapped with the thermally conductive stud because an imaginary vertical line can simultaneously penetrate the semiconductor component and the thermally conductive stud, regardless of whether there is another imaginary vertical between the semiconductor component and the thermally conductive stud. The element through which the wire runs, such as the cover, and whether or not another imaginary vertical line extends only through the semiconductor component does not extend through the thermally conductive stud (ie, outside the periphery of the thermally conductive stud). Similarly, the adhesive layer is overlaid on the pedestal and overlapped by the pads, and the pedestal is overlapped by the thermally conductive studs. Likewise, the thermally conductive stud is superposed on the base and is located within its circumference. In addition, "overlap" is synonymous with "below" and "overlap" is synonymous with "below".

The term "contact" means direct contact. For example, the dielectric layer contacts the pad but does not contact the thermally conductive stud or the pedestal.

The term "covering" means completely covering from above, from below and/or from the side. For example, the pedestal covers the thermally conductive stud from below, but the thermally conductive stud does not cover the pedestal from above.

The "layer" word contains a layer with or without a pattern. For example, when the substrate is disposed on the adhesive layer, the conductive layer may be a blank unpatterned flat plate on the dielectric layer; and after the semiconductor component is disposed on the heat sink, the conductive layer may be the dielectric layer A circuit pattern having spaced wires on the electrical layer. In addition, a "layer" may comprise a plurality of superposed layers.

The term "pad" as used in connection with the conductor means a connection area for connecting and/or engaging an external connection medium (such as solder or wire), and the external connection medium electrically connects the wire to the Semiconductor component.

The term "terminal" as used in connection with the conductor means a connection area which is capable of contacting and/or engaging an external connection medium (such as solder or wire) which electrically connects the wire to the lower One layer of an external device (such as a printed circuit board or a wire connected to it).

The term "cover" when used in conjunction with the heat sink refers to a contact area for connecting and/or bonding an external connection medium (such as solder or a thermally conductive adhesive), and the external connection medium can heat the heat sink. Connected to the semiconductor component.

The words "opening" and "through hole" refer to the through hole. For example, when the thermally conductive stud is inserted into the opening of the adhesive layer, the thermally conductive stud is exposed to the adhesive layer in an upward direction. Similarly, when the thermally conductive stud is inserted into the substrate In the through hole, the thermally conductive stud is exposed to the substrate in an upward direction.

The term "insertion" means the relative movement between components. For example, "inserting the thermal conductive stud into the through hole" includes: the thermally conductive stud is fixed and moved by the substrate toward the base; the substrate is fixed and moved by the thermally conductive stud to the substrate; and the thermal conduction Both the stud and the substrate abut each other. For another example, “inserting (or extending into) the through-hole of the heat-conducting stud includes: the heat-conducting stud penetrating (passing in and penetrating) the through-hole; and the thermally-conductive stud is inserted but not penetrated (penetrated) But did not wear out the through hole.

The phrase "together with each other" also refers to the relative movement between components. For example, "the pedestal and the substrate abut each other" includes: the pedestal is fixed and moved from the substrate to the pedestal; the substrate is fixed and moved by the pedestal to the substrate; and the pedestal and the pedestal The substrates are close to each other.

The term "aligned" means the relative position between components. For example, when the adhesive layer is disposed on the pedestal, the substrate is disposed on the adhesive layer, the thermal conductive stud has been inserted and aligned with the opening, and the through hole has been aligned with the opening, regardless of the thermal conduction. The stud is inserted into or located below the through hole, and the thermally conductive stud is aligned with the through hole.

The term "set in" encompasses contact and non-contact with a single or multiple support elements. For example, the semiconductor component is disposed on the heat sink, whether the semiconductor component is actually in contact with the heat sink or is separated from the heat sink by a solid crystal material. Similarly, the semiconductor component is disposed on the heat sink, and the semiconductor component is disposed only on the heat sink or on the heat sink and the substrate.

The phrase "adhesive layer...in the gap" means located in the gap The adhesive layer. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer within the gap extends across the dielectric layer. Similarly, "the adhesive layer contacts the gap and is between the thermal conductive stud and the dielectric layer" means that the adhesive layer in the notch contacts and the thermally conductive stud between the inner sidewall of the notch Between the dielectric layers of the outer sidewall of the gap.

The term "upper" is intended to mean an upward extension and encompasses contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, the thermally conductive stud extends above the pedestal while abutting, overlapping the pedestal and projecting from the pedestal. Similarly, the thermally conductive stud extends above the dielectric layer even if the thermally conductive stud does not abut or overlap the dielectric layer.

The word "below" is intended to mean a downward extension and includes contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, the pedestal extends below the thermally conductive stud, adjacent to the thermally conductive stud, and is overlapped by the thermally conductive stud and protrudes from the thermally conductive stud. Similarly, the thermally conductive stud extends below the dielectric layer even if the thermally conductive stud is not adjacent to or overlapped by the dielectric layer.

The vertical direction of "upward" and "downward" does not depend on the orientation of the semiconductor wafer package (or the thermal plate), and those skilled in the art can easily understand the actual direction. For example, the thermally conductive stud extends vertically above the pedestal in an upward direction, and the adhesive layer extends vertically below the solder pad in a downward direction, whether the set is inverted and/or is disposed at a It has nothing to do with the heat sink. Similarly, the pedestal extends laterally from the thermally conductive stud along a lateral plane, regardless of whether the set is inverted, rotated or tilted. Therefore, the upward and downward directions are related to each other. Paired and perpendicular to the side direction, in addition, the laterally aligned elements are coplanar with one another in a lateral plane perpendicular to the upward and downward directions.

The semiconductor wafer package of the present invention has a number of advantages. The group's reliability is high, the price is flat and it is very suitable for mass production. The group is particularly suitable for high-power semiconductor components that are prone to high heat and require excellent heat dissipation to operate efficiently and reliably, such as LED packages, large semiconductor wafers, and multiple small semiconductor components used simultaneously (eg, arrayed) Multiple small semiconductor wafers).

The manufacturing process of this case is highly applicable, and combines various mature electrical connections, thermal connections and mechanical joining technologies in a unique and progressive manner. In addition, the manufacturing process of this case can be implemented without expensive tools. As a result, this manufacturing process can significantly increase the yield, yield, performance and cost effectiveness of traditional packaging technologies. Furthermore, the group in this case is extremely suitable for copper wafers and lead-free environmental requirements.

The embodiments described herein are illustrative, and the elements or steps of the present invention are either simplified or omitted to avoid obscuring the features of the present invention. Similarly, in the drawings, the repeated or non-essential elements and reference numerals may be omitted.

Those skilled in the art can readily appreciate various changes and modifications to the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, steps, and order of steps are merely examples. The above-mentioned persons can make such changes, adjustments and equals without departing from the spirit and scope of the invention, and the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Metal plates

12, 14‧‧‧ surface

16, 52, 54‧‧‧ patterned etch stop

18‧‧‧Full coverage of the etch stop

20‧‧‧ Groove

22‧‧‧thermal pillar

24‧‧‧ Signal Stud

26‧‧‧Base

28‧‧‧Adhesive layer

30, 32‧‧‧ openings

34‧‧‧Substrate

36, 50‧‧‧ conductive layer

38‧‧‧Dielectric layer

40, 42‧‧‧through holes

44, 46‧‧ ‧ gap

56‧‧‧ solder pads

58‧‧‧Route line

60‧‧‧ cover

62‧‧‧ terminals

64‧‧‧Wire

66‧‧‧ Heat sink

68, 70‧‧‧Protective green paint

72‧‧‧covered contacts

74, 76‧‧‧ Thermal Conductive Plate

100, 200, 300‧‧‧ semiconductor wafer assembly

102, 202‧‧‧ LED package

104, 106, 204, 206‧‧‧ solder

108, 208‧‧‧ LED chips

110, 210‧‧‧ Pedestal

112, 212, 304‧‧‧

114‧‧‧Electrical contacts

116‧‧‧Hot junction

118, 218‧‧‧ Transparent packaging materials

214‧‧‧ pin

216‧‧‧ Thermal contact surface

302‧‧‧ wafer

306‧‧‧Solid crystal materials

308‧‧‧Packaging materials

310‧‧‧ top surface

312‧‧‧ bottom

314‧‧‧Wire mat

1A to 1D are cross-sectional views illustrating a method for fabricating a stud and a pedestal in accordance with an embodiment of the present invention; FIGS. 1E and 1F are a plan view and a bottom view, respectively, of FIG. 1D; FIGS. 2A and 2B are cross-sectional views. FIG. 2C and FIG. 2D are respectively a plan view and a bottom view of FIG. 2B; FIG. 3A and FIG. 3B are cross-sectional views illustrating an embodiment of the present invention for making an adhesive layer; FIG. FIG. 3C and FIG. 3D are respectively a top view and a bottom view of FIG. 3B; FIG. 4A to FIG. 4L are cross-sectional views illustrating a method for fabricating a heat conducting plate according to an embodiment of the present invention, wherein the heat conducting plate is adhered thereto 4M and FIG. 4N are respectively a top view and a bottom view of FIG. 4L; FIGS. 5A, 5B and 5C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conduction The board is provided with a wire on the adhesive layer. FIG. 6A, FIG. 6B and FIG. 6C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer assembly according to an embodiment of the present invention. The semiconductor chip assembly includes a heat conducting plate and a LED package having a back contact; 7A, 7B, and 7C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package including a heat conducting plate and an LED package having side pins; 8A, FIG. 8B and FIG. 8C are respectively half guides according to an embodiment of the present invention. A cross-sectional view, a top view, and a bottom view of the bulk wafer assembly, the semiconductor wafer package including a thermally conductive plate and a semiconductor wafer.

twenty two. . . Thermal conductive stud

twenty four. . . Signal stud

26. . . Pedestal

28. . . Adhesive layer

34. . . Substrate

38. . . Dielectric layer

56. . . Solder pad

58. . . Routing line

60. . . Cover

62. . . Terminal

64. . . wire

66. . . Heat sink

68, 70. . . Anti-weld green paint

74. . . Thermal plate

100. . . Semiconductor wafer package

102. . . LED package

104, 106. . . Solder

108. . . LED chip

110. . . Pedestal

112. . . Line

114. . . Electric contact

116. . . Hot junction

118. . . Transparent packaging material

Claims (50)

A semiconductor wafer assembly comprising: at least: a semiconductor component; an adhesive layer having at least first and second openings; a heat sink comprising at least one thermally conductive stud and a pedestal, wherein the thermally conductive stud is adjacent The pedestal extends above the pedestal in an upward direction, the pedestal extending below the thermally conductive stud in a downward direction opposite the upward direction and along a side perpendicular to the upward and downward directions a direction extending laterally from the heat conducting stud; and a wire comprising at least one pad, a terminal and a signal stud, wherein the signal stud extends below the pad and above the terminal, and the pad The conductive path between the terminal and the terminal includes the signal stud; wherein the semiconductor component is located above the thermally conductive stud and overlaps the thermally conductive stud, and the semiconductor component is electrically connected to the pad to be electrically connected to the a terminal, and the semiconductor component is thermally coupled to the thermally conductive stud to be thermally coupled to the pedestal; wherein the adhesive layer is disposed on the pedestal, extending over the pedestal, and from the thermally conductive stud side Extending to or over the terminal; wherein the pad extends over the adhesive layer, and the terminal extends below the adhesive layer; and wherein the thermally conductive stud extends into the first opening, the signal post extends Entering the second opening, the thermally conductive stud and the signal stud have the same thickness and are coplanar with each other, the pedestal having the same thickness as the terminal and being coplanar with each other. The semiconductor wafer package of claim 1, wherein the semiconductor component is an LED package comprising an LED chip. The semiconductor wafer package of claim 2, wherein the LED package system is electrically connected to the pad by a first solder and thermally coupled to the heat sink by a second solder. The semiconductor wafer package of claim 1, wherein the semiconductor component is a semiconductor wafer. The semiconductor wafer package of claim 4, wherein the wafer is electrically connected to the pad by a wire and thermally bonded to the heat sink by a die bonding material. The semiconductor wafer package of claim 1, wherein the adhesive layer contacts the thermally conductive stud and the signal stud, the base, the pad and the terminal. The semiconductor wafer package of claim 1, wherein the adhesive layer covers and surrounds the thermally conductive stud and the signal stud in the lateral direction. The semiconductor wafer assembly of claim 1, wherein the adhesive layer is isomorphously coated on the sidewalls of the thermally conductive stud and the signal stud. The semiconductor wafer package of claim 1, wherein the adhesive layer is coplanar with the heat conducting stud and the top and bottom of the signal stud. The semiconductor wafer package of claim 1, wherein the adhesive layer extends laterally from the thermally conductive stud and passes over the terminal. The semiconductor wafer package according to claim 1, wherein the The adhesive layer extends to the peripheral edge of the semiconductor wafer package. The semiconductor wafer package of claim 1, wherein the thermally conductive stud is integrally formed with the base, and the signal stud is integrally formed with the terminal. The semiconductor wafer assembly of claim 1, wherein the thermally conductive stud is a flat-topped tapered column having a diameter that decreases upward from the base to a flat top of the thermally conductive stud, and the signal The stud is a flat-topped conical cylinder whose diameter decreases upward from the terminal to a flat top of one of the signal studs. The semiconductor wafer package of claim 1, wherein the pedestal covers the thermally conductive stud from below to support the adhesive layer and maintain a distance from a peripheral edge of the semiconductor wafer assembly. The semiconductor wafer package of claim 1, wherein the wire is spaced from the heat sink and the pad, and the terminal and the signal stud contact the adhesive layer. The semiconductor wafer package of claim 1, wherein the terminal is adjacent to the signal stud, extends below the signal stud, and extends laterally from the signal stud along the lateral directions. The semiconductor wafer assembly of claim 1, wherein the heat sink comprises at least a cover, the cover is located above a top of one of the thermally conductive studs, adjacent to the top of the thermally conductive stud, and from above Covering the top of the thermally conductive stud while extending laterally from the top of the thermally conductive stud in the lateral direction. The semiconductor wafer package of claim 17, wherein the semiconductor wafer assembly The cover and the pad are coplanar above the adhesive layer. The semiconductor wafer package of claim 17, wherein the cover is rectangular or square, and the top of the thermally conductive stud is circular. The semiconductor wafer package of claim 17, wherein the size and shape of the cover are designed to match a thermal contact surface of the semiconductor component, and the size and shape of the top of the thermal conductive post are not matched. The thermal contact surface of the semiconductor component is designed. A semiconductor wafer assembly comprising: at least: a semiconductor component; an adhesive layer having at least first and second openings; a heat sink comprising at least one thermally conductive stud and a pedestal, wherein the thermally conductive stud is adjacent The pedestal is integrally formed with the pedestal, and the thermally conductive stud extends above the pedestal in an upward direction, the pedestal extending below the thermally conductive stud in a downward direction opposite the upward direction And extending laterally from the thermally conductive stud in a direction perpendicular to the upward and downward directions; and a wire comprising at least a pad, a terminal, a routing line and a signal stud, wherein the routing line Adjacent to the solder pad, the signal stud is adjacent to the routing line and the terminal, and extends below the solder pad and the routing line, and extends above the terminal, and a conductive path between the pad and the terminal includes The routing line and the signal stud; wherein the semiconductor component is disposed on the heat sink, overlaps the heat conducting stud but does not overlap the signal stud, and the semiconductor component is electrically connected to the pad Electricity Coupled to the terminals, and the semiconductor The component is thermally coupled to the thermally conductive stud to be thermally coupled to the pedestal; wherein the adhesive layer is disposed on the pedestal, extends over the pedestal, and covers and surrounds the thermally conductive stud in the lateral directions And the signal stud extending to the peripheral edge of the semiconductor wafer assembly; wherein the bonding pad extends over the adhesive layer; and wherein the thermal conductive post extends into the first opening, the signal stud extending into the first a second opening, the thermally conductive stud and the signal stud have the same thickness, are coplanar with each other, and extend through the adhesive layer, the pedestal and the terminal have the same thickness, are coplanar with each other, and extend below the adhesive layer The thermally conductive stud and the top and bottom of the signal stud are coplanar with the adhesive layer. The semiconductor wafer assembly of claim 21, wherein the semiconductor component is a semiconductor wafer, and is disposed on the heat sink by a die bonding material, and is electrically connected to the pad by using a wire. At the same time, the solid crystal material is thermally bonded to the heat sink. The semiconductor wafer package of claim 21, wherein the adhesive layer contacts the thermally conductive stud, the signal stud, the pedestal, the pad, the terminal and the routing line. The semiconductor wafer assembly of claim 21, wherein the thermally conductive stud is a flat-topped tapered cylinder having a diameter that decreases upward from the pedestal to a flat top of the thermally conductive stud, the thermally conductive convex The top of the column is circular, and a cover system is disposed on the top of the thermally conductive stud, above the top of the thermally conductive stud, adjacent to the top of the thermally conductive stud, and covering the thermally conductive stud from above The top, at the same time along the sides The top of the thermally conductive stud extends laterally and the cover is rectangular or square. The semiconductor wafer package of claim 24, wherein the cover and the bonding pad are coplanar above the adhesive layer. A semiconductor wafer assembly comprising: at least: a semiconductor component; an adhesive layer having at least first and second openings; a heat sink comprising at least one thermally conductive stud and a pedestal, wherein the thermally conductive stud is adjacent The pedestal extends above the pedestal in an upward direction, the pedestal extending below the thermally conductive stud in a downward direction opposite the upward direction and perpendicular to the upward and downward directions a side surface extending laterally from the heat conducting stud; a substrate comprising at least one pad and a dielectric layer, wherein the first and second through holes extend through the substrate; and a wire including at least the pad a terminal and a signal stud, wherein the signal stud extends below the solder pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud; wherein the semiconductor component is located The semiconductor element is electrically connected to the solder pad to be electrically connected to the terminal, and the semiconductor component is thermally coupled to the heat conducting stud to be thermally coupled to the heat conducting stud. a pedestal; the adhesive layer is disposed on the pedestal and extends over the pedestal and extends into the first through hole, and a first gap between the thermally conductive stud and the substrate extends into the second Inside the through hole a second gap between the pillar and the substrate, and extending across the dielectric layer in the gap, the adhesive layer extending laterally from the heat conducting stud to the terminal or over the terminal, and the adhesive layer is interposed Between the thermal conductive stud and the dielectric layer, between the signal stud and the dielectric layer, and between the pedestal and the dielectric layer; wherein the substrate is disposed on the adhesive layer and extends over the base Above the seat; wherein the soldering pad extends above the dielectric layer, and the terminal extends below the adhesive layer; and wherein the thermally conductive stud extends into the first opening and the first through hole, the signal stud Extending into the second opening and the second through hole, the heat conducting stud and the signal stud have the same thickness and are coplanar with each other, the pedestal and the terminal having the same thickness and being coplanar with each other. The semiconductor wafer package of claim 26, wherein the semiconductor component is an LED package comprising an LED chip. The semiconductor wafer package of claim 27, wherein the LED package system is electrically connected to the pad by a first solder and thermally coupled to the heat sink by a second solder. The semiconductor wafer package of claim 26, wherein the semiconductor component is a semiconductor wafer. The semiconductor wafer package of claim 29, wherein the wafer is electrically connected to the pad by a wire and thermally bonded to the heat sink by a die bonding material. The semiconductor wafer package of claim 26, wherein the Adhesively contacting the thermal conductive stud and the dielectric layer in the first notch, and contacting the signal stud and the dielectric layer in the second notch, and contacting the pedestal and the terminal outside the notch With the dielectric layer. The semiconductor wafer package of claim 26, wherein the adhesive layer covers and surrounds the thermally conductive stud and the signal stud in the lateral direction. The semiconductor wafer package of claim 26, wherein the adhesive layer is isomorphously coated on the sidewalls of the thermally conductive stud and the signal stud. The semiconductor wafer package of claim 26, wherein the adhesive layer is coplanar with the heat conducting stud and the top and bottom of the signal stud. The semiconductor wafer package of claim 26, wherein the adhesive layer extends laterally from the thermally conductive stud and passes over the terminal. The semiconductor wafer package of claim 26, wherein the adhesive layer extends to a peripheral edge of the semiconductor wafer assembly. The semiconductor wafer package of claim 26, wherein the thermally conductive stud is integrally formed with the base, and the signal stud is integrally formed with the terminal. The semiconductor wafer package of claim 26, wherein the thermally conductive stud is a flat-topped tapered cylinder having a diameter that decreases upward from the pedestal to a flat top of the thermally conductive stud, and the signal The stud is a flat-topped conical cylinder whose diameter decreases upward from the terminal to a flat top of one of the signal studs. The semiconductor wafer package of claim 26, wherein the The pedestal covers the thermally conductive stud from below to support the substrate and maintain a distance from a peripheral edge of the semiconductor wafer package. The semiconductor wafer package of claim 26, wherein the wire is kept at a distance from the heat sink, the pad contacts the dielectric layer, the terminal contacts the adhesive layer, and the signal post contacts the adhesive a layer and the dielectric layer. The semiconductor wafer package of claim 26, wherein the terminal is adjacent to the signal stud, extends below the signal stud, and extends laterally from the signal stud in the lateral directions. The semiconductor wafer package of claim 26, wherein the heat sink comprises at least a cover, the cover is located above a top of one of the thermally conductive studs, adjacent to the top of the thermally conductive stud, and from above Covering the top of the thermally conductive stud while extending laterally from the top of the thermally conductive stud in the lateral direction. The semiconductor wafer package of claim 42, wherein the cover and the pad are coplanar above the dielectric layer. The semiconductor wafer package of claim 42, wherein the cover is rectangular or square, and the top of the thermally conductive stud is circular. The semiconductor wafer package of claim 42, wherein the size and shape of the cover are designed to match a thermal contact surface of the semiconductor component, and the size and shape of the top of the thermal conductive post are not matched. The thermal contact surface of the semiconductor component is designed. A semiconductor wafer assembly comprising at least: a semiconductor component; An adhesive layer having at least first and second openings, a heat sink comprising at least one heat conducting stud, a base and a cover, wherein the heat conducting stud is adjacent to the base and integral with the base Forming, the heat conducting stud extending above the pedestal in an upward direction and providing thermal connection between the pedestal and the cover, the pedestal extending in the downward direction opposite to the upward direction Behind the studs and extending laterally from the thermally conductive studs in a direction perpendicular to the upward and downward directions, the cover is located above the top of one of the thermally conductive studs, adjoins the top of the thermally conductive studs, and Covering the top of the thermally conductive stud with the top portion extending laterally from the top of the thermally conductive stud; the substrate comprising at least one pad, a routing line and a dielectric layer, wherein the first And the second through hole extends through the substrate; and a wire comprising at least the pad, the routing line, a terminal and a signal stud, wherein the routing line is adjacent to the pad, and the signal stud is adjacent to the route a wire with the terminal and extending over the weld And the routing line is extended over the terminal, and a conductive path between the pad and the terminal includes the routing line and the signal stud; wherein the semiconductor component is disposed on the cover and overlaps the The heat conducting stud is not overlapped with the signal stud, the semiconductor component is electrically connected to the pad, electrically connected to the terminal, and the semiconductor component is thermally coupled to the cover, thereby thermally bonding to the a pedestal; the adhesive layer is disposed on the pedestal and extends over the pedestal and extends into the first through hole, and a first gap between the thermally conductive stud and the substrate extends into the second Inside the through hole a second gap between the pillar and the substrate, and extending across the dielectric layer in the gap, the adhesive layer is between the heat conducting stud and the dielectric layer, the signal stud and the dielectric layer Between and between the pedestal and the dielectric layer, the adhesive layer covers and surrounds the thermally conductive stud and the signal stud in the lateral direction and extends to a peripheral edge of the semiconductor wafer assembly; wherein the bonding a pad extending over the dielectric layer; and wherein the heat conducting stud extends into the first opening and the first through hole, the signal stud extending into the second opening and the second through hole, the thermally conductive stud and The signal studs have the same thickness, are coplanar with each other, and extend through the adhesive layer and the dielectric layer, the pedestal and the terminal have the same thickness, are coplanar with each other, and extend to the adhesive layer and the dielectric layer Below, the thermally conductive stud and the top and bottom of the signal stud are coplanar with the adhesive layer. The semiconductor wafer assembly of claim 46, wherein the semiconductor component is a semiconductor wafer, and is disposed on the cover by a die bonding material, and is electrically connected to the pad by a wire. At the same time, the solid crystal material is used to thermally bond to the cover. The semiconductor wafer package of claim 46, wherein the adhesive layer contacts the thermally conductive stud, the signal stud and the dielectric layer in the notches, and contacts the pedestal outside the notches. The terminal and the dielectric layer, the dielectric layer contacts the bonding pad and the routing line, and is spaced apart from the thermally conductive stud, the signal stud, and the base and the terminal. The semiconductor wafer assembly of claim 46, wherein the thermally conductive stud is a flat-topped tapered cylinder having a diameter from the pedestal to the cover system Decreasing upward, the signal stud is a flat-topped tapered cylinder whose diameter decreases upward from the terminal to the routing line, the top of the thermally conductive stud is circular, and the cover is rectangular or square. The semiconductor wafer package of claim 46, wherein the cover and the pad are coplanar above the dielectric layer.