TW201036212A - Semiconductor chip set - Google Patents

Abstract

A semiconductor chip set is disclosed, which comprises at least a semiconductor device, a heat-dissipation base, a substrate, and an adhesion layer. The semiconductor layer is electrically connected to the substrate, and thermally connected to the heat-dissipation base. The heat-dissipation base at least comprises a protrusion pillar and a base, where the protrusion pillar extends upward to pass through one opening of the adhesion layer and enters into a via hole of the substrate. The base extends from a side of the protrusion pillar. The adhesion layer stretches between the protrusion pillar and the substrate, and between the base and the substrate. The substrate at least comprises a first and a second electrically conductive layers and a dielectric layer between them. Also, the substrate provides a horizontal signal router between a bonding pad and a terminal on the first electrically conductive layer.

Description

201036212 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor crystal plate, and more particularly to a high power semiconductor device, particularly a semiconductor composed of a semiconductor device, a substrate, an adhesive layer, and a heat sink. Wafer assembly and method of manufacturing the same. [Prior Art] This application is part of the continuation of US Patent Application No. 12/4G6, 51G, which was filed on March 18, 2009, and the US Patent Secretary (10) stated that it was proposed on May 7, 2 years. US Provisional Patent Application No. 61/〇71,589, Application No. 61/071,588, filed on May 7, 2, and April 11, 2008 Case No. (4) Yang and No. ^^, and the priority of the US Provisional Patent Towels No. 61/G64/748, which is filed in the request, & this application# claims that the full text of the above cases is read in a cross-reference Into this article. The priority of the U.S. Provisional Patent Application Serial No. 61/150,98, filed on Feb. ^Semiconductor components such as packaged and unpackaged semiconductor wafers can be used for voltage, high-freshness, and high-efficiency; these fines are required to perform specific functions, so the power required is very high, but the higher the power, the higher the semiconductor components. The more the track is. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is also reduced. 'The heat generation is exacerbated. 半导体 ★ Semiconductor components are prone to performance degradation and shortened service life under high temperature operation, and may even cause immediate failure. High heat not only affects wafer performance, but also 201036212 can cause thermal stress on the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be quickly and efficiently dissipated to ensure the efficiency and reliability of its operation. A high thermal conductivity path typically conducts and dissipates thermal energy to a larger area than the die pad where the wafer or wafer is located. Light Emitting Diodes (LEDs) have recently become popular alternatives to incandescent, fluorescent, and lenticular sources. LEDs provide long-term, energy-efficient and low-cost solutions for medical, military, signage, signal, aerospace, marine, vehicle, portable, commercial, and residential lighting applications. For example, LEDs can provide light sources for lamps, flashlights, headlights, searchlights, traffic lights, and displays. The high-power chips in the beta LEDs provide high levels of thermal energy while providing high brightness output. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened service life, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. As a result, LEDs highlight the need for high-power chips with good thermal dissipation. The LED package typically includes a led wafer, a pedestal, an electrical contact, and a thermal contact. The pedestal is thermally coupled to the LED chip and used to support the LED chip; the electrical contact is electrically connected to the anode and the cathode of the LED chip, and the thermal contact is thermally coupled to the LED via the pedestal The wafer, the carrier underneath, can dissipate heat sufficiently to prevent overheating of the LED chip. The industry is actively investing in the development of high-power chip packages and heat-conducting panels with various design and manufacturing technologies, in order to meet the performance requirements in this extreme county environmental towel. The Plastic Ball Grid Array (pBGA) package encloses a wafer and a laminated substrate in a plastic case, and then adheres the 201036212 to a Printed Circuit Board (PCB) with solder balls. The laminated substrate comprises a dielectric layer usually composed of glass fibers, and the thermal energy generated by the wafer can be transmitted to the solder balls through the plastic and dielectric layers, and then transferred to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the PBGA has a poor heat dissipation effect. A quad flat no-lead (QFN) package places the wafer on a copper die pad soldered to a printed circuit board. The heat generated by the wafer can be transferred to the printed circuit board via the die pad. However, due to the limited routing capability of its pin-frame interposer, QFN packages are not suitable for high input/output (I/O) chips or passive components. The thermal pad provides electrical routing, thermal management, and mechanical support for the semiconductor components. The heat conducting board usually comprises a substrate for signal routing, a heat sink or heat sink for providing heat removal function, a power supply connection to the semiconductor component, a solder pad, and a terminal connectable to the next layer of the power supply. The substrate may be a laminated structure having a single layer or a plurality of routing circuitry and one or more dielectric layers; the heat sink may be a metal base, a metal block or a buried metal layer. Ο The heat transfer plate joins the next layer. For example, the next layer of the body can be a lamp holder having a printed circuit board and a heat sink. In this example, an LED package system is disposed on the heat conducting plate, and the heat conducting plate is disposed on the heat dissipating device, and the heat conducting plate/heat dissipating device sub-group and the printed circuit board are further disposed in the lamp holder. The heat conducting plate is electrically connected to the printed circuit board via a wire. Thereby, the substrate can guide the electrical signal from the printed circuit board to the LED package, and the heat sink can diverge and transfer the thermal energy of the LED package to the heat sink. Therefore, the thermal pad provides an important thermal path for the LED wafer. U.S. Patent No. 6,507,102 to the name of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of the entire disclosure of The heat dissipating block adheres to the side wall of the central opening and is coupled to the substrate, and the upper and lower conductive layers are respectively adhered to the top and bottom of the base plate, and are electrically connected to each other through the electric ore guiding holes penetrating the base plate. Sexual links. Furthermore, the wafer is disposed on the heat sink and bonded to the upper conductive layer, and has a package material molded on the wafer, and the lower conductive layer is provided with a solder ball. When the above patent was manufactured, the substrate was originally a B-stage resin film placed on the lower conductive layer. The heat dissipating block is inserted in the central opening, and thus is located on the lower conductive layer and separated from the substrate by a gap, and the upper conductive layer is disposed on the upper and lower conductive layers to be heated and mutually After the pressing, the resin is melted and flows into the gap to be solidified, and the upper and lower conductive layers are patterned. Thus, circuit wiring is formed on the substrate, and resin flash is exposed on the heat sink. Then, the resin flash is removed, the heat sink is exposed, and finally the wafer is placed on the heat sink and bonded and packaged. Therefore, the reduction generated by the above wafer can be transmitted to the printed 胄 板 via the heat sink. However, when mass production is performed, the operation of placing the heat slug in the I-cell opening is extremely laborious and costly. Moreover, since the mounting tolerance of the lateral direction is small, the heat dissipating block is not easily accurately positioned in the central opening, resulting in a situation in which the substrate and the heat dissipating block (4) are uneven and the wiring is uneven. Thus, the substrate is only partially adhered to the heat dissipating block, and it is impossible to obtain sufficient supporting force from the heat dissipating block and to easily delaminate. In addition, the chemical etching solution for removing a part of the conductive layer to expose the resin flash will also remove some of the heat-dissipating block which is not covered by the resin flash, so that the heat-dissipating block is not flat and difficult to combine, and finally the yield of the group is lowered, The disadvantages of insufficient reliability and high cost. A high heat-dissipating ball grid array package disclosed in U.S. Patent No. 6,528,882 to Ding et al., the entire disclosure of which is incorporated herein by reference. region. Wherein, an insulating layer is formed on the bottom surface of the metal core layer, and a blind hole is penetrated through the insulating layer to directly pass through the metal core and the layer, and the hole is filled with a heat-dissipating solder ball, and the substrate is further provided with The heat-dissipating solder ball corresponds to the solder ball. Thereby, the thermal energy generated by the wafer can flow to the heat-dissipating solder ball through the metal core layer and then to the printed circuit board; however, the insulating layer sandwiched between the metal core layer and the printed circuit board flows to the printed circuit board. The heat flow is a limitation. U.S. Patent No. 6,670,219 to Lee et al., the disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire portion a heat dissipating substrate, wherein a wafer is mounted on a recess formed by a central opening of the ground plate, and a substrate having a central opening is disposed on the ground plate through an adhesive layer having a central opening. Tin balls are provided on the substrate. However, since the solder ball is located on the substrate, the heat sink does not contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection rather than heat conduction, thereby greatly reducing the heat dissipation effect. U.S. Patent No. 7,038,311 to Woodall et al. provides a high-heat-dissipation BGA package having a heat sink having an inverted shape and including a column portion and a wide substrate. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate; a wafer is disposed on the pillar portion and wire bonded to the substrate 'A package material is molded onto the wafer, and the substrate is provided with solder balls. The pillar portion extends through the window opening ' and supports the substrate by the wide substrate, and the solder ball is located between the bottom of the wide base 201036212 and the periphery of the substrate. Thereby, the thermal energy generated by the wafer can be transmitted to the wide substrate via the pillar portion and then transferred to the printed circuit board; however, since the wide substrate must have a space for accommodating the solder ball, the wide substrate only corresponds to At the center window • The position between the innermost solder ball protrudes below the substrate. As a result, the base sheet is unbalanced during the manufacturing process and is easily shaken and bent, which in turn results in difficulty in mounting, wire bonding, and molding of the package. In addition, the wide substrate may be bent due to the molding of the encapsulating material, and once the solder ball collapses, the package may not be soldered to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high. U.S. Patent Application Publication No. 2007/0267642 to Erchak, et al., which is incorporated herein by reference in its entirety, which is incorporated herein by reference in its entirety, the entire disclosure of the disclosure of the entire disclosure of the disclosure of the disclosure of There are electrical contacts on the top. A package system having a through hole and a transparent upper cover is disposed on the electrical contact, an LED chip is disposed on the protruding portion and connected to the substrate by wire bonding, and the protruding portion is adjacent to the substrate and extends through the insulating layer And the through hole on the package enters the package body. Moreover, the insulating layer is disposed on the substrate, and the insulating layer is provided with electrical contacts, and the packaging system is disposed on the electrical contacts and spaced apart from the insulating layer. Thereby, the thermal energy generated by the wafer can be transmitted to the substrate via the protruding portion to reach a heat dissipating device; however, the electrical contacts are not easily placed on the insulating layer, and it is difficult to be electrically connected to the next layer. Linked and cannot provide multi-layer routing. Conventional packages and thermally conductive plates have major drawbacks. For example, an electrically insulating material having a low thermal conductivity such as an epoxy resin limits the heat dissipation effect; however, an electrically insulating material having a high thermal conductivity such as an epoxy resin filled with ceramic or tantalum carbide has low adhesion and The disadvantage of high production cost, so that the electrical insulating material 201036212 I can be installed as a female towel or silk _ that is due to the heat shouting layer. If the substrate is a single-layer circuit system, the routing capability is limited. However, if the substrate is a multi-layer circuit system, the excessively thick f layer will reduce the heat dissipation effect. In addition, Chi technology has some problems such as heat dissipation, lack of sharpness 9, excessive volume or difficulty in thermal connection to the lower-layer group, and the production of Weilin is suitable for low-cost mass production operations. In view of the development of existing high-power semiconductor device packages and heat-conducting plates, it is not cost-effective, reliable, and suitable for the industry to meet the needs of the industry. Mass production, enthalpy function, semiconductor wafer assembly with excellent routing and excellent scatter. SUMMARY OF THE INVENTION The main object of the present invention is to solve the above problems encountered by Kelly and to provide a high reliability, a low price and a very suitable mass production, and is particularly suitable for applications such as LED packages and large semiconductor crystals. High-power semiconductor components that are prone to high heat and require excellent heat dissipation for efficient and reliable operation.次 The secondary objective of the present invention is to provide an environmentally friendly requirement that can significantly increase throughput, yield, efficiency, and cost effectiveness, and is well suited for copper wafers and lead-free environments. To achieve the above object, the present invention is a semiconductor wafer package comprising at least a semiconductor component, a heat sink, a substrate, and an adhesive layer. The semi-conductor component is electrically connected to the substrate and thermally coupled to the heat sink; the heat sink has at least a stud and a base, and the stud extends upward through one of the adhesive layers and a through hole extending into the substrate, the base extending laterally from the stud; the adhesive layer extending between the stud and the substrate and between the base and the substrate; and the substrate is at least The first and second conductive layers and a dielectric layer of a layer 9 201036212 are disposed, and a horizontal signal route between a pad and a terminal on the first conductive layer is provided. [Embodiment] - The present invention is a system. A semiconductor wafer package comprising at least a semiconductor component, a heat sink, a substrate and an adhesive layer. The semiconductor component is electrically connected to the substrate and thermally coupled to the heat sink, and the heat sink includes at least a stud and a pedestal. The pillar extends upward through one of the openings of the adhesive layer and enters a through hole of the substrate, the base extends laterally from the pillar, and the adhesive layer extends from the pillar and the substrate And the substrate and the substrate of the substrate and at least the first and second conductive layers and a dielectric layer therebetween. The 忒 substrate can provide a pad and a terminal on the first conductive layer by using one of the routing lines on the second conductive layer and the first and second conductive holes extending through the dielectric layer between the conductive layers. Horizontal signal routing between. In the embodiment of the invention, the semiconductor "group system comprises at least three semiconductor elements, an adhesive layer, a heat sink and a substrate. The adhesive layer has at least one opening; the heat sink comprises at least one pillar and one a pedestal, and the stud is adjacent to the base of the ship and extends above the pedestal in an upward-upward direction, the pedestal extending downward in the downward direction opposite the upward direction below the stud, and perpendicular to the The lateral direction of the upward and downward directions extends laterally from the stud; the substrate is disposed on the adhesive layer and extends over the pedestal, and at least includes an S-pad, a terminal, a routing line, The first and second conductive vias and a dielectric layer ′ wherein the solder bump and the terminal extend over the dielectric layer, the routing line extending below the dielectric layer and embedded in the silk layer blanket, each conductive The hole system extends through the dielectric layer to the routing line, and the first conductive hole, the routing line, and the second conductive hole of the 1010636212 constitute a conductive path between the terminal and the terminal. a hole extending through the substrate; the semiconductor component is located Above the stud, overlapping the stud and electrically connected to the pad, electrically connected to the porch, and the material (4) is a scale _ secret, connected from the wheel to the pedestal 0 Extending through the opening into the through hole to reach the dielectric layer. The pedestal extends over the semiconductor component, the adhesive layer and the substrate, wherein the adhesive layer is disposed on the pedestal and The pedestal extends into the 孔it hole - a gap between the stud and the substrate, extending across the dielectric layer in the notch, and between the stud and the dielectric layer, the base Between the socket and the dielectric layer, and between the pedestal and the routing line. The thermal recording material includes a cover body woven on the top of the protrusion, adjacent to the top of the protrusion and covered from above And extending from the top side of the stud in the lateral direction. For example, the body may be rectangular or square and the top of the stud may be circular; the cover may also contact and cover the adhesive &-_The stud has no ribbed portion; the city body can also be attached to the solder pad and the terminal The protrusion is electrically coplanar. Further, the protrusion can thermally connect the holder to the cover. The heat sink can be (4) and is composed of the protrusion, the base and the cover. The heat sink can provide a heat dissipating side, and the thermal energy of the semiconductor component can be diffused to the next layer. The semiconductor component can be disposed on the heat sink. For example, the heat sink can be disposed on the heat sink. The semi-conducting element can be disposed on the heat sink and the substrate, and is overlapped with the pillar and the tantalum, and the first-itch is electrically connected to the impurity, and is thermally coupled to the cover through the H tin. The semiconductor component can be disposed on the heat sink instead of the substrate 201036212, and is not overlapped with the substrate, and is electrically connected to the cover through a wire. The semiconductor is bonded to the cover. The component can be a packaged or unpackaged semiconductor..μ. For example, the half-element element may be an LED including a coffee chip and placed on the heat sink and the substrate, overlapping the pillar and the solder pad, and connecting to the solder pad via a -_- button. And the second semiconductor element is connected to the bump or the semiconductor element can be a semiconductor wafer disposed on the heat sink instead of the substrate, overlapping the pillar instead of the substrate, via a snoring The material is connected to the pad and thermally bonded to the cover via a crystalline material. The adhesive layer can be connected to the aging layer in the π, and the pedestal, the t-layer and the routing line are connected outside the defect. The layup layer may also cover the substrate from below and cover and surround the studs in the lateral directions while extending to the matrix. The county level can also have no collateral _ top coplanar. The wire layer can also fill the gap and a space between the base and the county plate and is confined within a space between the heat sink and the substrate. The stud can be formed integrally with the base. For example, the stud and the pedestal may be G-metal bodies or include -mono-metal bodies in their interfaces. The stud can also extend through the through hole. The studs may also be coplanar with the adhesive layer above the dielectric layer. The stud may also be a flat-topped conical cylinder having a diameter that decreases upwardly from the base toward its flat top adjacent one of the covers. The pedestal can cover the semiconductor element, the stud, the substrate and the a-adhesive layer from below to support the substrate and extend to the peripheral edge of the group. The substrate can be spaced apart from the stud and the base. The substrate can also be a one-layer structure. The solder pad may be an electrical contact for connecting the + conductor component, the terminal may be an electrical contact for connecting the lower layer assembly, and the soldering pad and the terminal may be at the 12 201036212 semiconductor component Provide horizontal signal routing between the next layer of the group. The present embodiment can be a -stage or second stage single crystal or polycrystalline device. For example, the body can be a first level package containing a single wafer or multiple wafers. The _ group can be a 帛 two-level module comprising a single-LED package or a plurality of LED packages, wherein each of the LED packages can comprise a single-dated wafer or a plurality of LED chips. The present invention provides a method of fabricating a semiconductor wafer package, comprising: providing a stud and a pedestal; providing an adhesive layer on the pedestal and inserting the stud into one of the hybrid layers; The substrate is disposed on the hybrid layer, and the stud is inserted into the through hole of the substrate, thereby forming a gap π between the stud and the substrate in the through hole; causing the adhesive layer to flow upward into the defect σ; curing the adhesive layer; providing a semiconductor device on the heat sink, wherein the heat sink comprises at least 13⁄4 pillar thief; the semiconductor element is lightly bonded to the substrate; and thermally connecting the semiconductor component to the heat sink seat. The substrate includes at least a first and a second conductive layer and a dielectric layer therebetween to provide horizontal signal routing. According to the embodiment of the present invention, a method for fabricating a semiconductor wafer set includes the following steps: (A1) providing a stud, a pedestal, an adhesive layer, and a substrate wherein the substrate is at least Including a first conductive layer, a second conductive layer, and a dielectric layer therebetween, the pillar is adjacent to the pedestal, and extends in an upward direction over the pedestal to extend through an opening of the adhesive layer. And extending into one of the through holes of the substrate; the seat edge-downward direction extends downward in the downward direction of the pillar and extends laterally from the pillar in a direction perpendicular to the upward and downward directions. The adhesive layer is disposed on the pedestal, extends over the pedestal, and is located on the susceptor and is uncured; the substrate is disposed on the adhesive layer 13 201036212 and extends over the adhesive layer. The first conductive layer extends over the dielectric layer, the dielectric layer extends over the second conductive layer; and a notch is located in the via and between the stud and the substrate; B1) causing the adhesive layer to flow upward into the gap (C1) curing the adhesive layer; (D1) disposing a semiconductor component on a heat sink including at least the stud and the base, wherein the conductor component is a (10) stud, and the substrate is at least: a routing line and first and second conductive vias, the solder pads and the germanium comprising a selected portion of the conductive layer, the trace comprising a selected portion of the second conductive layer, and each of the conductive a hole extending through the dielectric layer; (Ε1) electrically connecting the semiconductor component to the material, thereby electrically connecting the semiconductor component to the terminal, and the conductive path between the solder and the terminal is included in the a first conductive hole, the routing line and the second conductive hole; and (F1) thermally bonding the semiconductor element to the stud, thereby thermally bonding the semiconductor element to the pedestal. According to another embodiment of the present invention The method for fabricating a semiconductor wafer set includes the following steps: (A 2) providing a stud and a pedestal, wherein the read stud is adjacent and integrally formed on the pedestal and is oriented in an upward direction Extending over the base and the base system /σ and the upward direction Conversely, the downward direction extends below the stud and extends laterally from the side of the 'column/. vertical H upward and downward directions; A (Β2) provides an adhesive layer, wherein an opening extends through the adhesive a layer, the adhesive layer may be an uncured epoxy film; (C 2 ) providing a substrate comprising at least first and second conductive layers, first and second conductive vias and a dielectric layer, Wherein the dielectric layer is located between the electrical layers of the conductive layer 14 201036212, and a routing line includes a selected portion of the second conductive layer, each of the conductive holes extending through the dielectric between the first conductive layer and the routing line a layer, and a through hole extending through the substrate; (D 2) disposing the adhesive layer on the base, and inserting the stud into the opening, wherein the adhesive layer extends over the base, and the stud extends Through the opening; (E 2) disposing the substrate on the adhesive layer, and inserting the stud into the through hole, wherein the substrate extends over the adhesive layer, and the first conductive layer extends from the dielectric Above the layer, the dielectric layer extends over the second conductive layer. The stud extends through the opening into the through hole. The adhesive layer is located between the pedestal and the substrate and is uncured. A notch is located in the through hole and interposed between the stud and the substrate; F2) heating and melting the adhesive layer; (G2) abutting the base and the substrate, thereby moving the stud upward in the through hole, and melting and bonding the base and the substrate The layer (ie, the molten uncured epoxy resin) applies a pressure that forces the molten adhesive layer to flow into the gap toward the crucible, and the stud and the molten adhesive layer extend above the dielectric layer; (Η 2) Heating and curing the molten adhesive layer (ie, molten uncured epoxy resin), thereby mechanically adhering the stud and the base to the substrate; (I 2) grinding the stud, the adhesive layer, and the first a conductive layer, such that the stud, the saddle layer and the first conductive layer are laterally flush with each other at an upper surface facing the upward direction, wherein the grinding may include grinding the adhesive layer without grinding the stud, And then grinding the stud, the adhesive layer and the first conductive layer; (J 2)h for And a terminal, the soldering pad and the terminal comprising a selected portion of the 15th 201036212 conductive layer, and removing a selected portion of the first conductive layer; j K 2 ) providing a cover body on the protruding post, the cover Above the top of one of the studs, adjacent to the top of the stud, adjacent to the top of the stud, while covering the top of the stud from above, and extending laterally from the top of the stud in the side directions; (L 2 a semiconductor device is disposed on the cover body, wherein a heat sink includes at least the stud, the weaving seat and the outer portion, and the half of the component is overlapped with the stud; (M2) electrically connecting the semiconductor component to the soldering a pad electrically connecting the semiconductor device to the terminal 'the wiper--the conductive path between the pad and the terminal sequentially includes the first conductive via, the routing line and the second conductive via; and N 2) thermally bonding the semiconductor element to the cover, thereby thermally bonding the semiconductor element to the pedestal. • the above step (A 2 ) provides that the stud and the base system can include: • providing a metal plate on the metal plate to form a patterned surname resist layer selectively exposing the metal plate; etching The metal plate is formed into a pattern defined by the patterned etch stop layer, thereby forming a recess in the metal plate that extends into but does not penetrate the metal plate; and then removes the patterned money a resist layer, wherein the stud is an unetched portion of the metal plate, protrudes above the pedestal, and is laterally surrounded by the recess. The pedestal is also an unetched portion of the metal plate, and Located below the stud and the groove. The step (C2) providing the substrate system may include: forming first and second holes penetrating the first and second conductive layers and the dielectric layer; depositing conductive metals in the first and second holes respectively Forming the first and second conductive holes; providing the routing line 'this step includes removing a selected portion of the second conductive layer; then forming 201036212 into the through hole, the above-mentioned lobes U 2 ) providing a switch Depositing a third conductive layer on the stud, bonding the first conductive layer, and then removing selected portions of the first and third conductive layers, wherein the solder fillet and the first and third conductive layers are included Choice and points. Depositing the third electroless ore to cover a first coating layer on the stud, the adhesive layer and the first conductive layer, and then electro-mining a second coating layer on the first coating layer, and removing the The mosquito portion of the third conductive layer can include a selected portion of the first and second cladding layers removed. The mention of the county secrets may include: after the 111 姊 layer, and the setting = conductor element read, provided by the thief, the cover is located above the top of the stud, adjacent to the top of the stud, and from above Covering the top of the stud and extending laterally from the top of the stud in the direction of the object surface. The step (K2) of the touch cover system can include depositing a third conductive layer on the stud after grinding and removing selected portions of the second conductive layer. For example, providing the job body may include: forming a patterned layer on the third conductive layer; the resist layer of the third conductive layer defines the two bodies and then removing the paste __. Similarly, the first and second conductive layers can also be patterned using the patterned side resist layer to define the pad and the terminal when the soldered mountain terminal is formed. The above step (G 2 ) causes the adhesive layer flow system to be filled with the adhesive layer to include a squeezed (four) adhesive layer, which passes through the notch, reaches the convex portion, and on the top surface of the convex column Locating the semiconductor device in the step (L 2) of the top surface of the substrate adjacent to the notch may further include: positioning the semiconductor element of the semiconductor 17 , the current component of the semiconductor 17 , the cover, the opening and the through hole, and The semiconductor element is overlaid on the stud, the cover, the opening, and the through hole.

The step (L 2) of disposing the semiconductor device may include: providing a first solder and a second solder, wherein the first solder is located between an LED package having a wafer and the pad, and the second solder is located The led package is between the cover and the cover. The step (M2) electrically connecting the semiconductor tree system comprises: providing the first branch located on the LED body and the impurity side. The step (N 2 ) thermally bonding the semiconductor device comprises: providing the second solder between the package and the cover. The step (L 2) of disposing the semiconductor device may further comprise: providing a die bonding material between the half of the conductor piece and the cover. Step (Μ 2) Electrically connecting the semiconductor component may further include: providing a wire between the wafer and the pad. The step (Ν2) thermally bonding the semiconductor device may further comprise: providing the die bonding material between the wafer and the cover. The adhesive layer may contact the stud, the base, the cover, the dielectric layer and the routing line, covering the substrate from below, covering and surrounding the stud in the lateral direction and extending to the After the assembly is completed, the peripheral edges formed by the separation from the other batches produced in the same batch are formed. The pedestal may cover the semiconductor element, the stud, the cover, the substrate and the adhesive layer from below, and simultaneously support the substrate, and extend to the other group separated from the same batch after the assembly is completed. Form the outer edge. The invention has several advantages. The heat sink can provide excellent heat dissipation effect and prevent thermal energy from flowing through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not easy to be delaminated; the pillar can be integrally formed with the base To improve reliability; the cover can be tailor-made for the semiconductor component to enhance the effect of the thermal bond 18 201036212; the layer can be between the land and the substrate and between the base and the substrate In order to provide a strong mechanical connection between the heat sink and the substrate, the substrate can provide a complex circuit system pattern to achieve flexible multilayer signal routing; and the base can provide mechanical support for the substrate to prevent it Bending deformation. In this way, the system can be manufactured by using a low-temperature process, which not only reduces the stress, but also improves the reliability. In addition, this (10) can also be applied to the high control process that can be easily implemented by the circuit board, the lead frame and the wire strip manufacturer. Manufacturing. The above and other features and advantages of the present invention will be further described hereinafter by way of various embodiments. Referring to FIG. 1A to FIG. 1F, which are schematic cross-sectional views showing a structure for forming a stud and a pedestal according to a preferred embodiment of the present invention, a post and a post are formed in a preferred embodiment of the present invention. A schematic cross-sectional view of a structure of a pedestal, a cross-sectional view of a structure for forming a stud and a pedestal in a preferred embodiment of the present invention, and a cross-sectional view of a structure for forming a stud and a pedestal in a preferred embodiment of the present invention. The schematic view, the top view of Fig. 1D, and the bottom view of Fig. 1D. As shown, a metal plate 10 is provided which includes opposing major surfaces 12, 14 as shown in Figure 1A. The metal sheet 1 can be made of a variety of metals such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold, mixtures thereof, and alloys thereof. In particular, copper has the advantages of high thermal conductivity, good bonding, and low cost. Therefore, the metal plate 10 of the present embodiment uses a copper plate having a thickness of 500 μm to form a patterned money on the metal plate 1 . The etch resist layer 16 and a etch stop layer 18 are provided as shown in FIG. 1B. The rounded etch stop layer 16 and the overlying etch stop layer 18 are deposited on the photoresist layer of the metal plate 10, and are formed by using a stamper technology to simultaneously press the photoresist layer with a hot roller. Combined with the surface 1 2, 1 4, in which the wet spin coating method and the shower 201036212 curtain coating method are also suitable photoresist forming techniques. Then, a photomask (not shown) is placed on the photoresist layer, and then light is selectively passed through the photomask by a conventional technique to remove the soluble photoresist portion to make the photoresist The layer 16 is patterned to form a pattern b such that the photoresist layer on the surface 12 has a selectively exposed pattern to form a patterned etch stop layer 16. The photoresist layer on the surface 14 is non-circular. And maintaining the cover to form a full-coverage etch stop layer 18 ° A recess 2 〇 is formed on the metal plate 1 掘 but not penetrated through the metal plate 1 〇, as shown in FIG. 1C. The recess 2 is formed by etching the metal plate 10 such that the metal plate 形成0 forms a pattern defined by the patterned etch stop layer 16. In this embodiment, the etching method is wet chemical etching, and a chemical etching solution may be sprayed on the metal plate 10 by using a top nozzle (not shown); or, an etch barrier layer 8 may be used. A backside protection is provided to immerse the structure in the chemical etchant to form the recess 2 〇. Among them, the chemical etching liquid can be highly targeted to copper, and can be engraved with the genus. Therefore, the groove 20 is extended from the surface 12 to penetrate the metal plate 1 〇, and the distance from the surface 14 is 200 micrometers, and the depth is 3 micrometers; The metal plate of the resistance of the resistance 1 Q caused the side secret person. Accordingly, the chemical side liquid can be a solution containing an alkali ammonia or a diluted mixture of nitric acid and hydrochloric acid, in other words, the above chemical etching solution can be acidic or testable. The ideal etching time for forming the recess 20 without causing the metal plate i Q to be excessively exposed to the chemical side liquid can be determined by trial and error. &quot; Remove the patterned resist layer 16 and the metal sheet 10 after the full coverage of the side barrier layer 8, as shown in Figures ID, 1E and 1F. Wherein the light 20 201036212 4 14 nitrogen oxide nano/2 and the base through the metal plate 1 (10), the protrusion 2 2 62 is the metal plate 1 〇 a patterned etching resistance layer ageing section. The studs 2 2 are adjacent to the pedestal 2 4, and the 'slot 2 is integral' and protrudes above the pedestal 2 4 and is laterally surrounded by Γη ^. Wherein the stud 22 is 300 microns high (equal to the groove Ο 1000^ degrees), the top surface thereof (ie, the circular portion of the surface 12) has a diameter of only the bottom portion (ie, the circle adjacent to the pedestal 24). The diameter of the part) is the cut H. Therefore, the stud 2 2 is flat lion _ (ie, similar to a flat head body), the side wall is tapered, and the diameter is decreased from the pedestal 24 toward the flat circular top surface thereof. . Among them, the tapered sidewall is formed by the chemical surname and the lateral surname of the engraved layer. 6 is formed below, so the top surface is concentric with the circumference of the bottom, as shown in Fig. 1. The pedestal 24 is an unetched portion of the metal plate 1 below the stud 2 2 , extending laterally from the stud 2 2 along the lateral plane, such as the left and right sides, the side direction, the thickness It is 200 microns (ie 500~300). The studs 2 2 and the pedestal 24 can be treated to enhance bonding with epoxy and solder. For example, the studs 2 2 and the susceptor 24 may be chemically oxidized or micro-etched to create a rougher surface. In this embodiment, the studs 2 2 and the pedestal 24 are through a single metal (copper) body formed by a reduction process. The metal plate 1 can also be stamped by a contact having a groove or a hole to define the portion of the protrusion 2 2, so that the protrusion 2 2 and the base 24 are stamped into a single metal body. Or, the protrusion 2 2 is formed by an additive method, for example, by electroplating, chemical vapor deposition 21 201036212 (Chemical Vapor Deposition, CVD), physical vapor deposition (PVD), etc. 2 2 is deposited on the pedestal 24, or alternatively, the stud 2 2 is formed by a semi-addition method, for example, the upper portion of the ribs 2 2 is deposited on the lower portion of the etched portion; Alternatively, the s-convex pillars 2 2 may also be sintered to the susceptor 24. In addition, the protrusion 2 2 and the shank 24 may also be a multi-piece metal body, for example, a solder bump 22 is plated on the copper base 24; in this case, the protrusion 22 and the pedestal The 24 series are connected by metallurgical interface, but adjacent to each other but not integrally formed. 0 s extravagance refers to "2A to 2D": ^ ' is a structure for making an adhesive layer in a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a schematic cross-sectional view showing a structure for forming an adhesive layer, a top view of FIG. 2B, and a bottom view of FIG. 2B. As shown in the figure: A film of B-stage uncured epoxy resin is provided as the adhesive layer 2 6, which is 15 μm thick, as shown in Fig. 2A. The adhesive layer 26 can be a variety of dielectric films or films made of a variety of organic or inorganic electrical insulators. For example, the adhesive layer 26 may initially be a film in which the ruthenium resin is thermally epee-embedded-reinforced (four) and partially cured to a later stage. The above epoxy resin may be FR-4, and other epoxy resins such as polyfunctional and bismaleimide-triazabenzene (BT) resins may also be used. In certain applications, cyanate vinegar, polyimine, and polytetracycline (PTFE) are also useful epoxy resins. The reinforcing material may be an electronic grade glass, or may be other reinforcing materials such as high-strength glass, low-inducing glass, quartz, Kevlar fiber (κ_Aramid), and paper. The reinforcing material can also be a woven fabric, a non-woven fabric or a non-directional microfiber. A filler such as hair (powder quartz) can be added to the film to enhance the guiding force, thermal shock resistance and difficulty. Among them, 22 201036212 may use a commercially available prepreg, such as SPEEDBOARD C film of WL Gore &amp; Associates of Oakley, Wisconsin, USA. The adhesive layer 26 has at least one opening 2 8, as shown in the second B, 2 C and 2, D. The opening 28 is formed by penetrating the central window of the adhesive layer 26 by mechanically drilling through the film and having a diameter of 115 Å. The opening 28 can also be made by other techniques such as punching and stamping. Referring to FIG. 3A to FIG. 3I, FIG. 3 is a cross-sectional view showing a structure of a substrate according to a preferred embodiment of the present invention, and a structure of a substrate fabricated in a preferred embodiment of the present invention. FIG. 3 is a schematic cross-sectional view showing a structure of a substrate in a preferred embodiment of the present invention, a schematic cross-sectional view showing a structure of a substrate according to a preferred embodiment of the present invention, and a structure for fabricating a substrate in a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a cross-sectional view showing the structure of a substrate produced in the preferred embodiment of the present invention. FIG. 2 is a cross-sectional view showing the structure of a substrate in a preferred embodiment. FIG. And a bottom view of Figure 3G. As shown in the figure, a substrate 30 is provided, which comprises a first conductive layer 3 2, a dielectric layer 34 and a second conductive layer 3 6, as shown in FIG. 3A. The first conductive layer 32 is in contact with and extends over the dielectric layer 34. The second conductive layer 36 contacts the dielectric layer 34 and extends under the dielectric layer 34. The first and second conductive layers 32, 36 are sandwiched therebetween. The first and second conductive layers 3 2 and 3 6 are electrical conductors, and the dielectric layer 34 is an electrical insulator. For example, the first and second conductive layers 3 2, 3 6 are 15 μm thick and unpatterned copper plates, and the dielectric layer 34 is 150 μm thick epoxy trees. The substrate 30 has holes 38, 40 which penetrate the first and second conductive layers 3, 3 6 and the dielectric layer 34, as shown in Fig. 3B. The holes 3 8 and 4 G are formed by mechanical drilling, and the village is made by other techniques, such as 23 201036212. Laser drilling is a suitable technique. The substrate 30 is provided with conductive holes 4^, 44 in the holes 38, 40, respectively. The conductive holes 42, 44 are electrical conductors, and are electrically and electrically connected to the first and second conductive layers. 3 6 'At the same time contact and penetrate the dielectric layer 3 4 , as shown in FIG. 3 C , the conductive holes 4 2 , 4 4 are electric conductive holes. For example, the body layer can be immersed in the immersion-activated sputum so that the dielectric layer 34 of the sidewalls of the holes 38, 4 可 can react with the non-bonded copper, and then the first steel layer is unrecorded. After the first and second conductive layers 3 2, 3 6 are in contact with the holes 38, 40, and then, a second copper layer is deposited on the first steel layer. Wherein the first copper layer is about 2 micrometers thick, and the second copper layer is about 13 micrometers thick, so that the total thickness of the coated copper layer is about 15 micrometers. Therefore, the thickness of the first and third conductive layers 3 2, 3 6 is increased to about 40 μm (i.e., 25 + 15 ), but is reduced to about 3 μm after successively removing the photoresist layer and cleaning the steps. In addition, the conductive holes 4 2, 4 4 are formed in the holes 38, 40, respectively. For the sake of explanation, the first and second conductive layers 3 2, 3 6 and the conductive holes 4 2, 4 4 of the 3 cth diagram are all single-layer bodies. Also for the sake of explanation, the conductive holes 4 2, 4 4 are all shown as embossed in the holes 38, 40 instead of the hollow tube. The substrate 30 has a etch stop layer 46 and a patterned etch stop layer 48 formed on the first and second conductive layers 3 2, 3 6 , respectively. The etch resist layers 46, 48 as shown in Fig. 3D are respectively photoresist layers similar to the etch resist layers 丄8 and 16. Wherein the surname resist layer 46 is without any pattern and covers the 5th first conductive layer 32, and the residual resist layer 48 is provided with a circular case for selectively exposing the second conductive layer 36. . In the substrate 3 of FIG. 3E, the selected portion of the second conductive layer 36 has been subjected to 'causing the far first conductive layer 36 to have a patterned resist layer 4 24 201036212 8 The pattern of righteousness. The reward is a chemical, which is similar to that used for the metal sheet. At this time, the first conductive layer 32 is still a copper plate without a circle, but the second conductive layer 36 is recorded to cause the dielectric layer 34 to be exposed, and the second conductive layer 36 is removed from the first conductive layer 36. The unpatterned layer is converted into a pattern layer. In the present embodiment, in order to facilitate comparison of the figures, the second conductive layer 36 is located under the dielectric layer 34 in the drawing, but in this step, the structure can be inverted to enhance the etching effect by gravity. . In the substrate of the 3F F®, the fully covered side resist layer 46 and the patterned resist layer 48 have been removed. The photoresist layer 4 6 and 48 may be stripped in the same manner as the photoresist layer i 6W 8 is stripped. The first conductive layer 36 after the job has a routing line 5 Q. Therefore, the routing line 5 〇 is protected by the patterned resist layer 48 from the second conductive layer 36. In addition, the routing line 5 is a copper wire that contacts the dielectric layer 34 and extends below it, and is adjacent to and electrically connected to the conductive vias 4, 4 4 . Therefore, the conductive vias 4 2, 4 4 each extend and are connected between the first conductive layer 3 2 and the routing line 50. The raft 30 has a through hole 5 2 as shown in the 3rd G, 3 Η and 3! The through hole 52 is a central window penetrating the substrate 3, and the first conductive layer 32 and the far dielectric layer 34 are mechanically drilled through (only the second conductive layer is not included therein). Since the layer has been removed from the region by wet chemical money, the diameter of the through hole 52 is (four) micrometers. The through hole 52 is formed by other techniques such as punching and stamping. Preferably, the opening 28 has the same straightness as the through hole 52 and is formed in the same manner on the same drill floor with the same drill bit. The substrate 30 is shown here as a laminated structure, but the substrate 3 can also be 25 201036212 as other multilayer electrical connectors, such as a ceramic ship or a circuit board. Similarly, the substrate 30 may additionally comprise a plurality of layers of embedded circuits. Please refer to FIG. 4A to FIG. 4N for the structure of the heat-shielding plate for the structure of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic cross-sectional view showing a structure for fabricating a heat conducting plate in the preferred embodiment, a fourth cross-sectional view showing a structure for fabricating a heat conducting plate in the preferred embodiment, and a structure for fabricating a heat conducting plate in the preferred embodiment of the present invention. FIG. 5 is a cross-sectional view showing a structure of a thermally conductive raft in a preferred embodiment of the present invention, and a cross-sectional view showing a structure of a heat conducting plate in a preferred embodiment of the present invention, in a preferred embodiment of the present invention. Manufacture of a heat-conducting eight-section schematic®, a preferred embodiment of the present invention, a schematic view of a structure of a hot plate, a cross-sectional view of a structure for fabricating a heat-conducting plate in the preferred embodiment of the present invention, and a preferred embodiment of the present invention. STRUCTURE OF THE SOLID PLATE TEMPERATURE PLATE STRUCTURE OF THE TEMPERATURE STRUCTURE OF THE TEMPERATURE STRUCTURE OF THE TEMPERATURE STRUCTURE OF THE TEMPERATURE STRUCTURE OF THE PREFERRED EMBODIMENT OF THE PREFERRED EMBODIMENT OF THE INVENTION As shown in the figure, the heat conducting plate of the present invention comprises the stud 22, the susceptor 24, the viscous layer 26 and the substrate 30. The adhesive layer 26 is disposed on the base 2 4 , as shown in FIG. 4A , the adhesive layer 26 is lowered onto the base 24 , and the protrusion 2 2 is inserted upward and penetrates the The opening 2 8 and the adhesive layer 26 are in contact with and positioned on the base 24. Preferably, the protrusion 2 2 is located at a central position in the opening 28 after being inserted and penetrated through the opening 28 without contacting the adhesive layer 2 β. The substrate 30 is disposed on the adhesive layer 26 , as shown in Figure 4. The substrate 30 is lowered onto the adhesive layer 26 such that the stud 2 2 is inserted upwardly and penetrates the through hole 52, and the substrate 30 contacts and is positioned on the adhesive layer 2 26 201036212 6 . Preferably, the stud 22 is located at a central position within the through hole 52 after being inserted through the through hole 52 and does not contact the substrate 30. Therefore, the generating port 5 4 is located in the through hole 52 and between the stud 22 and the substrate 3. The notch 5 4 laterally surrounds the stud 22 and is laterally surrounded by the substrate 3 . Further, the opening 28 and the through hole 52 are aligned with each other and have the same diameter. At this time, the substrate 30 is disposed on and in contact with the adhesive layer 26 and extends over the adhesive layer 26. The stud 2 2 extends through the opening 2 8 〇 into the through hole 52 and reaches the dielectric layer 34. The studs 2 2 are 60 microns lower than the top surface of the first conductive layer 32 and are exposed upwardly through the through holes 52. The adhesive layer 26 contacts the pedestal 24 and the substrate 30 and is interposed therebetween, but is spaced apart from the dielectric layer 34. At this stage, the adhesive layer 26 is still a film of a B-stage uncured epoxy resin, and the gap 54 is air. The adhesive layer 26 is heated and pressurized to flow into the notch 54, as shown in Fig. 4C. The method of forcing the adhesive layer 26 into the gap 5 4 is to apply downward pressure to the first conductive layer 3 2 and/or apply upward pressure to the susceptor 24 , that is, the susceptor 2 4 The substrate 30 is relatively pressed to thereby press the adhesive layer 26; at the same time, the adhesive layer 26 is also heated. The heated adhesive layer 26 can be arbitrarily shaped under pressure. Therefore, after the adhesive layer 26 between the susceptor 24 and the substrate 3 is pressed, it changes its original shape and flows upward into the notch 54. The susceptor 24 and the substrate 30 are still pressed against each other until the adhesive layer 26 fills the gap 504. In addition, after the gap between the susceptor 24 and the substrate 30 is reduced, the adhesive layer 26 still fills the narrowed gap. For example, the pedestal 24 and the first conductive layer 32 can be disposed on a press machine and between the lower pressing table (not shown), and a 27 201036212 upper baffle can be placed thereon. Buffer paper (not shown) is interposed between the first conductive layer 32 and the upper pressing table, and the lower baffle and the lower buffer paper (not shown) are placed on the base 2 4 and below. Between the pressure tables. The stacked body thus constructed is, in order from top to bottom, an upper press, an upper baffle, an upper baffle, a substrate 3, an adhesive layer 26, a susceptor 24, a T-buffer paper, a lower striker, and a lower waste table. In addition, the stack can be positioned on the lower pressing table by means of a tool pin (not shown) extending upward from the lower pressing table and passing through the base 24 (not shown). Subsequently, the upper and lower press tables are heated and pushed forward to each other, whereby the adhesive layer 2 ❹ 6 is heated and pressed. The heat of the platen is dispersed by a baffle to uniformly apply heat to the susceptor 24 and the substrate 3 or even to the adhesive layer 26. The cushioning paper disperses the pressure of the press table to uniformly apply pressure to the susceptor 24 and the substrate 3 乃 or even the adhesive layer 26. Initially, the second conductive layer 36 extends into the adhesive layer 26 and is embedded therein, causing the dielectric layer 34 to contact and be pressed against the adhesive layer 26. As the platen continues to operate and continues to heat, the adhesive layer 26 between the susceptor 24 and the substrate 3 is pressed and begins to melt, thereby flowing upward into the gap 5 4 through the dielectric layer 34. Finally, the first conductive layer 3 2 is reached. For example, after the uncured epoxy resin is melted by heat, it is pressed into the gap 5 4 by pressure, but the reinforcing material and the filler remain between the base 24 and the substrate 3 . The adhesive layer 26 rises faster in the through hole 52 than the stud 22, and finally fills the notch 54. The adhesive layer 26 also rises to a position slightly higher than the gap 5 4, and overflows to the top surface of the protrusion 2 2 and the top surface of the first conductive layer 32 to abut the gap before the pressure stop stops. 5 4 places. This can happen if the film thickness is slightly larger than actually needed. As a result, the adhesive layer 26 forms a thin layer of cover on the top surface of the &lt;2&gt; column. The platen stops after touching the stud 22, but continues to heat the adhesive layer 26. 28 201036212 The upward flow direction of the adhesive layer 26 in the notch 54 is as shown by the upward bold arrow in the figure, and the protrusion 2 2 and the base 24 move upward relative to the substrate 3 as upwards. As indicated by the arrow, the downward movement of the substrate 3 〇 relative to the stud 2 2 and the pedestal 24 is as indicated by the downwardly thin arrow. The adhesive layer 26 in Figure 4D has cured. For example, after the pressing table stops moving, the pillar 2 2 and the susceptor 24 are continuously clamped and heated, thereby converting the melted B-stage epoxy resin into a C-stage curing or hardening. Epoxy resin. Therefore, the epoxy resin is laminated in a similar manner as is conventional.彳^^ 0 After the oxygen resin is cured, the platen is separated to take the structure out of the press. The cured adhesive layer 26 provides a strong mechanical bond between the stud 2 2 and the substrate 30 and between the pedestal 24 and the substrate 30. The adhesive layer 26 can withstand normal operating pressure without deformation and damage, and is only temporarily distorted when excessive pressure is applied; further, the adhesive layer 26 can also absorb between the protrusion 2 2 and the substrate 30 and the base. The thermal expansion between the seat 2 4 and the substrate 3 不 does not match. At this stage, the studs 2 2 are substantially coplanar with the first conductive layer 32, and the adhesive layer 26 and the first conductive layer 32 extend to a top surface facing the upward direction. For example, The adhesive layer 26 between the pedestal 2 4 and the second conductive layer 36 is 90 microns thicker than the initial thickness of 150 microns by 60 microns; the stud 22 is raised by 60 microns in the through hole 52. The substrate 3 is lowered by 60 microns with respect to the stud 2 2 . The height of the stud 2 2 is substantially equal to the first conductive layer 32 (30 microns), and the dielectric layer 34 (150 microns). The height of the second conductive layer 36 (30 micrometers) and the adhesive layer 26 (90 micrometers) below. In addition, the stud 2 2 is still located at a central position of the opening 28 and the through hole 52 and spaced apart from the substrate 30, and the adhesive layer 26 fills the base 29 201036212 seat 24 and the substrate 3 The space between 0 and fills the gap 5 4 . For example, the notch 5 4 (and the adhesive layer 26 between the stud 22 and the substrate 30) is wide at the top surface of the stud 2 2 ((115〇-1〇〇〇)/2) . The adhesive layer 26 extends across the dielectric layer 34 in the gap 504. In other words, the adhesive layer 26 in the gap 5 4 extends in the upward direction and a downward direction and spans the thickness of the dielectric layer 34 of the outer sidewall of the gap 5 4 . The adhesive layer 26 also includes a thin top portion </ RTI> above the rim 5 4 that contacts the top surface of the stud 2 2 and the first conductive layer 32 and extends 1 〇 micron above the stud 2 2 . The pillar 2 2, the adhesive layer 26 and the top of the first conductive layer 3 2

Remove as shown in Figure 4E. The studs 2, the adhesive layer 26 and the top of the first conductive layer 32 are removed in a manner such as bribing a diamond wheel and a top portion of the distilled water treatment structure. Initially, the diamond wheel only grinds the adhesive layer 26; the grinding is continued, and the adhesive layer is moved downward and thinned. The diamond wheel will eventually contact the stud 22 and the first conductive layer 32 (not necessarily simultaneously) 'by grinding the stud 2 2 and the first conductive layer 3 2; the stud 2 2, the hybrid layer 2 6 and the first conductive layer 3 2 are grounded down and (4) Yan Yanlin continues to remove the required distilled water to rinse the structure to remove dirt. The steaming step is performed by grinding the top of the adhesive layer 26 to the top of the pillar 2 2 by grinding 15 μm and grinding the first portion to 15 μm. Where 'thickness is reduced to the convex &lt; ^ ^ The sound is not obvious, but the degree of the first conductive layer is greatly reduced from ^ m to 15 microns. So far, the stud—from the 3 〇 the first conductive layer 32 is located above the smooth splicing side top surface h 4 of the dielectric layer, the f-adhesive layer 6 6 - facing the money 201036212 Ο Ο Next, deposition A third conductive layer 56 is disposed on the stud 2 2, the adhesive layer 26 and the first conductive layer 32, as shown in FIG. The third conductive layer 56 contacts and covers the bump 2, the adhesive layer 26 and the first conductive layer 32 from above. For example, the structure is immersed in an activator solution so that the adhesion can be reacted with the electroless copper to generate a catalyst. Then a first copper layer is provided on the pillar 2 in a manner without a key bond. Adhesive layer 26 and the first conductive layer 32, and then a second copper layer is electroplated on the first copper layer. The first copper layer is about 2 microns thick. The second copper layer is about 13 microns thick. Therefore, the thickness of the third conductive layer 56 is about 15 micrometers. As a result, the thickness of the first conductive layer 32 is increased. It is about 30 microns (15+15). The third conductive layer 56 is used as a cover layer of the protrusion 2 2 and a thick layer of the first conductive layer 32. For convenience of description, the studs 2 2 and the third conductive layer 526 , and the first conductive layer 32 and the second conductive strips are displayed in a single layer. The pillars are homogenously coated by copper. The boundary between the second conductive layer 56 and the boundary between the first conductive layer 32 and the second conductive layer 56 (both shown by dashed lines) may be less noticeable or even undetectable. However, the boundary between the adhesive layer 26 and the third conductive layer 56 is clearly visible. On the upper and lower surfaces of the structure shown in Fig. 4G, there are respectively patterned four-etched resist layer 58 and a full-coverage _resistance 6... patterned as shown in the figure: The fully covered side resist layers 6 are respectively similar to the photoresist layers such as the resist layers 16 and 18. The rice resist layer 58 is optionally provided; the pattern of the third conductive layer 56 is exposed, and the side resist layer 6 is patterned and covered by the base 24. In the structure shown in Fig. 4, the first and third conductive layers 326 have been etched to form a pattern defined by the patterned etch stop layer 58. 201036212 Removing the first and third conductive layers 3 2, 5 6 is selected for the gold =, learning _ phase pure tender engraved =, two conductive layers 3 2, 5 6 to expose the adhesive layer =, and = the first pattern of the first, three conductive layer 32 , 56 conversion = layer, while the base 24 remains unpatterned. In Fig. 41, the patterned resist layer 58 and the overlying resist layer 6 G on the structure are removed in the same manner as the barrier layers 16 and 18 are removed. The first and second conductive layers 3 2, 5 6 on the side of the 包含 include the solder bumps 6 2, the routing lines 64, 66 and the terminals 68, and the third conductive layer 56 of the butterfly includes a cover body 70. The soldering wire 6 2, the routing line 6 4, 6 6 and the terminal 6 8 are the unaccepted portion defined by the patterned side resist layer 58 on the first and third conductive layers 3 2, 5 6 The third layer of the cover body 7 (10) is defined by the unrestricted portion defined by the patterned resist layer 58. The second conductive layer 3 2, 5 6 is a patterned layer on which the solder pad 6 is included. 2. The routing lines 6 4, 6 6 and the terminal 68 do not include the cover 7 〇. In addition, the routing line 64 is a copper wire that contacts the dielectric layer 34 and extends above it while abutting and electrically connecting the conductive via 4 2 and the pad 62. The routing line 66 is also a steel wire that contacts and extends over the dielectric layer 34 while abutting and electrically connecting the conductive via 44 to the terminal 68. The conductive holes 4 2, 4 4 , the routing lines 5 0 , 6 4 and 6 6 , the pads 6 2 and the terminals 68 form a wire 7 2 . Similarly, a conductive path between the pad 6 2 and the terminal 68 passes through the routing line 64, the conductive via 4, the routing line 5, the conductive via 4, and the routing line 6. 6 (and vice versa). The wire 7 2 provides a horizontal 201036212 (lateral) output/input route from the pad 6 2 to the terminal 68, and the wire 7 2 is not limited to this configuration 'eg, the pad 6 2 and the terminal 6 8 can be directly formed on the conductive holes 4 2, 4 4 respectively, thereby eliminating the routing lines 6 4, 6 6 respectively; further, the above-mentioned conductive circuit control can include other conductive holes and routing lines (which are located at the first, The second and/or other conductive particles and the passive components, such as resistors and capacitors disposed on other pads, are formed by the above-mentioned studs 2, the pedestal 24, and the cover 70. The protrusion 22 is formed integrally with the base 24, and the cover 7 Q is located above the protrusion 2 2 adjacent to the top of the protrusion 2 2 while covering the 4 protrusion 2 2 from above. The top portion extends laterally from the top of the stud 2 2 . After the cover body 7 is to be slanted, the protrusion 2 2 is located in a central area within the circumference of the cover body 7, and the cover body 7 is also contacted from above and covers the portion of the adhesive layer 26 below it. The portion of the adhesive layer 26 is coplanar with the stud 2 2 and is adjacent to the stud 2 2 '. The heat dissipating block 74 is substantially an inverted-chat-shaped heat dissipating block, which comprises a column portion (ie, a stud 22), a wing portion (ie, a portion of the base portion 24 extending laterally from the column portion), and a thermal pad ( That is, the cover body 7 〇). 〇 In the structure shown in Fig. 4J, a solder resist green paint 7 is provided on the dielectric layer 34, the third conductive layer 56, and the cover. The solder resist green paint 7 6 is an electric steep insulation layer, which can be patterned according to the choice of the person to expose the solder bump 6 2 , the terminal 6 8 and the cover body 7〇, and the top of the Zhao covers the routing line 64, 6 6 And the exposed portion of the electric layer 3 4, the thickness of the solder resist green paint 7 6 on the solder bump 6 • 2 and the terminal 68 is 25 μm, and the solder resist green paint 7 6 is on the dielectric layer 3 4 extends over 55 microns (3 (four)). Wherein, the solder resist green paint 7 6 is initially coated with a light-developing liquid resin on the structure, and then the 33 201036212 solder resist green paint 7 6 is formed on the shape of the method. The above steps are known through a mask (not shown) and then a developing solution is used to remove the soluble portion of the solder resist green paint 7 and finally hard baked. &quot; In the structure shown in Fig. 4K, a covered contact 7 is provided on the base 24, the pad 02, the terminal 68 and the cover 70: the covered contact 7 8 is a multi-layer metal bond layer which contacts and covers the susceptor 2 4 from below and contacts the (4) 6 2 from above, the terminal 6 8 and the cover 7 〇 simultaneously covering the exposed portion thereof. For example, a nickel layer is provided on the base block 24, the soldering ring 6, the terminal 6 8 and the cover 7 以 in an electroless ore-free manner, and then a metal phase is uncovered and covered. Set on the recording layer, #内内锦层 is about 3 microns thick. The surface gold layer is about 〇5 microns thick, so the thickness of the coated age 8 is about 3.5 microns. Furthermore, the surface treatment system using the covered contact 7 as the susceptor 24, the soldering ring 6, the terminal 68 and the cover has several advantages, including the internal nickel layer providing the main mechanical properties. It is electrically connected and/or thermally connected, while the surface gold layer is provided for the wettable surface to facilitate solder reflow; the covered contact 8 also protects the base 2 4, the soldering ring 6 2, the terminal 6 8 and the cover Body 7 〇 〇 ; ; ; ; ; ; ; 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 For convenience of explanation, the pedestal 2 4 having the covered contact 78, the soldering ridge 6, the terminal 6 8 and the cover 7 〇 are all displayed in a single layer manner, and the covered contact 7 8 and the base The boundary between the seat 24, the pad 62, the terminal 68 and the cover 70 (not π in the figure) is a copper/nickel interface. So far, the production of the heat conducting plate 8 is completed. The edge of the heat conducting plate 8 has been separated along the cutting line from the support frame and/or the adjacent heat transfer plates produced in the same batch, as shown by the 4th L, 4, and 4 turns. The heat conducting plate 80 includes the adhesive layer 26, the substrate 3, the heat sink 74, and the anti-34 201036212 green paint 7 6, wherein the substrate 3 includes the dielectric layer 34 and is electrically conductive* 4 2 4 4, § Hai routing line 5 〇, 6 4, 6 6 , the welding 塾 6 2 and the terminal 6 8 together constitute a wire 7 2 . The heat sink 7 4 includes the protrusion 2 · 2, the base 2 4 and the cover 7 〇. After the protrusions 2 2 extend through the opening 28 and enter the through hole 5 2 , they are still located at the center of the opening 28 and the through hole 52 , and are located at the dielectric layer 34 with the adhesive layer 26 . Upper-neighboring coplanar &lt;« The stud 2 2 maintains a flat-topped tapered cylindrical shape with its tapered side wall having its diameter decreasing from the base 24 toward the flat dome adjacent the cover body 70. The pedestal 2 4 covers the stud 2 2 , the adhesive layer 26 , the substrate 30 , the cover 70 , the wire 7 2 and the solder resist green paint 7 6 from below and extends to the heat conduction Board 8 〇 edge. The cover body 7 is located above the protrusion 2 2 and is adjacent to and thermally connected. The cover 7 〇 covers the top of the protrusion 2 2 from above and extends laterally from the top of the protrusion 2 2 . ' stretched. The cover body 7 is also contacted from above and covers a portion of the adhesive layer 26, the portion of the adhesive layer 26 is adjacent to the protrusion 2 2, coplanar with the protrusion 2 2, and laterally surrounding the cover Stud 2 2 . The cover 7 is also coplanar with the pad 6 2 and the koji 6 8 . The adhesive layer 26 is disposed on the base 24 and extends above it. The adhesive layer 26 is in contact with and between the pillar 2 2 and the dielectric layer 34 and the pillar 2 2 and the second conductive layer 36 to fill the pillar 2 2 and the dielectric layer The electrical layer 34 and the space between the pillar 2 2 and the second conductive layer 36. The adhesive layer 26 is also in contact with the periphery of the second conductive layer 36 and between the pedestal 24 and the dielectric layer 34 to fill the space therebetween. In addition, the adhesive layer 26 is also in contact with and between the susceptor 24 and the second conductive layer 36 to fill the space therebetween. The adhesive layer 26 is disposed outside the periphery of the stud 2 2, covering the pedestal 24 from the upper 35 201036212, and covering the substrate 3 从 from below while covering and surrounding the stud 22 in the lateral direction. The adhesive layer 26 is confined in the space between the substrate 3 〇 and the heat sink 7 4 and fills most of the space and has been cured. The substrate 30 is disposed on the adhesive layer 26 . And in contact with it, and extending above the lower adhesive layer 26 and the base 2 4 . The first conductive layer 32 (and the bonding pad 6.2, the routing lines 6.4, 666, and the terminal 6.8) contact the dielectric layer 34 and extend thereover; the dielectric layer 34 Contacting and extending the second 0 conductive layer 36 (including the routing line 50), and the dielectric layer 34 is interposed between the conductive layers 32 and 36; the second conductive layer 3 6 (including the routing line 50) contacts the adhesive layer 26 and is embedded therein. The protrusion 2 2, the pedestal 2 4 and the cover 70 are all spaced apart from the substrate 3 。. Therefore, the substrate 30 and the heat sink 7 are mechanically connected and electrically isolated from each other. After the heat-transfer plate 80 made in the same batch is cut, the base 24, the adhesive layer 26, the dielectric layer 34 and the solder resist green paint 7 6 are all extended to the cut vertical edge. The pad 6 2 is an electrical component that is specifically designed for a semiconductor component such as an LED package or a semiconductor wafer. The semiconductor component is disposed on the cover 70 in a subsequent process. The terminal 68 is an electrical interface tailored to the next set of bodies (e.g., solderable wires from a printed circuit board). The cover 7 is a thermal interface tailored specifically for the semiconductor component. The pedestal 24 is a thermal interface specially designed for the next group of components (for example, a heat sink of an electronic device). Further, the cover 70 is thermally coupled to the base via the studs 2 2 . Block 2 4 0 36 201036212 The pad 6 2 and the terminal 6 8 are laterally displaced from each other and exposed on the top surface of the heat conducting plate 80, thereby improving the horizontal output of the semiconductor component and the lower layer_8 routing,. The soldering pad 6 2, the terminal portion 6 8 and the top surface of the cover body 7 above the dielectric layer 34 are coplanar with each other. For convenience of description, the wire 72 is shown in a cross-sectional view. Continuous circuit trace; however, the conductor 7 2 typically provides horizontal signal routing in the X and gamma directions, that is, the solder tab 6 2 and the terminal 68 form lateral misalignment with each other in the X and γ directions, and the routing line Each of 50, 64, and 6 6 forms a path of XjY. The heat sink 74 can diffuse the heat generated by the semiconductor device subsequently mounted on the cover 7 to the lower layer of the heat conducting plate 8 . The heat generated by the semiconductor element flows into the cover 7 and enters the &lt;2&gt;2 from the cover 7 and enters the base 24 via the studs 2 2 . Thermal energy is dissipated from the susceptor - 2 4 in the downward direction, for example, to a lower heat sink. The bumps 2 2 of the heat conducting plate 80, the conductive holes 4 2 and 4 4 or the routing lines 50, 6 4 and 6 6 are not exposed. The studs 2 2 are covered by the cover γ ,, and the conductive holes 4 2 and 4 4 and the routing lines 5 0 ′ 6 4 and 6 6 are covered by the solder resist varnish 7 6 to the adhesive layer The top surface of the cover is simultaneously covered by the cover body 7 and the solder resist green paint 7 6 . For convenience of explanation, in the fourth drawing, the stud 2 2, the adhesive layer 26, the conductive holes 4 2 and 4 4 and the routing lines 5 〇, 6 4 and 6 6 are shown by broken lines. The heat conducting plate 80 also includes other wires 72. The wires 7 2 are basically composed of the conductive holes 4 2 and 4 4 , the routing wires 5 〇 , 64 and 66 , the bonding pads 6 2 and the terminals 6 8 . It is constructed and has a plurality of conductive paths between the pad 6 2 and the terminal 68. For ease of explanation, only the single 37 201036212 wire 72 is illustrated and illustrated herein. The shirts 42 and 44, the pads, and the sliders 68 generally have the same shape and size, and the routing line 5 is generally used. Different routing configurations. For example, some of the wires 0 are separated from each other and electrically isolated, and the partial wires γ2 are staggered with each other or directed to the same pad 6 2, routing lines 50, 6 4, 6 6 or terminals 6 8 and electrically connected to each other. Similarly, the partial pad 6 2 can be used to receive an independent signal and the partial pad 6 2 can share a signal, power supply or ground. In addition, a portion of the wires 72 may include conductive holes 42 and 44 and routing lines 5 to provide routing, while a portion of the wires 72 do not include the conductive holes 4 2, 4 4 and the routing line 50, and only The first conductive layer 32 provides a single layer routing. The heat conducting plate 80 is suitable for an LED package having blue, green and red LED chips, wherein each LED chip comprises an anode and a cathode, and each (4) package contains a pair of red secrets and a hybrid. The fan 80 can include six soldering knives 62 and four terminals 68, each of which is a separate conductive terminal 6 2 - a separate terminal 6 8 and each cathode is guided from a separate bonding pad 6 2 to a common ground. Terminal 6 8. m At each stage of manufacture, the oxides and residues on the exposed metal can be removed. For example, a short oxygen polymerization cleaning step can be applied to the structure. Or a 'short-over (10) (four) Linben case structure for a brief >1 type chemical ageing. At the job site, you can also use the water to wash the case. This cleaning step can be used to fine the surface without causing significant damage or damage to the structure. An advantage of the present invention is that there is no need to separate or separate the confluence points or associated circuitry from the conductors 7 2 after formation. The confluence point can be separated in the step of forming the pad 6 2, the routing wires 6 4 and 6 6 , the terminal 6 8 and the cover body 7 湿 wet chemical etching 38 201036212. The heat conducting plate 80 may include a counter hole (not shown) which is drilled or cut through the base 24, the adhesive layer 26, the substrate 30 and the solder resist green paint 7 6 . As a result, when the heat conducting plate 8 is later placed on a lower carrier, the tool pins can be inserted into the alignment holes to position the heat conducting plate 8 in position. The heat shield 80 can omit the cover 70. To achieve this purpose, the patterned etch stop layer 5 8 can be adjusted so that the third conductive layer 56 over the entire via hole 52 is exposed to form the pad 6 2. The routing line 6 4, 6 6 and the chemical etching solution of the terminal 0 68. The heat conducting plate 80 can accommodate a plurality of semiconductor components instead of only a single half of the conductor components. To achieve this goal, the patterned etch stop layer 6 can be adjusted to define more bumps 2 2 , and the adhesive layer 26 can be adjusted to include more openings 2 8 to adjust the substrate 30 to include more vias 5 . 2, adjust the patterned residual resist layer 4 8 to define more routing lines 5 〇, adjust the patterned surname resist layer 5 8 to define more solder 塾 6 2, routing lines 6 4, 6 6 , terminal 6 8 with the cover 7 〇, and adjust s Hai anti-weld green paint 7 6 to contain more openings. Similarly, the substrate 3 can also include more conductive vias 4 2 and 4 4 and routing lines 50. Elements other than the terminals 68 can change the lateral position to provide a 2 χ 2 array for the four semiconductor components. In addition, the cross-sectional shape and height (ie, side shape) of some but not all components may be adjusted. For example, the pad 6 2, the terminal 6 8 and the cover 7 〇 can maintain the same side shape, and the routing lines 50, 6 4 and 6 6 have different routing configurations. 'Please refer to FIG. 5 to FIG. 5C for a schematic view of a semiconductor wafer according to a preferred embodiment of the present invention, and a schematic view of a semiconductor wafer assembly of the preferred embodiment of the present invention. And the present invention - a half of the preferred embodiment 39 201036212 The conductor chip assembly looks up SI. As shown in the figure, the assembly 100 of the present embodiment comprises a heat conducting plate 8A, a body 10 2 having a back contact, and solders 1〇4 and 106. The LED package 0 2 includes an LED chip 1 Q 8 , a pedestal 丄i 〇, a wire 丄丄 2, an electrical contact 114, a thermal contact 116, and a transparent encapsulation material 118. The electrode (not shown) of the LED chip 1 〇8 is connected to the conductive hole (not shown) in the pedestal 1 through the wire bonding, thereby the LED chip 1 〇 8 is electrically connected to the electrical contact i 丄 4; the LED wafer 〇 0 8 is disposed on the pedestal 丄i 透过 through a die bonding material (not shown), so that the LED chip 1 〇 8 thermally bonding and mechanically adhering to the pedestal of the susceptor to thermally bond the LED wafer 1 〇 8 to the thermal junction 1 16 . The base 1 10 is a ceramic block having high thermal conductivity, and the contact worker 4, 116 is covered on the back of the base 10 and protrudes from the back of the base i1. The LED package 1 〇 2 is disposed on the substrate 3 〇 and the heat sink 7 4 , electrically connected to the substrate 3 , and thermally coupled to the heat sink γ 4 ^ 〇 in detail, the LED The package 1 0 2 is disposed on the pad 6 2 and the cover 70, and is superposed on the stud 22, and is electrically connected to the substrate 30 via the solder 1〇4, and via the solder. 1 〇6 thermally connects to the heat sink 7 4 . For example, the solder 1〇4 is in contact with the solder pad 6 2 and the electrical contact 1 1 4 , and electrically and mechanically adheres the solder pad 6 2 and the electrical contact 1 1 4 , The LED chip 1 〇 8 is electrically connected to the terminal 6 8 °. The solder 106 is in contact with and is located between the cover 70 and the thermal contact 1 16 while being thermally coupled and mechanically Adhering to the cover 7 and the thermal contact 1 16 , the LED chip 108 is thermally coupled to the pedestal 2 201036212. The 塾6 6 has a recording/gold covered metal joint to make the fresh tin 丄 4 firmly combined, a the shape and size of the bonding pad 62 are matched with the electrical contact 丄i to improve the self-service board 3Q to The signal of the LED package lQ2=the sample ground, the cover body 7 is provided with the metal cover of the metal, so that the J(4)1〇6 is firmly combined' and the miscellaneous and size of the cover body 7 Q are matched with the hybrid joint 1 1 6 ' thereby improving the heat transfer from the LED package i Q 2 to the loose rail mount 74. ...' The stencil 1 0 8 and the splicing line 1 1 2 are embedded in the transparent encapsulating material 〇 1 18 . The transparent encapsulating material 118 is a solid-state electrically insulating protective plastic covering, which can provide environmental protection such as moisture-proof fishing and anti-particles for the wafer cassette 8 and the bonding tool 2 . Wei manufactures the above semiconductor wafer package 100, and can deposit - solder on the mat 6 2 and the cover 7 ,, and then place the joint worker 4 and the 6 6 6 Pad 6 2 and the cover 7 are over the solder on the top, which in turn reflows the solder to form subsequent solder kicks 104 and 1〇6. For example, the solder paste is selectively printed on the bonding pad 6 〇 2 and the cover 7 Q by screen printing, and then the -grassing head and the -automatic pattern recognition system are used to step by step. The LED sealing i Q 2 is placed on the heat conducting plate 80. The joints ii 4 and ii 6 are respectively placed on the solder paste 6 2 and the solder paste above the cover 7 by the gripping head of the reflow machine, and then the tin is heated to a relatively low temperature. (eg 190. 〇 reflow, then remove the heat source, wait for the solder paste to cool and solidify to form hardened solder 丄〇 4 and 丄〇 6. Or, can be used on &quot;Haizhi mat 6 2 and the cover 鳢7 0 Place the solder ball, and then place the contacts 1 14 and 116 on the solder ball of the soldering surface 2 and the cover body 7 respectively, and then heat the solder ball to reflow to form the solder i 〇 4 And ^ 〇 6. 41 201036212 The solder may initially be deposited on the heat conducting plate 80 or the LED package χ 2 via coating or printing or placement techniques, such that it is located on the heat conducting plate 8 〇 and the LED package 1 q 2 Between and reflow soldering. Solder can also be placed on the terminal 68 for use in the next layer. In addition, conductive adhesives (such as refining epoxy) or other connecting media can be used. Instead of the solder, the bonding pad 6 2, the terminal 68 and the connecting medium on the cover 70 do not have to be the same. Up to now, the semiconductor chip set 10 0 is a second-stage single crystal module. Please refer to FIG. 6A to FIG. 6C for a schematic cross-sectional view of a semiconductor wafer assembly according to another preferred embodiment of the present invention. A schematic view of a semiconductor wafer package in another preferred embodiment of the present invention, and a bottom view of a semiconductor wafer assembly according to another preferred embodiment of the present invention. As shown in the figure, in the embodiment, the LED package system has a side lead. The foot does not have a back contact. For the sake of brevity, the descriptions relating to the group 1000 (see Figure 5A to Figure 5C) apply to this embodiment and are incorporated herein. The same description is not repeated. Similarly, the components of the group of the embodiment are similar to those of the component i 0 〇, and the corresponding reference numerals are used, but the base number of the coding is changed from i 2 to 2 〇〇. For example, the 〇LED chip 208 corresponds to the LED chip 1 〇8, and the pedestal 2 i 对应 corresponds to the susceptor 110, and so on. The semiconductor wafer package 2 〇0 of the embodiment includes a heat conducting plate 80, an LED package 2 〇 2 with side pins and solder 2 〇 4 and 2 0 6 . The package 2 〇 2 includes an LED chip 2 〇 8 , a pedestal 2 10 , a wire 212 , a pin 214 , and a transparent encapsulation material 218 . The LED chip 208 is electrically connected to the LED chip 208 via the wire 2 1 2 . Pin 214. The back surface of the susceptor 210 includes a thermal contact surface 216. Further, the susceptor 210 is narrower than the pedestal 11 and has a lateral dimension and shape of the same as the thermal junction 116. 2 0 8 is disposed on the pedestal 2 1 经由 via a die bonding material (not shown), and the LED wafer 208 is thermally bonded to and mechanically adhered to the pedestal 2 1 0 , thereby The LED wafer 206 is thermally bonded to the thermal contact surface 2 16 . Therein, the pin 2 1 4 extends laterally from the base 11 , and the thermal contact surface 21 β faces downward. The LED package 2 0 2 is disposed on the substrate 3 〇 and the heat sink 7 4 , electrically connected to the substrate 3 , and thermally coupled to the heat sink 7 4 . In detail, the LED package 2 〇 2 is disposed on the solder pad 6 2 and the cover body 7 ' 'overlapped on the stud 2 2 , and is electrically connected to the substrate 30 via the solder 2 〇 4, and via the solder 2 0 6 is thermally coupled to the heat sink 7 4 . For example, the solder is in contact with the solder pad β 2 and the pin 214, and is electrically and mechanically adhered to the pad 6 2 and the pin 2, thereby The LED chip 206 is electrically connected to the terminal 68. Similarly, the solder 20 is in contact with and located between the cover 7 and the thermal contact surface 2 while thermally bonding and mechanically adhering to the cover 7 and the thermal contact surface 2 1 . Thereby, the LED chip 206 is thermally coupled to the susceptor 24. ° If the semiconductor wafer package 200 is to be fabricated, a solder may be placed on the solder fillet 6 2 and the cover body 70, and then on the solder joint 6 2 and the solder on the cover body 7 respectively. The pin 214 is placed with the thermal contact surface 216, which in turn reflows the solder to form solder 2〇4 and 2〇6. So far, the semiconductor wafer package 2 is a second-stage single crystal module. Referring to FIG. 7A to FIG. 7C, FIG. 7 is a schematic cross-sectional view showing a semiconductor wafer package according to still another preferred embodiment of the present invention, and a schematic view of a semiconductor wafer assembly according to still another preferred embodiment of the present invention. A schematic view of a semiconductor wafer package in accordance with still another preferred embodiment of the present invention. As shown in the figure, in the present embodiment, 43 201036212, the semiconductor device is a wafer instead of a package, and the wafer is disposed on the hot holder instead of the substrate. The wafer is overlapped with the bump. It is not the aforementioned substrate, and the wafer is galvanically-used to the front scale and utilized, and the solid crystal material is thermally bonded to the cover. Wherein the semiconductor wafer package comprises a heat conducting plate and a semiconductor wafer. The semiconductor wafer package 30 of the present embodiment comprises a heat conducting plate 80, an LED chip 306, a wire 340, a die bonding material 3〇6, and a transparent packaging material 308. The LED chip 3 〇 2 includes a top surface 2 and a wire bonding pad 314. Wherein the top surface 31 is an active surface and comprises the wire contact 3 1 4, and the bottom surface 3 1 2 is a thermal contact surface. The LED chip 306 is disposed on the heat sink 74, electrically connected to the substrate 3, and thermally coupled to the heat sink 74. In detail, the LED chip 306 is disposed on the cover 7 , and is located in the periphery of the cover 7 , and overlaps the stud 22 but does not overlap the substrate 3 〇. In addition, the LED chip 306 is electrically connected to the substrate 3 〇 ’ ′ via the bonding wire 306 and is thermally coupled via the die bonding material 306 and mechanically adhered to the heat sink 7 4 . For example, the bonding wire 300 is connected and electrically connected to the bonding pad 6 2 and the bonding pad 3 1 4 , thereby electrically connecting the LED chip 3 〇 2 to the terminal 68. Similarly, the die bonding material 306 is in contact with and located between the cover body 70 and the thermal contact surface 312, while being thermally bonded and mechanically adhered to the cover body 70 and the thermal contact surface 3 1 2 . This thermally bonds the led wafer 302 to the pedestal 24. The pad 6 2 is provided with a nickel/silver coated metal pad to securely bond with the wire 340 to improve the signal transmission from the substrate 30 to the LED chip 3 〇 2 . In addition, the shape of the cover body 70 and the size of the 201036212 are matched with the thermal contact surface 31, thereby improving the heat transfer from the LED 曰Η302 to the heat sink 7. The transparent encapsulating material 3 〇 8 is similar to the transparent encapsulating material 118. To manufacture the semiconductor wafer assembly 3 右, the LED chip 3 〇 2 can be disposed on the cover 7 by using the die bonding material 306, and then the bonding pad 6 2 and the bonding wire 3 4 bonding by wire bonding, and then forming the transparent = loading material 3 0 8 ^ 匕 for example, 'the IU crystal (four) 306 county - silver-containing epoxy resin paste having high thermal conductivity, and selectively printing by screen printing On the cover 7 ,, and then using a grab head and an automated pattern recognition system in a step-and-repeat manner = the LED wafer 300 is placed on the epoxy silver paste, and then the epoxy resin is heated The paste is allowed to harden at a relatively low temperature (e.g., 19 〇〇c) to complete the solid. The wire is 3; 〇4 is a gold wire, which is then connected to the wire 塾 6 2 and the wire 塾 3 1 4 by thermal ultrasonic wave, and finally the transparent packaging material 3 〇 8 is transferred and molded onto the structure. The LED chip 306 can be electrically connected to the C) through the plurality of bonding media. The bonding pad 6 2 ′ is thermally bonded or mechanically adhered to the heat sink 7 4 by a plurality of thermal adhesives and encapsulated in a plurality of packaging materials. So far, the semiconductor wafer package 3 is a first-order single crystal package. Referring to FIG. 8A1I to FIG. 8C, FIG. 8 is a schematic cross-sectional view of a sub-group of light source according to a preferred embodiment of the present invention, and a schematic view of a sub-group of light source sub-groups according to a preferred embodiment of the present invention, and A light source sub-assembly of a preferred embodiment of the invention. As shown in the figure, the light source sub-assembly 4 of the present embodiment includes a semiconductor wafer package 1 〇 〇 (see FIGS. 5A to 5C) and a heat sink 410. The heat dissipating device 4 〇 2 includes a thermal contact surface 4 0 贽 45 201036212 4 , a recording sheet 4 0 6 and a fan 4 0 8 » wherein the group 1 is disposed on the heat dissipating device 220 and mechanically coupled The heat sink 4 〇 2 is coupled, for example, by screws (not shown). Therefore, the susceptor 24 is clamped to and thermally coupled to the thermal contact surface 406, whereby the heat sink 7 4 is thermally coupled to the heat sink 4 〇 2 . The heat sink 74 can diffuse the heat generated by the LED chip 1 〇 8 and transfer the heat energy of the diffusion to the heat sink 4 〇 2, and the heat sink 410 then utilizes the sheet 4 〇 6 and the fan 4 0 8 This heat is distributed to the external environment. 〇 The above-mentioned light source sub-group 4 〇 0 is designed as a lamp holder (not shown) that can be replaced with a standard incandescent bulb. The lamp holder comprises the sub-assembly 4 〇 , a glass cover, a threaded base, a control board, a circuit and a casing. The sub-assembly 400, the control board and the circuit are wrapped in the outer casing. The line extends from the control panel and is soldered to the terminal 68. The glass cover and the threaded base respectively protrude from the ends of the casing. The glass cover exposes the LED chip 1 〇 8 which can be screwed into the light source socket, and the control board is electrically coupled to the terminal 68 through the line. The outer casing is a two-piece plastic shell divided into upper and lower jaws. The β-glass cover adheres and protrudes above the upper half of the casing, the threaded base is mixed and protrudes below the lower half of the casing, and the sub-assembly 400 and the control panel are disposed on the casing The lower half extends into the upper half of the outer casing. When operating, the threaded base transfers AC power from the light source socket to the control panel. The control panel converts the alternating current to a rectified direct current. On the one hand, the line delivers the rectified direct current to the terminal 68, and on the other hand grounds the other terminal 68. Therefore, the LED wafer process 8 can illuminate through the glass cover. The strong local thermal energy generated by the LED chip i 〇 8 flows into the heat sink 74 of the ψ 46 201036212 and is dispersed by the heat sink 74 to the heat sink 40 2 . The fins 406 in the heat sink 4 将 2 transfer heat energy to the air, and the fan 4 将 8 transmits the hot air through the long holes in the casing to be radially blown out into the peripheral environment. The semiconductor wafer package and the heat conducting plate described above are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with other embodiments or in combination with other embodiments in consideration of design and reliability. For example, a heat conducting plate having a plurality of protrusions to fit a plurality of LED packages, a part of the wires 7 2 thereof may include conductive holes 4 2 and 4 4 and a routing line 50, and a part of the wires 7 2 may be free of conductive holes 4 2 and 4 4 and the routing line 50 and do not extend through the dielectric layer 34. Similarly, the semiconductor component can be an LED package having a plurality of LED wafers and the substrate can include other wires to match the electrical connections of other electrical contacts on the package. Similarly, the semiconductor element and the cover may overlap the substrate and the underlying adhesive layer. The semiconductor element can use the heat sink alone or share the heat sink with other semiconductor elements. For example, a single semiconductor component may be disposed on the heat sink 0 or a plurality of semiconductor components may be disposed on the heat sink. For example, four small wafers arranged in a 2x2 array can be attached to the stud, and the substrate can include additional wires to accommodate the electrical connections of the wafers. This practice is far more economical than setting a tiny stud on each wafer. The semiconductor wafer can be optical or non-optical. For example, the wafer can be an LED, a solar cell, a power die or a controller wafer. Similarly, the semiconductor package can be an -LED package or a radio frequency (10) module. Thus, the semiconductor component can be a packaged or unpackaged optical or non-optical wafer. In addition, a plurality of connecting media can be used to connect, electrically connect and thermally couple the semi-navigation member mechanically 201036212 to the heat conducting plate, including by welding and using conductive and/or thermal conductive adhesives. The heat sink can quickly, efficiently and evenly and uniformly distribute the thermal energy generated by the semiconductor component to the next layer assembly without passing heat through the adhesive layer, the substrate or the heat conducting plate. In this way, an adhesive layer having a lower thermal conductivity can be used, thereby greatly reducing the cost. The magenta seat can be made of copper and includes an integrally formed stud and base 'and a metallurgical and thermally bonded cover without the stud, thereby improving reliability and reducing cost. The cover can be The pads are coplanar so as to be in a form-fitting, ship-and mechanical connection with the semi-conductor. In addition, the cover is tailor-made for the semiconductor component, and the wire holder can also be tailor-made for the lower-layer assembly, thereby forcibly bonding the thermal connection from the semiconductor component to the lower-layer can. For example, the stud may be in the - lateral plane and may be in the form of a square or a series in the lateral plane, the sides of the scorpion body being identical or similar in shape to the side of the de-conducting element. The heat sink can be electrically or electrically isolated from the semiconductor component and the substrate. For example, the routing line of the third conductive layer may extend between the substrate and the cover to be electrically connected to the cavity by a layer-thickness semiconductor element. Then, the heat sink can be grounded, and the (10) material conductor element is electrically connected to the ilk 〇. The stud can be deposited on the base or formed integrally with the base. For example, the stud can be formed into a single metal body with the pedestal body, or the stud and the pedestal can comprise a mono-metal body in its interface and other genus in other parts. The stud may comprise a flat top surface portion. For example, the post can be coplanar with the adhesive layer or the stud can be engraved after the adhesive layer is cured, —*. We can also choose to have a choice.

4S 201036212 The stud is formed in the stud to form a recess extending below its top surface. In the above-described case, the semiconductor element may be disposed on the stud and located in the recess, and the hitting may extend to the recessed conductor element, and then exit the recess and extend to the The solder pad 4 is a conductor element; it is a LED chip, and the recess can direct the LED light in the upward direction. The base can provide a mechanical support for the substrate. For example, the susceptor prevents the substrate from being deformed in the course of metal grinding, (9) placement, wire bonding, and difficult-to-package materials. Additionally, the back of the base may include a protrusion extending in the downward direction. For example, the bottom surface of the pedestal to form a lateral groove, and the lateral grooves are Korean. For example, the susceptor has a thickness of 700 microns and the depth of the grooves is 5 (8) microns, i.e., the fins have a height of 500 microns. The Korean sheets can increase the surface area of the susceptor. If the scales are exposed to the air rather than being disposed on a heat sink, the susceptibility of the susceptor via thermal convection can be enhanced. The cover may be formed by various deposition techniques before, during, or after the formation of the pad and/or the terminal, including electroplating, electroless plating, 蒸发 evaporation, and sputtering. Or multilayer structure. The cover body can be made of the same metal material as the protrusion. In addition, the cover may extend across the through hole and reach the substrate or be maintained within the circumference of the through hole. Thus, the cover can contact or be spaced from the substrate. In either of the above cases, the cover extends laterally from the top of the stud in the lateral direction. The adhesive layer provides a strong mechanical bond between the heat sink and the substrate. For example, the adhesive layer can fill the space between the heat sink and the substrate, the adhesive layer can be located in the space, and the adhesive layer can be a non-porous structure with uniformly distributed bonding wires. The adhesive layer can also absorb the mismatch caused by thermal expansion between the heat sink and the substrate. In addition, the adhesive layer can be a low cost dielectric and does not require high thermal conductivity. Furthermore, the adhesive layer is not easily delaminated. We can adjust the thickness of the adhesive layer so that the adhesive layer substantially fills the gap and allows all of the adhesive to be substantially within the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error. The substrate provides flexible multilayer signal routing in the X and gamma directions to provide a complex routing pattern. The pad and the terminal can be used in a variety of sealing forms depending on the needs of the semiconductor component and the next layer. Further, the substrate can be a low-lying laminate structure without high thermal conductivity. The tan pad and the top surface of the cover may be coplanar, so that the soldering between the semiconductor component and the heat conducting plate can be strengthened by controlling the degree of collapse of the solder ball. The pad, the terminal and the routing line above the dielectric layer can be formed by various deposition techniques before or after the adhesive layer, including electroplating, electroless ore coating, evaporation, and ejection Other technologies form a single layer or a multilayer structure. For example, the first and second conductive layers may be formed on the substrate when the substrate is not yet placed on the adhesive layer.表面 The surface treatment process on the contact surface can be performed before or after the formation of the pad and the terminal. For example, the coating layer can be deposited on the third conductive layer, and then the pad is defined with the patterned photoresist layer and etched to impart a pattern to the coating layer. The $ wire may contain additional materials, materials, conductive holes and road sisters, and the driven 7G piece' and may be differently turned. The wire may be a germanium layer, a power layer or a ground layer, depending on the purpose of soldering the corresponding semiconductor component. The wire may also contain various conductive metals such as steel, gold, brocade, silver, handle, tin, mixtures thereof, and alloys thereof. The ideal composition depends on the nature of the externally connected medium, and 50 201036212 depends on design and reliability considerations. A person skilled in the art should understand that the copper in the semiconductor wafer package may be pure copper, but is usually a copper-based alloy such as steel, zirconium (999% copper), copper, silver. · Town (997% • 'copper) and copper-tinu (99.7% steel) to improve mechanical properties such as tensile strength and ductility. Preferably, the cover, the solder resist green lacquer, the coated contact and the second conductive layer are provided in the general case, but may be omitted in some embodiments. 4 The working format of the heat-conducting plate can be either one or two heat-conducting plates, 彳1 manufacturing design ° towel: for example, 'single-heating plate can be made separately. Alternatively, a plurality of thermally conductive plates can be fabricated in batches using a single-metal plate, a single-adhesive layer, a single-substrate, and a single-shield green paint, and then separated. Similarly, for each heat-conducting plate in the same batch, we can also use _ single-metal plate, single-adhesive layer, single substrate and single anti-welding, transfer the same miscellaneous record to make spicy sub-single-casting body to make Xiao Zhi Heat sink and wire. For example, a plurality of grooves may be engraved on the metal plate to form the pedestal and the plurality of columns, and then an unfixed wire layer corresponding to the opening D of the corresponding column may be disposed on the pedestal. Extending each of the studs through the pair of thin ports; then the substrate (which has a single-first conductive layer, a single-dielectric layer, a through hole corresponding to the studs, and a peach tree under the The sigh (four) material is disposed on the adhesive layer, and each of the protrusions extends through a corresponding one, for example, and enters a corresponding through hole, and then the base and the substrate are combined with each other by the pressing table. '(10) causes Na to enter the layer and enter the gap between the substrate and the substrate; then cure the adhesive layer', and then grind the pillars, the adhesive layer and the first conductive layer to form a top And then the third conductive layer is coated on the pillars, the adhesive layer and the first conductive layer; then the first 201036212 and the third conductive layer are formed to form corresponding pads and the pads a terminal, simultaneously etching the second conductive layer to form a cover corresponding to the stud; and then placing the solder resist green paint on the junction Constructing a pattern on the solder resist green lacquer to expose the pads, the terminals and the covers; and then the pedestal, the pads, the terminals, and the cover The contact surface is subjected to coating treatment of electroplating; finally, the base, the substrate, the adhesive layer 'and the solder resist green paint' are separated at appropriate positions on the peripheral edge of the heat conducting plates to separate the individual heat conducting plates from each other . The operational format of the semiconductor wafer package can be a single group or a plurality of groups, depending on the manufacturing design. For example, a single set can be manufactured separately. Alternatively, a plurality of groups may be simultaneously manufactured in batches, and then the heat conducting plates may be separated one by one; similarly, a plurality of semiconductor elements may be electrically connected, thermally coupled, and mechanically coupled to each of batches. A heat conducting plate. For example, a plurality of solder paste portions may be separately deposited on the plurality of solder pads and the cover body, and then the plurality of LED package bodies are respectively placed on the solder paste portions, and then the solder paste portions are simultaneously heated to be returned. Welding, hardening and forming a plurality of solder joints, and then separating the heat conducting plates. In another example, a plurality of solid crystal materials Ο may be separately deposited on the plurality of covers, and then the plurality of wafers are respectively placed on the solid crystal materials, and then the solid crystal materials are simultaneously heated. It is hardened and formed into a plurality of solid crystals, and then the wafers are wire bonded to the corresponding pads, and then corresponding packaging materials are formed on the wafers and the wires, and finally the heat conducting plates are separated one by one. We can separate the heat conducting plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements are placed on the flat plate, and then the plurality of semiconductor wafer assemblies constituted by the flat plates are separated one by one. Alternatively, a plurality of heat conducting plate batches can be made into a flat plate, and then 52 201036212: a heat conducting plate is cut into a plurality of heat conducting strips, and then a plurality of + conductor readings (four) are placed on the heat conducting strips. Finally, each of the semi-conducting _ group _ is separated into healthy. In addition: when cutting the guide f, mechanical cutting, laser cutting, bifurcation or other applicable techniques can be used. The manufacturing process of the present case is highly applicable, and is unique and combines various maturities. Electrical connection, hot surface and surface bonding technology. The manufacturing process of this case can be carried out without expensive tools. As a result, manufacturing processes can significantly increase the yield, yield, performance and cost effectiveness of traditional packaging technologies. Furthermore, the group _ _ _ 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶The term "adjacent" as used herein means that the elements are integrally formed, i.e., formed as a single face; or as an overview, that is, without each other. For example, the studs are adjacent, and the pedestal&apos; is independent of the addition or reduction method when forming the studs. ο “Overlap” – means the upper part and extends within the perimeter of a lower element. "Overlap" includes extending within, outside or within the periphery of the rim. In the example t, the semiconductor device is overlapped with the stud, because an imaginary vertical line is the same, and the semiconductor element and the stud are penetrated, regardless of whether there is another imaginary vertical line between the semiconductor element and the stud. The through element (such as the cover), and whether or not there is another imaginary vertical line, only extends through the semiconductor element without penetrating the stud (ie, outside the periphery of the stud). Similarly, the adhesive layer overlaps the pedestal and is overlapped with the terminal by the pad while the stud is superposed on the pedestal. Likewise, the stud is superposed on the base and is located within its circumference. In addition, 'overlap' is synonymous with "below" and "overlap" is "same". The term "contact" means direct contact "for example, the dielectric layer contacts the first and second conductive layers but does not contact the stud or the pedestal. η 53 201036212 Covering means to completely cover from above, from below and/or from the side. For example, the base covers the tenon from below, but the stud does not cover the base from above. · The "layer" word contains a layer with or without a pattern. For example, when the substrate is disposed on the adhesive layer, the first conductive layer may be a blank unpatterned plate and the second conductive layer may be a circuit pattern having spaced wires; when the semiconductor component is disposed on the heat dissipation When seated, the first conductive layer can be a patterned circuit. Further, the "layer" may comprise a plurality of superposed layers. The term "weld" as used in connection with the substrate refers to a bonded region for connecting and/or bonding an external connection medium (such as solder or wire), and the external connection medium causes the pad and the semiconductor device Reach an electrical connection. The term "terminal", when used in conjunction with the substrate, refers to a bonded area that can be contacted and/or connected to an externally connected medium (such as solder or wire) that is interconnected to an external device ( Such as -_ board or one of the wires connected to it). The term "cover" when used in conjunction with the heat sink refers to a contact area for connecting and 0/or engaging an external connection medium (such as a viscous or thermally conductive adhesive) that is used by the external connection medium. The body is connected to the semiconductor component. "Open" and "through hole" are the same as the through hole. For example, when the stud is inserted into the opening of the hybrid layer, it is exposed to the adhesive layer in an upward direction. Similarly, when the stud is inserted into the through hole of the substrate, the stud is exposed upward toward the substrate. The term "insertion" means the relative movement between components. For example, "inserting the tenon into the S-through hole" includes: the stud is fixed and moved by the substrate toward the base; the acoustic substrate is fixed and moved by the stud to the substrate; and the stud is Ψ 54 201036212 The substrate is placed against each other. For another example, "inserting (or extending into) the through hole" includes: the through hole penetrating (passing in and out) the through hole; and the protruding post is inserted but not penetrated (penetrating but not wearing) Out) the through hole. The phrase "together with each other" also refers to the relative movement between components. For example, "the pedestal and the substrate abut each other" includes: the susceptor is fixed and moved from the substrate to the pedestal, the substrate is fixed and moved by the pedestal to the substrate; and the pedestal and the pedestal The substrates are close to each other. The term "set in" encompasses contact with a single or multiple support members. For example, the semiconductor component is disposed on the heat sink, whether the semiconductor component is actually in contact with the heat sink or is separated from the heat sink by a solid crystal material. Similarly, the semiconductor component is disposed on the heat sink, whether the semiconductor component is disposed only on the heat sink or simultaneously disposed on the heat sink and the substrate. 0 “Adhesive layer·•• in the gap The term means the adhesive layer located in the gap. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer within the gap extends and spans the dielectric layer. Similarly, "the adhesive layer contacts the gap between the pillar and the dielectric layer" means that the adhesive layer in the gap contacts and the pillar between the inner sidewall of the gap Between the dielectric layers of the outer sidewall of the notch. The term "upper" is intended to mean an upward extension and includes contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, the studs extend above the base while abutting, overlapping the base and projecting from the base. Similarly, the stud extends above the dielectric layer even if the stud does not abut or overlap the dielectric layer. The word "below" is intended to mean a downward extension and includes contiguous and non-contiguous elements with * 55 201036212 and overlapping and non-overlapping components. For example, the pedestal extends below the stud, adjacent to the stud, is overlapped by the stud, and protrudes from the stud. Similarly, the stud is extended below the dielectric layer, even if the stud is not adjacent to the dielectric layer or __ is overlapped by the dielectric layer. The vertical direction of the so-called "upward" and "downward" does not depend on the vertical direction. In the orientation of the semiconductor wafer package (or the heat conducting plate), those skilled in the art can easily understand the direction in which they actually refer. For example, the stud is extending vertically above the pedestal in an upward direction and the adhesive layer extends vertically below the tamper in a downward direction, whether the set is inverted and/or is disposed at a It has nothing to do with the heat sink. Similarly, the base extends "laterally" from the stud along a lateral plane. This is independent of whether the set is inverted, rotated or tilted. Therefore, the upward and downward directions are opposite to each other and perpendicular to the side direction, and further, the lateral alignment of the elements (4) is coplanar with each other in the lateral direction of the _vertical_upward and downward directions. The semiconductor wafer package of the present invention has a number of advantages. The reliability of this group is south, the price is flat and it is very suitable for mass production. This group is especially suitable for high-power semiconductor components such as LED packaged bodies and large-sized semiconductor wafers that are prone to high heat JL and require excellent heat dissipation to operate efficiently and reliably. The embodiments described herein are illustrative, and the elements or steps of the present invention are either simplified or omitted to avoid obscuring the features of the present invention. Similarly, in the drawings, the repeated or non-essential elements and reference numerals in the drawings may be omitted. Those skilled in the art will readily appreciate various changes and modifications in the embodiments described herein. For example, the aforementioned raw materials, dimensions, shapes, sizes, steps, and steps are all fine. The above-mentioned persons can engage in scale change, machine and equalization skills without departing from the spirit and fineness of the invention. The fine gamma of the present invention is defined in detail. In summary, the present invention is a semiconductor wafer package, which can effectively improve various shortcomings. The reliability of the group is high, the price is flat, and it is very suitable for mass production, especially for a semiconductor package such as an LED package. High-power semiconductor elements that are easy to produce high-efficiency and require excellent heat dissipation to operate effectively and reliably, can greatly increase production, yield, efficiency and cost-effectiveness, and meet environmental protection requirements, thereby making the invention more productive. The more practical and more user-friendly tenants need to meet the requirements of the invention patent application and file a patent application according to law. However, the above is only a preferred embodiment of the present invention, and the axis of the present invention cannot be limited by this; therefore, it is simple to make a special use of the genomic θ θ Equivalent changes and (4) should still belong to the present invention. [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view showing a structure of a preferred embodiment of the present invention. Fig. 1B is a schematic cross-sectional view showing the structure of the stud and the pedestal in a preferred embodiment of the present invention. Fig. 1c is a diagram showing the formation of a stud and a pedestal in a preferred embodiment of the present invention. Fig. 1D is a schematic cross-sectional view showing a structure in which a stud and a pedestal are fabricated in a preferred embodiment of the present invention. Figure 1E is a top plan view of the i-th D. The first F11 ’ is a bottom view of the figure D. 57 201036212 Figure 2A is a cross-sectional view showing the structure of an adhesive layer in a preferred embodiment of the present invention. Fig. 2B is a schematic cross-sectional view showing the structure of the adhesive layer in a preferred embodiment. Figure 2C is a top plan view of the 2nd θ diagram. Figure 2D is a bottom view of the 2nd figure. Fig. 3 is a cross-sectional view showing the structure of a substrate in a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a cross-sectional view showing the structure of a preferred embodiment of the present invention. Figure 3C is a schematic cross-sectional view showing the structure of a substrate produced in a preferred embodiment of the present invention. Port 3D is a schematic view of the structure of the substrate produced in the preferred embodiment. Fig. 3 is a schematic cross-sectional view showing the structure of a substrate in a preferred embodiment of the present invention. 〇 3F ® ' is a schematic cross-sectional view of the structure of the substrate of the preferred actual wipes. Fig. 3G is a schematic cross-sectional view showing the structure of the substrate in the preferred embodiment of the present invention. • Figure 3 is a top view of the 3rd Gi|. Figure 3I is a bottom view of Figure 3G. Fig. 4A is a cross-sectional view showing the structure of a heat conducting plate in a preferred embodiment of the present invention. 'Block 4B' is the structure of the present invention - a preferred embodiment for making a thermally conductive plate. 58 201036212 is not intended to be a cross-sectional view. Figure 4C Figure's invention - the structure of her three-shot structure. The cross-sectional view of the fourth D @ ′′ (4)—the structure of the better-off toweling inspection. Fig. 4E is a cross-sectional view showing the structure of the present invention - a preferred solid side cap as a heat conducting plate. Figure 4F is a cross-sectional view of a structure for fabricating a heat conducting plate in the preferred embodiment of the present invention. Fig. 4G is a schematic view of the structure of the preferred embodiment of the present invention. Fig. 4 is a cross-sectional view of the structure of the preferred embodiment of the present invention. Figure 4 is a structure of the present invention - preferably a fine-grained hot plate. Figure 4J is a cross-sectional view showing the structure of a heat conducting plate in the preferred embodiment of the present invention. Fig. 4 is a cross-sectional view showing the structure of a heat conducting plate in the preferred embodiment of the present invention. Fig. 4L is a cross-sectional view showing the structure of the heat conducting plate in a preferred embodiment of the present invention. Figure 4 is a top plan view of Figure 4L. Figure 4 is a bottom view of Figure 4L. Figure 5 is a cross-sectional view showing a semiconductor wafer package in accordance with a preferred embodiment of the present invention. 59 201036212 Figure 5B is a top plan view of a semiconductor wafer assembly of the preferred embodiment of the invention. Figure 5C is a bottom plan view of the semiconductor wafer assembly of the present invention. Fig. 6A is a view of the semiconductor wafer package of the preferred embodiment of the present invention. FIG. 6B is a view of the semiconductor wafer assembly of the present invention.

D. Fig. 6C is a view of a semiconductor wafer package in accordance with another preferred embodiment of the present invention. Fig. 7A is a view showing a semiconductor wafer package in accordance with still another preferred embodiment of the present invention. Fig. 7B is a perspective view of a semiconductor wafer package in accordance with still another preferred embodiment of the present invention. Figure 7C is a schematic elevational view of a semiconductor wafer package in accordance with still another preferred embodiment of the present invention. Figure 8A is a schematic cross-sectional view of a sub-group of light sources in accordance with a preferred embodiment of the present invention. Figure 8B is a top plan view of a sub-group of light sources in accordance with a preferred embodiment of the present invention. Figure 8C is a bottom plan view of a sub-group of light sources in accordance with a preferred embodiment of the present invention. [Main component symbol description] Metal plate 1 0 60 201036212 Surface 1 2, 1 4 Patterned money etched layer 16, 4 8 , 5 8 Fully covered etch stop layer 18, 4 6 , 6 0 Groove 2 0 convex Column 2 2 pedestal 2 4 adhesive layer 2 6 opening 2 8 substrate 3 0 first conductive layer 32 dielectric layer 3 4 second conductive layer 3 6 hole 3 8, 4 0 conductive hole 4 2, 44 routing line 50, 64 , 66 through hole 5 2 notch 5 4 third conductive layer 56 solder pad 6 2 terminal 6 8 cover body 7 0 wire 7 2 heat sink 7 4 solder resist green paint 76 covered joint 7 8 201036212 heat conducting plate 8 0 semiconductor wafer set Body 100, 200, 300 LED package 1 〇 2, 2 0 2 Solder 104, 106, 204, 206 LED chip 1 〇 8, 2 0 8 , 3 0 2 pedestal 110, 2 1 0 wire 112, 212, 3 04 Electrical contact 114 Thermal contact 116 Transparent encapsulation material 118, 218, 3 0 8 Pin 2 14 Thermal contact surface 216, 40 4 Solid crystal material 3 0 6 Top surface 3 1 底面 Bottom surface 3 1 2 Wire bonding pad 314 Light source Subgroup 4 0 0 Heat sink 4 0 2 Fin 4 0 6 Fan 4 0 8 62

Claims (1)

201036212 VII. Patent application scope: 1. A semiconductor wafer assembly, comprising: an adhesive layer having at least one opening; a heat sink having at least one protrusion and a base, wherein the protrusion is adjacent to the The pedestal extends in the upward-upward direction above the pedestal, and the pedestal extends below the stud in a downward direction opposite the upward direction and in a direction perpendicular to the upward and downward directions Extending laterally from the stud; a substrate disposed on the adhesive layer and extending over the pedestal, the Ο comprising at least a solder fillet, a terminal routing line, first and second conductive holes, and a dielectric a layer, wherein the pad and the terminal extend over the dielectric layer, the routing line extends below the dielectric layer and is embedded in the adhesive layer, and each of the vias extends through the dielectric layer The routing line is composed of the first conductive hole, the 'road peak and the second conductive hole—a guiding path between the _ sub-sub-sections, and a through-hole extends through the substrate; a semiconductor s piece is located at the convex Above the column, overlapping the stud, and The semiconductor element is electrically connected to the terminal, and the semiconductor element is thermally coupled to the protruding post to be thermally coupled to the base; and the protruding post extends through the opening into the through hole Above the dielectric layer, the pedestal extends over the semiconductor component, the adhesive layer and the substrate, wherein the adhesive layer is disposed on the pedestal and extends into the through hole above the pedestal a gap between the stud and the substrate extending in the gap = between the dielectric layer and between the stud and the dielectric layer, between the pedestal and the dielectric layer, and The base is between the routing line. 2. The semiconductor wafer package according to claim 1, wherein the semiconductor component is an LED package comprising an LED crystal. The semiconductor chip assembly of the first aspect of the invention, wherein the semiconductor component is an LED package including an LED chip, electrically connected to the pad via a solder, and via A second solder is thermally coupled to the stud. The semiconductor wafer package according to the invention of claim 2, wherein the adhesive layer contacts the stud and the dielectric layer in the notch, and contacts the pedestal and the slab outside the notch Electrical layer and the routing line. 5. The semiconductor wafer package according to claim 1, wherein the C) layer is under the surface of the substrate, and is substantially covered in the hemp direction and surrounds the stud. 6. The semiconductor wafer package of claim 1, wherein the adhesive layer fills the gap and a space between the pedestal and the substrate. The semiconductor wafer package according to the invention of claim 2, wherein the 'adhesive layer is limited to a space between the heat sink and the substrate. The semiconductor wafer package of claim i, wherein the adhesive layer extends to a peripheral edge of the group. The semiconductor wafer package according to claim 1, wherein the stud is integrally formed with the pedestal system. The stud and the adhesive layer are coplanar above the dielectric layer. The semiconductor wafer assembly of claim 1, wherein the stud is a flat-topped taper having a diameter that decreases upward from a county seat to a flat top of the stud. 12. The semiconductor wafer package according to claim 1, wherein the pedestal covers the semiconductor element, the stud, the substrate, and the adhesive layer from below, and extends to the group The outer edge. The semiconductor wafer package according to the invention, wherein the substrate is separated from the pillar and the base. The semiconductor wafer assembly according to the above-mentioned claim, wherein the heat sink includes a cover body located above the top of one of the protrusions, adjacent to the top of the protrusion and covered from above. At the same time, the side faces extend laterally from the top of the stud. The semiconductor wafer package according to claim 4, wherein the cover system is rectangular or square, and the top of the protrusion is circular. 16. A semiconductor wafer assembly, comprising: an adhesive layer having at least one opening; - a heat sink portion comprising at least a - stud and a base and a cover, wherein the stud is adjacent to the base Forming a body with the base, and the post extends above the county seat in an upward direction, and the base is thermally coupled to the cover, the base is oriented in an opposite direction to the upward direction a lower direction extending below the ^ post and extending laterally from the stud in a direction perpendicular to the upward and downward directions. The cover is located above the blue of the stud, adjacent to the top of the stud and from Covering the upper side and extending from the lateral direction of the protruding column; the substrate is disposed on the adhesive layer and extending over the base, and comprises at least a first-and second conductive layer, a first a second conductive via and a dielectric layer '3 of the first conductive layer contacting the dielectric layer and extending over the dielectric layer'. The second conductive contact contacts the dielectric layer JL and extends below the dielectric layer Buried in the adhesive layer, and having a solder pad and a terminal included therein a selected portion of the electrical layer, the solder tab and the terminal contact the dielectric layer and extending over the dielectric layer at 65 201036212, and having a routing line included in a portion of the second conductive layer 'the routing line contact The dielectric layer extends under the dielectric layer and the conductive holes are hard to reach and extend through the first (four) and the dielectric layer of the route, and sequentially, the first conductive hole, the routing line, and the first Two conductive holes are formed - a guide hole between the terminals of the solder fillet, and - a through hole penetrates the substrate; a semiconductor element is positioned on the cover, superposed on the stud, electrically connected to the pad, and (4) electrically connected to the terminal (10), and the semiconductor element is thermally coupled to the cover to be thermally coupled to the cover The pedestal; and the protruding post extends through the opening into the through hole to reach the dielectric layer, the pedestal extends over the semiconductor component, the adhesive layer and the substrate, and covers the semiconductor component from below The pillar, the cover, the substrate and the adhesive layer, wherein the adhesive layer is disposed on the base and extends into the through hole above the base and is located between the pillar and the substrate a gap extending across the dielectric layer in the gap and between the pillar and the dielectric layer in the gap, and between the pedestal and the dielectric layer outside the gap And between the S-base and the second conductive layer, and the adhesive layer covers the substrate from below and covers and surrounds the protruding column along the lateral directions. The semiconductor chip assembly of claim 16, wherein the semiconductor component is an LED package including an LED chip, electrically connected to the pad via a first solder, and via A second solder is thermally coupled to the cover body. The semiconductor wafer package according to claim 16 wherein the semi-conductor component is a semi-conducting chip and is electrically connected via a wire. Bonded to the pad 'and thermally bonded to the cover via a die bond material. The semiconductor wafer assembly of claim 16, wherein the substrate and the stud and the pedestal, the rib adhesive layer fill the gap and the pedestal and the substrate One of the spaces. 2G. The semiconductor wafer package according to claim 16, wherein the 35-pillar is round and the cover is rectangular or square, and the cover is a flat-topped cone. The cylindrical shape has a diameter that decreases upward from the base to the cover system. A semiconductor wafer assembly comprising: an adhesive layer having at least one opening; - a heat sink comprising at least a - stud and a base and a cover, wherein the stud is adjacent to the base The base is formed integrally with the base, and the post extends above the base in an upward direction, and the base is thermally coupled to the cover, the base is opposite to the upward direction Extending downwardly from the island column in a downward direction and extending laterally from the stud in a direction perpendicular to the upward and downward directions, the cover system is located above the top of the stud, adjacent to the top of the stud Covering from above, and extending laterally from the top of the stud in the lateral direction; the substrate is disposed on the adhesive layer and extends above the base, and is closed with the *Hello post and the base And comprising at least a first conductive layer and a second conductive via and a dielectric layer, wherein the first conductive layer contacts the dielectric layer and extends over the dielectric layer ±, the second conductive Layer contact with the dielectric layer 1 extending below the dielectric layer and embedded in the layer Shooting, and having a soldered-and-terminal included in a selected portion of the first conductive layer, the terminal and the terminal contacting the dielectric layer and extending over the dielectric layer, and having a routing line included therein a second conductive portion, the selected portion, the routing line contacting the dielectric layer 67 201036212 j extending below the dielectric layer, and the conductive holes contacting and extending through the dielectric between the first conductive layer and the routing line a layer, and sequentially consisting of the first conductive hole, the routing line and the second conductive hole - a conductive path between the solder pad and the terminal, and a through hole extending through the substrate; a semiconductor piece, the system position The cover body is superposed on the protruding post and electrically connected to the rotating pad, and is connected to the base by a (four) connection, and the semiconductor element is thermally coupled to the cover body to be thermally coupled to the base; and The pillars extend through the through hole to reach the via hole to reach the dielectric layer, and the bump and the adhesive layer are coplanar above the dielectric layer, and the pedestal extends to the semiconductor component and Under the floor and the board, and from below Covering the semiconductor component, the stud, the cover, the substrate and the adhesive layer, and simultaneously supporting the substrate and extending to a peripheral edge of the group, wherein the adhesive layer is disposed on the base And extending over the pedestal into the through hole - a gap between the stud and the substrate, and extending across the dielectric layer in the notch and being interposed between the stud and the stud Between the dielectric layers, outside the contact and between the susceptor and the electrical layer, and between the pedestal and the second conductive layer, and the adhesive layer covers the substrate from below, and Covering and surrounding the studs in the lateral directions while extending to the peripheral edges of the assembly. The semiconductor wafer package according to claim 21, wherein the conductor 7G is - the LED package containing the LED chip is electrically connected to the pad via a first solder. And connected to the cover via a second solder heat. The semiconductor wafer package according to claim 2, wherein the semiconductor component is a two-semiconductor wafer, which is disposed on the cover and electrically connected to the solder via a wire of 68 201036212. The semiconductor wafer assembly according to claim 21, wherein the substrate is attached to the pillar and the pedestal, and the pedestal is thermally bonded to the cover by a solid crystal material. Separating, the adhesive layer fills the gap and a space between the base and the substrate, and is confined in a space between the heat sink and the substrate. 2 5. The semiconductor wafer package according to the scope of claim 2, wherein The top of the stud is circular, and the cover is rectangular or square, and the cover system and the pad and the terminal ride on the plane above the dielectric layer, and the cover is a flat lion The diameter of the hearing from the base to the listening system is upward. 6 i The semiconductor wafer package according to claim 2, wherein the material of the heat sink is copper. , 69