TW201218468A - Semiconductor chip assembly with bump/base heat spreader and cavity in bump - Google Patents

Abstract

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and an adhesive. The heat spreader includes a bump, a base and a flange. The conductive trace includes a pad and a terminal. The semiconductor device extends into a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Description

201218468 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor wafer package, and more particularly to a semiconductor wafer package comprising a semiconductor component, a wire, an adhesive layer and a heat sink Production method. [Prior Art] Semiconductor components such as packaged and unpackaged semiconductor wafers can provide applications for south voltage, high frequency, and high performance; these applications require very high power for performing special functions. The higher the power, the more heat is generated in the semiconductor components. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is reduced, which further increases heat generation.

Semiconductor components are prone to performance degradation and shortened service life at high temperatures, and may even fail immediately. High heat not only affects wafer performance, but may also cause thermal stress on the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be quickly and efficiently dissipated to ensure the efficiency and reliability of its operation. The strip high thermal conductivity path typically conducts and dissipates thermal energy to a region that is larger than the die pad where the wafer or wafer is located. Light-emitting diodes (LEDs) have recently become the alternative source of white-ray light source, Dengguang light and light source. LED彳 provides high energy efficiency and low cost for medical, military, signage, No. 1, aviation, marine, vehicle, portable equipment, commercial and residential lighting applications (4). For example, ^ can provide light sources for fixtures, flashlights, headlights, searchlights, switch lights, and displays.

High-powered wafers in LEDs also produce high-brightness wafers while still producing 201218468

A lot of heat. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened life, and immediate failure. In addition, LED has its limitations in terms of heat dissipation, which in turn affects its light output and reliability. Therefore, LEDs highlight the market's need for high-power chips with good heat dissipation. 〇 led packages typically include —LED曰曰曰#, a pedestal, electrical contacts, and a hot junction. The pedestal is thermally coupled to the LED a 曰曰 > {and used to support the LED crystal > {. The electrical contacts are electrically connected to the anode and cathode of the coffee chip. The hot junction is connected to the i LED曰曰曰# via the pedestal & the lower carrier can be sufficiently dissipated to prevent overheating of the LED chip. The industry is actively investing in the development of high-power chip packages and thermal boards with various design and manufacturing technologies to meet the performance needs in this extremely cost-competitive environment. A plastic ball grid array (PBGA) package encloses a wafer and a laminate substrate in a stencil, and then adheres to a printed circuit board (PCB) with solder balls. The laminate substrate comprises a dielectric layer typically composed of glass fibers. The heat generated by the wafer can be transferred to the solder ball via the plastic and dielectric layers and then to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the PBGA has poor heat dissipation. A quad flat no-lead (QFN) package places the wafer on a copper die pad that is soldered to the printed circuit board. The heat generated by the wafer can be transferred to the I3 brush board via the die pad. 'However, due to the limited routing capability of its leadframe interposer', the #QFN package cannot be applied to high input/output (1/〇) chips or passive components. . 201218468 Thermally conductive plates provide electrical routing, thermal management and mechanical support for semiconductor components. The heat conducting board usually comprises a substrate for signal routing, a heat sink or heat sink for providing heat removal, a solder pad electrically connectable to the semiconductor component, and a terminal connectable to the next layer. The board can be a laminated structure with a single layer of multilayer routing circuitry and one or more dielectric layers. The heat sink can be a metal base, a metal block or a buried metal layer. The heat conducting plate engages the next layer of the body. For example, the next layer of the body can be a lamp holder with a printed circuit board and a heat sink. In this example, a led package system is mounted on the heat conducting plate, and the heat conducting plate is mounted on the heat sink, and the heat conducting plate/heat sink sub-group and the printed circuit board are mounted in the lamp holder. In addition, the heat conducting plate is electrically coupled to the printed circuit board via wires. The substrate directs the electrical signal from the printed circuit board to the LED package, and the heat sink radiates and transfers the thermal energy of the LED package to the heat sink. Thus, the heat shield provides an important thermal path for the LED wafer. U.S. Patent No. 6,5,7,1,2, issued to J.S., issued to U.S. Patent No. 6, the disclosure of which is incorporated herein by reference. A square or rectangular heat sink is adhered to the central opening sidewall and thus bonded to the substrate. The upper and lower conductive layers are attached to the top and bottom of the substrate, and are electrically connected to each other through the electric ore guiding holes penetrating the substrate. The wafer system is disposed on the heat slug and bonded to the upper conductive layer, the package material is patterned on the wafer, and the lower conductive layer is provided with solder balls. At the time of manufacture, the substrate was originally a B-mge 201218468 resin film placed on the lower conductive layer. The heat dissipating block is inserted in the central opening so as to be located on the lower conductive layer: and spaced apart from the substrate by a gap. The upper conductive layer is disposed on the substrate. After the lower conductive layer is heated and combined with each other, the resin is dazzled and flows into the middle curing layer. The lower conductive layer forms a pattern, thereby forming a circuit wiring on the substrate, and causing the resin to flash. Appeared on the heat sink block. Then remove the resin flash to expose the heat sink. Finally, the wafer is placed on the heat slug and bonded and packaged.

Therefore, the heat generated by the wafer can be transferred to the printed circuit board by the heat sink block, ', and the manual operation of placing the heat sink in the central opening is extremely labor intensive and costly. Moreover, since the mounting tolerance of the lateral direction is small, the heat dissipating block is not easily positioned in the central opening, which causes a gap between the substrate and the heat radiating block and uneven wiring. As a result, the substrate is only partially attached to the heat sink & the substrate cannot be obtained from the heat sink block and is easily delaminated. In addition, the chemical etching solution used to remove part of the conductive layer to reveal the resin flash will also remove some of the heat-dissipating block that is not covered by the resin flash, so that the heat-dissipating block is not flat and difficult to combine, and finally the yield of the group is lowered. Insufficient reliability and high cost. U.S. Patent No. 6,528,882 to Ding et al. discloses a high heat-dissipating ball grid array package having a substrate comprising a metal core layer and a wafer disposed in a die pad region on the top surface of the metal core layer. An insulating layer is formed on the underside of the metal core layer. The blind hole penetrates the insulating layer through the metal core layer, and the hole is filled with a heat-dissipating solder ball. Further, a solder ball corresponding to the heat-dissipating solder ball is disposed on the substrate. The thermal energy generated by the wafer can flow through the metal core to the heat sink balls and then to the printed circuit board. However, the 201218468 edge layer sandwiched between the metal core layer and the printed circuit board limits the heat flow to the printed circuit board. U.S. Patent No. 6,670,219 to the disclosure of the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire portion A substrate having a central opening is disposed on the ground plate through an adhesive layer having a central opening. A chip is mounted on the heat sink in a recess formed by a central opening of the ground plate, and the substrate is provided with a solder ball. However, since the solder ball is tied to the substrate, the heat sink cannot contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection instead of heat conduction, thereby greatly reducing the heat dissipation φ effect. U.S. Pat. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate. A wafer system is disposed on the pillar portion and wire bonded to the substrate, and a packaging material is molded on the wafer, and the substrate is provided with a solder ball. The post extends through the window opening and supports the substrate by a wide substrate, with the solder balls being located between the wide substrate and the peripheral edge of the substrate. The thermal energy generated by the wafer can be transferred to the wide substrate via the post and then to the printed circuit board. However, since a space for accommodating the solder balls must be left on the wide substrate, the wide substrate protrudes below the substrate only at a position corresponding to the center window and the innermost solder ball. As a result, the substrate is unbalanced during the manufacturing process, and the valley is easily shaken and bent, which in turn leads to difficulty in mounting the wafer, bonding the wire, and molding the packaging material. In addition, the wide substrate may be bent due to the molding of the encapsulating material, and once the solder ball collapses, the 201218468 may prevent the package from being soldered to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high.

A illuminating device assembly is disclosed in U.S. Patent Application Publication No. 2007/0267642, wherein the pedestal-shaped pedestal comprises a substrate, a protrusion, and an insulating layer having a through hole, and the insulating layer is With electrical contacts. A packaging system having a through hole and a transparent upper cover is disposed on the electrical contact. - The LED & film is placed on the protrusion and connected to the substrate by wire bonding. The protruding portion abuts the substrate and extends through the insulating layer and the through hole in the package into the package. An insulating layer is disposed on the substrate, and an electrical contact is disposed on the insulating layer. A package system is disposed on the electrical contacts and spaced apart from the insulating layer. The thermal energy generated by the wafer can be transmitted to the substrate via the protruding portion, thereby reaching the heat sink. However, the electrical contacts are not easily disposed on the insulating layer, and are difficult to be electrically connected to the lower-layer assembly, and cannot provide multi-layer routing. . Conventional packages and thermally conductive plates have major drawbacks. For example, an electrically insulating material having a low thermal conductivity such as an epoxy resin limits the heat dissipation effect. However, an electrically insulating material having a high thermal conductivity such as an epoxy resin filled with ceramic or tantalum carbide has low adhesion. The disadvantage of high production cost. The electrically insulating material may be delaminated by heat during the manufacturing process or at the beginning of the operation. If the substrate is a single-layer t-channel system, the routing capability is limited, but if the substrate is a multi-layer circuit system, the excessively thick dielectric layer will reduce the heat dissipation effect; in addition, the 'previous case technology has insufficient heat sink performance, excessive volume or It is not easy to connect to the lower-layer group and other issues. The manufacturing process of the prior art is also not suitable for low-cost mass production operations. In view of the development of 201218468 and the related limitations of the existing high-power semiconductor package and heat-conducting board, the industry needs a cost-effective, reliable, suitable for quantity i, multi-function & flexible adjustment of signal routing and excellent A heat dissipating semiconductor wafer package. [CLOSURE OF THE INVENTION] Cross-Reference to Related Applications This application is a continuation of the US Patent Application No. 12/616,773 filed on November 11, 2009, and is also filed on the 11th of the 9th Part of the continuation of the US special shots No. 12/616,775, the contents of both cases are incorporated herein by reference. This application also advocates May 2010! In the case of the US Provisional Patent Application No. 61/350,036, the US Provisional Patent Application No. 61/350,036, which was filed on June 1st, The content is also incorporated herein by reference. Before the opening of November 2009, u曰 filed an application for the mountain τ «Monthly US Patent Application No. 12/616,773 and US Patent No. 12/616,775, which was filed on the next day of the next year. The application cases are all 9 H in 2009, . The 12/557 of the month of the filing of the month of the month, the part of the continuation case of the 54G US special account is 2_U.S. U.S. No. 12/557 541 Part of the continuation of the patent application. The first US patent application No. 12/557 540, which was issued by the sergeant and the singer, was opened on September 11, 2009, and was opened in 2009. 9曰n ' ' 1Λ/月11曰US Patent Application No. /557,54! is 2〇〇9 on the 18th of the month; ψThe part of the π/Shouchuan No. US patent φ request is extended: 12/4〇6,51〇 U.S. Patent Application No.... Dijon), 7th, 7th, 10th, 18th, 18th, s, s, s, s, s, s, s, s, s, s, s, s, s, s, Priority in the provisional patent, the US Provisional Patent Application No. 61/071,072, filed on April 11, 2008, the priority of the US provisional patent No. 61/064,748 filed on March 25, G8 The contents of the above-mentioned cases (4) are incorporated in this article. The US patent application No. 12/557,540, filed before 2_ "月n曰, and the previous 9-year-old 9 gu

The application for US Treasury No. 2/557,541 of the application also claims the priority of the US Provisional Patent Application No. 61/15, No. 98, filed on February 9 of the following year, the contents of which are incorporated by reference. Into this article. The present invention provides a semiconductor wafer package body component, a heat sink, a wire and an adhesive layer. The heat sink includes the bump, a base and a flange layer. The wire includes a pad and a terminal. The semiconductor component extends into a recess of the bump, is electrically connected to the wire, and is thermally coupled to the bump. The bump extends from the base into an opening of the adhesive layer, the base extending from the bump in a direction opposite to the recess, the flange layer being attached to the entrance of the recess from the side of the bump Extend out. The wire is located outside of the recess and provides a signal path between the pad and the terminal. According to one aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink and a wire. The adhesive layer has at least one opening. The heat sink includes a bump, a base and a flange layer, wherein (1) the bump abuts the base and the flange layer, and is integrated with the flange layer, the bump is along the base Extending in a first vertical direction and extending from the 201218468 flange layer in a second vertical direction opposite the first vertical direction; (ii) the base extends from the bump in the second vertical direction and from a bump extending laterally in a side direction perpendicular to the vertical direction; (Hi) the flange layer extending laterally from the bump and maintaining a distance from the base; and (iv) the bump having a side a recess facing the first vertical direction, the recess being covered by the bump in the second vertical direction, the bump also separating the recess and the base, and further, the _, shai recess is in the convex There is an entrance at the edge. The wire includes a pad and a terminal. The hexagonal semiconductor component extends into the recess and is electrically connected to the solder pad ′ to electrically connect to the terminal; the semiconductor component is also thermally coupled to the bump ′ to be thermally coupled to the pedestal. The adhesive layer contacts the bump, the base and the flange layer and is located between the base and the flange layer while extending laterally from the projection to the terminal or past the terminal. The wire is located outside the pocket. The bump extends into the opening and covers the semiconductor component in the second vertical direction. The pocket extends into the opening. According to another aspect of the present invention, a semiconductor wafer package includes at least

I-a semiconductor component, an adhesive layer, a heat sink, a substrate and a wire. The adhesive layer has at least one opening. The heat sink includes a bump, a base and a flange layer, wherein (1) the bump abuts the base and the flange layer, and is integrated with the flange layer, the bump is along the base a first vertical direction extending 'and extending from the flange layer in a second perpendicular direction opposite the first vertical direction; (ii) the pedestal extending from the bump in the second vertical direction, and Covering the bump in a vertical direction while extending from the side of the bump in a side direction perpendicular to the vertical direction; (iii) the flange layer from the side of the bump

S 12 201218468 white k stretches and maintains a distance from the base; and (iv) the bump has a recess facing the first vertical direction, the recess being covered by the bump in the second vertical direction The protrusion also separates the recess from the base, and further, the recess is provided with an inlet at the flange layer. The substrate includes a dielectric layer and through holes extend through the substrate. The wire includes a pad and a terminal. The semiconductor component extends into the recess and is electrically connected to the solder pad to electrically connect to the solder terminal; the semiconductor component is also thermally coupled to the bump and thermally coupled to the solder. The adhesive layer contacts the pedestal, the flange layer and the dielectric layer, and is located between the bump and the dielectric layer, between the flange layer and the dielectric layer, and between the pedestal and the pedestal The adhesive layer between the flange layers also extends laterally from the bump to the peripheral edge of the assembly. The wire is located outside the pocket. The bump extends into the opening and the via and covers the semiconductor component in the second vertical direction. The pocket extends into the opening and the through hole. "Haizhen hot seat can be composed of the bump, the base and the flange layer. The heat sink can also consist essentially of copper, aluminum or copper/nickel/aluminum alloy. The heat sink can also be composed of an inner steel, aluminum or copper/nickel/aluminum alloy core and covered contacts, wherein the covered contacts are composed of gold, silver and/or recording. Regardless of the composition, the heat sink can provide heat dissipation to spread the heat of the semiconductor component to the next layer. " a semiconductor device can be disposed on the bump, overlap the bump without overlapping the substrate or the wire, and electrically connect to the pad through a wire extending outside the cavity, and pass through a A die bond material located within the pocket is thermally bonded to the bump 35. For example, the body element can extend inside and outside the pocket 13 201218468 and the line can be located outside the a hole. Alternatively, the semiconductor component can be located within the recess and the wire can extend inside and outside the recess. Regardless of the use of any mode, the semiconductor component extends into and is located within the n-edge of the recess, the wire extending within and outside the periphery of the pocket. The 〆Semiconductor 7C device can be a stencil or an unpackaged semiconductor wafer. For example, the semiconductor component can be - containing a wafer "(4) package -. Alternatively, the semiconductor component may be such as [the semiconductor wafer of the ED wafer - the edge layer may be in contact with the substrate between the bump and the substrate" and the dielectric layer And extending across the dielectric layer in the gap and contacting the pedestal, the dielectric layer and the terminal outside the gap. The grading layer may also cover the portion of the susceptor outside the bump in the first-vertical direction and cover the substrate in the first-vertical direction, and cover and surround the bump in the lateral direction. The adhesive layer may also be isomorphously coated on the sidewall of the bump, a surface portion of the base and a surface of the dielectric layer, wherein the surface portion of the base abuts the bump and is laterally from the bump Extending while facing the first vertical direction, the surface of the dielectric layer also faces the first vertical direction. The adhesive layer may also fill the space between the bump and the dielectric layer, the space between the pedestal and the flange layer, and the space between the pedestal and the substrate. The adhesive layer may extend laterally from the bump to the terminal or over the terminal. For example, the adhesive layer and the terminal may extend to a peripheral edge of the set; in this case, the adhesive layer is from the bump Extend laterally to the terminal. Or ' the adhesive layer may extend to the peripheral edge of the group, and the terminal is

S 14 201218468 Group. The peripheral edge of the sea or the like maintains a distance; in this case, the adhesive layer extends laterally from the bump and passes over the terminal.

The adhesive layer may pass through an imaginary horizontal line between the bump and the dielectric layer, an imaginary horizontal line between the bump and a covered perforation, an imaginary horizontal line between the bump and the pedestal, the bump and the An imaginary vertical line between the pedestals, an imaginary vertical line between the pads and the dielectric layer, an imaginary vertical line between the flange layer and the dielectric layer, and a vertical line between the flange layer and the pedestal, An imaginary line between the bump and the terminal, an imaginary line between the flange layer and the terminal, an imaginary line between the pad and the pedestal or one of the solder joint and the terminal Imaginary line. The bump can be in % with the flange layer body. In the case of the mouth, the bump and the flange layer may be a single-metal germanium or a single metal body in the interface thereof, wherein the single-metal it may be _. The thickness of the bump may also be greater than the thickness of the pedestal. Additionally, the bump and the adhesive layer may be coplanar at the base and the flange layer. The I bump may also contact the adhesive layer but maintain a distance from the dielectric layer while extending into the opening and the through hole. The bump 彳 includes - a first bent corner adjacent to the base t and a second bend angle adjacent to the flange layer. The bumps may also have a stamped special irregular thickness. In addition, the diameter of the bump at the flange layer may be greater than the diameter of the s-bump at the base. For example, the bump may be in the form of a flat-topped cone: or a pyramid having a diameter that increases from the base along the first-perpendicular direction toward the two-edge layer. For another example, the bump may include a third bent corner, and the diameter of the bump is increased from the base along the first vertical direction to the: the three corners of the bend. The three bent corners extend along the vertical direction of the -15th 201218468 to the portion of the flange layer, and the diameter remains unchanged. Further, the vertical position of the third bent corner may be between the opposite major surfaces of the semiconductor component. The bump can also be a cylindrical shape that is always fixed. The bumps also provide a recessed wafer holder and a reflector for the semiconductor component. The diameter of the entrance of the pocket may be greater than the diameter of the bottom of the pocket. For example, the pocket may be in the form of a flat-topped cone or pyramid having a diameter that increases from its bottom plate toward the entrance of the first vertical direction. Alternatively, the diameter of the recess may be increased from the bottom plate along the first vertical direction to the third f-fold corner, and the recess extends from the third material corner along the first vertical direction to the recess The diameter of the part of the entrance remains unchanged. The recess can also be a cylindrical shape having a fixed diameter. The entrance of the recessed six and the bottom plate may also have a circumference of a circle, a square or a rectangle. The recess may also have a shape conforming to the bump extending into the opening and the through hole and extending across the majority of the bump in the vertical and lateral directions. The i-base can have a uniform thickness and maintain a distance from the conductive layer and the dielectric layer. For example, the pedestal may occupy the same spatial extent as the bump' or extend laterally from the bump to the adhesive layer without extending to the conductive layer or the dielectric layer. The pedestal may have a first thick ridge adjacent to the bump and a second thickness greater than the first thickness adjacent to the dielectric layer, and the pedestal may also have a face-to-face Two flat surfaces in the vertical direction. The susceptor may be connected to the adhesive layer and the portion away from the dielectric layer may have the first thickness, and the pedestal may have the second portion adjacent to the adhesive layer and the dielectric layer. thickness. The pedestal may also contact the adhesive layer and the 201218468 5 dielectric layer to cover the flange layer in the second vertical direction, laterally extending beyond the flange layer, the substrate and the adhesive layer, and Keep the distance between the edges of the group. The surface area of the pedestal in the lateral plane can be large (iv) the surface area of the bump and the flange layer in a lateral plane, and more than twice the surface area of the block in the lateral plane. The thickness of the flange layer may be greater than the thickness of the base. The flange layer may also contact the adhesive layer, maintain a distance from the dielectric layer, and extend to the adhesive layer

The dielectric layer is along the outer side in the first-vertical direction. The flange layer can also have a circular, square or rectangular perimeter. The flange layer and the pad may have the same thickness and are co-located on the surface of the one side I in the t-th direction. The pedestal and the terminal may have the same thickness adjacent to each other. The thickness of the pedestal adjacent to the ridge may not be greater than the thickness of the _ sub, and the pedestal and the terminal may be co-located with the first vertical On the surface of the direction. The substrate can contact the pedestal and maintain a distance from the bump, the flange layer, and the pad. The substrate can also be a laminated structure. * The wire may comprise a routing wire located on the conductive circuit between the soldering pad and the submount and extending along the outer side of the adhesive layer and the dielectric layer in the first vertical direction. Similarly, the wire can include a through-hole that is located on the conductive path between the pad and the terminal and extends through the adhesive layer and the dielectric layer. For example, the solder bump may extend on the outer side of the adhesive layer and the dielectric layer along the first vertical direction. The terminal may extend on the outer side of the adhesive layer and the dielectric layer along the second vertical direction. Through the adhesive layer and the dielectric layer 'and electrically connected to the solder 17 201218468 pad and the terminal. Similarly, the routing line and the routing line may extend along the first and the outer sides of the adhesive layer and the dielectric layer, and the terminal may extend between the adhesive layer and the dielectric layer along the second vertical direction. On the outer side, the covered through hole may penetrate the adhesive layer and the dielectric layer 'and electrically connect the routing line and the terminal. The wire can contact the adhesive layer and the dielectric layer and hold the distance. For example, the solder bump may contact the adhesive layer but be in contact with the dielectric layer, the terminal may contact the dielectric layer but maintain a distance from the adhesive layer, the covered via may contact and extend through the adhesive layer and the dielectric layer The electrical layer thus provides vertical signal routing between the pad and the terminal. Similarly, the bonding pad and the routing line can contact the adhesive layer but maintain a distance from the dielectric layer, and the terminal can contact the dielectric layer but maintain a distance from the adhesive layer. The covered through hole can contact and extend through the adhesive layer. The layer and the dielectric layer provide horizontal signal routing between the bond pad and the broken via and provide vertical signal routing between the routing line and the terminal. Further, the coated perforations may extend to a peripheral edge of one of the groups or be spaced from the peripheral edge of the set. The wire may consist of the pad, the terminal and the covered perforation. The spring line can also be composed of copper. The wire may also consist of an inner copper core and a covered joint of the surface layer, wherein the covered joints are composed of gold, silver and/or nickel. The wire can provide signal routing between the pad and the terminal, regardless of the composition. The pad can serve as an electrical contact of the semiconductor component, the terminal can serve as an electrical contact of the next layer, and the pad and the terminal can provide a signal between the semiconductor component and the next layer routing. 5 18 201218468 The bump, the base, the flange layer, the pad, the terminal and the covered perforation may be made of the same metal. For example, the bump, the pedestal, the bead layer 'the pad, the terminal and the capped via may comprise a gold, silver or nickel surface layer and an inner copper core, and are predominantly copper. In this example, a covered contact may include a gold or silver surface layer and an inner nickel layer, wherein the inner recording layer contacts and is located between the surface layer and the inner copper core; or, the covered contact may A nickel surface layer contacting the inner copper core is included. this

In addition, the heat sink can include a copper core shared by the bump, the base and the flange layer, and the wire can include a copper core shared by the solder pad and the terminal and the through hole. For example, the heat sink and the wire may comprise a gold, silver or nickel surface layer and an inner copper core, and are primarily copper. In this example, the heat sink τ includes a covered contact which is disposed on the bump and the edge layer and maintains a distance from the base; the heat sink may include another covered joint. Further, the pedestal is spaced apart from the bump and the flange layer; and the wire may include a covered contact layer disposed on the mat, the ridge and the overlying perforation. The assembly may include a step of extending the material into the recessed six and covering the conductor 7L in a first vertical direction. The encapsulating material may also be located in the driving pocket or extend in the pocket. The lateral spacing of the encapsulating material may be limited by the recess, and the enclosing material, the bucket or the Sx encapsulating material is from the recess. Extending sideways. The package material is rough » The recess ^ contacts the semiconductor component while filling the remaining pockets in the pocket. The encapsulating material within the recess can also extend into the opening and the through hole/port. The side of the sorrow and the slanting side of the south of the certificate extend across most of the bump. For example, the encapsulating material may be a packaging material for changing color of 19 201218468, which contacts an LED chip, a wire, a die bonding material and the bump in the cavity, and the wire and the base The adhesive layer is spaced from the dielectric layer, and the encapsulating material converts the blue light emitted by the LED chip into white light. In this case, the group may include a transparent encapsulating material that contacts the encapsulating material for converting color, the flange layer, the bonding pad and the bonding wire outside the cavity, and the LED chip, The solid crystal material, the susceptor and the terminal maintain a distance 'and cover the first vertical direction - the encapsulating material for converting color, the flange layer and the wire. Further, the encapsulating material for converting color may comprise a phthalocyanine resin and a phosphor, and the ruthenium encapsulating material may comprise a phthalocyanine resin but no phosphor. The group can be a first or second stage single crystal or polycrystalline device. For example, the group can be a first level package containing a single wafer or multiple wafers. Alternatively, the assembly may be a second level module comprising a single LED package or a plurality of LED packages, wherein each of the LED packages may comprise a single lED wafer or a multi-leaf LED wafer. The invention provides a method for fabricating a semiconductor wafer package, comprising: providing a bump and an overhanging platform; and providing an adhesive layer on the overhanging platform; the step comprising inserting the bump into the adhesive layer An opening; a conductive layer is disposed on the adhesive layer, the step of aligning the bump with a through hole of the conductive layer; causing the adhesive layer to flow between the bump and the conductive layer; curing the adhesive layer; Providing a wire comprising a pad, a selected portion of the terminal extension 0; providing a heat sink, the heat sink base 3, the bump-base and a selected portion of the overhanging platform; and providing a semiconductor 70 pieces on the bump 'where the semiconductor component extends into the bump

S 20 201218468 a recess; electrically connecting the semiconductor component to the wire; and thermally bonding the semiconductor component to the heat sink. According to one aspect of the invention, a method of fabricating a semiconductor wafer package includes: (1) providing a bump, an overhanging platform, an adhesive layer, and a conductive layer, wherein (a) the bump has a recess 'The recess is facing in a first vertical direction, and an inlet is provided at the overhanging platform, the protrusion abuts and is integrated with the overhanging platform, and further, the bump is along the first and the first a second vertical direction opposite to the vertical direction extending perpendicularly from the overhanging platform while extending into one of the openings of the adhesive layer and aligning with one of the through holes of the conductive layer, (b) the overhanging platform is perpendicular to the same The side direction of the vertical direction extends from the side of the bump. ((c) the adhesive layer is disposed on the overhanging platform, between the overhanging platform and the conductive layer, and is not cured, and further, (d The conductive layer is not placed on the far adhesive layer, (2) the adhesive layer flows into the through hole in the second vertical direction, a gap between the bump and the conductive layer; (3) curing the adhesive a layer; (4) providing a wire comprising a pad, a terminal, and the a selected portion of the extension platform 'the selected portion is spaced from the bump; (5) providing a heat sink comprising the bump, a base and a flange layer, wherein (a) the bump Adjacent to the base and extending perpendicularly from the base along the first vertical direction' (b) the base extends from the bump in the second vertical direction, and (c) the flange layer includes the a selected portion of the overhanging platform 'the selected portion abuts the bump and is integrated with it, and protrudes from the side of the bump; (6) a semiconductor component is disposed on the bump, wherein the semiconductor component extends into the The four holes; (7) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the terminal; and (8) thermally bonding 21 201218468 the semiconductor component to the bump, thereby thermally connecting The semiconductor component is to the pedestal. According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a bump and an overhanging platform, wherein the bump has a recess, the recess facing a first a vertical direction, and an inlet is formed at the overhanging platform, the protrusion abuts and is integrated with the overhanging platform, and further, the protrusion is in a second vertical direction opposite to the first vertical direction The overhanging platform extends vertically, and the overhanging platform extends from the side of the protrusion in a direction perpendicular to the vertical direction; (2) providing an adhesive layer, wherein an opening extends through the adhesive layer; 3) providing a conductive layer, wherein a through hole extends through the conductive layer; (4) providing the adhesive layer on the overhanging platform, wherein the bump extends into the opening; (5) providing the conductive layer to the adhesive layer The step of aligning the bump with the through hole is such that the adhesive layer is between the overhanging platform and the conductive layer and is not cured; (6) heating and melting the adhesive layer; (7) making the outer layer Extending the platform and the conductive layer against each other, thereby Moving in the second vertical direction in the through hole while applying pressure to the molten adhesive layer between the overhanging platform and the conductive layer, the pressure forcing the molten adhesive layer to flow into the through hole in the second vertical direction; a gap between the bump and the conductive layer; (8) heat curing the molten adhesive layer, thereby mechanically adhering the bump and the overhanging platform to the conductive layer; (9) providing a wire 'the wire includes a solder a selected portion of the overhanging platform and the conductive layer, the selected portions are spaced apart from the bump; (10) providing a heat sink, the heat sink including the bump and a base And a flange layer, wherein (a) the bump abuts the base and extends perpendicularly from the base in 201218468 along the first vertical direction, and (b) the base is from the second vertical direction Extending vertically and extending laterally from the bump, and (c) the flange layer includes a selected portion of the overhanging platform, the selected portion abuts the bump and is integral therewith, and from the side of the bump Extend out; (丨) set a semiconductor component to the convex Wherein the semiconductor component extends into the recess; (丨2) electrically connects the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the terminal; and (13) thermally bonding the semiconductor component to the And arranging the conductive layer to the pedestal. And disposed on the adhesive layer such that the conductive layer contacts and is interposed between the adhesive layer and the carrier, and then after the adhesive layer is cured, the carrier is first removed, and then the wire is provided. Alternatively, the conductive layer is disposed. The layer may include: disposing the conductive layer together with a dielectric layer on the adhesive layer to keep the conductive layer away from the adhesive layer, and contacting the dielectric layer between the conductive layer and the adhesive layer According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a bump, an overhanging platform, an adhesive layer, and a substrate, wherein (a) the bump Have one a hole, the recess is facing in a first vertical direction, and an inlet is provided at the overhanging platform, the protrusion abuts and is integrated with the overhanging platform, and further, the bump is along the first a second vertical direction opposite to the vertical direction extending perpendicularly from the overhanging platform while extending into one of the openings of the adhesive layer and aligned with a through hole of the substrate, (b) the overhanging platform is perpendicular to the same The lateral direction of the vertical direction extends from the side of the bump 23 201218468, and (C) the adhesive layer is disposed on the overhanging platform between the overhanging platform and the substrate, and is not cured, in addition, d) the substrate is disposed on the adhesive layer, wherein the substrate comprises a conductive layer and a dielectric layer, the dielectric layer is located between the conductive layer and the adhesive layer; (2) the adhesive layer is along the a second vertical direction flows into the through hole, a gap between the bump and the conductive layer; (3) curing the adhesive layer; (4) providing a wire, the wire comprising a solder pad, a terminal, a covered perforation, a selected portion of the overhanging platform and one of the conductive layers a fixed portion, wherein the selected portions are adjacent to the covered through hole and spaced apart from the bump, and the covered through hole is a conductive path between the pad and the terminal; (5) providing a heat sink, the heat sink comprising The bump, a base and a flange layer, wherein (a) the bump abuts the base and extends perpendicularly from the base in the first-vertical direction, and (8) the base covers the second vertical direction The bump extends laterally from the bump and includes a selected portion of the conductive layer, the selected portion is spaced from the wire, and (4) the flange layer includes a selected portion of the overhanging platform, The selected portion abuts the bump and is integrally formed with it while extending from the side of the bump; (6) providing a semiconductor component on the bump into which the semiconductor component extends; (7) electrically connecting the semiconductor component To the solder tab, thereby electrically connecting the semiconductor component to the terminal; and (6) thermally bonding the semiconductor component to the bump, thereby thermally bonding the semiconductor component to the pedestal. According to still another aspect of the present invention, a method of fabricating a semiconductor crystal 0 includes: (1) providing a bump and an overhanging platform, wherein the convex portion has a recessed surface that faces the first vertical direction And having a population at the outrigger, the bump abutting the outreaching platform and forming a

S

24 201218468 , in addition, a bump is perpendicularly extended from the outer perpendicular σ to the second perpendicular direction opposite to the first perpendicular direction, and the overhanging platform is convex from the side perpendicular to the vertical direction The block side is extended (7) to provide an adhesive layer 'one of the openings extending through the adhesive layer; (3) providing a substrate comprising a conductive layer and a dielectric layer, wherein the through hole extends through the substrate (4) Layered on the 4 outsole platform ±, this step includes inserting the bump into the opening 'where 4 bumps extend through the opening; (5) placing the substrate on the adhesive layer'. This step includes inserting the bump into the opening The bump extends into the via hole to form a layer between the outer layer and the dielectric layer and is not cured, and the dielectric layer is located between the conductive layer and the adhesive layer; 6) = thermally melting the layer; (7) causing the material stretching platform and the substrate to abut each other, thereby moving the bump in the second vertical direction in the through hole, and simultaneously between the overhanging platform and the substrate Applying pressure to the molten adhesive layer, the pressure forcing the glazing adhesive layer; a vertical direction into the through hole and a gap between the bump and the substrate; (8) heating and curing the molten adhesive layer, thereby mechanically adhering the bead stud and the overhanging platform to the substrate; providing a covered perforation The covered through hole extends through the overhanging platform, the adhesive layer, the dielectric layer and the conductive layer; (10) providing a solder pad, a terminal, a base and a flange layer; (11) providing a wire The wire includes the bonding pad, the terminal covered aperture, a selected portion of the overhanging platform, and a selected portion of the conductive layer, wherein the selected portions each abut the covered via and maintain a distance from the bump And the coated via is a conductive path between the pad and the terminal; (12) providing a heat sink, the heat sink comprising the bump 'the base and the flange layer' wherein (a) the bump is adjacent The pedestal extends vertically from the pedestal along the first vertical direction 25 201218468 '(b) the pedestal covers the bump in the second vertical direction and extends from the side of the bump along the lateral direction Out, including one of the conductive layers selected The selected portion is spaced from the wire, and the (C) edge flange layer includes a selected portion of the overhanging platform that abuts the bump and is integral therewith while extending laterally from the bump And (13) providing a semiconductor component on the bump, wherein the semiconductor component extends into the recess; (14) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to The terminal; and (15) thermally bonding the semiconductor component to

The bumps thereby thermally bond the semiconductor component to the pedestal. Providing the bump can include: mechanically stamping a metal plate. The bump and the recess in the bump are formed on the metal plate. In this case, the bump (four) metal plate is the stamped portion, and the overhanging platform is an unpunched portion of the metal plate.

A flaw may include: providing a collapse of an uncured epoxy resin. Flowing the adhesive layer may include: refining the uncured epoxy resin; and pressing the uncured epoxy resin between the overhanging platform and the substrate. Curing the layer may comprise curing the melted uncured epoxy resin. Providing the pad can include: curing the : selected portion of the platform. The removing may include: humidifying the overhanging platform with a patterned patterned resist layer such that the pad includes a selected portion of the overhanging platform. , ·, ^ 2 The flange layer may comprise: after curing the (four) layer, the selected portion of the flange. The removing may include: utilizing - a definable: a patterned etched resist layer of the edge layer to wet the overhanging platform;

26 S 201218468 ' so that the flange layer contains the selected portion of the overhanging platform. Providing the terminal can include removing a selected portion of the conductive layer after curing the delamination layer. The removing may include: wet-chemically aligning the conductive layer with a patterned (four) resistive layer of a determinable terminal such that the terminal includes a selected portion of the conductive layer. Providing the susceptor may include removing the selected material of the conductive layer after curing the adhesive layer. The removing may include: (4) - the base may be defined

The patterned (four) resist layer wet chemically seals the conductive layer such that the pedestal includes a selected portion of the conductive layer. Providing the solder fillet and the flange layer can include removing a selected portion of the overhang + table using a patterned button etch resist layer defining the solder fillet and the flange layer. In this manner, the pad and the flange layer can be formed simultaneously using the same patterned etch stop layer in the same wet-method lithography step. Likewise, providing the terminal and the pedestal can include: defining a selected portion of the terminal and the patterned side resist layer of the pedestal to remove the conductive layer. In this way, the terminal and the susceptor can be simultaneously formed by the same patterning etch resist layer in the same-wet chemical (four) step. The contact pad can be formed before, after, or during the formation of the terminal. The pad and the terminal can utilize different (four) chemical etching layers simultaneously with the same thirst. The formation is formed by using different patterned etching resist layers. Similarly, the flange layer can be formed by the person before, after, or at the formation of the susceptor. Therefore, the flange layer and the susceptor can be simultaneously formed by using different patterned etch resist layers in the same wet-wetting process, or by using patterned etch resist layers of different 27 201218468. Similarly, the solder bump, the terminal, the flange layer and the pedestal may be formed simultaneously or sequentially. Providing the terminal may include: after curing the adhesive layer, grinding the bump, the adhesive layer and the conductive layer '俾 such that the bump, the adhesive layer and the conductive layer are laterally facing the first vertical direction The surfaces are laterally flush with each other; then the selected portion of the conductive layer is removed using a patterned etch stop layer defining the terminal such that the terminal includes a selected portion of the conductive layer. The grinding may comprise grinding the adhesive layer without grinding the bump; then grinding the bump, the adhesive layer and the conductive layer. The removing may include wet chemical etching of the conductive layer using a patterned etch stop layer of the terminal. Providing the bonding pad may include: depositing a conductive metal on the bump and the overhanging platform to form a coating layer after the polishing is completed; and then removing selected portions of the overhanging platform and the covering layer to enable the The pad includes selected portions of both the overhanging platform and the cover layer. Depositing the conductive metal to form the coating layer may include: disposing a thin coating layer on the bump and the overhanging platform in an electroless plating manner; and then plating a thick coating layer on the _S-thick coating On the floor. The removing may include wet chemical etching the overhanging platform and the coating layer with a patterned #etching layer defining the bonding pad. Providing the terminal may include: depositing a conductive metal on the bump, the adhesive layer and the conductive layer to form a coating layer after the polishing is completed; and then removing selected portions of the conductive layer and the coating layer, so that The terminal includes selected portions of both the conductive layer and the cover layer. Depositing a conductive metal to shape

S 28 201218468 The coating layer may include: disposing a thin coating layer on the bump, the adhesive layer and the conductive layer in an electroless plating manner; and then plating a thick coating layer on the thin coating layer by electroplating The removal may include: wet chemical etching the conductive layer and the coating layer with a patterned etch stop layer defining the terminal. Providing the wire can include: providing the pad, the terminal, and a through-hole [wherein the covered via is located on a conductive path between the pad and the terminal. The pad and the terminal may be formed first, and the covered via is formed, and the covered via extends through the overhanging platform, the adhesive layer, the dielectric layer and the conductive layer. Providing the bonding pad, the flange layer and the coated perforation may include: after curing the adhesive layer, drilling through the overhanging platform, the dielectric layer, the adhesive layer and the S-conducting layer to form a hole; Depositing a conductive layer on the bump, the overhanging platform, the dielectric layer, the adhesive layer and the conductive layer and the hole to form a coating layer, wherein the covering layer forms a first covering layer, the first covering layer The layer covers the bump and the overhanging platform in the first vertical direction while covering the covered perforation in the hole; and then forming a pattern on the first covering layer to define the bonding pad and the flange layer Etching the resist layer; etching the overhanging platform and the first cladding layer to form a pattern defined by the patterned etch stop layer by using a etched etch resist layer; and removing the patterned etch stop layer. Providing the pedestal, the terminal and the coated perforation may include: after curing the adhesive layer, drilling through the overhanging platform, the dielectric layer, the adhesive layer and the conductive layer to form a hole; and then extending the protrusion a conductive layer is deposited on the platform, the dielectric layer, the adhesive layer, and the conductive layer to form a coating layer, wherein the coating layer forms a second coating layer, and the second coating layer is wider than the second layer Covering the bump, the adhesive layer and the conductive layer in a vertical direction while covering the covered perforation in the hole; and then forming a patterned touch on the second coating layer a patterned resist layer; the patterned resistive layer is used to engrave the conductive layer and the second cladding layer to form a pattern defined by the patterned etch stop layer; and the patterned etch stop layer is removed

Providing the susceptor, the flange layer, the bonding pad, the terminal and the covering J hole may include: after curing the adhesive layer, drilling through the overhanging platform, the electrical layer, the adhesive layer and the conductive layer Forming a hole; then depositing a conductive metal on the protrusion, the overhanging platform, the dielectric layer, the adhesive layer, the conductive layer, and the hole to form a __coated layer, wherein the coated layer is shaped by a moon a first covering layer and a second covering layer, the first covering layer covers the bump and the overhanging platform in the first writing direction, and the second covering layer covers the bump in the second vertical direction, Adhesive layer and the conductive layer simultaneously covering the covered via hole in the hole; then forming a patterned etch stop layer on the first cover layer and the pad and the flange layer, using the patterning The excavation layer (4) the overhanging platform and the first coating layer are formed such that the H is defined by the engraving layer on the second coating layer to define a pattern of the pedestal and the terminal (4) a resist layer, using the pattern (4) a resist layer (4) the conductive layer and the second cover , To form rings of silver t patterning this resist layer as defined in the engraved; and removing the plurality of I engraved patterned resist layer. In addition, etching the overhanging platform and the first covering layer may include: exposing the adhesive layer 30 5 201218468 in a first vertical direction of 3 hai, but not making the dielectric layer in the first vertical direction " engraved. The conductive layer and the second coating layer may include exposing the dielectric layer to a second vertical direction of 4, but not exposing the adhesive layer to the second vertical direction. Flowing the wicker layer can include filling the gap with the adhesive layer. Flowing the adhesive layer may also include: pressing the adhesive layer through the gap and extending the first vertical direction to the bump and the conductive layer

And reaching a surface portion of both the bump and the conductive layer, wherein the surface portions are adjacent to the notch and facing the second vertical direction, and the adhesive layer extends to the bump and the electrical layer along the The outer side of the second vertical direction. Curing the adhesive layer can include mechanically bonding the bump to the overhanging platform to the substrate. The placing of the semiconductor component can include: providing a die-bonding material between the semiconductor wafer (eg, a (f) s-chip) and the bump. Electrically connecting the semiconductor element

The piece may include: providing a wire between the wafer and the pad. Thermally bonding the semiconductor component can include: the θ gA material. Providing the solid crystal material between the I piece and the bump, the semiconductor component can be packaged in the following manner: depositing a liquid seal in the cavity to fill the cavity, and in the The package material is hardened by covering the semiconductor element 1 in the vertical direction. In addition, the recess can provide a dam body to limit the sealing material when the core of the package extends perpendicularly to the outside of the recess. The adhesive layer can contact the bump, the pedestal, and the convex The edge layer 'the solder fillet 31 201218468 , the covered via and the dielectric layer, and covering the substrate and the terminal ' in the first vertical direction and covering the solder pad and the flange layer in the second vertical direction The bumps are covered and surrounded in the lateral direction while extending to the peripheral edge formed by the separation of the other components of the same batch after the assembly is completed. The pedestal may cover the semiconductor element, the bump block and the flange layer in the second vertical direction without covering the adhesive layer, the dielectric layer, the terminal or the covered via. The susceptor can support the substrate and the adhesive layer, and after the set is fabricated and separated from other groups produced in the same batch, the distance from the outer edge of the set is maintained. The invention has several advantages. The heat sink provides excellent heat dissipation and allows thermal energy to flow through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not easily delaminated. The bump and the flange layer can be integrally formed to improve reliability. The bump may have a tapered sidewall and a highly reflective surface layer for collecting light emitted by a led wafer disposed in the bump recess to increase the amount of light emitted. In addition, since the recess can provide a clean and unambiguous space for the encapsulation material for color conversion on the LED wafer, the encapsulation material for converting color is not only used in the cavity but also Fixed, so that 'improves optical performance while reducing costs. To increase reliability, the pedestal can include a selected portion of the conductive layer overlying the dielectric layer. The adhesive layer can be located between the bump and the substrate, between the base and the substrate, and between the flange layer and the substrate to provide a strong mechanical bond between the heat sink and the substrate. The wire can form a simple circuit pattern to provide signal routing, or

S 32 201218468 Forms complex circuit patterns to achieve flexible multilayer signal routing. The wire may also utilize a coated via extending through the adhesive layer and the dielectric layer to provide vertical signal routing between the pad and the terminal. In addition, the coated perforation may be formed after the adhesive layer is cured, and maintain a hollow tubular shape, or be cleaved at the peripheral edge of the group, so that the solder which is subsequently reflowed to the surface of the terminal is wetted and flows into the covered perforation, thereby This design helps to improve reliability because the coated perforations are filled with a far adhesive layer or other non-wettable insulating material to form voids in the solder. The pedestal can be known to the substrate: for mechanical support to prevent bending deformation. This group can be manufactured by a low temperature process, which not only reduces stress but also improves reliability. The assembly can also be fabricated using the same control procedures that can be easily implemented by circuit boards, lead frames, and tape and roll substrate manufacturers. The above and other features and advantages of the present invention will be further described hereinafter by way of various embodiments. The above and other technical contents, features and effects of the present invention will be apparent from the following detailed description of the embodiments of the invention. 1A and 1B are cross-sectional views showing a method of fabricating a bump and an overhanging platform in an embodiment of the present invention, and Figs. 1C and 1D are a plan view and a bottom view, respectively, of Fig. 1B. Figure 1A is a cross-sectional view of a metal plate 10 containing opposing major surfaces 12 and 14. The illustrated metal plate 1 is a copper plate having a thickness of 7 μm. Copper has the advantages of high thermal conductivity, good bonding and low cost. Gold 33 201218468 Dependent plates ίο can be made of a variety of metals, such as copper, Ming, iron-nickel alloy π, iron, nickel, silver, gold, mixtures thereof and alloys thereof. The first IB, 1C, and 1D drawings are respectively formed by forming a bump 16 and a flattening flat on the metal plate. 18 and (2) a cross-sectional view, a top view and a bottom view of the hole 20. The bump 16 and the recessed six 20 are mechanically stamped from a metal plate 1〇. Therefore, the bump 16 is the portion of the metal plate 10 that is stamped, and the overhanging flat 18 is the portion of the gold-plate 10 that is not stamped. The _i 16 abuts the overhanging platform 18, is integral with the overhanging platform 18, and extends from the overhanging platform 18 in a downward-to-deep direction. The bumps 16 include bend corners 2 and 24 tapered side walls 26 and bottom plates 28 » bent corners 22 and 24 are formed by stamping operations. The f-folded corner 22 abuts the overhanging platform 18 and the tapered side wall 26' and the f-folded corner 24 abuts the tapered side wall 26 and the bottom plate 28. The side walls 26 are expanded outwardly in the upward direction and the bottom plate 28 extends in the side direction (e.g., left and right) perpendicular to the upward and downward directions. Therefore, the projection 16 has a flat-topped tapered cylindrical shape (similar to a frustum) whose diameter decreases downward from the overhanging platform U toward the bottom plate 28, that is, from the bottom plate 28 toward the overhanging platform. The height of the bumps 16 (relative to the overhanging platform 为) is (four) micrometers. The diameter at the overhanging platform 18 is 15 GG microns, and the height at the bottom plate 28 is 1 micron. Further, the bumps 16 have an irregular thickness due to the rushing operation. For example, the tapered side wall 26 elongated by (4) is thinner than the bottom plate U. For ease of illustration, the bumps 16 have a uniform thickness in the figure. The flat projecting platform 18 extends from the side of the bump in the side direction and has a thickness of 70 μm. The pocket 20 faces upwardly and extends into the bump 16 and is convex

34 S 201218468 Block 16 is covered from below. The pocket 20 has an inlet at the outrigger platform 18. Furthermore, the shape of the recess 20 conforms to the projection μ. The flat-topped tapered cylinder (like a flat head body) has its diameter entrance which decreases downward toward the bottom plate 28, i.e., upward from the entrance of the overhanging platform 18. Furthermore, the face direction extends across most of the bumps 16, and is micron. Therefore, the recess 20 is also a cross-sectional view from the bottom plate 28 of the overhanging platform 18 toward the recess 20 along the vertical and side recesses 20, the second portions 2A and 2B, illustrating an embodiment of the present invention. Method of making an adhesive layer 1 The 2CA 2D drawing is a top view and a bottom view, respectively, drawn according to the a picture. Fig. 2A is a cross-sectional view of the adhesive layer 3, wherein the adhesive layer % is a Β-stage uncured epoxy film which is an uncured and unpatterned sheet having a thickness of 150 μm.黏 Adhesive layer 30 can be a variety of dielectric films or films made of a variety of organic or inorganic electrical insulators. For example, the adhesive layer 3 can initially be a film in which the tree

The greased thermosetting epoxy resin is immersed in the reinforced material to strengthen the material to the middle. The epoxy resin may be FR_4, but other epoxy resins such as polyfunctional and bismaleimide-triazabenzene (BT) resins may also be used. Cyanate, polyimide and polytetrafluoroethylene (PTFE) are also available in special applications. The reinforcing material may be an electronic grade glass, or may be other = strong materials, such as high-strength glass, low-inductance glass, stone keWar aramid, and paper. The reinforcing material may also be a woven fabric, a non-woven fabric or a non-directional microfiber. Filling/adding to the film such as enamel (melting fused silica) to enhance thermal conductivity, thermal shock resistance and thermal expansion 35 201218468 . Commercially available prepreg can be used, such as the United States ^ _ . Oswego W.L.

The SPEEDB〇ar l film of Gore & ASSOClates is an example. The 2B, 2C, and 2D drawings are a cross-sectional view, a plan view, and a bottom view, respectively, of the adhesive layer 30 having the opening 32 in the η^ well. Opening * A two-horse window that runs through the Leying layer 30 and has a diameter of 1550 microns. Openings and teeth are difficult to open 32 is formed by mechanically drilling through the film, but it can also be made by other techniques such as punching and stamping. Figs. 3 and 3 are cross-sectional views showing a method of fabricating a substrate in an embodiment of the present invention, and a first plan view and a bottom view, respectively, according to a third drawing. The first substrate 34 includes a cross-sectional view of the conductive layer 36, the substrate 34, and a dielectric layer 38. The conductive layer 36 is an electrical conductor that contacts the dielectric layer % and extends over the dielectric layer 38. The dielectric layer % is an electrical insulator. For example, the conductive layer 36 is a copper plate having no pattern and having a thickness of 3 Gm, and the dielectric layer 38 is an epoxy resin having a thickness of 120 μm.

The 3B, 3C, and 3D drawings are a cross-sectional view, a plan view, and a bottom view, respectively, of the substrate 34 having the through holes 4A. The through hole 4 is a window which penetrates the substrate W and has a diameter of 1550 μm. The via 40 is mechanically drilled through the conductive layer % and the dielectric layer 38 to form 'but may be fabricated by other techniques such as stamping and stamping. The opening 32 has the same diameter as the through hole 40. Further, the drill having the same opening 32 as the through hole 40 may be formed in the same manner on the same drill stand, or may be formed in the same manner on the same punch by the same punch. The substrate 34 is illustrated herein as a laminate structure, but the substrate 34 can be other electrically connected, such as a ceramic plate or a printed circuit board. Similarly, substrate 34 can additionally comprise a plurality of layers of embedded circuitry.

S 36 201218468 A to 4M B are cross-sectional views illustrating a method of fabricating a thermally conductive plate in accordance with an embodiment of the present invention, the thermally conductive plate comprising bumps 16, adhesive layers and ^4N and 40, respectively, of FIG. 4M The top view and the bottom view 〇A and 4B are in a state in which the recesses are inverted downward so that the adhesive layer 30 and the substrate 34 are placed on the overhanging platform 18 by gravity. The structure in Figures 4C to 4E still maintains the pocket down. The structure of the 4th F to 4th figure ^ is flipped again to the upward direction of the pocket as shown in Figs. 1A to m.

simple. The concave eight 20 faces downward in the 4A to 4E, and faces upward in the 4F to 40. Despite this, the relative orientation of the structure has not changed. Regardless of whether the structure is inverted, rotated or tilted, the pockets 2〇 always face a vertical direction and are covered by the bumps in a second vertical direction. Similarly, regardless of whether the structure is inverted, rotated or tilted, the bumps extend outside the substrate 34 in the first-perpendicular direction and along the second perpendicular: to the outside of the overhanging platform 18. Therefore, the first and second vertical directions are both in the direction of the structure, and are always opposite to each other, and the side direction of the perpendicular direction is recorded. The 4A picture shows that the adhesive layer 3 is disposed on the overhanging platform a. Dropped onto the overhanging platform 18, the bumps 16 are inserted upwardly and the two preferred 32 embossed layers are positioned and positioned in the center of the opening 32 after the insertion and penetration openings 32 are aligned. The adhesive layer 30 is not in contact. In the structure shown in Fig. 4, the substrate 34 is placed on the adhesive layer, and the anti-four system is lowered onto the adhesive layer 3〇, so that the bumps are inserted upward into the through holes 37 201218468 4〇', and finally the substrate 34 is contacted and positioned. On the adhesive layer 3 〇. The bump 16 is aligned with the through hole 4A after insertion (but not through) the through hole 4, and is located at a central position within the through hole 40 without contacting the substrate 34. Therefore, the notch 42 is located in the through hole 4A and between the bump 16 and the substrate 34. The notch 42 laterally surrounds the bump 16 while being laterally surrounded by the substrate 34. Further, the opening 32 and the through hole 40 are aligned with each other and have the same diameter. At this time, the substrate 34 is disposed on and in contact with the adhesive layer 30 and extends over the adhesive layer 30. After the bumps 16 extend through the openings 32, they enter the vias 40 and reach the dielectric layer 38. The bump 16 is 50 μm lower than the top surface of the conductive layer %, and is exposed outward through the through hole 4〇. The adhesive layer 3 is in contact with the overhanging platform 18 and the substrate 34 and between the two. The adhesive layer 3 is in contact with the dielectric layer 38 but at a distance from the conductive layer 36 (four). At this stage, the adhesive layer % is still a B-stage uncured epoxy film and the notch 42 is air. The 4C @ shows that the adhesive 3530 is heated and pressurized and flows into the gap. In this figure, the method of forcing the adhesive layer 3G to flow σ 42 is to apply downward pressure to the conductive layer % and/or to apply upward pressure to the outwardly extending platform 18, that is, to press the overhanging platform 18 against the substrate 34. In order to apply pressure to the adhesive layer 3; at the same time, the adhesive layer 30 is also heated. The layer % of heat can be arbitrarily formed under waste force. Therefore, the adhesive layer 3 located between the overhanging platform 18 and the substrate 34 is pressed to 'change its original shape and flow upward into the notch & the overhanging platform 18 and the substrate 34 are continuously pressed toward each other until the adhesive layer 3 () Fill the gap 42. Further, after the gap between the overhanging platform 18 and the substrate 34 is reduced, the adhesive layer 30 still fills the reduced gap. 201218468 For example, the history of the overhanging platform 18 and the conductive layer 36 can be placed between the press machine and the lower press table (not shown). In addition, an upper baffle and an upper buffer paper (not shown) may be interposed between the conductive layer 36 and the upper pressing table, and the lower and lower cushioning sheets (not shown) may be placed on the outer flat surface.纟18 The superposed body of this structure is, in order from top to bottom, an upper pressing table, an upper playing board, a buffer paper, a substrate 34, an adhesive layer 3, an overhanging flat 18, a lower cushioning paper, a lower supporting plate, and a lower pressing table. In addition, it can be extended upward from the lower pressing table and passed through the outer flattening

. A tooling pin (not shown) of the 8-position hole (not shown) positions the & superimposed body on the lower pressing table. ^ Then the upper and lower parts are heated and pushed forward to each other, thereby heating and applying pressure to the adhesive layer. The baffle disperses the heat of the platen so that heat is evenly applied to the overhanging platform 18 and the base 34 or even the adhesive layer 3〇. The cushioning paper spreads the pressure knives of the pressing table, so that the pressure is evenly applied to the overhanging platform 丨8 and the substrate Μ or even the lag 30. Initially, the dielectric layer 38 contacts and is pressed against the soil adhesion layer. As the platen continues to act and continues to heat, the adhesive layer 30 between the overhanging platform 18 and the substrate is squeezed and begins to refine. Thus, it flows upwardly into the gap and reaches the conductive layer 36 after passing through the dielectric layer 38. For example, after the uncured epoxy is melted by heat, it is forced into the notch 42 by pressure, but the reinforcing material remains between the overhanging platform 18 and the substrate 34. The grading layer 30 rises faster in the through hole 4 大于 than the bump 16 , and finally fills the notch 耆 耆 layer 30 and rises to a position higher than the σ 42 and flows to the convex before the pressing stage stops. The top surface of the block and the conductive layer 36 are adjacent to the missing portion D42. This may occur if / thickness is slightly larger than actually needed. " β t. As a result, the layer 30 is only formed on the top surface of the bump 16 and the conductive layer 36 to form a cover layer 39 201218468 . The press table is heated by touching the bumps. After 16 stops the action, but still (4) the direction of the layer 30 adhesive layer 30 flowing upward in the notch 42 as shown by the upward bold arrow in the figure, the bump and the overhanging platform, " The downward movement of the base plate 34 relative to the projection 16 and the overhanging platform 18 is indicated by a downwardly fine arrow. The adhesive layer 30 of the 4D pattern has been cured. For example, after the pressing table stops moving, the bump 16 and the outer flattening Δ 18 are continuously clamped and heated, thereby curing or melting the melted B-stage epoxy resin into an e-stage. Epoxy resin. Therefore, the epoxy resin is cured in a manner similar to conventional multilayer bonding. After the epoxy resin is cured, the press table is separated 'to remove the structure from the press. The cured adhesive layer 30 provides a secure mechanical bond between the bumps 16 and the substrate 34 and between the overhanging platform 18 and the substrate 34. The adhesive layer can withstand the normal operating pressure without deformation and damage, and only temporarily distort when subjected to excessive pressure. Furthermore, the adhesive layer 3G can absorb the thermal expansion mismatch between the bump 16 and the substrate 34 and between the overhanging platform 18 and the substrate 34. At this stage, the bumps 16 are substantially coplanar with the conductive layer 36, and the adhesive layer 30 and the conductive layer 36 extend to the top surface of the upward direction. For example, the adhesive layer 3 between the overhanging platform 18 and the dielectric layer 38 is 1 μm thick, which is 5 μm smaller than the initial thickness of 150 μm; that is, the bump 16 is raised 50 μm in the through hole 4〇. The substrate 34 is opposite to the bump! 6 drops 5 〇 micron. The height of the bump 16 of 250 micrometers is substantially equivalent to the combination of the conductive layer 36 (3 micrometers), the dielectric layer 38 (120 micrometers) and the lower adhesive layer (micrometers).

S

40 201218468 degrees. In addition, the bumps 16 are still located at the center of the openings 32 and the through holes 4, and are spaced apart from the substrate 34, and the adhesive layer 3〇 fills the space between the overhanging platform and the substrate 34 and fills the gaps 42. For example, the gap 42 (and the layer 3 点 between the bump 16 and the substrate 34) has a width of 225 microns ((1550 1000)/2) at the bottom plate 28. The adhesive layer 3 extends across the dielectric layer within the gap 42

38. In other words, the adhesive layer 3 () in the notch 42 extends in the upward and downward directions and across the thickness of the dielectric layer 38 of the outer sidewall of the notch 42. The adhesive layer 30 also includes a thin top portion over the notch 42 that contacts the top surface of the bump 16 and the top surface of the conductive layer 36 and extends iq microns above the bump 16. In the structure shown in Fig. 4E, the tops of the bumps 16, the adhesive layer 3, and the conductive sound 36 have been removed. The tops of the bumps 16, the adhesive layer 3G and the conductive layer 36 are removed by grinding, for example, by rotating the diamond wheel and the top of the steaming water treatment structure. At first the diamond wheel was only polished (four)%. Continuous grinding changes due to the downward movement of the crepe layer 30 under the surface of the surface. The diamond wheel will eventually contact the bump 16 fish conductive layer 36 (not necessarily at the same time), so after the grinding bump 16 and the conductive layer are continuously polished, the bump 16, the adhesive layer 3 θ, the lower m and the conductive layer 36 are all caused by The surface being worn is moved down and ". The grinding is continued until the desired thickness is removed. The distilled water rinses the structure to remove dirt.旻人熬 The above grinding step grinds the top of the adhesive layer 3 to the top of the 25 micro ghost and rubs it to 5 micrometers, and rubs the conductive slanting m from the top of the bamboo isoelectric layer 36. Also reduce the *block 16 or (four) layer 3. (4) The roof of the conductive layer 36 &..., ., ,, and the monthly shirt, but the degree is reduced to 15 microns. Thus, the bumps 16, the adhesive layer 3, and the conductive layer 36 are collectively located on the top side of the smooth splicing side above the electrical layer 38 of the layer 201216468. The 4F figure reverses the above structure. The structure shown in Fig. 4G has a hole 44. The holes 44 are perforations through the overhanging platform 18, the adhesive layer 30, the conductive layer 36, and the dielectric layer, and have a diameter of 300 microns. The holes 44 are formed by mechanical misalignment but can be fabricated by other techniques, such as laser drilling and plasma etching. The structure shown in Fig. 4 has a coating layer 46. The coating layer 46 is deposited on the bump 16, the overhanging platform 18, the adhesive layer 3, the conductive layer % and the dielectric layer 38, and the coating layer 46 forms the upper cladding layer 48, the lower cladding layer 5 () and the perforations 52. The upper cladding layer 48 is deposited on the surface i2 of the bump 16 and the overhanging platform 18 while contacting and covering both from above. The upper cladding layer 48 is a non-patterned steel layer having a thickness of 20 μm. The lower cladding layer 50 is deposited on the lateral surface of the bump 16, the adhesive layer 3, and the conductive layer % while contacting and covering the three from below. The lower cladding layer is a non-patterned copper layer having a thickness of 20 microns. The coated vias 52 are deposited in and in contact with the vias 44 to extend the platform 18: the adhesive layer 30, the conductive layer 36 and the dielectric layer 38 while covering the inner sidewalls of the holes 44 in the lateral direction. The coated perforations 52 are a copper tube having a thickness of 20 μm which is adjacent to and integrally formed with the covering layers 48, 50 and electrically connected to each other. For example, the structure can be immersed in an activator solution, so that the tensile layer 30 and the dielectric layer 38 can react with the electroless copper to generate a catalyst, and then a first copper layer is provided in an electroless plating manner. On the bump 16, the overhanging platform 201218468 18, the adhesive layer 30, the conductive layer 36 and the dielectric layer 38, a second copper layer is then electroplated on the first copper layer. The first copper layer is about 2 microns thick and the second copper layer is about 18 microns thick, so that the total thickness of the cover layer 46 (and the cover layer 48, and the coated perforations 52) is about 2 microns. As a result, the thickness of the bump and the overhanging platform 18 is substantially increased in the upward direction, and the thickness of the conductive layer % is substantially increased in the downward direction. In addition, the pockets 2〇 rise about 20 microns in the upward direction and still extend across the majority of the bumps 16 in the vertical and side directions, while the depth of the pockets 20 is maintained at 25 microns. The upper cladding layer 48 serves as a thickened layer of the bumps 16 and the overhanging platform 18. The lower cladding layer 50 serves as a bottom of one of the bumps 16, a thick layer of the conductive layer 36, and a bridging structure between the bumps 16 and the conductive layer 36. The over-cladding hole 52 serves as an electrical interconnection structure between the overhanging platform 18 and the conductive layer 36. For convenience of illustration, the bump 16, the overhanging platform 18, the upper cladding layer 48 and the covered perforation 52 are all shown in a single layer. Similarly, for convenience of illustration, the bump i 6 , the conductive layer 36 , the lower cladding layer 50 and the covered via 52 are also displayed in a single layer. The copper is homogenously coated, and the boundary between the bump 16 and the upper cladding layer 48 is outside. The boundary between the extension platform 18 and the upper cladding layer 48, the boundary between the overhanging platform a and the covered perforation 52, the boundary between the bump 16 and the lower cladding layer 50, the boundary between the conductive layer 36 and the lower cladding layer 50, and the conductive layer The line between 36 and the covered perforations 52 (both shown in dashed lines) may be less noticeable or even undetectable. However, the boundary between the adhesive layer 30 and the lower coating layer 50 outside the hole 44, the boundary between the adhesive layer 3〇 and the covered perforation 52 in the hole 44, and the boundary between the dielectric layer 38 and the covered hole 52 in the hole 44 are clearly visible. 43 201218468 The patterned etching resist layers 54, 56 are respectively provided on the coating layers 48, 50 of the structure shown in Fig. 41. The patterned patterned resist layers 54, 56 are respectively deposited on the coating layers Μ, 50, and are formed by using a dry hard technique to simultaneously bond the photoresist layers to the coating layer 48. 50. The wet 'spin-coating method and the curtain coating method are also suitable photoresist forming techniques. , a photomask (not shown) and a second photomask (not shown) are respectively coupled; the optical layer 54 56 is then selectively passed through the first and second portions according to conventional techniques. The mask is such that the light-receiving portion of the light-receiving portion becomes insoluble, and then the unexposed and still soluble portion of the filament is removed by the developer to pattern the photoresist layers 54, 56. Therefore, the photoresist layer 54 has a pattern of selectively exposed upper cladding layer 48, and the photoresist layer % has a pattern for exposing the underlying cladding layer 5'. However, the photoresist layers 54, 56 cover the bumps 16 and the covered vias 52 from above and below, respectively. In the structure shown in Fig. 4J, the overhanging platform 18 and the overlying layer = have been removed from (4) selected portions to form a patterned (four) resistive layer. The pattern ❿ conductive layer 36 and the lower cladding layer 5 have also been etched. The selected portion is removed to form a patterned etch stop layer _ defined pattern. The touch is a double-sided wet chemical button. For example, use a top 嗔 (not shown) and bottom. (5 nozzles (not shown) spray the chemical money engraving on the top and bottom surfaces of the structure respectively, or immerse the structure in the chemical etching solution. The engraving can be used to excel the overhanging platform 18 and the upper jaw 48. The adhesive layer is exposed in the upward direction of the moon, thereby converting the originally unpatterned overhanging platform 18 and the upper covering layer 48 into a pattern layer. The chemical money engraving also penetrates the conductive layer % and

44 S 201218468 The lower cladding layer 50' exposes the dielectric layer 38 downward toward the lower side, thereby converting the conductive layer 36 and the lower cladding layer 5 of the original pattern into a pattern layer. Therefore, the adhesive layer 30 is exposed only outward toward the upper side and is not exposed outward toward the lower side, and the dielectric layer μ is exposed only outward toward the lower side and not outwardly toward the upper side. The chemical etching solution suitable for the above etching operation and highly selective to copper may be a solution containing ammonia or a diluted mixture of acid and hydrochloric acid. In other words, 'the chemical etchant can be gambling or alkaline. </ br> is sufficient to form a pattern without causing the overhanging platform 18, the conductive layer 36 and the coating layer Μ, % to be excessively exposed to the chemical etching solution. The ideal etching time can be determined by trial and error. In Figure 4K, the patterned etch stop layers 54, 56 on the structure have been removed. The photoresist layers are removed by solvent treatment. For example, the solvent used may be a strong alkaline potassium hydroxide solution having a pH of 14. The post-engagement extension platform 18 and the upper cladding layer 48 comprise a solder bump (9) and a flange layer 62. The solder bump 6 is patterned with the flange layer 62. The resist layer μ is formed on the outer surface σ 18 and the portion defined and selected on the upper cladding layer 48, and the solder bumps 6 and the flange layer 62 are spaced apart from each other. The bead 6 〇 is adjacent to the covered perforation η and extends laterally from the covered perforation 52 to electrically connect to the covered perforation μ ′ and maintain a distance from the bump. The flange layer 62 abuts the projection 16 and forms a body with the projection, and is laterally extended by the projection 16 while being thermally coupled to the projection 16 and spaced apart from the covered perforation 52. After the flange layer is provided, the bumps 16 and the pockets 2 are heated, which is a central portion of the periphery of the flange layer 62. This solder joint and the flange layer 62 are in contact with each other. Layer 3G, but also both with ^: into the = distance. Tan 6 〇 and flange layer 62 extends over the adhesive layer 30; 丨曰% above, and are flat, thickness 90 microns (7 (four) 0) 45 201218468. The soldering pad 60 and the flange layer 62 (four) are located on the top surface of the top surface in the upward direction, and the conductive layer 36 and the lower cladding layer 50 include the base 64 and the terminal 66. The base 64 and the terminal 66 are patterned. The etch stop layer 56 is defined and selected on the conductive layer 36 and the lower cladding layer 5G, and the susceptor and the terminal 66 are kept away from each other. The pedestal "adjacent to the bump 16 and extending below the bump 16" and self-convex The block 16 extends laterally while being thermally coupled to the bump 16. The pedestal "covers the bump 16 and the flange layer from below and maintains a distance from the covered perforation 52. The thickness of the pedestal 64 is 2 Å at the abutment bump 16 and 35 microns at the contiguous dielectric layer 38. (15+2〇). Further, the pedestal is 2 μm thick adjacent to the portion of the adhesive layer 30 and spaced apart from the dielectric layer 38, and the pedestal 64 is adjacent to one of the sides of the layer 30 and the bottom surface of the dielectric layer 38. The corner of the shape 2 is 35 microns thick. The terminal 66 is electrically connected to the hole and is kept away from the bump 16, and the thickness of the terminal 66 is _"5+20). Furthermore, the pedestal 64 contacts the adhesive layer 3 〇 and the dielectric layer π, while the : 66 contacts the dielectric layer 38 but remains at a distance from the paste 3 。. The pedestal scorpion 66 extends below the adhesive layer Μ and the dielectric layer 38. The thickness of the pedestal 64::6; 6 is equal to each other, but the thickness of the base is different at the terminal 66. . The pedestal 64 and the terminal are "co-located on the bottom surface of the face-down direction. ^The perforation 52, the ferrule 60 and the terminal 66 together form a wire comprising a selected portion of the overhanging platform 18 and the upper cladding layer 48. For selected portions, the selected U-knife are adjacent to the covered perforations 52 and are spaced apart from the bumps 16. Leads 7〇

46 S 201218468 Located outside the pocket 20. In addition, the cover is passed through a conductive path between the fuse pad 60 and the terminal 66. The level (the lateral wire 70 is provided not only from the pad 6 to the covered perforation 52)

The routing also provides a vertical (top to bottom) routing from the pad 6 to the terminal % through the covered vias 52. The wire 70 is not limited to this configuration. For example, the solder fillet 60 can be electrically connected to the covered via 52 by a routing line defined above the adhesive layer 3A and the dielectric layer 38 and defined by the patterned etch resist layer 54, and the terminal 66 can be utilized. A routing line, which is located below the adhesive layer 3 and the dielectric layer 38 and defined by the patterned (four) resist layer 56, is electrically coupled to the coated via 52. In addition, the conductive path may further include conductive vias penetrating the adhesive layer % and/or the dielectric layer 38, additional routing lines (which are located above and/or below the adhesive layer 3 and/or the dielectric layer 38), and passive Components (such as resistors and capacitors placed on other pads). The bump 16, the flange layer 62 and the pedestal 64 together form a heat sink 72. Thus, the heat sink 72 includes selected portions of both the overhanging platform 18 and the upper cladding layer 48, wherein the selected portions abut the bumps 16 and are spaced from the wire %; the selected portion of the conductive layer 36, wherein the selected portion Maintaining a distance from the bumps 16 and the wires 70; and selecting a selected portion of the lower cladding layer 5, wherein the selected portion abuts the bumps 16 and is spaced from the wires 7A. In addition, the bumps 16 provide a thermally conductive path to the pedestal 64. The heat sink 72 is substantially an inverted τ-shaped heat sink block including a pillar portion (bump 16), a wing portion (a portion of the pedestal 64 extending laterally from the pillar portion), and a thermal pad (flange layer 62) . The conductor 7 of the structure shown in Fig. 4L and the heat sink 72 are provided with a cover 47 201218468 contact 74. The coated contact 74 is a multi-layer metal coating that contacts the exposed steel surface. Therefore, the 'covered contact 74 contacts the bump 16, the covered via 52, the pad 60 and the flange layer 62' and covers the four from above, and also contacts the covered via 52, the pedestal 64 and the terminal 66, and is covered from below. These three. For example, a layer of gold is provided on the exposed copper surface in an electroless plating manner, and then the silver layer is provided on the nickel layer in an electroless plating manner, wherein the inner nickel layer is about 3 μm thick, and the silver layer is The surface layer is about 0.5 microns thick, so the thickness of the coated contact 74 is about 3.5 microns. The surface treatment with the coated contacts 74 as bumps 16, pads 60, flange layer 62, base 64 and terminals 66 has several advantages. The inner nickel layer provides primary mechanical and electrical bonding and/or thermal bonding, while the silver surface layer provides a wettable surface for solder reflow to match solder and wire. The covered contacts 74 also protect the wires 7 and the heat sink 72 from corrosion. The coated contacts 74 can contain a variety of metals to meet the needs of externally coupled media. For example, a gold layer may be coated on the inner nickel layer or a nickel surface layer may be used alone. For convenience of illustration, the wires 70 and the heat sinks 72 provided with the covered contacts 74 are each represented by a single layer. The boundary between the wire 70 and the covered contact 74 (not shown) and the boundary between the heat sink 72 and the covered contact 74 (not shown) are copper/recording surfaces. The fabrication of the heat conducting plate 80 is thus completed. 4M, 4N and 40 are respectively a cross-sectional view, a top view and a bottom view of the heat conducting plate 80, in which the edge of the heat conducting plate 80 has been separated along the cutting line from the support frame and/or the adjacent heat transfer plate produced in the same batch. 201218468 The heat conducting plate 8G is provided with a layer 3G, a substrate 34, a wire 7G and a heat sink 72. Substrate 34 includes a dielectric layer 38. The wire 7A includes a covered perforation &amp; solder wire 6 and a terminal 66. The heat sink 72 includes a bump 16, a flange layer 62, and a base 64. The projection 16 abuts the flange layer 62 at the corner 22 and abuts the base 64 at the corner 24 and the bottom plate 28. The & block 16 extends from the base μ in the upward direction, extends downward from the flange layer 62, and forms a body with the flange layer. The bump 16 extends into the opening 32 and the through hole opening 32 and the through hole 40 (see the central position in the 4th R, the upper cymbal). The top of the bump 16 is adjacent to the adhesive layer 30 and one of the contact flange layers 62. Part of the coplanar plane j and the bottom of the bump 16 is adjacent to one of the contact pedestals 64 of the adhesive 0: a common plane. The bump 16 also contacts the adhesive layer 3 〇 and is at a distance from the dielectric layer while The flat-topped cone layer 62 is maintained to be upwardly increased. The red color extends from the base 64 toward the flange surface toward the upward direction of the pocket 2〇 into the bump, the opening, and the through hole 40, and is always located at the bump 16 2n. The central partition door in the hole 4 is smeared with the shackle 20 and the sump 20 and the pedestal 64. The recess 2 〇 has a 盥. The shape of the bulge 16 conforms, and the yoke extends across the bulge in the vertical and lateral directions. 16 The cone-shaped column, the knives, on the one hand, maintains the bottom of the flat top at the bottom of the bottom plate 28 toward the flange layer 62. The inlet layer is extended upward from the projection j 6 . And ψ, dielectric; 38, ..., side out, while extending over the layer 30 H / 肖口 肖通孔40 and overlapping the four. Flange The layer 62 contacts the adhesive layer 3() but maintains a distance from the meso-convex layer 38 and the pedestal 64. 201218468 The thickness of the flange layer 62 can be greater than the thickness of the pedestal 64. The pedestal 64 extends from the side of the bump 16 along the side. Laterally extending beyond the opening 32 of the opening 32 and the flange layer 62, and covering the bump μ, the opening and the flange layer 62 from below. The pedestal 64 contacts the adhesive layer 30 and the dielectric layer 38 and: On the outer side in the downward direction, the base 64 supports the adhesive layer '34' and is spaced from the peripheral edge of the heat conducting plate 8(). The base has a first thickness (2 μm) at the abutting bump 16 adjacent to The dielectric 8 has a second thickness micrometer greater than the first thickness, and the pedestal 64 has a flat surface with a downward direction. Further, the susceptor 64 (four) has a viscous layer 30 and is spaced from the dielectric layer 38. The portion also has the first thickness. The pedestal 64 also has the second thickness at a corner formed by the adjacent adhesive layer 30 and the dielectric layer 38. The layer 3 接触 is in contact within the notch 42 and is located between the bumps 16 Between the dielectric layer 38 and the space between the bump 16 and the dielectric layer 38. The adhesive layer % contacts the dielectric layer 38 outside the 42 layer, The perforation 52 is overlapped with the flange layer 62. The adhesive layer 30 contacts the susceptor 64 but is spaced from the terminal 66. The adhesive layer extends not only across the dielectric layer 38 within the indentation 42 but also over the bump 16 and the flange layer 62. Between the bumps 16 and the pedestal 64, between the bumps « and «the perforations 52 (9) and the flange layer 62 and the pedestal 64. The adhesive layer 3 〇 also extends from the bumps, over the wires 7 〇, Finally, the peripheral edge of the group is reached. At this time, the adhesive layer 3 is cured. The adhesive layer 30 covers and surrounds the bump 16 in the lateral direction, and covers the portion of the base 64 outside the periphery of the bump 16 from above, covering the dielectric from above. Layer % and terminal 66, and covering the tan pad 6 〇 from the bottom and the flange layer 仏 adhesive layer 3 〇 201218468 is also coated on the side wall 26 of the bump 16 (see Figure 1B), the top surface of the dielectric layer 38 and the base The top portion of the seat 64, wherein the top surface portion abuts the projection 16 and extends laterally from the projection 16 with the face facing upward.

The adhesive layer 30 passes through an imaginary horizontal line between the bump 16 and the dielectric layer %, an imaginary horizontal line between the bump 16 and the covered through hole 52, an imaginary horizontal line between the bump 16 and the pedestal 64, and a bump 16 An imaginary vertical line between the pedestals 64, an imaginary vertical line between the solder bumps 60 and the dielectric layer 38, an imaginary vertical line between the flange layer 62 and the 'an electric layer 38, and a flange layer 62 and a pedestal 64 - the imaginary vertical line. 'However, the adhesive layer % does not pass through the imaginary line between the bump 16 and the terminal 66 alone, the imaginary line between the solder bump 6 () and the pedestal 64, the imaginary line between the solder bump 6G and the terminal 66 or &amp; wants to line between flange layer 62 and terminal %. Therefore, although the imaginary horizontal line extending from the bump 丨6 to the dielectric layer 38 only passes through the adhesive layer 30, there is no horizontal, vertical or other orientation at the bump 16 and the terminal 66. The imaginary line passes only through the adhesive layer 30. This imaginary line passes through the dielectric layer 38 and/or the pedestal 64 except for the adhesive layer 3 除 between the bump 16 and the terminal %. * The dielectric layer 38 is in contact with and between the landing layer 3A and the pedestal 64 and between the adhesive layer 30 and the terminal 66. Both the solder fillet 60 and the flange layer 62 contact the adhesive layer 3, but the layer 38 also maintains a distance. The coated perforation 52 is in contact with the hole 44X^J_liLiL and extends through the adhesive layer 30 and the dielectric layer 38' to the upper and lower sides of the adhesive layer and the dielectric layer μ. The coated perforation 52 maintains a tubular shape and has a vertical inner and outer side wall 'where the diameter of the covered perforation 52 extends in the straight direction of the pad 6G to the terminal 66. 201218468 is fixed in the straight direction and the top of both the beta bump 16 and the adhesive layer 30 is fixed. The flange layers 62 are coplanar and the bottoms of the two are coplanar at the base 64. Further, the pad 6 and the bump layer 62 have the same thickness (9 μm) and are co-located on the surface of the adhesive layer and the upper side of the dielectric layer 38 in the upward direction. The pedestal "has the same thickness (35 microns) as the terminal 66 adjacent the two, but the thickness of the pedestal 64 adjacent the bump 16 is different from the terminal 66 (2 () and % micro pedestal 64, respectively. Cooperating with the terminal 66 on the surface of the adhesive layer 30 and the lower side of the dielectric layer 38 in the downward direction. After the heat-transfer plate 80 of the same batch is cut, the adhesive layer 3 and the dielectric layer 38 both extend to the cutting. The vertical pad is formed. The pad 60 is an electrical interface specially designed for semiconductor components such as LED chips, and the semiconductor device is disposed on the bump 丨6 in a subsequent process. The terminal 66 is dedicated to the next layer. A tailor-made electrical interface (eg, a solderable wire from a printed circuit board). The pedestal 64 is tailored to the next layer of components (such as the aforementioned printed circuit board or an electronic device heat sink) The custom-made thermal interface. The pad 60 and the terminal 66 are offset from each other in the horizontal and vertical directions, and are respectively exposed on the top surface and the bottom surface of the heat conducting plate 80 to provide horizontal and vertical routing between the semiconductor component and the next layer assembly. For ease of illustration, the wire 70 is in section The middle is depicted as a continuous circuit trace. However, the conductor 70 typically provides horizontal signal routing in both the X and gamma directions, i.e., the pads 60 and the terminals 66 are laterally offset from each other in the X and gamma directions. 52 can be located at the corner of the heat conducting plate 80. 201218468 The wire 70 and the heat sink 72 are kept away from each other, so the heat sink 72 is difficult to connect to read the electrical _. The heat sink 72 can be used to place the semiconductor component subsequently disposed on the bump 16. The thermal energy is diffused to the lower layer of the heat conducting plate 80. The thermal energy generated by the semiconductor component flows into the bump 16 and enters its seat via the bump “. The thermal energy is downward from the pedestal 64. Directions are scattered, such as diffusion: thermal devices.

The covered contact 74 occupies 85% to 95% of the top surface of the heat conducting plate 8, so that a top surface having high reflectivity can be provided. This highly reflective top surface is particularly useful if the component that is subsequently disposed in the recess 2 of the bump 16 is an -LED component. The bumps 16, the covered vias 52, the pads 60, the flange layer 62, the pedestals 64, and the terminals 66 are all of the same metal, i.e., copper/nickel/silver. The bump 16, the covered via 52, the pad 60, the flange layer 62, the pedestal 64 and the terminal 66 are composed of a silver surface layer, an inner copper core and an inner nickel layer, wherein the inner nickel layer contacts and Between the silver surface layer and the inner copper core. &amp; Block 16, Covered Through Hole 52, Pad 60, Flange Layer 62 'The base copper core of terminal 64 and terminal 66 is primarily copper. The silver surface layer and the inner recording layer are provided by the covered contact 74, and the inner copper core is provided by a metal plate 1 〇 (iljj, a plurality of combinations of the conductive layer 36 and the cover layer 46. The wire 70 includes a cover layer The vias 52, the pads 60 and the internal copper cores shared by the terminals 66, and the heat sinks 72 include an inner copper core shared by the bumps 16, the flange layer 62 and the base 64. In addition, the wires 70 are covered with perforations 52, The pad 60 and the terminal 66 each include a covered contact 74. The bump 16 and the flange layer 62 of the heat sink 72 also include a covered contact 74 (which is at a distance from the pedestal 64 201218468) and the base of the heat sink 72 The seat 64 also includes a covered contact 74 (which is spaced apart from the bump 16 and the flange layer 62. The wire 7 and the heat sink 72 are composed of copper/nickel/silver, and the inner copper core is mainly copper. 80 may include a plurality of wires 70 formed by coated perforations 52, pads 6 and terminals 66. For ease of explanation, only a single wire 70 is described and illustrated herein. In the wires 70, the perforations 52 are welded. The pad 6 and the terminal 66 generally have similar shapes and sizes. For example, some of the wires are provided with % The pitches are 'separated from each other' and are electrically isolated' and the partial wires 7() are staggered or directed to the same-pad 60 or terminal 66 and electrically connected to each other. Similarly, the trowel pads 60 can be used to receive independent signals. The part of the pad 6 共用 shares a signal, power or ground. The heat conducting plate 80 can be applied to a LED package having blue, green and red led chips, wherein each LED chip comprises an anode and a cathode, and each of the coffee The package package reads the anode terminal and the cathode (four). In this example, the heat conducting plate 80 may include six pads (9) and four terminals 66 for guiding each of the = poles from the independent pads 6G - the individual terminals 66 And each cathode is guided from a separate pad 6 一 to a common ground terminal Μ. The oxides and residues on the exposed metal can be removed by using a simple cleaning step in each of the read sections, for example, the structure of the present invention A short slurry β cleaning step is performed. Alternatively, the structure of the present invention may be subjected to a short wet chemical cleaning step using a potassium permanganate solution. Similarly, the structure may be rinsed with a crucible to remove dirt. This cleaning step can be cleaned The surface does not have a significant influence or damage to the structure. The advantage of this case is that the wire 7G does not need to be separated or divided from the 201218468 outlet point or related circuitry. The junction can form the pad 6 and the flange layer 62. The wet-type chemical is separated in the step of engraving. The heat-conducting plate 80 may include a counter hole (not shown) formed by drilling or cutting through the adhesive layer 3〇 and the substrate 34. Thus, when the heat-conducting plate 8 is in need of subsequent When the process is set in a lower carrier, the tool pins can be inserted into the alignment holes, so that the heat conducting plate 80 is placed in position. The heat conducting plate 80 can accommodate multiple semiconductor components instead of a single bump or multiple The bumps can only accommodate a single semiconductor component. Therefore, one can arrange a plurality of semi-conductor elements on a single bump or a plurality of semiconductor elements on different bumps. If the celebrity allows a single bump of the thermally conductive plate 80 to accommodate a plurality of semiconductor components, additional holes can be drilled to define more of the coated vias 52, the patterned etch stop layer 54 can be modified to define more pads 6〇, and the patterning can be adjusted. Etching the resist layer to define more terminals 66. The coated vias 52, pads 6 and terminals 66 can be changed in lateral position to provide a 2 χ 2 array for the four semiconductor components. In addition, the cross-sectional shape and height (ie, side shape) of the pad 60, the pedestal 64, and the terminal 66 may be adjusted. If a plurality of bumps are to be formed on the heat conducting plate 80 to accommodate a plurality of semiconductor components, an additional bump 16 can be punched on the metal plate 1 , the adhesive g 3 调整 is adjusted to include more openings 32 , and the substrate 34 is adjusted. More vias are included to define additional vias 52, the patterned etch stop 54 is modified to define more pads 60 and flange layers 62, and the patterned etch layer 56 is modified. More base 64 and terminal 66 are defined. The bumps 16, the overlying 塾 60, the flange layer 62, the pedestal 64, and the terminals 66 can change the lateral 55 201218468 position to provide a 2x2 array for the four semiconductor components. Further, the cross-sectional shape and the low cross-sectional shape (i.e., the side shape) of the bump 16, the solder bump 60, the flange layer 62, the susceptor 64, and the terminal 66 may be adjusted. Moreover, the plurality of bumps 16 can have separate pedestals 64 or a common pedestal 64, depending on the design of the patterned etch stop layer 56. 5A, 5B, and 5C are respectively a cross-sectional view of a heat conducting plate according to an embodiment of the present invention. "Top view and bottom view" The peripheral edge of the heat conducting plate is provided with a covered perforation. In this embodiment, the coated perforations are located at the peripheral edges of the thermally conductive plate separated from the adjacent thermally conductive plates of the same batch. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 8A, and corresponding reference numerals are used. The heat conducting plate 82 includes an adhesive layer 30, a substrate 34, a wire 7 and a heat sink 72. Substrate 34 includes a dielectric layer 38. The wire 7A includes a covered perforation 52, a pad 60 and a terminal 66. The heat sink 72 includes a bump 16, a flange layer 62 and a base 64. The coated perforations 52 are located at the peripheral edge of the thermally conductive plate 82 rather than at a distance from the peripheral edge of the thermally conductive plate 82. The coated perforations 52 do not have the shape of a full circumference, but are semi-tubular, i.e., have only a semicircular circumference. Adhesive layer 30 extends laterally from bump 16 to cover via 52, pad 6 and terminal 66, but does not pass over capping 52, pad 6 and terminal 66. In addition, the heat conducting plate 82 is smaller than the heat conducting plate 8A. The heat conducting plate 82 is fabricated in a manner similar to the heat conducting plate 8〇, but must be appropriately adjusted by the 56 5 201218468 overlying perforations 52. For example, the adhesive layer 3 is first placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 3''. The adhesive layer 30 is heated and pressurized to cause the adhesive layer 30 to flow and solidify. The lateral surfaces of the bump 16, the adhesive layer 30, and the conductive layer 36 are planarized by polishing. The overhanging platform 18, the adhesive layer 30, the conductive layer 36, and the dielectric layer 38 are drilled to form the holes 44' and then the coating layers 48, 50 and the coated perforations 52 are deposited onto the structure in the manner previously described. Next, the overhanging platform 18 and the upper cladding layer 48 are etched to form the bonding pad 60 and the flange layer 62, and the conductive layer 36 and the lower cladding layer 50 are etched to form the pedestal 64 and the terminal 66, and then the embossed contacts 74 are convex. Block 16, pad 60, flange layer 62, pedestal 64 and terminal 66 are surface treated. Finally, the adhesive layer substrate 34, the covered perforations 52, the pads 60, the pedestals 64 and the terminals 66 are cut or cleaved at the peripheral edges of the heat conducting plates 82 to separate the heat conducting plates 82 from the other thermally conductive plates produced in the same batch. As a result, one half of the tubular portion of the covered perforation 52 is separated from the peripheral edge of the heat conducting plate 82, and the other half of the tubular portion of the covered perforation 52 remains intact at the peripheral edge of the heat conducting plate 82. 6A, 6B, and 6C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, the bumps of the heat conducting plate having the same spatial extent as the base. In the present embodiment, the bump and the pedestal occupy the same spatial extent. For the sake of brevity, the description of the heat-conducting plate 8 适用 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used. The heat conducting plate 84 includes an adhesive layer 3G, a substrate 34, a wire 7G, and a heat sink 57 201218468 72. Substrate 34 includes a dielectric layer 38. The wire 7A includes a covered perforation 52, a solder joint 6〇 and a terminal 66. The heat sink 72 includes a bump 16, a flange layer 62 and a base 64. The pedestal 64 and the bump 16 have the same spatial extent at the bottom plate 28. Therefore, the pedestal 64 does not extend laterally from the bump 16, and the adhesive layer 3 is exposed outward toward the lower side. In addition, the heat conducting plate 84 is smaller than the heat conducting plate 8〇.

The heat conducting plate 84 is fabricated in a manner similar to the heat conducting plate 80, but must be properly adjusted for the base 64 and the terminal 66 of the mattress 60. For example, the adhesive layer 3 is first placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 3''. The adhesive layer 3G is heated and pressurized to cause the adhesive layer 30 to flow and solidify. The lateral surfaces of the bumps 16, the adhesive layer 3, and the conductive layer % are planarized by polishing. The overhanging platform 18, the adhesive layer 30, the conductive layer 36 and the dielectric layer 38 are drilled to form the holes 44, and then the coating layers 48, 50 and the covered perforations 52 are deposited on the structure in the manner described above, wherein the positions of the holes 44 are Shifting toward the bump 16 laterally 'so the position of the covered perforation 52 is also toward the bump 16

The lateral offsets then form patterned retardation layers 54, 56 on the cladding layers 48, 5q, respectively. The patterned (four) resist layer 54 is adjusted to shrink the size of the solder, and the patterned memory is etched. Layer 56 is also adjusted so that the pedestal 64 is aligned with the bottom plate 28 of the bump 16 and the position of the terminal &amp; is laterally offset toward the convex #16. Then, the overhanging platform 18 and the upper cladding layer μ are formed to form the bonding pad 60 and the flange layer 62, and the conductive layer % and the lower cladding layer μ are decorated to form the pedestal 64 and the terminal 66, and then the overlapping contacts are formed. 74 is a bump 16, a pad edge layer 62, a pad 64 and a terminal 66 for surface treatment. At last,

S 58 201218468 Cutting or splitting the adhesive layer 30 and the substrate 34 at the peripheral edge of the heat conducting plate 84 separates the heat conducting plate 84 from other thermally conductive plates produced in the same batch. 7A and 7C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate t according to an embodiment of the present invention, the heat conducting plate having a thickened base and a * terminal 〇 - in this embodiment, the substrate is a thick conductive Layer and no dielectric layer. For the sake of clarity, the description of the heat-conducting plate 8G is applicable to this embodiment. The same description will not be repeated. Similarly, the elements of the heat conducting plate of the embodiment of the heat conducting plate 80 are similar, and the corresponding reference numerals are used. The heat conducting plate 86 includes an adhesive layer 30, a wire 7 and a heat sink 72. The wire 0 includes a covered hole 52, and the welding塾6〇 and terminal 66. The heat sink Μ includes &amp; 16, the flange layer 62 and the pedestal 64. The conductive layer 36 in the present yoke example is thicker than the conductive layer 36 in the previous embodiment. For example, the conductive layer 36 The thickness is 13 〇 micron (instead of 3 〇 micron), 64, the mountain can prevent the conductive layer from bending or shaking during transportation, and the pedestal _ ', the terminal 66 is also thickened. The heat conducting plate 86 is missing - corresponding The dielectric layer of the dielectric layer is similar to the heat conducting plate 80, but must be properly adjusted for the guiding device. For example, 'the adhesive layer is first placed on the extended T-stage 18, and then The conductive layer 36 is separately disposed on the adhesive layer 3. The adhesive layer 3 is heated and pressurized to cause the adhesive layer 30 to flow and solidify. The side surfaces of the bump 16, the adhesive layer and the conductive layer 36 are polished by grinding. Plane, drill, overhanging flat 18, adhesive layer 30 and conductive layer 36 to form holes 44 and then to cover layer 48 '50 and the coated perforations 52 are deposited on the 59 201218468 structure in the manner previously described. The overhanging platform 18 and the upper cladding layer 48 are then etched to form the pad 60 and the flange layer 62, and the conductive layer % and the lower cladding layer 5 are etched to The pedestal 64 and the terminal 66 are formed, and then the surface of the bump 16, the soldering pad 60, the flange layer 62, the pedestal 64 and the terminal 以 are surface-treated with the covered contact 74. Finally, at the peripheral edge of the heat conducting plate 86 Cutting or splitting the adhesive layer 3 and the substrate 34 to separate the heat conducting plate 86 from other heat conducting plates produced in the same batch. FIGS. 8A, 8A and 8C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the invention. Round, the upper and lower surfaces of the heat conducting plate each have a layer of anti-welding green paint. In this embodiment, the top layer and the bottom layer of the anti-welding green paint are selected as the heat sink. For the sake of simplicity, the relevant description of the heat conducting plate 8. 3 The same applies to the same description. The same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 8Q, and the reference numerals of the deer are adopted. &quot; Thermal Conductive Plate 88 Including adhesive layer 3G, substrate 34, wire %, heat sink and The solder resist green paint 76, 77. The substrate 34 includes a dielectric layer 38. The wire includes a covered via 52, a pad 6G and a terminal 66. The heat sink 72 includes a bump 16, a flange layer 62 and a pedestal 64. 76 ^ - Electrically insulating layer, which can be used to make the bump 16, the solder pad 60 and the flange layer 62 face upward and cover the portion of the layer 30 which is originally exposed upward and outward. A π-electrically insulating layer which, depending on the range selected by us, exposes the susceptor Μ and the end 66 outwardly and covers the portion of the dielectric layer 38 which is originally oriented downwardly outward;

S

60 201218468

The heat conducting plate 88 is fabricated in a manner similar to the heat conducting plate 80, but must be suitably adjusted for the solder resist green paint 76, 77. For example, the adhesive layer 3 is first placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30. The adhesive layer 30 is heated and pressurized to cause the adhesive layer 30 to flow and solidify. The lateral surfaces of the bump 16, the adhesive layer 30, and the conductive layer 36 are planarized by polishing. The overhanging platform 18, the adhesive layer 30, the conductive layer 36, and the dielectric layer 38 are drilled to form the holes 44, and then the coating layers 48, 50 and the covered perforations 52 are deposited on the structure in the foregoing manner. Next, the overhanging platform 8 and the upper cladding layer 48 are sequentially formed to form the bonding pad 60 and the flange layer 62, and the conductive layer 36 and the lower cladding layer 5 are etched to form the pedestal 64 and the terminal 66, and then formed on the top surface of the structure. The solder resist green paint 76 forms a solder resist green paint 77 on the bottom surface of the structure, and then the surface is treated with the bump contacts 74 as the bumps 16, the pads 6〇, the flange layer 62, the pedestal 64 and the terminals . Finally, at the peripheral edge of the heat conducting plate 88, the adhesive layer 30, the substrate 34 and the solder resist green, and the clip 77.. ^ Dan β Ping green paint 76, 77 ' are made at the peripheral edge of the heat conducting plate 88 to make the heat conducting plate 88 and the same batch. Other heat transfer plates are separated. The first step is to apply a light-visible liquid resin coated on the bottom surface of the top surface of the structure, and then form (4). The method is to selectively pass the light through the mask (not shown) to make the part of the light-receiving green. The paint becomes insoluble. After the solution is removed, the unprotected green paint which is not exposed to light and still soluble is removed, and finally hard baked. The above steps are conventional techniques. 9A, 9B & 9C are respectively a cross-sectional view, a plan view, a bottom view, and a green paint in the embodiment of the present invention. _. The heat-conducting plate has a layer-in-line prevention. In this embodiment, the layer of the anti-weld green paint is embedded and interposed between the pad 61 201218468 and the flange layer. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 8A, and the corresponding reference numerals are adopted. The heat conducting plate 90 includes an adhesive layer 3, a substrate 34, a wire 7, a heat sink 72, and a solder resist green paint 76. Substrate 34 includes a dielectric layer 38. Conductor 70 includes coated vias 52, pads 60 and terminals 66. The heat sink 72 includes a bump 16, a flange layer 62 and a pedestal 64. The solder resist green lacquer 76 is an electrically insulating layer that contacts and is interposed between the pad 6 〇 and the flange layer 62 while being recessed relative to the pad 60 and the flange layer 62. The solder resist green paint 76 contacts the adhesive layer 3 and covers the portion of the adhesive layer 3 which is originally exposed upward. The heat conducting plate 90 is fabricated in a manner similar to the heat conducting plate 8〇, but must be appropriately adjusted for the metal plate 10 and the solder resist green paint 76. For example, the metal plate 10 is first etched using a patterned etch stop layer to form a trench on the surface 14 of the metal plate 10, wherein the pattern of the patterned etch stop layer is similar to the patterned etch stop layer 54 but slightly wider . The groove extends into but not through the metal plate 1 so as to maintain a distance from the surface 12, and the groove also defines the lower portion of the pad 6〇 and the lower portion of the flange layer 62. A solder resist green paint 76 is formed in the trench, and then the metal plate 10 is stamped to form the bumps 16. Subsequently, the adhesive layer 3 is placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30. The adhesive layer 30 is heated and pressurized to cause the adhesive layer 3 to flow and solidify. The lateral surfaces of the bump 16, the adhesive layer 30, and the conductive layer 36 are planarized by polishing. Drilling through the overhanging platform 18, the adhesive layer 30, the conductive layer 36 and the dielectric layer 38 to form the holes 201218468 44-(......., then the covering layers 48, 50 and the covered perforations 52 are previously described The method is deposited on the structure. Then, the upper coating layer 48 is separately etched to form the upper portion of the bonding pad 60 and the upper portion of the flange layer 62, and the solder resist green paint 76 is exposed but the adhesive layer 3 is not exposed. Further, the conductive layer is etched. The layer 36 and the lower cladding layer 50 are formed to form the pedestal 64 and the terminal 66, and then the surface of the ferrule 16, the pad 60, the flange layer 62, the pedestal 64 and the terminal 66 are surface-treated with the other contact points 74. Finally, The adhesive layer 30, the substrate 34 and the solder resist green paint 76 are cut or cleaved at the peripheral edge of the heat conducting plate 90, so that the heat conducting plate 9 is separated from the other heat conducting plates produced in the same batch. Initially, the solder resist green paint 76 is coated. The light developing liquid resin is disposed on the surface 14 of the metal sheet 1 and fills the groove. When the liquid resin is applied, the metal plate 1G can be inverted to face the surface 14 to facilitate the liquid resin. It flows into the groove by gravity, and then the solder resist green paint is hardened by hard baking, 9 which is a conventional technique. Turn the metal plate 1〇 so that the surface is facing down,

The sliding splicing side bottom surface, and the solder resist green paint 76 is located in the groove. The face is flat in the downward direction and is filled in the groove. 63 201218468 FIGS. 10A, 10B and 10C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the present invention, which can provide horizontal signal routing. In this embodiment, the pads and the terminals are both located above the adhesive layer and the dielectric layer. Further, in this embodiment, the covered vias are omitted. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the elements of the heat conducting plate of the present embodiment are similar to those of the heat conducting plate 8'. The heat conducting plate 92 includes an adhesive layer 3, a substrate 34, a wire 7', a heat sink 72, and a solder resist green paint 76. Substrate 34 includes a dielectric layer 38. The conductor includes a solder wire 60, a routing line 65 and a terminal 66. The heat sink 72 includes a bump 16, a flange layer 62 and a base 64. Wire 70 provides a horizontal (lateral) routing from pad 60 to terminal 66, while routing line 65 forms a conductive path between pad 6 and terminal pad. The solder bumps 65, routing lines 65 and terminals + 66 are all over the adhesive layer 30, contacting the adhesive layer 3 but maintaining a distance ' from the dielectric layer 38 while overlapping the dielectric layer 38. The soldering potential 60 is coplanar with the terminal 66 above the adhesive layer 3(). The pedestal 64 covers the bumps 16, the adhesive layer 3, the substrate 34, the flange layer 62' wire 70 and the anti-U paint 76' from the lower side and the pedestal 64 extends to the peripheral edge of the heat conducting plate 92. P-square solder green paint 76 is an electrically insulating layer that selectively exposes the bumps, the solder bumps 6〇 flange layer 62 and the terminals 66' from above to cover the routing lines 65, and extends the peripheral edge of the board 92 Therefore, the wire 70 is separated from the dielectric layer 38, the temple is large, and the heat conducting plate 92 lacks a coated perforation corresponding to the covered perforation 52. 201218468 The heat conducting plate 92 is fabricated in a manner similar to the heat conducting 8〇, but must be the pedestal 64 The wire 7G and the solder resist green paint 76 are appropriately adjusted. For example, the adhesive layer 30 is first placed on the (four) platform 18, and then the substrate 34 is placed on the adhesive layer 30 1. The adhesive layer 30 is heated and pressurized to make an adhesive layer. 3〇 flowing and solidifying. The lateral surfaces of the bump 16, the adhesive layer 3, and the conductive layer % are planarized by grinding, and then the coating layers 48, 5 are deposited on the structure in the aforementioned manner. The coated vias 52 are also absent. The overhanging platform 18 and the overlying layer Μ are then etched using a single-patterned etch stop to form the solder bumps 60, &lt; the edge layer 62, the routing lines 65 and the terminal %, as to the conductive layer 36. And the lower cladding layer 50 maintains a state without a pattern. After the surface is formed with the solder resist green paint 76, the surface is treated by the bumps 74, the bumps 16, the solder bumps 60, the flange layer 62, the pedestal 64 and the terminal %. Finally, at the peripheral edge of the heat conducting plate 92. The adhesive layer 3q, the substrate ^, the pedestal 64 and the solder resist green lacquer 76 are cut to separate the heat conductive plate % from the other heat conductive plates produced in the same batch. The solder resist green paint 76 is initially applied to the top surface of the structure. - the patterning of the liquid-developing liquid resin is followed by a pattern in which the light is selectively transmitted through the mask (Fig. 7F) so that part of the solder resist green paint of the t-light becomes insoluble and then the developing solution is used to remove the un-lighted and still A part of the heat-resistant plate is a cross-sectional view, a top view and a bottom view of a heat-conducting plate according to an embodiment of the present invention, which is a part of the heat-resistant plate. Having a raised edge 〇 In this embodiment, a raised edge is disposed on the top surface of the structure. For the description of 65 201218468, the description of the heat conducting plate 80 is applicable to the embodiment. Do not repeat" Similarly, this implementation For example, the components of the heat conducting plate are similar to those of the heat conducting plate 80. The heat conducting plate 94 includes an adhesive layer 30, a substrate 34, a wire 7A, a heat sink 72 and a raised edge 78. The substrate 34 includes a dielectric layer. 38. The wire 70 includes a covered perforation 52, a pad 60 and a terminal 66. The heat sink 72 includes a bump 16, a flange layer 62 and a base 64.

The raised edge 78 is a square frame that contacts the bond pad 60 and extends over the solder fillet 60. Both the projection 16 and the flange layer 62 are located at a central position within the periphery of the ridge edge %. For example, the height of the raised edge 78 is _micron, the width (distance between the inner and outer sidewalls) is micrometers, and the lateral spacing of the raised edge Μ and the flange layer 62 is 5 〇〇 micrometers. However, for ease of illustration, the raised edge 78 is only in the figure as a single layer body. The solder resist green paint contacts the laminate and extends over it, thereby forming a side. The film (four) is connected to the laminate and is stretched underneath, thus opening

- Bottom. The body contacts and (4) fits between the solder resists. The solder resist green paint m 3 composite and the film adhesive are both electrical phase edges 0, for example, the anti-media, the jg, the green paint is 50 microns thick, the laminated body is thick, the film adhesive The thickness of the material is half a m ^ 畛 hand 刈 micro water, therefore, the edge of the ridge is 78 microns (50 + 500 + 50). The orientation is such that the laminate can be a plurality of organic and inorganic dielectric dielectric films. For example, the ingredients made by the righteous person are "imine or looking for a 4-ring gas injection but can also be used such as a multi-bureau ώ μ 氧 秘 · · b b b h h h (ΒΤ)

S 66 201218468 He epoxy resin. Alternatively, the raised edge 78 can comprise a metal ring disposed on the film-like adhesive. The heat conducting plate 94 is fabricated in a manner similar to the heat conducting plate 8〇, but must be appropriately adjusted for the raised edge 78. For example, the adhesive layer 3 is first placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 3''. The adhesive layer 3 is heated and pressurized to cause the adhesive layer 3 to flow and solidify. The lateral surfaces of the bumps 16, the adhesive layer 30 and the conductive layer 36 are planarized by grinding, and then the overhanging platform 18, the adhesive layer 30, the conductive layer 36 and the dielectric layer % are drilled to form the holes 44, which are then covered. Layers 48, 5 and coated perforations 52 are deposited on the structure in the manner previously described. Next, the overhanging platform 18 and the upper cladding layer 48 are etched to form the pad 60 and the flange layer 62, the conductive layer 36 and the lower cladding layer 50 are etched to form the pedestal 64 and the terminal 66, and then the ridged edge 78 is placed on the top of the structure. surface. The bumps 74 are then surface treated with bumps 16, pads 6A, flange layer 62, pedestal 64 and terminals 66. Finally, the adhesive layer 3 and the substrate 34 are cut or cleaved at the peripheral edge of the heat conducting plate 94 to separate the heat conducting plate 94 from the other heat conducting plates produced in the same batch. 12A, 12B and 12C are respectively a cross-sectional view, a top view and a bottom view of a half-conductor chip assembly according to an embodiment of the present invention, the semiconductor wafer assembly comprising a heat conducting plate, a semiconductor component and a packaging material. In this embodiment, the semiconductor component is a blue-emitting LED chip which is disposed on the bump and electrically connected to the pad by a wire, and is thermally bonded to the bump by a die bonding material. The LED chip is covered by a packaging material that converts blue light into white light. The semiconductor wafer package 100 includes a heat conducting plate 8 , an LED chip 1 2 , 67 201218468 a wire 104 , a solid crystal material i 〇 6 , and a packaging material 1 〇 8 e LED wafer ι 2 includes a top surface 11G, a bottom surface 112 and a wire bonding塾114. The top surface UG is the active surface and includes the wire bonding pads 114, while the bottom surface 112 is the thermal contact surface. The LED chip 102 is disposed on the heat sink 72, electrically connected to the wire 70, and thermally coupled to the heat sink 72. In detail, the wafer 1() 2 is disposed on the bump 16 and overlaps the bump 16 but does not overlap the substrate 34 or the wire 7?. The LED chip 102 is laterally surrounded by the bumps 16 and the adhesive layer 3〇 and electrically connected to the bonding pads 6〇 via the bonding wires 1〇4, and is thermally bonded and mechanically adhered to the bumps 16 by the bonding material 〇6. . In addition, the bump 16 covers the LED chip 1〇2 from below, and provides a concave wafer holder for the LED chip 1〇2 and a reflector 8 LED has a thickness of 150 μm, and the thickness of the solid crystal material is 1〇. The thickness of 6 is 25 micrometers. Therefore, the combined height of the LED wafer 1〇2 and the underlying solid crystal material 1〇6 is 175 μm, which is 75 μm less than the depth of the recess 2〇 (25 μm). The length and width of the LED chip 1〇2 are both 5 μm. The LED chip 1〇2 and the die-bonding material 1〇6 are both located in the recess 2〇, and the bonding wire 104 and the encapsulating material 1 both extend inside the cavity 2〇, and the substrate and the wire 70 are located outside the cavity 20. The bonding wires 1 to 4 are connected to and electrically connected to the bonding pads 60 and the bonding pads 114, thereby electrically connecting the LED chips 1〇2 to the terminals 66. The die attach material 1〇6 is in contact and is located between the bump 16 and the thermal contact surface 112 while thermally bonding and mechanically bonding the bump 16 to the thermal contact surface 112&apos; thereby thermally bonding the LED wafer 102 to the pedestal 64. The encapsulating material 108 is a solid electrical insulating protective covering for converting color, which can provide moisture resistance for the LED chip 1〇2 and the wire 1〇4 and 201218468

Anti-particle and other environmental protection. The encapsulating material 1〇8 contacts the bump W in the recess 2〇, and the bonding material 102′ is bonded to the bonding material 106, and contacts the n-electrode layer 38, the bonding pad 60 and the flange layer 62 in the recess 20. However, the encapsulating material 1 〇 8 is kept at a distance from the adhesive layer 30, the covered perforations 52, the susceptor 64, and the terminal %. The encapsulation material 108 fills the remaining space within the pocket 2 and seals the led wafer 102 within the recess 2'. In addition, the encapsulating material 1〇8 covers the convex layer 16 of the convex ghost layer 62, the LED wafer 102, the bonding wire 104 and the solid crystal material 106° from above. The pad 60 is provided with a nickel/silver coated metal pad to facilitate the bonding of the wire 104. Stable bonding, thereby improving signal transmission from the wire 70 to the LED chip 1〇2. The bump 16 is also provided with a nickel/silver coated metal pad to securely bond with the die bonding material ι 6 to improve heat transfer from the LED chip 1 〇 2 to the heat sink 72. In addition, a nickel/silver coated metal pad is also provided on the flange layer 62. Thus, the bumps 16, pads 60 and flange layer 62 provide a highly reflective surface that reflects the light from the LED wafer 1 射 2 toward the silver surface layer, thereby increasing the amount of light exiting in the upward direction. • LED chip 1〇2 is a compound semiconductor that emits blue light and has high luminous efficiency and forms a p-n junction. Suitable compound semiconductors include gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (Gap), gallium arsenide (GaAsp), gallium phosphide (GaAlP), gallium arsenide (GaA1As), Indium phosphide (Inp) and indium gallium phosphide (InGaP). In addition, the amount of light emitted by the LED chip 1〇2 is high but also generates considerable thermal energy. The encapsulating material 108 comprises a transparent epoxy resin and a yellow phosphor (indicated by black dots in Figure 12A). For example, the enamel resin may be a polyoxynium oxide 69 201218468 alkane resin, and the yellow phosphor may be a yttrium-doped yttrium aluminum garnet (Ce:YAG) fluorescent powder. The yellow phosphor emits yellow light when it is irradiated with blue light, and the blue and yellow light are mixed to form white light. Therefore, the package material #1〇8 can convert the blue light emitted by the LED chip 1G2 into white light to make the group! (10) Become a white light source. In addition, the encapsulating material 108 is in the shape of a hemispherical dome which provides a convex refractive surface to concentrate the white light upward. If the semiconductor wafer package 100 is to be fabricated, the LED crystal material #102 can be disposed on the bumps 16 by using a solid crystal material, and then the bonding pads and the bonding pads 114 are bonded, and finally the packaging material is 〇8. Forming. For example, the die bond material 106 is originally a silver-containing epoxy resin paste having high thermal conductivity and is selectively printed on a portion of the bumps 16 located in the recesses 18 by screen printing. The LED wafer 1 () 2 is then placed on the epoxy resin paste in a step-and-repeat manner using a gripping head and an automated round disc identification system. The epoxy silver paste is then heated to harden at a relatively low temperature (e.g., 19 〇 sC) to complete the die bonding. The wire 1〇4 is a gold wire, which is then connected to the wire pad 114 and the wire bonding pad 114 by thermal ultrasonic waves. Finally, the encapsulating material 1〇8 is molded on the structure. The LED chip 1〇2 can be electrically connected to the soldering pad through a plurality of connecting media. The jacquard J is thermally bonded by a plurality of thermal adhesives and mechanically adhered to the heat sink 7 2 and packaged in a plurality of packaging materials. The βH semiconductor wafer package 100 is a first-level single crystal package. 13A, 13A and 13C are respectively a cross-sectional view, a plan view and a bottom view of a half-conductor chip assembly according to an embodiment of the present invention, the semiconductor wafer assembly comprising - a heat conducting plate, a semiconductor element, a packaging material and a lens.

S 70 201218468 In this embodiment, the semiconductor component is covered by a packaging material for converting color and a transparent lens. For the sake of brevity, the relevant description of the group (10) is applicable to this embodiment and is incorporated herein. Similarly, the components of the group of the present embodiment are identical to those of the group (10), but the base number of the code is changed from (10) to fine. For example, the LED chip 202 corresponds to (4) the cymbal 1 〇 2, the wire 2 〇 4 corresponds to the wire 1 〇 4, and so on. The semiconductor wafer package 200 includes a heat conductive plate 80, an LED wafer 202, a wire 2〇4, a die bonding material 2〇6, a sealing material 2〇8, and a lens w. The coffee wafer 202 includes a top surface 210, a bottom surface 212 and a wire bonding pad 2i4. The top surface 210 is the active surface and includes a wire bond 214, while the bottom surface 212 is a hot contact surface. The LED chip 202 is disposed on the heat sink 72, electrically connected to the wire 7' and thermally coupled to the heat sink 72. In detail, the LED chip 2() 2 is disposed on the bump 16 and is electrically connected to the solder bump 6 via the bonding wire 204, and is thermally coupled via the bonding material 206 and mechanically adhered to the bump 16. The encapsulating material 208 contacts the bumps 16, the LED chips 2〇2, the bonding wires 204, and the die bonding material 2〇6 in the recesses 20, but is spaced apart from the adhesive layer 3〇, the dielectric layer %, the susceptor 64, and the wires 70. The encapsulating material 208 fills the remaining space in the recess 2, seals the LED wafer 202 within the recess 2, and covers the LED wafer 202 from above. The encapsulating material 208 extends 1 micron above the pocket 20 and is constrained by the pocket 20 in its lateral extent. In addition, the cover material 2〇8 is located almost entirely within the pocket 20 and provides partial protection only for the wire 2〇4. Since the pocket 20 has a stamped, precisely controlled and well defined space 71 201218468, we only need to apply a small amount of encapsulating material 2〇8, and the amount is fixed. The lens 216 is a transparent plastic upper cover which has an arcuate hollow dome (like a hemisphere) disposed on the top surface of the structure to provide environmental protection such as moisture resistance and particle resistance for the wire 2〇4 and the encapsulating material 208. The lens 216 contacts the pad 60' but is spaced from the adhesive layer 3, the dielectric layer 38, the covered via 52, the terminal 66, the heat sink 72, the LED wafer 202, the wire 204, the die attach material 206, and the package material 208. The lens 216 covers the bump 16, the flange-layer 62, the LED chip 202, the wire 204, the die bonding material 206, and the encapsulating material 208 from above. Further, the lens 216 contains transparent plastic but does not contain fluorescent powder, so _ cannot be converted. Light color. The blue light emitted from the LED chip 202 is converted into white light via the encapsulating material 2〇8, and then emitted through the lens 216, thereby making the assembly 200 a white light source. In addition, the convex refractive surface formed by the hemispherical dome of the lens 216 concentrates the white light emitted by the encapsulating material 208 in the upward direction. Since the volume of the encapsulating material 208 is much smaller than the encapsulating material 1〇8, and the lens 216 does not need to contain phosphor or phosphor powder, the structure is highly cost-effective. If the semiconductor wafer package 200 is to be fabricated, the die bonding material 206 can be used to place the LED chip 202 on the bumps 16 and then wire bond the bonding pads 60 to the bonding pads 214. Then, an A-stage uncured epoxy type encapsulant 208 is deposited in the recess 20 and the LED wafer 202 is printed by screen printing or by a stepwise repeating application through a nozzle. Hit line 204. The liquid epoxy will fill the remaining space in the pocket 20 and extend slightly above the pocket 20. At this time, the recess 20 acts as the same dam to limit the lateral extent of the liquid epoxy. Then at a relatively low temperature (eg

S 72 201218468 190eC) The liquid epoxy resin is heated to harden it, thereby converting the liquid A-stage uncured epoxy resin into a c-stage cured or hardened epoxy resin. Finally, the lens 216 is placed on the structure. The semiconductor wafer package 200 is a first-level single crystal package. 14A, 14B, and 14C are respectively a cross-sectional view of a half-conductor chip assembly in accordance with an embodiment of the present invention. The semiconductor wafer assembly includes a heat conducting plate, a semiconductor element, and a two-layer packaging material. In this embodiment, the semiconductor component is covered by a packaging material for converting color and a transparent encapsulating material. For the sake of brevity, the description of the group 2 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the group of the embodiment are similar to those of the component of the group 2, and the corresponding reference numerals are used, but the base number of the code is changed from 2 to 300. For example, the LED chip 3〇2 corresponds to the LED chip 2〇2, the wire 3〇4 corresponds to the wire 204, and so on. The semiconductor wafer package 300 includes a heat conductive plate 80, an LED chip 3〇2, a wire bonding 304, a die bonding material 306, and packaging materials 3〇8, 318. The led wafer 3〇2 includes a top surface 31〇, a bottom surface 312, and a wire bonding pad 314. The top surface is an active surface and includes a wire bonding pad 314, and the bottom surface 312 is a thermal contact surface. The LED chip 302 is disposed on the heat sink 72, electrically connected to the wire 〇, and thermally coupled to the heat sink 72. In detail, the LED chip is disposed on the bump 16 and electrically connected to the pad 6 through the wire 3〇4, and is thermally coupled via the die bond material 306 and mechanically adhered to the bump 16. The encapsulation material 308 covers the LED wafer 302 from above, and almost all of the 73 201218468 is located within the pocket 20. The encapsulating material 318 is a solid electrically insulating transparent protective covering body, which can provide environmental protection for moisture-proof fishing and anti-particles for the wire 104 and the material. The encapsulating material 318 contacts the adhesive layer 30, the bonding pad 60, the flange layer 62, the bonding wires 304, and the encapsulating material 308' but with the bump 16, the dielectric layer 38, the covered via 52, the pedestal 64, the terminal 66, the LED chip 302, and Solid crystal material 3〇6 · Keep the distance. The encapsulating material 318 covers the bumps 16, the flange layer 62, the wafer wafer, the wire bonding, the die bonding material 306, and the encapsulating material 3〇8 from above. In addition, the package (4) 318 contains transparent stone oxide resin but does not contain the work powder, and therefore cannot convert the light color. The blue light emitted by the LED chip 3〇2 is converted into light through the encapsulating material and then 'passes through the encapsulating material 318', thereby making the group fine into a white light source. Further, since the encapsulating material 318 is a hemispherical dome shape, the convexity is formed. The refractive surface can concentrate the white light of the encapsulating material 318 # toward the upper layer. Furthermore, since the encapsulating material is much smaller than the encapsulating material and the encapsulating material 318 does not need to contain phosphor or fluorescent powder, the cost is beneficial. Very high σ

If the semiconductor wafer package 300 is to be fabricated, the die bonding material _ LED wafer 302 can be disposed on the bumps 16 and then bonded to the bonding pads 6 to the bonding pads 314. Then use the pocket 2 as a &quot; material 3. 8 and solidify it, most: reshape. (4) Molding the encapsulating material 318 a The semiconductor wafer package is a first-order single crystal package. The 15th and 8th drawings are respectively the invention - the embodiment - the semi-guide

S 74 201218468 A cross-sectional view, a top view, and a bottom view of a bulk wafer assembly including a thermally conductive plate having raised edges, a semiconductor component, and a two-layer package. In this embodiment, the semiconductor component is covered by a packaging material for converting color and a transparent encapsulating material. For the sake of brevity, the descriptions of the components are applicable to this embodiment, and the same description will not be repeated. Similarly, the elements of the embodiment of the present embodiment are similar to those of the group 3, and the corresponding reference numerals are used, but the base number of the code is changed from 300 to 400. For example, LED chip 402 corresponds to LED chip 3〇2, wire bonding 4〇4 corresponds to wire bonding 304, and so on. The semiconductor wafer package 400 includes a thermally conductive plate 94, an LED wafer 402 'wire 404' die bonding material 406, and encapsulation materials 408, 418. The LED wafer 402 includes a top surface 410, a bottom surface 412, and a wire bonding pad 414. The top surface 410 is an active surface and includes a wire bonding pad 414' and the bottom surface 412 is a thermal contact surface. The LED chip 402 is disposed on the heat sink 72, electrically connected to the wire 7' and thermally coupled to the heat sink 72. In detail, the LED chip 4〇2 is disposed on the bump 16 and electrically connected to the pad 6〇 via the bonding wire 404, and is thermally coupled through the solid crystal material 406 and mechanically adhered to the bump 16. The encapsulating material 408 covers the LED wafer 4〇2 from above and is located almost entirely within the recess 20. The encapsulating material 418 covers the wire bonding and encapsulating material 408 from above and is located outside the recess 2G. The encapsulating material 418 also contacts the raised edge 78 and is constrained by the raised edge 78 in its lateral extent. The blue light emitted by the LED chip 402 is completely converted into white 75 201218468 light through the encapsulating material, and then passes through the encapsulating material 418 to emit light, thereby making the assembly 400 a white light source. If the semiconductor wafer package 4 is to be fabricated, the LED wafer 402 can be placed on the bumps 16 by using the die bonding material 4〇6, and then the bonding pads 6〇 and the bonding pads 414 can be bonded. Next, the recess 2 is used as a dam, and the encapsulating material 408 is deposited therebetween and solidified. Finally, the embossed edge 78 is used as a dam body to deposit the encapsulating material 418 therebetween and solidify it. The semiconductor wafer package 400 is a first-level single crystal package. 16A, 16B, and 16C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package including an embossed edge heat conducting plate, a semiconductor component, a package material, and a bottom view of the semiconductor wafer package. One cover. In this embodiment, the semiconductor component is covered by a packaging material for converting color and a transparent upper cover. For the sake of brevity, the relevant descriptions of the components are applicable here. The same description will not be repeated. Similarly, the components of the assembly of this embodiment are similar to those of the components of the group 4, and the corresponding reference numerals are used, but the base number of the code is changed from 4 to 500. For example, LED die 502 corresponds to LED die 4〇2, wire bond 504 corresponds to wire bond 404, and so on. The semiconductor wafer package 500 includes a heat conducting plate 94, an LED chip 5〇2, a wire 504, a die bonding material 506, a sealing material 5〇8, and an upper cover 52〇. The wafer 502 includes a top surface 510, a bottom surface 512, and a wire bonding pad 514. Top surface 510 is the active surface and includes a wire bond 514, while bottom surface 512 is a hot contact surface.

The 76 S 201218468 LED chip 502 is disposed on the heat sink 72, electrically connected to the wire 70, and thermally coupled to the heat sink 72. In detail, the LED chip 502 is disposed on the bump 16 and electrically connected to the pad 60 via the bonding wire 504, and is thermally coupled through the solid crystal material 506 and mechanically adhered to the bump 16. The encapsulation material 508 covers the LED wafer 502 from above and is located almost entirely within the recess 20. The upper cover 520 is a glass plate disposed on the raised edge 78 to provide environmental protection against moisture and particulates for the wire 504 and the encapsulating material 508. The upper cover 520 contacts the raised edge 78, but is spaced from the adhesive layer 30, the dielectric layer 38, the wire 70, the heat sink 72, the LED wafer 502, the wire 504, the die attach material 506, and the encapsulating material 508. The upper cover 520 covers the bump 16, the flange layer 62, the LED wafer 502, the wire 504, the die bonding material 506, and the encapsulating material 508 from above. In addition, the upper cover 520 contains transparent glass but does not contain fluorescent powder, and thus cannot convert the color of light. After the blue light emitted from the LED chip 502 is converted into white light via the encapsulating material 508, the light is emitted through the upper cover 520, thereby making the assembly 500 a white light source. If the semiconductor wafer package 500 is to be fabricated, the LED wafer 502 can be placed on the bumps 16 by the die bonding material 506, and then the bonding pads 60 and the bonding pads 514 can be bonded. Next, the recessed six 20 is used as a dam, and the encapsulating material 508 is deposited therebetween and solidified. Finally, the upper cover 520 is placed on the raised edge 78. The semiconductor wafer package 500 is a first-level single crystal package. 17A, 17B, and 17C are respectively a cross-sectional view, a top view, and a bottom view of a half-guide 77 201218468 body wafer assembly including an embossed edge heat conducting plate, a semiconductor component, and a first embodiment of the present invention. Upper cover 0 In this embodiment, the semiconductor component is a white light-emitting LED chip and is covered by a transparent upper cover. For the sake of brevity, the relevant description of the group is applicable here. The same description is not to be repeated. Similarly, the components of the group of the present embodiment are similar to those of the component of the group 5, and the corresponding reference numerals are used, but the base number of the code is changed from 5 〇〇 to 6 〇〇. For example, the 'LED wafer 602 corresponds to the LED chip 502, the wire 604 corresponds to the wire 504, and so on. The semiconductor wafer package 600 includes a heat conductive plate 94, an LED wafer 602, a wire bonding 604, a die bonding material 606, and an upper cover 620. The LED wafer 602 includes a surface 610, a bottom surface 612, and a wire bonding pad 614. Top surface 610 is the active surface and includes wire bonding pads 614, while bottom surface 612 is the thermal contact surface. The LED chip 602 is disposed on the heat sink 72, electrically connected to the wire 70' and thermally coupled to the heat sink 72. In detail, the LED chip 602 is disposed on the bump 16 and electrically connected to the pad 6 through the wire 604, and is thermally bonded by the solid material 606 and mechanically adhered to the bump 16. The upper cover 620 is a glass plate disposed on the raised edge 78 to provide environmental protection against moisture and particulates for the LED chip 602 and the wire 604. The upper cover 620 contacts the raised edge 78 but is spaced from the adhesive layer 30, the dielectric layer 38, the wires 70, the heat sink 72, the LED wafer 602, the wire 604, and the die attach material 606. The upper cover 620 covers the bump 16, the flange layer 62, the LED wafer 602, the wire 604, and the die bonding material 606 from above. In addition, the upper cover 62〇 201218468 contains clear glass but does not contain fluorescent powder, so the color cannot be converted. (4) The white light emitted from the wafer 602 passes through the upper cover 62 to emit light, and therefore, the assembly 600 is a white light source. If the semiconductor wafer package is to be fabricated, the LED wafer 602 can be disposed on the bumps 16 by using the die bonding material 606, and then the bonding pads 6 and the bonding pads 614 are bonded. Finally, the upper cover 620 is placed on the raised edge 78. The semiconductor wafer package 600 is a first-level single crystal package.

The semiconductor wafer package and the heat conducting plate described above are merely illustrative examples, and the present invention can be implemented in various other embodiments. In addition, the above embodiments may be used in combination with or in combination with other embodiments in accordance with the X and the guilty. For example, the substrate can comprise a complex array of single layer conductors and a plurality of layers of multilayer conductors. The thermally conductive plate may comprise a plurality of bumps, and the bumps are arranged in an array for use by a plurality of semiconductor components. In addition, the heat conducting plate is matched with additional semiconductor components, and more H heat conducting plates may also include solder resist green paint extending over the pads, bumps and flange layers and selectively exposing the three. Tan green paint is placed on the edge of the ridge. The thermally conductive plate may also include covered perforations on the peripheral edge and in-line anti-weld green paint. The semiconductor component may be covered by a transparent, translucent or opaque encapsulation material in a first-perpendicular direction, and/or covered by a transparent, translucent or opaque upper cover. For example, the semiconductor component of the present invention may be a blue-emitting LED. The wafer is covered by a transparent encapsulating material or an upper cover to make the group a blue light source; or the LED chip is covered by a packaging material or an upper cover for converting colors, thereby making the group A green, red or white light source. Similarly, the semiconductor component of the present invention can be an LED package having a plurality of LED 79 201218468 wafers. And the heat conducting plate can contain more wires to share the heat sink with the additional conductor elements. . For example, a single semiconductor component can be set

The semiconductor component of the present invention can be used alone or in combination with other semiconductor wafers which are optical or non-optical. For example, the cymbal can be an LED, an infrared (ir) 4 detector, a solar cell, a microprocessor, a controller, or a radio frequency (RF) power amplifier. Similarly, the semiconductor package of the present invention can be an LED package or a radio frequency module. Thus, the semiconductor component of the present invention can be an optical or non-optical wafer that is packaged or unpackaged. In addition, a variety of bonding media can be used to mechanically bond, electrically connect, and thermally bond semiconductor components to a thermally conductive plate, including by soldering and using conductive and/or thermally conductive adhesives. The heat sink of the present invention can quickly, efficiently and evenly dissipate the heat generated by the semiconductor component to the next layer without passing heat through the adhesive layer, the substrate or the heat conducting plate. In this way, the adhesive layer having a lower thermal conductivity can be used, thereby greatly reducing the cost. The heat sink can include integrally formed bumps and flange layers ′ and a pedestal that is metallurgically bonded and thermally coupled to the bumps for improved reliability and reduced cost. In addition, the bumps can be tailored to the semiconductor component 'and the pedestal can be tailored to the next layer' to enhance the thermal connection from the conductor element to the lower-layer body. For example, the bottom plate of the bump may be square or rectangular, and the side shape of the bump may be the same as or similar to the shape of the side of the thermal junction of the semiconductor element. In either of the above designs, the heat sink can be constructed with a variety of different thermally conductive metal structures.

The heat sink can be electrically or electrically isolated from the semiconductor component and the substrate. For example, the solid crystal material may have electrical conductivity, or a routing line above the adhesive layer and the dielectric layer may electrically connect the bonding pad and the flange layer, or the routing line under the adhesive layer and the dielectric layer may be The base and the terminal are electrically connected to electrically connect the heat sink to the semiconductor component. The heat sink can be further electrically grounded to electrically ground the semiconductor component. The bumps can be formed with the flange layer body and thus become a single metal body (e.g., copper or aluminum). The bumps may also be integrally formed with the flange layer such that the interface between the two comprises a single metal body (e.g., copper), while other locations include other metals (e.g., a spot). The bumps may also be integrally formed with the flange layer, and the two layers of the bread may be formed as a metal body (e.g., a nickel buffer layer is disposed outside the aluminum core and a copper layer is disposed on the nickel buffer layer). The earth seat provides mechanical support for the substrate. For example, the pedestal prevents the sheet from bending and deforming during metal grinding, wafer placement, wire bonding, and molding of the packaging material. Further, the portion f of the base may include a tab projecting in a downward direction. For example, a rig can be used to cut the exposed lateral surfaces of the pedestal to form lateral grooves, and the lateral grooves form fins. In this case, the thickness of the pedestal may be 500 microns, and the depth of the aforementioned grooves may be 300 micrometers, i.e., the height of the fins may be &amp; 300 microns. The fins increase the surface area of the pedestal, and the swarf is exposed to the air, rather than being disposed on the device, to enhance the thermal conductivity of the susceptor via thermal convection. The susceptor can be formed by a variety of deposition techniques after the adhesive layer is cured, including single or multi-layer structures by electroplating, electroless plating, evaporation, and sputtering. The base can be made of the same or different metal material as the bump. Additionally, the pedestal can span the via and extend to the substrate or within the perimeter of the via. Thus, the pedestal can contact or remain at a distance from the substrate. In either case, the pedestals abut the bumps ' and project perpendicularly from the bumps in a direction away from the pockets. The adhesive layer of this case provides a strong mechanical bond between the heat sink and the substrate. For example, the adhesive layer can extend laterally from the bump and over the wire to the peripheral edge of the assembly. The adhesive layer fills the space between the heat sink and the substrate, and is a non-porous structure with a uniform distribution of bonding wires. The adhesive layer also absorbs the mismatch between the heat sink and the substrate due to thermal expansion. The material of the adhesive layer may be the same as or different from the dielectric layer. In addition, the adhesive layer can be a low cost dielectric and does not require high thermal conductivity. Furthermore, the adhesive layer of this case is not easily delaminated. We can adjust the thickness of the adhesive layer so that the adhesive layer substantially fills the gap and allows almost all of the adhesive to be in the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error. Similarly, we can also adjust the thickness of the dielectric layer to achieve this effect. The substrate of the present invention can be a low cost laminated structure and does not require high thermal conductivity. Further, the substrate may comprise a single conductive layer or a plurality of conductive layers. Furthermore, the substrate may comprise or consist of a conductive layer. The conductive layer can be separately disposed on the adhesive layer. For example, a via hole may be formed on the conductive layer 201218468, and then the conductive layer is disposed on the adhesive layer, so that the conductive layer contacts the adhesive layer to expose the upward direction, and at the same time, the convexity extends into the through hole, and It is exposed outward through the through hole. In this case, the conductive layer may have a thickness of 100 to 200 micrometers, for example, 125 micrometers, and the thickness is thick enough on the one hand, so that it is not very rough when transported, and the thinner double is thinner on the one hand. The pattern can be formed without excessive etching. The conductive layer and the dielectric layer may also be disposed on the adhesive layer. For example, a conductive layer may be first disposed on the dielectric layer, and then a via hole is formed on the conductive layer and the dielectric layer, and then the conductive layer and the dielectric layer are disposed on the adhesive layer, so that the conductive layer faces Exposed in an upward direction, and the dielectric layer is in contact with and between the conductive layer and the layer, thereby separating the conductive layer from the adhesive layer, and the bump extends into the through hole. And exposed outward through the through hole. In this case, the conductive layer may have a thickness of 10 to 50 micrometers, for example, 30 micrometers, which is thick enough to provide reliable signal transmission, and is thin enough to reduce weight and cost. In addition, the dielectric layer value is part of the heat conducting plate. The conductive layer and the carrier may also be disposed on the adhesive layer at the same time. For example, a thin film can be used to adhere a layer of conductive material such as a shovel, such as a double-oriented polyethylene terephthalate film (Mylar), # &amp; no + body, and then only The conductive layer is formed on the conductive layer instead of the via hole, and then the conductive layer and the carrier are disposed on the adhesive layer, so that the carrier covers the conductive layer and the electrical layer is exposed outwardly and exposes the film. And between the carrier and the conductive conductive layer, as the conductive layer contacts and is between the ;; 4 film and the adhesive layer between ρ彳., S, at the same time, the bump The through hole is aligned and covered by the carrier from above. After the (four) layer is cured, the film is decomposed by ultraviolet light to remove the carrier from the conductive layer, so that the conductive layer is exposed outwardly, and then the conductive layer can be polished and patterned. The layers form a pedestal and a terminal. In this case, the conductive layer may have a thickness of 10 to 50 micrometers, for example, 30 micrometers, which is thick enough on the one hand to be sufficient for reliable signal transmission, and thin on the one hand to reduce weight and cost; The thickness of the carrier can be 300 to 5 micrometers, and the thickness is one side. The surface is thick enough, so that it does not bend and shake when transported, and is thin enough on the one hand to help reduce weight and cost. The carrier is only a temporary fixture and is not permanently part of the heat conducting plate. Tan pads and terminals are available in a variety of packages depending on the needs of the semiconductor components and the next layer. The pads and terminals can be formed by a variety of deposition techniques, such as with an electric clock, no electrical keying, evaporative sputtering, etc., to form a single or multi-layer structure when the substrate has not been or has been placed on the adhesive layer. For example, a pattern of a conductive layer may be formed on the substrate when the substrate has not been placed on the adhesive layer, or after the substrate has been adhered by the adhesive layer (4).

Similarly, the overhanging platform can be patterned when the coated perforations have not been formed, thereby forming a pad and a flange layer. The surface treatment by the covered joint can be carried out before or after the material and the end. For example, it may be desirable to first etch the cladding layer to form the Hui, i, pedestal, and flange layers, and to deposit the bump contacts on the coatings or deposit the coatings. The coated layers are formed to form the bonding pad, the money (9) ^ re-etching the 忒 忒 terminal, the pedestal and the flange layer. The raised edge of the case can be and the ancient + τ η with or without reflection, can be transparent

S 84 201218468 Transparent. For example, the raised edge may comprise silver having a sloping inner side surface s ^ , a metallic metal, and reflecting upwardly, the light entering the side surface and thereby increasing in the upward direction. The raised edge may comprise, for example, glass. Similarly, a transparent material, or a material such as an epoxy tree that is non-reflective, opaque, and low cost. ^ (4) Months Special =: Seal _ or limit the range of packaging materials 2 = Reflective ridges. j』 Use the package material of this case (or double package)

Bright or opaque material, and can be T-transparent, semi-transparent and ugly with different shapes and sizes. The material may be a transparent oxygen-cutting resin, an epoxy resin or a combination thereof. In terms of the conductivity: and the stability of the color conversion, the epoxy resin has higher cost, lower hardness and poor adhesion. The upper cover of the case may overlap or replace the packaging material. The top cover seals the crystal and the wire and provides both anti-(4) and anti-micro protection for both. The upper cover can be made from a variety of transparent, translucent or opaque materials and can have different shapes and sizes. For example, the upper cover may be transparent ceria. a The lens of this case may overlap or replace the packaging material. The lens seals the wafer and wires and provides protection such as anti-(4) and anti-particle protection for both. The lens can also provide a convex refractive surface, and the light will be directed upwards: medium. The lens may be made of a variety of transparent 'translucent or opaque materials, and have different shapes and sizes, and a hollow hemispherical dome-shaped glass lens may be disposed on the heat conducting plate 'and keep the lens away from the packaging material; or Place a solid-hemispherical dome-shaped plastic lens on the encapsulation material 85 201218468 and keep the lens at a distance from the thermal pad. The wires of this case may include additional pads, terminals, covered vias, routing wires, conductive vias, and passive components&apos; and may be of different configurations. The wires can be used as signal layers, power layers or ground planes depending on the purpose of soldering their respective semiconductor components. The wires may also contain various conductive metals such as steel, gold, nickel, silver, palladium, tin, mixtures thereof, and alloys thereof. The ideal composition depends on the nature of the externally connected medium and on the design and reliability considerations. In addition, those skilled in the art should be able to understand that the copper used in the semiconductor wafer package of this case may be pure copper 'but usually copper-based alloys, such as copper-wrong (99.9% copper), copper-silver- Phosphorus-magnesium (99.7% copper) and steel-tin-iron_disc (99.7% copper) to improve mechanical properties such as tensile strength and ductility. In general, it is preferable to provide the dielectric layer, the coated perforation, the upper and lower coating layers, the coated contacts, the solder resist green paint, the encapsulating material, the lens, the raised edge and the upper cover, but in some embodiments Can be omitted. For example, if only single layer signal routing is used, the dielectric layer can be omitted to reduce cost. If the light emitted by the LED chip is originally the color we need, the packaging material used to convert the color can be omitted. Similarly, if the transparent encapsulating material is molded onto the thermally conductive plate and the lateral extent of the transparent encapsulating material is limited by the recess (or the encapsulating material is not provided at all) and the reflector is not required, the raised edge can be omitted. The heat conducting plate of the present invention may include a heat conducting hole that is spaced apart from the bump and extends through the adhesive layer and the dielectric layer outside the opening and the through hole while abutting and thermally joining the base and the flange layer. Thereby lifting from the flange layer to. The heat dissipation effect of the mysterious base and promote the diffusion of thermal energy in the base. 201218468 The group of this case can provide horizontal or vertical single-layer or multi-layer signal routing. 0 Lin Wenqiang et al. filed the application for the first US 6,667 US special application in May 2009, 2009: "with pillar / pedestal The semiconductor wafer package of the heat sink and the substrate is disclosed as a structure having a horizontal single layer signal routing, wherein the pads, terminals and routing lines are all located above the dielectric layer, the contents of which are incorporated herein by reference. The manner is incorporated herein. Lin Wenqiang et al. filed an application for the US Special Report No. 12/616,775 on November 30, 2009: "Semiconductor Chip Assembly with #Column/Base Heatsink and Conductor" reveals another level The structure of the layer signal routing, wherein the pads, the terminals and the routing wires are located above the adhesive layer, and the structure is not provided with a dielectric layer, the contents of which are incorporated herein by reference. U.S. Patent Application Serial No. 12/557,540, the entire disclosure of which is hereby incorporated by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire content a routing structure in which pads and terminals above the dielectric layer are electrically connected by using first and second conductive vias through the dielectric layer and routing lines under the dielectric layer. US Patent Application The content is hereby incorporated by reference. U.S. Patent Application Serial No. 12/557,541, the entire disclosure of which is hereby incorporated by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire content a routing structure in which a pad above the dielectric layer and a terminal below the adhesive layer 87 201218468 utilize a first conductive via through the dielectric layer, a routing line under the dielectric layer, and a pass through the adhesive layer The two conductive vias are electrically connected, and the contents of this U.S. Patent Application is hereby incorporated herein by reference. The working format of the heat conducting plate in this case can be single or multiple heat conducting plates, depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a plurality of thermally conductive plates can be fabricated from a single metal sheet, a single adhesive layer, a single substrate, and a single coating layer in the same time batch, and then separated. Similarly, for each of the heat transfer plates in the same batch, we can also simultaneously manufacture a plurality of sets of heat sinks and wires for a single semiconductor component by using a single metal plate, a single adhesive layer, a single substrate, and a single coating layer. For example, a plurality of bumps may be stamped on a metal plate; and then an uncured adhesive layer having openings corresponding to the bumps is disposed on the overhanging platform such that each of the bumps extends through a corresponding opening; Then, a substrate (having a single conductive layer, a single dielectric layer, and a through hole corresponding to the bumps) is disposed on the adhesive layer, so that each of the bumps extends through a corresponding opening and enters a corresponding through hole; Then, the overhanging platform and the substrate are pressed against each other by the pressing table to force the adhesive layer into the gap between the bumps and the substrate in the through holes; then curing the adhesive layer and then grinding the same a bump, the adhesive layer and the conductive layer to form a lateral surface; then drilling through the structure to form a plurality of holes; and then placing a coating layer on the structure to form upper and lower coating layers, respectively Forming a covered via in the holes; then etching the overhanging platform and the upper cladding layer to form a plurality of flange layers corresponding to the bumps and a plurality of pads corresponding to the coated vias; etching the conductive layer And the next The coating layer is formed to form a plurality of pedestals corresponding to the bumps, and a plurality of 88 £ 201218468 corresponding to the terminals of the covered perforations; and then the covered joints are the bumps, the one seat, the material flange layer, and the (four) (four) And the materials are cut at the surface and finally cut or split at a suitable position on the peripheral edge of each of the heat conducting plates to separate the individual heat conducting plates from each other. ^ The operating format of the semiconductor wafer package in this case can be single-group or multiple-group, depending on the manufacturing design. For example, a single group can be manufactured separately, and multiple groups can be manufactured in batches at the same time, and then each heat conducting plate is one to eight.

from. Similarly, a plurality of semiconductor elements can be electrically connected to each other 'thermally coupled: mechanically coupled to each of the heat conducting plates in mass production.

For example, a plurality of solid crystal materials may be separately deposited in the recesses of the plurality of bumps, and then a plurality of wafers are respectively placed on the solid crystal material in the recesses, and (4) the solid crystal materials are heated to be Hardens and forms a plurality of solid crystals. The wafers are then wire bonded to the corresponding solder pads outside the recesses and then deposited on the wafer and the wires in the recesses to separately convert the color of the encapsulation material, and then simultaneously heat the encapsulation materials to harden them. Become a packaging material for convertible colors. After the transparent encapsulating material is molded in the packaging materials for converting colors, the heat conducting plates can be separated one by one. D We can separate the heat conducting plates from each other in a single-step or multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements are placed on the flat plate, and then the plurality of semiconductor wafer assemblies constituted by the flat plates are separated. Alternatively, a plurality of heat conducting plates can be batched into a flat plate, and then the plurality of heat conducting plates formed by the flat plate are slit into a plurality of heat conducting strips, and then a plurality of semiconductor elements are respectively disposed on the heat conducting strips. Finally, the plurality of semiconductor wafer assemblies 89 201218468 formed by the heat conducting strips are separated into individual by mechanical cutting and lightning. In addition, cutting, splitting or other suitable techniques can be used when splitting the thermal plate. As used herein, the term "adjacent" means that the elements are formed (formed as a single solid) or in contact with one another (with or without separation from one another). For example, the bump base and the flange layer, but not adjacent to the dielectric layer. The term “inside” means that it is located above and extends in the week of the lower element. The overlap includes extending inside, outside or on the circumference of the circumference: . For example, in the state in which the pocket is facing upward, the semiconductor component of the present invention is heavy-to-bumped' because an imaginary vertical line can penetrate both the semiconductor component and the bump between the component (four) component and the bump. Whether there is another element (such as a solid crystal material) through which the imaginary vertical line penetrates, and whether or not there is another imaginary vertical line that penetrates only the bump and does not penetrate the semiconductor element (ie, is located in the semiconductor element) Outside the periphery). Similarly, the bumps are overlaid on the pedestal&apos;s pad system, overlying the adhesive layer, and the pedestals are overlapped by bumps. In addition, "overlap" and "above" @义, "overlap" are synonymous with "underlying. Contact" means direct contact. For example, the dielectric layer contacts the terminals but does not contact the bumps. The term "covering" means completely covering in a vertical and/or lateral direction. If the base extends laterally beyond the through hole and contacts the dielectric layer, the pedestal is from below. The bump is covered, but the bump does not cover the pedestal from above. The layer includes a layer with or without a pattern. For example, when the substrate is disposed on the adhesive layer, the conductive layer may be a blank on the dielectric layer without the flat plate of 201218468; and when the semiconductor component is disposed on the heat sink, the conductive layer may have a space on the dielectric layer. The circuit pattern of the wire. In addition, the "layer" may comprise a plurality of superposed layers. The term "weld" is used in conjunction with a conductor to refer to a connection area for connecting and/or bonding an external connection medium (such as solder or wire) that electrically connects the wire to the semiconductor component. . The term "terminal" when used in conjunction with a conductor means a connected area that can be contacted and/or joined to an externally connected medium (such as solder or wire) that electrically connects the conductor to the next layer. One of the external devices (such as a printed circuit board or a wire connected to it). The term "coated perforation" when used in conjunction with a conductor means an electrical interconnection structure formed in a hole in a covered manner. For example, a coated perforation may remain intact and remain at a distance from the peripheral edge of the assembly, or may be cleaved or trimmed into a groove in a subsequent process such that the remainder of the coated perforation is in the group The groove in the peripheral edge of the body; the presence of the coated perforation is independent of which configuration is used. The words "opening", "through hole" and "hole" refer to the through hole. For example, the bump is inserted into the opening of the adhesive layer with the recess facing downward, and is exposed from the adhesive layer in the upward direction. Similarly, the bumps are inserted into the via holes of the substrate and are exposed from the substrate in the upward direction. The term "insertion" means the relative movement between components. For example, "inserting the bump into the through hole" includes: the bump is fixed and moved by the substrate toward the overhanging platform, the substrate is fixed and moved by the bump toward the substrate; and the bump and the substrate are in contact with each other. For another example, "insert (or extend) the bump into the through hole" 91 201218468 package s · bump through (through and through) through hole; and bump inserted but not through (penetrating but not worn out) Through hole. The phrase "together with each other" also refers to the relative movement between components. For example, "the extension platform and the substrate abut each other" include: the overhanging platform is fixed and moved by the substrate toward the outwardly extending platform; the substrate is fixed and moved by the overhanging platform toward the substrate; and the overhanging platform and the substrate are close to each other. Alignment § I mean the relative position between components. For example, when the adhesive layer has been placed on the overhanging platform, the substrate has been placed on the adhesive layer, the bump has been inserted and aligned with the opening and the through hole has been aligned with the opening, whether the bump is inserted into the through hole or under the through hole And keep away from it, the bumps are aligned with the through holes. The phrase "set in" includes contact and non-contact with a single or multiple support members. For example, a semiconductor component is disposed on the bump, whether the semiconductor component is in continuous contact with the bump or is separated from the bump by a die attach material. The term "adhesive layer...in the gap" means the adhesive layer located in the gap. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer within the gap extends across the dielectric layer. Similarly, "the adhesive layer is in contact with the gap and between the bump and the dielectric layer" means that the adhesive layer in the gap contacts and &quot; the dielectric layer of the bump on the inner side wall of the notch and the outer side wall of the notch between. The term "the base extends laterally from the bump" means that the base extends laterally from the adjacent projection. For example, in the state where the pocket is facing upward, the base extends laterally from the bump and thus contacts the adhesive layer, which is independent of whether the base extends laterally to the outside of the bump to extend to the flange layer or cover the bump from below. . Similarly, if the pedestal and the bump occupy the same spatial extent at the bump floor, the base 201218468 does not extend laterally beyond the bump. "Upper" means to extend upwards and includes contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, in the state in which the pocket is facing upward, the bump extends over the base and abuts the g main suppressor, overlaps the base, and protrudes from the base. Similarly, the tenon g 4 bumps may extend over the dielectric layer even if they are not adjacent or overlapping the dielectric layer. ,,, a few 〇 '3· foot press Xing and adjacent yuan

Pieces and overlapping and non-overlapping components. For example, in a state in which the pockets face upward, the pedestal extends below the bumps, and the abutting convex H bumps overlap and protrude from the projections in the downward direction. Similarly, the terminals can extend below the flange layer even if they are not adjacent to or overlapped by the flange layer. The "vertical direction" and "second vertical direction" do not depend on the orientation of the semiconductor chip package (or the heat transfer plate), and those skilled in the art can easily understand the direction in which they actually refer. For example, the bumps extend perpendicularly to the outside of the base in a first vertical direction and extend perpendicularly to the outside of the flange layer in a second vertical direction, whether the assembly is inverted and/or the assembly is disposed on a heat sink. Nothing. Similarly, the flange layer projects "laterally" from the bump along a lateral plane, regardless of whether the assembly is inverted, rotated or tilted. Thus, the first and second vertical directions are opposite each other and perpendicular to the side direction, and further, the laterally aligned elements are coplanar with each other in a lateral plane perpendicular to the first and second vertical directions. Further, when the pocket is upward, the first vertical direction is the upward direction, and the second vertical direction is the downward direction; when the recess is downward, the first vertical direction is the downward direction, and the second vertical direction is the upward direction. 93 201218468 The semiconductor a y of the invention has high reliability and price == has many advantages. This group can generate high heat and requires excellent heat dissipation; The group is especially suitable for easy-to-produce conductor components, such as high-power semiconductor chips for efficient and reliable operation of LED chips, and a plurality of simultaneous::: germanium conductor elements (for example, arrays of multi-grass The combination of the unique and progressive method of the present invention and the mechanical joining technology can be implemented. Therefore, the manufacturing throughput, yield, efficiency and cost of the copper wafer and the error-free environmental protection process have Highly adaptable, and with various mature electrical connections, thermal connection, the manufacturing process of this case does not require expensive tools to greatly enhance the benefits of traditional packaging technology. Furthermore, the group of this case is very suitable. The embodiments described herein are for illustrative purposes, and the elements or steps of the present invention are either simplified or omitted in order to avoid obscuring the features of the present invention. Repeated or non-essential elements and reference numerals may be omitted in the specification. Those skilled in the art can readily appreciate each of the embodiments described herein. For example, the above-mentioned materials, dimensions, shapes, sizes, steps, and the order of the steps are merely examples. The above-mentioned persons can make such changes without departing from the spirit and scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention to the present invention. j solid β, Gong Shizhi&################################################################################################ BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] and FIG. 1 are cross-sectional views illustrating a method for using gas as a bump and an overhanging platform in an embodiment of the present invention; FIGS. 1C and 1D are respectively a first diagram. FIG. 2 is a cross-sectional view showing the present invention - a method for forming an adhesive layer in the embodiment; and 2C and 2D are respectively a top view and a bottom view of the second drawing; 3rd and 3rd views; The picture is a cross-sectional view A method for using I as a substrate in an embodiment of the present invention; 3C and 3D are top and bottom views, respectively, of FIG. 3; and FIGS. 4 to 4 are cross-sectional views showing an embodiment of the present invention. The method of making a heat conducting plate; the fourth drawing "40" is a top view and a bottom view of the second drawing; the &amp;5&lt;: the drawings are respectively the invention - in the embodiment - the heat conducting plate = figure, top view and bottom view, The outer edge of the heat conducting plate is provided with the sixth and the following: a view of the heat conducting plate in an embodiment of the invention; a top view and a bottom view, the same spatial extent of the heat conducting plate; 7A, 7B &amp; 7C is a cross-sectional view, a top view, and a bottom view terminal of a heat conducting plate 95 201218468 according to an embodiment of the present invention; the δ hai heat conducting plate has a thickened pedestal and 8A, 8B & 8C are respectively an embodiment of the present invention. The cross-sectional view, the top view and the bottom view of the middle guide plate have a layer of anti-welding green paint on the upper and lower surfaces of the heat conducting plate; and FIGS. 9A 9B & 9C are respectively sectional views of a rail plate in an embodiment of the present invention, Top view and bottom view, the heat conducting plate There is a layer embedded: anti-weld green paint; the first layer, the first 10B and the 10C are respectively a cross-sectional view, a top view and a top view of a heat conducting plate according to an embodiment of the present invention, which can provide horizontal signal routing; The cross-sectional view of the board, 11B and 11C are respectively a heat-conducting top view and a bottom view of the present invention - the heat conducting board has a raised edge

12A, 12B, and 12C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package in the embodiment of the present invention, the semiconductor wafer package including a heat conducting plate, a semiconductor component, and a packaging material; 13A, 13B And FIG. 13C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package according to an embodiment of the present invention, the semiconductor wafer package including a heat conductive plate, a semiconductor component, a packaging material, and a lens; 14A, 14B and 14C is a cross-sectional view, a top view, and a bottom view, respectively, of a semiconductor wafer package including a heat conducting plate, a semiconductor component, and a double-layer packaging material; and FIGS. 15A, 15B, and 15C, respectively. One half of the guide in one embodiment of the present invention

S 96 201218468 A cross-sectional view, a top view and a bottom view of a body wafer assembly comprising a heat conducting plate having a raised edge, a semiconductor component and a Shuanglu package material; 16A, 16B and 16C is a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package according to an embodiment of the present invention. The semiconductor a-piece assembly includes a heat-conducting plate having a raised edge, a semiconductor component, a package* material, and an upper cover; And FIGS. 17A, 17B, and 17C are respectively a cross-sectional view, a top view, and a bottom view of a half-conducting φ body wafer assembly including an embossed edge heat conducting plate, a semiconductor component, and a bottom view. Upper cover 97 201218468 [Explanation of main component symbols] 10........ • Metal plate 12, 14· • Surface 16........ • Bumps 18........ • Outside Stretching platform 20........ • Pocket 22 ' 24 · • Bent corner 26........ • Tapered side wall 28........ • Base plate 30... ..... • Adhesive layer 32........ . Opening 34........ • Substrate 36........ • Conductive layer 38....... • Introduction Layer 40........ • Through Hole 42........ • Notch 44..... • Hole 46........ • Covering Layer 48.. ...... • Upper cladding layer 50........ • Lower cladding layer 52........ • Covered perforation 54........ • Patterned etch resistance Layer 56 layer 60.........pad 62.........flange layer 64 .... pedestal 65 ......... Routing line 66 .... terminal 70 ... ... wire 72 ... ... heat sink 74 ... ... covered contact 76 .........solderproof green paint 77 .........solderproof green paint 78 ......... raised edges 80, 82, 84, 86, 88, 90 , 92 ' 94 ... ... heat conducting plate 100 ' 200 , 300 , 400 ' 500 , 600 · ... semiconductor chip set 102 , 202 ' 302 ' 402 , 502 , 602 — LED chip 104 , 204 , 304 , 404 , 504 ' 604 — etched lines 106 , 206 , 306 , 406 , 506 patterned etch resistance , 606 · · · · solid crystal material 201218468 108 , 208 , 309 , 408 , 508 1 14 , 214 , 314, 414, 514 ............ encapsulation material, 614·... wire bonding pads 110, 210, 310, 410, 510 216....... lens, 610···· Top surface 520 . . . top cover 112, 212, 312 412, 512 620 ....... cover, 612-- bottom surface 99

Claims (1)

201218468 VII. Patent application scope: 1. A semiconductor wafer assembly comprising at least: a semiconductor component; an adhesive layer having at least one opening; a heat sink comprising a bump, a base and a flange layer Wherein the bump abuts the base and the flange layer and is integral with the flange layer, the bump extends from the base in a first vertical direction, and from the flange layer a second vertical direction opposite to the first vertical direction; the base extending from the bump in the second vertical direction; the flange layer extending from the side of the bump along a side perpendicular to the vertical direction And maintaining a distance from the base; the bump has a recess facing the first vertical direction, the recess being covered by the bump in the second vertical direction, the bump also separating the recess And the pedestal, the recess is provided with an inlet at the flange layer; and a wire comprising a pad and a terminal; wherein the semiconductor component extends into the cavity and is electrically connected to the pad 'The electrical connection to the terminal, a semiconductor component is also thermally bonded to the bump to be thermally bonded to the pedestal; wherein 'the adhesive layer contacts the bump and the flange layer and extends laterally from the bump to the terminal or over the terminal; The wire is located outside the recess; wherein 'the bump extends into the opening and covers the semiconductor component in the second vertical direction; and 201218468, wherein the recess extends into the opening. 2. The semiconductor wafer package of claim 2, wherein the semiconductor component is an LED chip. 3. The semiconductor wafer package of claim 2, wherein the semiconductor component is located in the recess, electrically connected to the solder pad by a wire extending inside and outside the cavity, and utilizing a A die attach material located within the recess is thermally bonded to the bump. 4. The semiconductor wafer package of claim 2, wherein the adhesive layer contacts the wire. 5. The semiconductor wafer package of claim 2, wherein the adhesive layer laterally covers and surrounds the bump while being isomorphously coated on one of the sidewalls of the bump. 6. The semiconductor wafer package of claim 2, wherein the adhesive layer extends to a peripheral edge of the semiconductor wafer assembly. 7. The semiconductor wafer package of claim 2, wherein the ridge bump and the adhesive layer are coplanar at the pedestal. 8. The semiconductor wafer package of claim 1, wherein the germanium block and the adhesive layer are coplanar at the flange layer. 9. The semiconductor wafer package of claim 2, wherein the bump comprises a first bent corner adjacent the base and a second bent corner adjacent the flange layer. The semiconductor wafer package of claim 2, wherein the bump has a stamped special irregular thickness. The semiconductor wafer package of claim 1, wherein the concave direction of the crucible and the lateral direction extend across a majority of the projection. 12. The semiconductor wafer package of claim </ RTI> wherein the susceptor * has a single thickness and a flat surface facing the second vertical direction. 13. The semiconductor wafer package of claim i, wherein the pedestal extends from the side of the bump. 14. The semiconductor wafer package of claim ii, wherein the flange layer and the pad are co-located on a surface facing the first vertical direction. The semiconductor wafer assembly of the invention, wherein the susceptor and the terminal are co-located on a surface facing the second vertical direction. The semiconductor wafer assembly, wherein the bonding pad extends from the adhesive layer along the first vertical direction, and the n sub-extends the outer side of the adhesive layer along the second vertical direction. 17. The semiconductor wafer package of claim 2, wherein the wire comprises a coated via, the coated via being located on a conductive path between the solder fillet and the terminal. 18. The semiconductor wafer package of claim 2, wherein the bump, the pedestal, the flange layer, the pad, and the terminal are metal. The semiconductor wafer package of claim </ RTI> wherein the bump, the pedestal, the flange layer, the pad and the terminal comprise a surface layer and a surface of a silver or nickel layer Internal copper core, and mainly steel. The semiconductor wafer package of claim 1, wherein the heat sink comprises a copper core shared by the bump, the base and the flange layer, the wire comprising a solder The steel core that the pad shares with the terminal. 21 _ a semiconductor wafer package comprising: at least: a semiconductor component; 'an adhesive layer having at least one opening; a heat sink comprising a bump, a pedestal and a flange layer, a bump abutting the base and the flange layer, and integral with the flange layer, the bump extending from the base in a first vertical direction, and from the flange layer along a first vertical direction Conversely extending in a second vertical direction; the base extending from the bump in the second vertical direction and extending from the side of the bump in a side direction perpendicular to the vertical direction; the flange layer The bump protrudes sideways and is kept at a distance of 9% from the base. The bump has a recess facing the first vertical direction, and the recess is covered by the bump in the second vertical direction. The bump also separates the recess from the pedestal, the recess is provided with an inlet at the flange layer, and a wire includes a pad and a terminal; wherein the semiconductor component extends into the recess, and Electrically connected to the pad' to electrically connect to the terminal, The semiconductor component is also thermally bonded to the bump 'to be thermally coupled to the pedestal; wherein the adhesive layer contacts the bump, the pedestal and the flange layer, 103 201218468 the adhesive layer is laterally from the bump Located between the pedestal and the flange layer to the terminal or over the terminal; wherein 'the wire is outside the recess; wherein the bump extends into the opening and covers the semiconductor in the second vertical direction An element; and wherein the pocket extends into the opening. 22. The semiconductor wafer package of claim 21, wherein the semiconductor component is a led wafer. 23. The semiconductor wafer package of claim 21, wherein the semiconductor component is located in the recess, electrically connected to the "-", and (4) the heat of the solid crystal material of the recess Connect to the bump. 24. The semiconductor wafer package of claim 21, wherein the adhesive layer contacts the wire. The semiconductor wafer package of claim 21, wherein the adhesive layer laterally covers and surrounds the bump while being isomorphously coated on one of the sidewalls of the bump. 26. The semiconductor wafer package of claim 21, wherein the adhesive layer extends to a peripheral edge of the semiconductor wafer assembly. 27. The semiconductor wafer package of claim 21, wherein the bump and the adhesive layer are coplanar at the base. 28. The semiconductor wafer package of claim 21, wherein the bump and the adhesive layer are coplanar at the flange layer. 29. The semiconductor wafer package of claim 21, wherein: S 104 201218468 the bump comprises a first bent corner adjacent to the base and a second bent corner adjacent to the flange layer . 30. The semiconductor wafer package of claim 2, wherein the block has a stamped special irregular thickness. The semiconductor wafer package of claim 21, wherein the recess extends across the majority of the bumps in the perpendicular direction and the lateral directions. 32. The semiconductor wafer package of claim 21, wherein the crucible base has a single thickness adjacent the bump, the base further having a flat surface facing the second vertical direction. 33. The semiconductor wafer package of claim 21, wherein the pedestal covers the flange layer in the second vertical direction, laterally extending across the flange layer, supporting the adhesive layer, and The peripheral edges of the semiconductor wafer package maintain a distance. 34. The semiconductor wafer package of claim 21, wherein the flange layer and the pad have the same thickness and are co-located on a surface facing the first vertical direction. The invention relates to a semiconductor wafer package according to the second aspect of the invention, wherein the β-helium and the terminal have the same thickness 相邻 adjacent to each other, but the thickness of the base adjacent to the bump is The thickness of the terminal is different, and the base and the terminal are co-located on a surface facing the second vertical direction. The semiconductor wafer assembly of claim 21, wherein the bonding pad extends over the outer side of the adhesive layer along the first vertical direction, and the terminal extends along the second vertical direction of the adhesive layer. Outside. The semiconductor wafer package of claim 21, wherein the wire comprises a covered via, the coated via being located on a conductive path between the pad and the terminal. 38. The semiconductor wafer package of claim 21, wherein the bump, the pedestal, the flange layer, and the pad are the same metal as the terminal. 39. The semiconductor wafer package of claim 21, wherein the bump, the pedestal, the flange layer, the pad and the terminal comprise a gold, silver or nickel surface layer and a Internal copper core, and mainly copper. 40. The semiconductor wafer package of claim 21, wherein the heat sink comprises a copper core shared by the bump and the flange layer, the wire comprising a solder pad A copper core shared with the terminal. 41. A semiconductor wafer package comprising at least one semiconductor component; an adhesive layer having at least one opening; a heat sink comprising a bump 'a base and a flange layer, wherein the bump Adjacent to the base and the flange layer, and integral with the flange layer, the bump extends from the base in a first vertical direction and is opposite to the first vertical direction from the flange layer Extending in a second vertical direction; wherein the base extends from the bump in the second vertical direction, and covers the bump in the second vertical direction, and the side of the bump is perpendicular to the vertical direction The flange layer extends from the side of the protrusion and is spaced from the base 20218468; wherein the protrusion has a concave surface 6 toward the first vertical direction, The recess is covered by the bump in the second vertical direction, the bump also separating the recess and the base. The recess 6 is provided with an inlet 9 and a substrate at the flange layer, and the dielectric layer comprises a dielectric a layer, wherein a through hole extends through the substrate; and a wire The semiconductor device extends into the recess and is electrically connected to the solder pad to be electrically connected to the terminal, and the semiconductor component is also thermally coupled to the bump. Thereby thermally bonding to the susceptor; wherein 'the adhesive layer contacts the bump, the pedestal, the flange layer and the dielectric layer, and between the bump and the dielectric layer, the flange layer and Between the far dielectric layers and between the pedestal and the flange layer, the adhesive layer extends laterally from the bump to a peripheral edge of the semiconductor wafer assembly; wherein 'the wire is outside the recess; 'The bump extends into the opening and the through hole and covers the semiconductor element in the second vertical direction; and wherein the recess extends into the opening and the through hole. 42. The semiconductor wafer package of claim 41, wherein the germanium semiconductor component is an LED wafer. 43. The semiconductor wafer package of claim 41, wherein the semi-conductive material is located in the recess, and is electrically connected to the solder pad by a wire extending in the recess. And bonding to the bump by a solid crystal material located in the recess 107 201218468. 44. The semiconductor wafer package of claim 41, wherein the adhesive layer contacts the wire. 45. The semiconductor wafer package of claim 41, wherein the adhesive layer laterally covers and surrounds the bump while being isomorphously coated on one of the sidewalls of the bump. 46. The semiconductor wafer package of claim 41, wherein the adhesive layer is isomorphously coated on a surface portion of the base, the surface portion abutting the bump and extending laterally from the bump, and Facing the first vertical direction. 47. The semiconductor wafer package of claim 41, wherein the bump is coplanar with the adhesive layer at the base. 48. The semiconductor wafer package of claim 41, wherein the bump is coplanar with the adhesive layer at the flange layer. 49. The semiconductor wafer package of claim 41, wherein the bump comprises a second corner that is adjacent to the first corner of the base and __ adjacent to the flange layer. The semiconductor wafer package of claim 41, wherein the bump has a stamped special irregular thickness. The semiconductor wafer package of claim 41, wherein the recess extends across the majority of the bumps in the vertical direction and the lateral directions. The semiconductor wafer assembly of claim 41, wherein the pedestal has a -th thickness adjacent to the bump and has a greater than the first thickness adjacent to the electrical layer 201218468 The second thickness of the base further has a flat surface facing the second vertical direction. 53. The semiconductor wafer package of claim 41, wherein the pedestal covers the flange layer in a second vertical direction laterally across the flange layer to support the substrate and the adhesive layer, And maintaining a distance from the peripheral edges of the semiconductor wafer package. 54. The semiconductor wafer package of claim 41, wherein the flange layer and the pad have the same thickness and are co-located on a surface facing the first vertical direction. The semiconductor wafer package according to claim 41, wherein the base and the terminal have the same thickness adjacent to each other, but the thickness of the base adjacent to the bump is different from the thickness of the terminal. The base and the terminal are co-located on a surface facing the second vertical direction. 56. The semiconductor wafer package according to claim 41, wherein the solder pad contacts the adhesive layer but is spaced apart from the dielectric layer, the solder pad extending from the adhesive layer and the dielectric layer An outer side of the first vertical direction; the terminal contacts the dielectric layer but is spaced apart from the adhesive layer, the terminal extending from the adhesive layer and the dielectric layer on the outer side of the second vertical direction. 57. The semiconductor wafer package of claim 41, wherein the wire comprises a covered via, the coated via being on a conductive path between the pad and the terminal. 58. The semiconductor wafer package of claim 41, wherein the bump, the pedestal, the flange layer, and the pad are the same metal as the terminal. The semiconductor wafer assembly of claim 41, wherein the bump, the pedestal, the flange layer, the bonding pad and the terminal comprise a gold, silver or nickel surface layer And an internal copper core, and mainly copper. 60. The semiconductor wafer package of claim 41, wherein the heat sink comprises a copper core shared by the bump, the base and the flange layer, the wire comprising a bond pad A copper core shared with the terminal. 61. A semiconductor wafer package comprising: at least: a semiconductor component; an adhesive layer having at least one opening; a heat sink comprising a bump, a base and a flange layer 9 wherein a bump abutting the base and the flange layer, and integral with the flange layer, the bump extending from the base in a first vertical direction, and from the flange layer along a first vertical direction Conversely extending in a second vertical direction; the pedestal extending from the bump in the second vertical direction and covering the bump in the second vertical direction, and from the side of the bump perpendicular to the vertical direction a direction extending from the side of the bump; the flange layer extending from the side of the bump and maintaining a distance from the base 9 the bump having a recess facing the first vertical direction, the recess being at the second Vertically covering the bump, the bump also separating the recess and the base, the recess is provided with an inlet at the flange layer; a substrate 'containing a dielectric layer, wherein a through hole extends Through the 201218468 substrate; and a wire, which is made up of a pad a terminal and a covered perforation, wherein 'the covered perforation is a conductive path between the pad and the terminal; wherein the semiconductor element extends into the cavity and is electrically connected to the pad to electrically connect To the terminal, the semiconductor component is also thermally coupled to the bump to be thermally coupled to the pedestal; wherein the adhesive layer contacts the dielectric layer in the via and the adhesive layer is located at the bump Between the dielectric layers, between the bump and the covered via, between the flange layer and the dielectric layer, and between the base and the flange layer, and extending laterally from the bump to the a peripheral edge of the semiconductor wafer assembly; wherein the wire is located outside the recess, the solder pad contacts the adhesive layer but maintains a distance from the dielectric layer, the solder pad extends between the adhesive layer and the dielectric layer On the outer side of the first vertical direction, the terminal contacts the dielectric layer but maintains a distance from the adhesive layer, and the terminal extends on the outer side of the adhesive layer and the dielectric layer along the second vertical direction, and the covered perforation contacts and extends Through the adhesive layer The dielectric layer; the bump contacts the adhesive layer but maintains a distance from the dielectric layer, the bump extends into the opening and the through hole, and covers the semiconductor component in the second vertical direction, and The semiconductor device provides a concave wafer holder, wherein the pedestal contacts the adhesive layer and the dielectric layer, and covers the flange layer in a vertical direction of the 111th 201218468, and laterally extends over the flange layer, The pedestal system extends on the outer side of the adhesive layer and the dielectric layer along the second vertical direction; wherein the flange layer contacts the adhesive layer but is spaced apart from the dielectric layer, the flange layer extends over the adhesive layer And the dielectric layer is along the outer side of the first vertical direction; and the concave portion extends into the opening and the through hole, and extends across the majority of the protruding block along the vertical direction and the lateral direction. 62. The semiconductor wafer package of claim 61, wherein the i semiconductor component is a led wafer and is located in the recess, the semiconductor component utilizing a wire bonding electrical property extending inside and outside the cavity Attached to the pad and thermally bonded to the bump using a die attach material located within the recess. The semiconductor wafer package of claim 61, wherein the adhesive layer passes through an imaginary horizontal line between the bump and the dielectric layer, an imaginary horizontal line between the bump and the covered perforation, An imaginary horizontal line between the bump and the pedestal, an imaginary vertical line between the bump and the pedestal, an imaginary vertical line between the pad and the dielectric layer, and one of the flange layer and the dielectric layer An imaginary vertical line and an imaginary vertical line between the flange layer and the base, but the adhesive layer does not individually pass through an imaginary line between the bump and the terminal, and one of the flange layer and the terminal a line, an imaginary line between the pad and the pedestal or an imaginary line between the pad and the terminal. 64. The semiconductor wafer package of claim 61, wherein: 201218468 the bump is coplanar with the landing force and the flange layer is coplanar, and the flange The layer is thicker than the base, the flange layer has the same thickness as the pad, and the flange layer and the pad are co-located on a surface _L facing the first-vertical direction; the pedestal and the pedestal The terminals have a same thickness adjacent to each other, but the thickness of the base adjacent to the bump is different from the thickness of the terminal, and the base and the terminal are co-located on a surface facing the second vertical direction. 65. The semiconductor wafer package of claim 6, wherein the bump, the pedestal, the flange layer, the solder pad, the terminal and the covered via comprise a gold, silver or a recording The surface layer is mainly copper, and the heat sink comprises a copper core shared by the bump, the base and the flange layer, the wire comprising a copper core shared by the solder pad, the terminal and the covered through hole 〇 66. A semiconductor wafer assembly comprising at least: an LED chip, an adhesive layer having at least one opening; a heat sink comprising a bump, a base and a flange layer, wherein the bump a block adjoins the base and the flange layer, and is integral with the flange layer </ s> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> a second vertical direction extending in a direction opposite to the vertical direction; the base extending from the protrusion in the second vertical direction and extending from the side of the protrusion in a side direction perpendicular to the vertical direction; the flange The layer extends from the side of the bump and maintains a distance 113 from the base 201218468 The bump has a recess facing the first vertical direction, the recess is covered by the bump in the first vertical direction of the crucible, and the recess is also separated from the base, the recess is The lead layer is provided with an inlet; a wire comprising a pad and a terminal; and a packaging material; wherein the LED chip is located in the cavity and electrically connected to the swell and thus electrically Connected to the terminal, the LED chip is also thermally coupled to the bump to be thermally coupled to the pedestal; wherein the encapsulating material extends into the recess and covers the LED wafer in the first vertical direction; wherein An adhesive layer contacting the bump, the base and the flange layer, and between the base and the flange layer, the adhesive layer extending laterally from the bump to the terminal or over the terminal; wherein A lead is located outside the recess; wherein 'the bump extends into the opening and covers the LED wafer in the second vertical direction; and wherein the recess extends into the opening. The semiconductor wafer assembly of claim 66, wherein the LED chip is electrically connected to the bonding pad by a wire extending inside and outside the cavity, and utilizes a solid located in the cavity. The crystalline material is thermally bonded to the bump. 68. The semiconductor wafer package of claim 66, wherein the adhesive layer contacts the wire, laterally covering and surrounding the bump, and the same shape is covered by one side of the sidewall of the child bump by 201218468 and extending to The peripheral edge of the semiconductor wafer assembly. 69. The semiconductor wafer package of claim 66, wherein the packaging material is a packaging material that can be used to convert color. 70. The semiconductor wafer package of claim 69, wherein the semiconductor wafer 1 and the body S comprise a transparent encapsulating material contacting the packaging juice bucket for converting color, and the first The packaging material used to convert the color is covered vertically. The semiconductor wafer package of claim 7, wherein the encapsulating material for converting color comprises a cerium oxide resin and a phosphor, the transparent encapsulating material comprising a cerium oxide resin but no phosphor. The semiconductor wafer package of claim 66, wherein the bump comprises a first bent corner adjacent to the base and a second bent corner adjacent to the flange layer; The recess extends across the plurality of the projections in the vertical direction and the lateral direction; the base covers the flange layer in the second vertical direction and extends laterally across the flange layer to support the adhesive The layer 'and maintains a distance from the peripheral edge of the semiconductor wafer package. The semiconductor wafer package of claim 66, wherein the bump and the edge adhesive layer are coplanar at the base and are coplanar at the flange layer; the flange layer and the solder layer The pads have a same thickness and are co-located on a surface facing the first vertical direction; the base and the terminal have the same thickness adjacent to each other, but the thickness of the base adjacent to the bump is The thickness of the terminal is different, and the base and the terminal are located together on the surface facing the second vertical direction. The semiconductor wafer assembly of claim 66, wherein the soldering system extends on the outer side of the adhesive layer along the first vertical direction, the terminal system extends over the adhesive layer along the second vertical On the outside of the direction, a covered perforation extends through the layer and is located on a conductive path between the pad and the terminal. 75. The semiconductor wafer package of claim 66, wherein the bump, the pedestal, the flange layer, the solder pad and the metal having the same terminal each comprise a gold, silver or a nickel surface layer, and mainly copper, the heat sink includes an inner copper core shared by the bump, the base and the flange layer, the wire comprising an inner copper core shared by the pad and the terminal . 76. A semiconductor wafer package comprising: at least: an LED wafer; an adhesive layer having at least one opening; a heat sink comprising a bump, a base and a flange layer, wherein the bump Adjacent to the base and the flange layer, and integral with the flange layer. The bump extends from the base in a first vertical direction and is opposite to the first vertical direction from the flange layer Extending in a second vertical direction; the base extends from the bump in the second vertical direction, and covers the bump ' in the second vertical direction and from the side of the bump along a side perpendicular to the vertical direction Extending out; the flange layer extends from the side of the bump and maintains a distance from the base 201218468. The β-bump has a recess facing the first-vertical direction, the recess being at the second vertical The direction is covered by the bump, the bump also separating the recess and the base, the recess is provided with an inlet at the flange layer; a wire comprising a pad and a terminal; and a package a material; wherein the S-Xuan LED chip is located in the cavity and utilized The wire is electrically connected to the pad to be electrically connected to the terminal, and the LED chip is also thermally bonded to the bump by a die bonding material to be thermally coupled to the pedestal; wherein the encapsulating material is in the cavity Contacting the LED chip 'the wire, the die bonding material and the bump, and the package material is spaced from the wire, the pedestal and the adhesive layer by the package material and covering the LED wafer in the first vertical direction; Wherein the adhesive layer contacts the bump, the base and the flange layer, and is located between the base and the flange layer, the adhesive layer extending laterally from the bump to the terminal or over the terminal; Wherein the solid crystal material is located in the recess, the wire extends inside and outside the 6-well recess, and the wire is located outside the recess; wherein the bump extends into the opening and is in the second vertical The LED wafer is oriented to provide a concave wafer holder and a reflector for the LED wafer; and wherein the recess extends into the opening. 77. The semiconductor wafer package of claim 76, wherein the adhesive layer contacts the bond pad but is spaced from the terminal, the adhesive layer extending laterally from the 117 201218468 and over the terminal. The semiconductor wafer assembly of claim 76, wherein the adhesive layer contacts the wire to laterally cover and surround the bump, and is conformally coated on one side wall of the bump and extends to the The peripheral edge of the semiconductor wafer assembly. 79. The semiconductor wafer package of claim 76, wherein the encapsulating material is an encapsulating material that can be used to convert color. The semiconductor wafer package of claim 79, wherein the semiconductor wafer package further comprises a transparent encapsulating material contacting the encapsulating material for converting color outside the recess, the flange The soldering layer and the black layer and the transparent packaging material and the LED wafer and the die bonding material. The pedestal and the terminal maintain a distance, and the transparent encapsulating material covers the encapsulating material for converting color, the flange layer and the bonding wire in the vertical direction. 81. The semiconductor wafer package of claim 80, wherein the encapsulating material for converting color comprises a stone oxide resin and a phosphor, the transparent encapsulant comprising a broken oxygen resin but not containing the light. body. The semiconductor wafer package of claim 76, wherein the bump comprises - adjacent to the (-)th corner of the pedestal and __ adjacent to the second bent corner of the flange layer a recess extending across the plurality of the projections in the vertical direction and the lateral direction, the base being perpendicular to the flange layer and extending over the flange layer to support the adhesive The layer 'and maintains a distance from the peripheral edge of the semiconductor wafer package. The semiconductor wafer package of claim 76, wherein: 201218468 the bump and the adhesive layer are coplanar at the base and the dome plane at the flange layer. The pads have a same thickness and collectively - facing the surface in the first-vertical direction; the pedestal and the terminal have - the same thickness 相邻 adjacent to each other but the thickness of the pedestal adjacent to the bump The thickness of the terminal is different from the thickness of the terminal, and the base and the terminal are located on the surface facing the second vertical direction. 84. The semiconductor wafer package of claim 76, wherein the bonding pad extends over the outer side of the adhesive layer along the first vertical direction, and the terminal system extends along the second vertical direction of the adhesive layer. On the outside, a covered via extends through the adhesive layer and is located on a conductive path between the pad and the terminal. The semiconductor wafer package of claim 76, wherein the bump, the base, the flange layer, the solder pad and the terminal are the same metal, each comprising a gold, silver or a nickel surface layer, and mainly copper, the heat sink includes an inner copper core for the bump, the base and the flange layer. The wire includes an inner copper shared by the pad and the terminal Core 0 119