TWI445222B - Semiconductor chip assembly with bump/base heat spreader and inverted cavity in bump - Google Patents

Description

Heat sink with bump/base and semiconductor wafer package with inverted recess Cross-references to relevant applications:

This application is a continuation-in-part of U.S. Patent Application Serial No. 12/911,729, filed on Jan. 26,,,,, The present application claims priority to US Provisional Patent Application Serial No. 61/429,455, filed on Jan. 4, 2011, the content of

The continuation of US Patent Application No. 12/616,773, filed on November 11, 2009, which is filed on October 26, 2010, is also a part of the continuation of US Patent Application No. 12/616,773, filed on November 11, 2009, also November 2009 A continuation of the application of U.S. Patent Application Serial No. 12/616,775, filed on the entire entire entire filing date of

U.S. Patent Application Serial No. 12/911,729, filed on Oct. 26, 2010, filed on Jun. 1, 2010, filed on Jun. 1, 2010, filed No. 61/350,036, and filed on May 1, 2010. The priority of U.S. Provisional Patent Application Serial No. 61/330,318, the contents of which are incorporated herein by reference.

U.S. Patent Application No. 12/616,773, filed on November 11, 2009, and U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, filed on Sep. 11, 2009 Part of the continuation of U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009.

U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009, and filed No. 12/557,541, filed on Sep. 11, 2009, filed on March 18, 2009 Partial continuation of U.S. Patent Application Serial No. 12/406,510. U.S. Patent Application Serial No. 61/071,588, filed on May 7, 2008, and U.S. Provisional Patent Application No. 61/071,588, filed on May 7, 2008. Priority of US Provisional Patent Application No. 61/071,072, filed on Apr. 11, 2008, and U.S. Provisional Patent Application No. 61/064,748, filed on March 25, 2008, the content of each of This is incorporated herein by reference. U.S. Patent Application Serial No. 12/557,540, filed on Sep. 11, 2009, and filed on Sep. 11, 2009, filed on Sep. 11, 2009. The priority of U.S. Provisional Patent Application Serial No. 61/150,980, the disclosure of which is incorporated herein by reference.

The present invention relates to a semiconductor wafer package, and more particularly to a semiconductor wafer package comprising a semiconductor component, a wire, an adhesive layer, and a heat sink, and a method of fabricating the same.

Semiconductor components such as packaged and unpackaged semiconductor wafers can provide high voltage, high frequency, and high performance applications; these applications require a very high amount of power to perform a particular function, but the higher the power, the higher the semiconductor component More heat. In addition, after the package density is increased and the size is reduced, the surface area available for heat dissipation is reduced, which further increases heat generation.

Semiconductor components are prone to performance degradation and shortened service life under high temperature operation, and may even malfunction immediately. High heat not only affects wafer performance, but may also cause thermal stress on the wafer and its surrounding components due to thermal expansion mismatch. Therefore, the wafer must be quickly and efficiently dissipated to ensure the efficiency and reliability of its operation. A high thermal conductivity path typically conducts and dissipates thermal energy to a region of greater surface area than the die pad in which the wafer or wafer is located.

Light-emitting diodes (LEDs) have recently become an alternative source of incandescent, fluorescent, and halogen sources. LEDs provide high energy efficiency and low cost long-term illumination for medical, military, signage, signal, aerospace, marine, vehicle, portable, commercial and residential lighting applications. For example, LEDs can provide light sources for fixtures, flashlights, headlights, searchlights, traffic lights, and displays.

The high power chips in the LEDs also produce a large amount of thermal energy while providing high brightness output. However, under high temperature operation, LEDs may suffer from color shift, brightness reduction, shortened service life, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. Therefore, LEDs highlight the market's need for high-power chips with good heat dissipation.

The LED package typically includes an LED chip, a pedestal, electrical contacts, and a thermal contact. The pedestal is thermally coupled to the LED wafer and used to support the LED wafer. The electrical contacts are electrically connected to the anode and cathode of the LED chip. The thermal contacts are thermally coupled to the LED wafer via the pedestal, and the underlying carrier is sufficiently thermally dissipated to prevent overheating of the LED wafer.

The industry is actively investing in the development of high-power chip packages and thermal boards with various design and manufacturing technologies in order to meet performance requirements in this extremely cost-competitive environment.

A plastic ball grid array (PBGA) package encloses a wafer and a laminate substrate in a plastic case and then adheres to a printed circuit board (PCB) with solder balls. The laminate substrate comprises a dielectric layer typically composed of glass fibers. The heat generated by the wafer can be transferred to the solder ball via the plastic and dielectric layers and transferred to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, the PBGA has a poor heat dissipation effect.

A quad flat no-lead (QFN) package places the wafer on a copper die pad that is soldered to a printed circuit board. The thermal energy generated by the wafer can be transferred to the printed circuit board via the die pad. However, due to the limited routing capabilities of its leadframe interposer, QFN packages are not suitable for high input/output (I/O) chips or passive components.

The heat conducting plate provides electrical routing, thermal management, and mechanical support for the semiconductor components. The heat conducting board usually comprises a substrate for signal routing, a heat sink or heat sink for providing heat removal function, a solder pad electrically connectable to the semiconductor component, and a terminal electrically connectable to the next layer assembly. The substrate can be a laminate structure having a single or multi-layer routing circuitry and one or more dielectric layers. The heat sink can be a metal base, a metal block or a buried metal layer.

The heat conducting plate engages the next layer of the body. For example, the next layer of the body can be a lamp holder having a printed circuit board and a heat sink. In this example, an LED package system is disposed on the heat conducting plate, and the heat conducting plate is disposed on the heat dissipating device, and the heat conducting plate/heat dissipating device sub-group and the printed circuit board are further disposed in the lamp holder. In addition, the heat conducting plate is electrically connected to the printed circuit board via wires. The substrate directs the electrical signal from the printed circuit board to the LED package, and the heat sink scatters and transfers the thermal energy of the LED package to the heat sink. Therefore, the heat conducting plate can provide an important thermal path for the LED wafer.

U.S. Patent No. 6,507,102 to the disclosure of U.S. Pat. A heat dissipating block having a square or rectangular shape similar to the central opening is adhered to the central opening side wall and thus joined to the substrate. The upper and lower conductive layers are respectively adhered to the top and bottom of the substrate, and are electrically connected to each other through the plating vias penetrating the substrate. A wafer is disposed on the heat dissipation block and wire bonded to the upper conductive layer, a package material is molded on the wafer, and a lower conductive layer is provided with a solder ball.

When manufactured, the substrate was originally a B-stage resin film placed on the lower conductive layer. The heat dissipating block is inserted in the central opening so as to be located on the lower conductive layer and separated from the substrate by a gap. The upper conductive layer is disposed on the substrate. After the upper and lower conductive layers are heated and pressed together, the resin is melted and flows into the gap to be solidified. The upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate and exposing the resin flash to the heat sink. The resin flash is then removed to expose the heat sink. Finally, the wafer is placed on the heat sink block and bonded and packaged.

Therefore, the thermal energy generated by the wafer can be transferred to the printed circuit board via the heat slug. However, in mass production, the manual placement of the heat sink in the central opening is labor intensive and costly. Moreover, since the mounting tolerance of the lateral direction is small, the heat dissipating block is not easily positioned in the central opening, which may cause a gap between the substrate and the heat dissipating block and uneven wiring. As a result, the substrate is only partially adhered to the heat dissipation block, and sufficient support force cannot be obtained from the heat dissipation block, and the layer is easily delaminated. In addition, the chemical etching solution for removing part of the conductive layer to expose the resin flash will also remove some of the heat-dissipating block which is not covered by the resin flash, so that the heat-dissipating block is not flat and difficult to combine, and finally the yield of the group is lowered, Insufficient reliability and high cost.

US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package having a substrate comprising a metal core layer and a wafer disposed in a die pad region on the top surface of the metal core layer. An insulating layer is formed on the bottom surface of the metal core layer. The blind hole penetrates the insulating layer through the metal core layer, and the hole is filled with the heat-dissipating solder ball, and the solder ball corresponding to the heat-dissipating solder ball is further disposed on the substrate. The thermal energy generated by the wafer can flow through the metal core to the heat sink balls and then to the printed circuit board. However, the insulating layer sandwiched between the metal core layer and the printed circuit board limits the heat flow to the printed circuit board.

U.S. Patent No. 6,670,219 to Lee et al., the disclosure of which is incorporated herein by reference. A substrate having a central opening is disposed on the ground plate through an adhesive layer having a central opening. A chip is mounted on the heat sink in a recess formed by the central opening of the ground plate, and the substrate is provided with a solder ball. However, since the solder ball is located on the substrate, the heat sink cannot contact the printed circuit board, and the heat dissipation effect of the heat sink is limited to heat convection instead of heat conduction, thereby greatly reducing the heat dissipation effect.

U.S. Patent No. 7,038,311 to Woodall et al. provides a high-heat-dissipating BGA package having a heat sink that is inverted T-shaped and includes a post portion and a wide base. A substrate having a window-shaped opening is disposed on the wide substrate, and an adhesive layer adheres the pillar portion and the wide substrate to the substrate. A wafer system is disposed on the pillar portion and wire bonded to the substrate, and a packaging material is molded on the wafer, and the substrate is provided with a solder ball. A post extends through the window opening and supports the substrate by a wide substrate, with the solder ball being between the wide substrate and the periphery of the substrate. The thermal energy generated by the wafer can be transferred to the wide substrate via the post and then to the printed circuit board. However, since a space for accommodating the solder balls must be left on the wide substrate, the wide substrate protrudes below the substrate only at a position corresponding to the central window and the innermost tin ball. As a result, the substrate is unbalanced during the manufacturing process, and is easily shaken and bent, thereby causing difficulty in mounting, wire bonding, and molding of the package material. In addition, the wide substrate may be bent due to the molding of the encapsulating material, and once the solder ball collapses, the package may not be soldered to the next layer. Therefore, the yield of the package is low, the reliability is insufficient, and the cost is too high.

U.S. Patent Application Publication No. 2007/0267642 to Erchak et al., which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire contents There are electrical contacts. A packaging system having a through hole and a transparent upper cover is disposed on the electrical contact. An LED chip is disposed on the protruding portion and connected to the substrate by wire bonding. The protrusion is adjacent to the substrate and extends through the insulating layer and the through hole on the package to enter the package. An insulating layer is disposed on the substrate, and an electrical contact is disposed on the insulating layer. The packaging system is disposed on the electrical contacts and spaced apart from the insulating layer. The heat generated by the wafer can be transferred to the substrate via the protrusions to reach a heat sink. However, the electrical contacts are not easily disposed on the insulating layer, and are difficult to electrically connect with the next layer of the assembly, and cannot provide multilayer routing.

Conventional packages and thermally conductive plates have major drawbacks. For example, an electrically insulating material having a low thermal conductivity such as an epoxy resin limits the heat dissipation effect, however, an electrically insulating material having a high thermal conductivity such as an epoxy resin filled with ceramic or tantalum carbide has low adhesion. The disadvantage of high production cost. The electrically insulating material may be delaminated by heat during the manufacturing process or at the beginning of the operation. If the substrate is a single-layer circuit system, the routing capability is limited. However, if the substrate is a multi-layer circuit system, the excessively thick dielectric layer will reduce the heat dissipation effect. In addition, the previous case technology still has problems such as insufficient heat sink performance, excessive volume or difficulty in thermally connecting to the next layer. The manufacturing process of the prior art is also not suitable for low-cost mass production operations.

In view of the various developments and related limitations of the existing high-power semiconductor device packages and heat-conducting plates, the industry needs a cost-effective, reliable, mass-produced, multi-functional, flexible signal routing and excellent heat dissipation. Semiconductor wafer assembly.

The invention provides a semiconductor wafer package comprising at least a semiconductor component, a heat sink, a wire and an adhesive layer. The heat sink includes at least one bump and a base. The wire includes a pad and a terminal. The semiconductor component is disposed on the bump and located on a side opposite to a recess in the bump, and is electrically connected to the wire and thermally coupled to the bump. The bump extends from the base into an opening of the adhesive layer, and the base extends from the side of the bump. The wire is located outside the recess and provides a signal route between the pad and the terminal.

According to one aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink and a wire. The adhesive layer has at least one opening. The heat sink includes at least a bump and a base, wherein (i) the bump abuts the base and is integral with the base, and protrudes from the base in a first vertical direction; (ii) the heat sink The pedestal extends from the side of the bump in a side direction perpendicular to the first vertical direction; and (iii) the bump has a recess, the recess is bounded by the bump in the first vertical direction Covering, but the recess is not covered by the bump in a second vertical direction opposite the first vertical direction. The wire includes a pad and a terminal.

The semiconductor component is disposed on the bump, extends on an outer side of the bump along the first vertical direction, and is located outside the recess and extends inward of a periphery of the recess. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal. The semiconductor component is also thermally bonded to the bump to thermally bond to the pedestal. The adhesive layer contacts the bump and the base and extends laterally from the bump to the terminal or over the terminal. The wire is located outside of the recess. The bump and the recess both extend into the opening.

According to another aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink and a wire. The adhesive layer has at least one opening. The heat sink includes at least one bump, a base and a cover, wherein (i) the bump abuts the base and is integral with the base, and protrudes from the base in a first vertical direction, The bump also abuts the cover body and protrudes from the cover body in a second vertical direction opposite to the first vertical direction; (ii) the base is perpendicular to the vertical direction from the bump a side surface extending laterally; (iii) the cover body covers the bump in the first vertical direction and protrudes from the side of the bump; and (iv) the bump has a recess, the recess The first vertical direction is covered by the bump, but the recess is not covered by the bump in the second vertical direction, the bump separates the recess from the cover, and the recess Extending across the majority of the bumps along the vertical directions and the lateral directions. The wire includes a pad and a terminal.

The semiconductor component is disposed on the cover body, extends on the outer side of the cover body along the first vertical direction, and is located outside the recess and extends inward of a circumference of one of the recesses. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal. The semiconductor component is also thermally coupled to the cover to be thermally coupled to the pedestal. The adhesive layer contacts the bump, the base and the cover, and is located between the base and the solder pad and between the base and the cover, and extends laterally from the bump to the terminal or Cross the terminal. The wire is located outside of the recess. The bump and the recess both extend into the opening.

According to another aspect of the invention, a semiconductor wafer package includes at least a semiconductor component, an adhesive layer, a heat sink, a substrate and a wire. The adhesive layer has at least one opening. The heat sink includes at least one bump, a base and a cover, wherein (i) the bump abuts the base and is integral with the base, and protrudes from the base in a first vertical direction, The bump also abuts the cover body and protrudes from the cover body in a second vertical direction opposite to the first vertical direction; (ii) the base is perpendicular to the vertical direction from the bump a side surface extending laterally; (iii) the cover body covers the bump in the first vertical direction and protrudes from the side of the bump; and (iv) the bump has a recess, the recess The first vertical direction is covered by the bump, but the recess is not covered by the bump in the second vertical direction, the bump separates the recess from the cover, and the recess Extending across the majority of the bumps along the vertical directions and the lateral directions. The substrate includes a dielectric layer with a via extending through the substrate. The wire includes a pad and a terminal.

The semiconductor component is disposed on the cover body, extends on the outer side of the cover body along the first vertical direction, and is located outside the recess and extends inward of a circumference of one of the recesses. The semiconductor component is electrically connected to the pad to be electrically connected to the terminal. The semiconductor component is also thermally coupled to the cover to be thermally coupled to the pedestal. The adhesive layer contacts the bump, the pedestal, the cover and the dielectric layer, but is spaced from the bond pad. The adhesive layer is located between the bump and the dielectric layer, between the pedestal and the bonding pad, between the pedestal and the cover, and between the pedestal and the dielectric layer, and The bump extends laterally to the terminal or over the terminal. The substrate is disposed on the adhesive layer. The dielectric layer contacts the pad and the cover, but is spaced from the bump and the base. The wire is located outside of the recess. The bump and the recess extend into the opening and the through hole, and the protrusion extends outside the through hole in the vertical direction. The cover covers the opening and the through hole in the first vertical direction.

The semiconductor component can be disposed on the bump outside the recess and extend inward of the periphery of the bump and the recess. For example, the semiconductor device may be disposed on the bonding pad and the cover body, extending on the outer side of the bonding pad and the cover body along the first vertical direction, and electrically connecting to the bonding pad by using a first solder, and The cover is thermally coupled to the second solder. In this example, the semiconductor component can extend laterally within the perimeter of the lead and beyond the perimeter and laterally extend within the perimeter of the bump and the recess and beyond the perimeter. Alternatively, the semiconductor device may be disposed on the cover and not disposed on the pad, and extend on the outer side of the pad and the cover along the first vertical direction, and electrically connected to the pad by using a wire. And thermally bonded to the cover by a die bonding material. In this case, the semiconductor component can be located outside the circumference of the wire and within the periphery of the bump and the recess and covered by the bump and the recess in the second vertical direction. In this example, the semiconductor component may be located outside the circumference of the wire, extending laterally beyond the periphery of the bump and the periphery of the cavity, and covering or not covering the bump in the first vertical direction. The pocket. In this example, the semiconductor component may be located outside the circumference of the wire and in the periphery of the bump, extending laterally in the periphery of the cavity and outside the periphery, and covering the cavity in the first vertical direction. And covered by the bump in the second vertical direction. Regardless of any arrangement, the semiconductor component is disposed on the bump, outside the recess, and extends inward of the periphery of the recess.

The semiconductor component can be a packaged or unpackaged semiconductor wafer. For example, the semiconductor component can be an LED package including an LED chip, and is disposed on the bonding pad and the cover, and extends on the outer side of the bonding pad and the cover along the first vertical direction, wherein the semiconductor component The semiconductor component is electrically connected to the pad by a first solder and thermally coupled to the cover by a second solder. Alternatively, the semiconductor device can be a semiconductor wafer such as an LED chip, and is disposed on the cover body and is not disposed on the solder pad, and extends on the outer side of the solder pad and the cover body along the first vertical direction, wherein The semiconductor component is electrically connected to the pad by a wire and thermally bonded to the cover by a die bonding material.

The adhesive layer contacts the bump and the dielectric layer in a gap between the bump and the substrate in the through hole, and contacts the base, the cover and the dielectric layer outside the notch . The adhesive layer may also contact and be located between the bump and the base, between the bump and the cover, between the bump and the dielectric layer, and between the base and the dielectric layer . The adhesive layer may also cover the portion of the base outside the bump in the first vertical direction, and cover the substrate in the second vertical direction while covering and surrounding one side wall of the bump in the lateral direction. The adhesive layer may also be isomorphically coated on the sidewall of the bump, a surface portion of the pedestal, and a surface of the dielectric layer, wherein the surface portion of the pedestal is adjacent to the bump and from the bump Projecting laterally while facing the first vertical direction, the surface of the dielectric layer faces the second vertical direction. The adhesive layer may also fill a space between the bump and the dielectric layer, a space between the base and the cover, and a space between the base and the substrate.

The adhesive layer can extend laterally from the bump to the terminal or across the terminal. For example, the adhesive layer and the terminal can extend to the peripheral edge of the set. In this case, the adhesive layer extends laterally from the bump to the terminal. Alternatively, the adhesive layer can extend to the peripheral edge of the set and the terminal is spaced from the peripheral edge of the set. In this example, the adhesive layer extends laterally from the bump and over the terminal.

The adhesive layer may pass through an imaginary horizontal line between the bump and the cover, an imaginary horizontal line between the bump and the dielectric layer, an imaginary horizontal line between the bump and a covered perforation, and the bump An imaginary horizontal line between one of the peripheral edges of the group, an imaginary vertical line between the pedestal and the cover, and an imaginary vertical line between the pedestal and the dielectric layer. If the dielectric layer is omitted, the adhesive layer may also pass through an imaginary vertical line between the pedestal and the pad, and an imaginary vertical line between the pedestal and the terminal.

The bump can be integrally formed with the base. For example, the bump and the pedestal may be a single metal body or comprise a single metal body in its interface, wherein the single metal body may be copper. The bump and the adhesive layer are coplanar at the cover. The bump may also contact the adhesive layer but maintain a distance from the dielectric layer and extend into the opening and the through hole while extending in the vertical direction outside the through hole.

The portion of the bump extending to the base may include a first bent corner, and the portion of the bump extending to the cover may include a second bent corner. The protrusion may be bent laterally outwardly at an angle of about 90 degrees adjacent to the base, and the protrusion may be bent laterally inwardly at an angle of about 90 degrees adjacent the cover. The bumps may also have a stamped special irregular thickness. In addition, the diameter of the bump at the base may be larger than the diameter of the bump at the cover. For example, the bump can be a flat-topped cone or a pyramidal shape having a diameter that decreases from the base toward the cover along the first vertical direction. Alternatively, the bump may be cylindrical or rectangular prism shaped, the diameter of which is fixed during the process of the bump extending from the base along the first vertical direction to the cover.

The pocket may be a flat-topped cone or a pyramidal shape having a diameter that decreases toward the cover along the first vertical direction. Alternatively, the recess may be cylindrical or rectangular prism shaped with a diameter that is fixed during the extension of the recess toward the cover in the first vertical direction. The pocket may also have a circumference of a circle, a square or a rectangle, and a circular, square or rectangular entrance. The recess may also have a shape conforming to the bump and extend into the opening and the through hole while extending across a substantial portion of the bump in the vertical and lateral directions.

The recess may be exposed toward the second vertical direction or may be covered in the second vertical direction. For example, the pocket can be in a hollow and non-sealed state. In this case, the recess is exposed toward the second vertical direction and the bump is also exposed toward the second vertical direction. Alternatively, the recess may be filled with a filler such as epoxy, polyimide or solder, wherein the filler contacts the bump and extends across the majority of the bump in the vertical and lateral directions. In addition, the filler is limited to the pocket and fills most or all of the pocket. For example, the pocket can be in an unsealed state and the filler can be substantially coplanar with the base and exposed toward the second vertical direction. As another example, the recess can be sealed by the base and the filler can contact the bump and the base while being surrounded by the two and covered by the base in the second vertical direction.

The pedestal can support the bump, the substrate and the adhesive layer, extending laterally to the outside of the cover, and extending to a peripheral edge of the set or at a distance from a peripheral edge of the set. The pedestal may also contact the adhesive layer and maintain a distance from the substrate while extending the outer side of the adhesive layer and the substrate along the second vertical direction. The pedestal may also cover the wire and the substrate in the second vertical direction.

The cover may have a uniform or uneven thickness. For example, the cover can have a uniform thickness and maintain a distance from the conductive layer and the dielectric layer. In this case, the cover may extend laterally from the bump to the adhesive layer without extending to the conductive layer or the dielectric layer, and cover the opening in the first vertical direction without covering the through hole. Alternatively, the cover body may have a first thickness adjacent to the bump and have a second thickness greater than the first thickness adjacent to the dielectric layer, and further have a side facing the first vertical direction Flat surface. In this case, the cover may contact the adhesive layer and the dielectric layer, wherein a portion of the cover adjacent to the adhesive layer and at a distance from the dielectric layer may have the first thickness, and the cover contacts the The dielectric layer, the portion adjacent to the pad and covering the opening and the through hole in the first vertical direction has the second thickness. The cover may also be spaced from the peripheral edge of the assembly and provide a wafer holder for the semiconductor component.

The cover may be rectangular or square, and the protrusion may be circular. In this case, the size and shape of the cover can be designed to match the thermal contact surface of the semiconductor component, and the size and shape of the bump are not designed in accordance with the thermal contact surface of the semiconductor component. In any case, the cover is thermally coupled to the base through the bump.

The heat sink can be composed of the bump, the base and the cover. The heat sink can also consist essentially of copper, aluminum or copper/nickel/aluminum alloy. The heat sink can also be composed of an inner copper, aluminum or copper/nickel/aluminum alloy core and a covered joint of the surface layer, wherein the covered joints are composed of gold, silver and/or nickel. Regardless of any composition, the heat sink can provide heat dissipation to diffuse the thermal energy of the semiconductor component to the next layer.

The substrate can contact the cover and maintain a distance from the bump and the base. The substrate can also be a laminated structure. The substrate may also include the pad and may or may not include the terminal.

The pad and the cover may have the same thickness adjacent to each other, but the thickness of the cover adjacent to the bump may be different from the thickness of the pad. In addition, the pad and the cover may be co-located on a surface facing the first vertical direction.

The pad and the terminal may have the same thickness and are co-located on a surface facing the first vertical direction. Alternatively, the pedestal and the terminal may have the same thickness and be co-located on a surface facing the second perpendicular direction.

The wire can contact or be spaced from the adhesive layer. For example, the pad and the terminal may contact the adhesive layer and extend beyond the first vertical direction of the adhesive layer. In this case, the pads can have the same thickness as the terminals and be coplanar with each other. Similarly, the bonding pad may contact the adhesive layer and extend on the outer side of the adhesive layer along the first vertical direction, and the terminal contacts the adhesive layer and extends on the outer side of the adhesive layer along the second vertical direction. In this case, the pedestal and the terminal can have the same thickness and be coplanar with each other. Alternatively, the pad and the terminal may contact the dielectric layer and maintain a distance from the adhesive layer while extending the outer side of the adhesive layer and the dielectric layer along the first vertical direction. In this case, the pads can have the same thickness as the terminals and be coplanar with each other. For another example, the bonding pad can contact the dielectric layer but maintain a distance from the adhesive layer, and extend along the outer side of the adhesive layer and the dielectric layer along the first vertical direction, so that the terminal contacts the adhesive layer and The dielectric layer maintains a distance and extends along the outer side of the adhesive layer and the dielectric layer along the second vertical direction. In this case, the pedestal and the terminal can have the same thickness and be coplanar with each other.

The wire may include a routing line extending from the adhesive layer and the dielectric layer on the outer side of the first vertical direction and on a conductive path between the pad and the terminal. For example, the pad, the terminal and the routing line may extend beyond the first vertical direction of the adhesive layer and the dielectric layer. In this example, the routing line can provide a horizontal route between the pad and the terminal. Similarly, the wire can include a coated via extending through the adhesive layer and the dielectric layer and on a conductive path between the bond pad and the terminal. For example, the bonding pad may extend on the outer side of the adhesive layer and the dielectric layer along the first vertical direction, and the terminal may extend on the outer side of the adhesive layer and the dielectric layer along the second vertical direction, the covered perforation The adhesive layer and the dielectric layer may be penetrated. In this example, the coated via can provide a vertical route between the pad and the terminal. Similarly, the bonding pad and the routing line may extend along the first vertical direction of the adhesive layer and the dielectric layer, and the terminal may extend between the adhesive layer and the dielectric layer along the second vertical direction. On the outer side, the covered through hole may penetrate the adhesive layer and the dielectric layer, and electrically connect the routing line and the terminal. In this example, the routing line can provide a horizontal route between the bond pad and the covered via, the covered via providing a vertical route between the routing line and the terminal. Additionally, the coated perforations may extend to a peripheral edge of one of the sets or at a distance from a peripheral edge of the set.

The wire can consist essentially of copper. The wire may also be composed of an inner copper core and a covered contact layer of the surface layer, wherein the covered contacts are composed of gold, silver and/or nickel. Regardless of the composition of the device, the wire can provide a signal route between the pad and the terminal.

The pad can serve as an electrical contact of the semiconductor component, the terminal can serve as an electrical contact of the next layer, and the pad and the terminal can provide a signal between the semiconductor component and the next layer routing.

The base, the cover, the solder pad and the terminal can be made of the same metal. For example, the pedestal, the cover, the pad and the terminal may comprise a gold, silver or nickel surface layer and an inner copper core, but mainly copper, as for the bump, the routing line and the coated perforation It can be mainly copper or all copper. In this example, a covered contact may include a gold or silver surface layer and an inner nickel layer, wherein the inner nickel layer contacts and is located between the surface layer and the inner copper core; or the covered contact may A nickel surface layer contacting the inner copper core is included.

The heat sink can include a copper core shared by the bump and the base and the cover. The wire can include a copper core shared by the pad and the terminal. For example, the heat sink may include a gold, silver or nickel surface layer disposed on the base and the cover, and an inner copper core disposed on the bump, the base and the cover, and the heat dissipation The seat is mainly copper. In this example, the pedestal may include a covered contact as its surface layer, and the cover may also include a covered contact as its surface layer, the bump may be copper, or include a covered contact. As the surface layer of the bump at the recess. Similarly, the wire may include a gold, silver or nickel surface layer disposed on the pad and the terminal, and an inner copper core disposed on the pad and the terminal, and the wire is mainly copper. In this case, the pad may include a covered contact as its surface layer, and the terminal may also include a covered contact as its surface layer.

The assembly may include an encapsulation material covering the semiconductor component in the first vertical direction. For example, the encapsulating material may be a packaging material for converting color, contacting an LED chip, a wire and a die bonding material, and converting the blue light emitted by the LED chip into white light. In this case, the assembly may include a transparent encapsulating material that contacts the encapsulating material for converting color and covers the encapsulating material for converting color in the first vertical direction. In addition, the encapsulating material for converting color may comprise a phthalocyanine resin and a phosphor, and the transparent encapsulating material may comprise a cerium oxide resin but no phosphor.

The group can be a first or second stage single crystal or polycrystalline device. For example, the group can be a first level package containing a single wafer or multiple wafers. Alternatively, the group may be a second-level module comprising a single LED package or a plurality of LED packages, wherein each of the LED packages may comprise a single LED chip or a plurality of LED chips.

The present invention provides a method of fabricating a semiconductor wafer package, comprising: providing a bump and an overhanging platform; and providing an adhesive layer on the overhanging platform, the step comprising inserting the bump into the adhesive layer Opening a conductive layer on the adhesive layer, the step of aligning the bump with one of the conductive layers; causing the adhesive layer to flow between the bump and the conductive layer; curing the adhesive layer; providing a wire comprising a pad, a terminal and a selected portion of the conductive layer; a semiconductor component disposed on the bump and having the semiconductor component on a side opposite to a recess in the bump, wherein A heat sink includes the bump and a pedestal, the pedestal includes a portion of the overhanging platform adjacent to the bump; electrically connecting the semiconductor component to the wire; and thermally bonding the semiconductor component to the heat sink.

According to one aspect of the invention, a method of fabricating a semiconductor wafer package includes: (1) providing a bump, an overhanging platform, an adhesive layer, and a conductive layer, wherein (a) the bump abuts the overhang Forming and integrating with the platform, further, the bump extends perpendicularly from the overhanging platform in a first vertical direction while extending into one of the openings of the adhesive layer and aligning with one of the through holes of the conductive layer, (b The exuding platform extends from the side of the protrusion in a side direction perpendicular to the first vertical direction, and (c) the protrusion has a recess facing the first vertical direction a second, opposite vertical direction, and covered by the bump in the first vertical direction, (d) the adhesive layer is disposed on the overhanging platform between the overhanging platform and the conductive layer, and Uncured, in addition, (e) the conductive layer is disposed on the adhesive layer; (2) causing the adhesive layer to flow into the through hole in the first vertical direction, a gap between the bump and the conductive layer; 3) curing the adhesive layer; (4) providing a wire comprising a solder pad, a terminal and one of the conductive layers (5) providing a semiconductor component on the bump, wherein (a) a heat sink includes the bump and a base, (b) the bump abuts the base and along the first vertical direction Extending vertically from the base, (c) the base includes a portion of the overhanging platform that abuts the bump and is integral with it and extends from the side of the bump, and (d) the The semiconductor component extends on the outer side of the bump along the first vertical direction, outside the recess, and extends inward of one of the circumferences of the recess; (6) electrically connecting the semiconductor component to the solder pad, The electrically connecting the semiconductor component to the terminal; and (7) thermally bonding the semiconductor component to the bump, thereby thermally bonding the semiconductor component to the pedestal.

According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a bump and an overhanging platform, wherein (a) the bump abuts and is integrated with the overhanging platform, Further, the bump extends perpendicularly from the overhanging platform in a first vertical direction, and (b) the overhanging platform extends from the side of the bump along a side direction perpendicular to the first vertical direction, and (c) the bump has a recess, wherein (i) the recess faces in a second perpendicular direction opposite the first vertical direction, (ii) the recess is in the first vertical direction The bump covers, and (iii) the recess extends across the majority of the bump in the vertical and lateral directions; (2) providing an adhesive layer, wherein an opening extends through the adhesive layer; (3) provides a a conductive layer, wherein a through hole extends through the conductive layer; (4) providing the adhesive layer on the overhanging platform, the step comprising inserting the bump into the opening, wherein the bump and the recess extend into the hole Opening the (5) the conductive layer on the adhesive layer, the step of aligning the bump with the through hole, wherein An adhesive layer is located between the overhanging platform and the conductive layer and is uncured; (6) heating and melting the adhesive layer; (7) causing the overhanging platform and the conductive layer to abut each other, thereby causing the bump to be The through hole moves in the first vertical direction, and at the same time, a pressure is applied to the molten adhesive layer between the overhanging platform and the conductive layer, and the pressure forces the molten adhesive layer to flow into the through hole in the first vertical direction. a gap between the bump and the conductive layer; (8) heat curing the molten adhesive layer, thereby mechanically adhering the bump to the overhanging platform to the conductive layer; (9) providing a wire, the wire comprising a solder a pad, a terminal and a selected portion of the conductive layer; (10) a semiconductor component is disposed on the bump, wherein (a) a heat sink includes the bump and a base, and (b) the bump abuts the a pedestal extending perpendicularly from the pedestal in the first vertical direction, (c) the pedestal comprising a portion of the overhanging platform that abuts the slab and is integral therewith and from the bulge Side protruding, and (d) the semiconductor component extends beyond the first vertical direction of the bump Located outside the recess and extending inwardly of one of the circumferences of the recess; (11) electrically connecting the semiconductor component to the pad, thereby electrically connecting the semiconductor component to the terminal; and (12) heat The semiconductor component is bonded to the bump, thereby thermally bonding the semiconductor component to the pedestal.

The disposing the conductive layer may include: disposing the conductive layer separately on the adhesive layer. Alternatively, the providing the conductive layer may include: disposing the conductive layer on the adhesive layer together with a carrier, so that the conductive layer contacts and is located between the adhesive layer and the carrier, and then after the adhesive layer is cured, first The carrier is removed and the wire is provided. Alternatively, the providing the conductive layer may include: disposing the conductive layer on the adhesive layer together with a dielectric layer, so that the conductive layer is kept away from the adhesive layer, and the dielectric layer is in contact with and located at the conductive layer. Between the layer and the adhesive layer.

According to another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a bump, an overhanging platform, an adhesive layer, and a conductive layer, wherein (a) the bump abuts the outer Extending and integrating with the platform, further, the bump extends perpendicularly from the overhanging platform in a first vertical direction while extending into one of the openings of the adhesive layer and aligning with one of the through holes of the conductive layer, b) the overhanging platform extends from the side of the bump along a side direction perpendicular to the first vertical direction, (c) the bump has a recess, wherein (i) the recess is facing one a second perpendicular direction opposite the first vertical direction, (ii) the recess is covered by the bump in the first vertical direction, and (iii) the recess extends across the vertical and lateral directions a majority of the bumps, (d) the adhesive layer is disposed on the overhanging platform between the overhanging platform and the conductive layer, and is uncured, and (e) the conductive layer is disposed on the (2) causing the adhesive layer to flow into the through hole in the first vertical direction between the bump and the conductive layer (3) curing the adhesive layer; (4) providing a wire comprising a pad and a terminal, wherein the pad comprises a selected portion of the conductive layer; (5) providing a heat sink, the heat dissipation The base includes the protrusion, a base and a cover, wherein (a) the protrusion abuts the base and protrudes perpendicularly from the base along the first vertical direction, (b) the base includes the outer Extending a portion of the platform adjacent to the projection and integral therewith and extending from the side of the projection, and (c) the cover abuts the projection and covering the first vertical direction a bump extending from the side of the bump and including a selected portion of the conductive layer; (6) providing a semiconductor component on the cover, wherein the semiconductor component extends along the cover along the first The outer side of the vertical direction is located outside the recess and extends inward of one of the circumferences of the recess; (7) electrically connecting the semiconductor component to the solder pad, thereby electrically connecting the semiconductor component to the terminal; (8) thermally bonding the semiconductor element to the cover, thereby thermally bonding the semiconductor element to the pedestal.

According to still another aspect of the present invention, a method of fabricating a semiconductor wafer package includes: (1) providing a bump and an overhanging platform, wherein (a) the bump abuts and is integrated with the overhanging platform, In addition, the bump extends perpendicularly from the overhanging platform in a first vertical direction, and (b) the overhanging platform extends from the side of the bump along a side direction perpendicular to the first vertical direction. And (c) the bump has a recess, wherein (i) the recess is facing a second perpendicular direction opposite the first vertical direction, (ii) the recess is in the first vertical direction Covered by the bump, (iii) the recess extends across the majority of the bump in the vertical and lateral directions, and (iv) the recess has an entrance at the overhanging platform; (2) provides a An adhesive layer, wherein an opening extends through the adhesive layer; (3) providing a conductive layer, wherein a through hole extends through the conductive layer; (4) providing the adhesive layer on the overhanging platform, the step comprising the bump Inserting the opening, wherein the bump and the recess extend into the opening; (5) disposing the conductive layer on the adhesive layer The step of aligning the bump with the through hole, wherein the adhesive layer is between the overhanging platform and the conductive layer and is not cured; (6) heating and melting the adhesive layer; (7) making the overhang The platform and the conductive layer abut each other, thereby moving the bump in the first vertical direction in the through hole, and applying pressure to the molten adhesive layer between the overhanging platform and the conductive layer, the pressure forcing the melting Adhesively flowing into the through hole in the first vertical direction, a gap between the bump and the conductive layer; (8) heating and curing the molten adhesive layer, thereby mechanically adhering the bump to the overhanging platform to The conductive layer; (9) providing a wire comprising a pad and a terminal, wherein the pad comprises a selected portion of the conductive layer; (10) providing a heat sink, the heat sink comprising the bump, a base and a cover, wherein (a) the protrusion abuts the base and extends perpendicularly from the base in the first vertical direction, and (b) the base includes a portion of the overhanging platform, a portion is adjacent to the bump and integral with the same, and protrudes from the side of the bump, and (c) The cover body abuts the bump and covers the bump in the first vertical direction while extending from the side of the bump and includes a selected portion of the conductive layer; (11) providing a semiconductor component to the cover Body, wherein the semiconductor component extends on the outer side of the cover body along the first vertical direction, outside the recess, and extends inward of one of the circumferences of the recess; (12) electrically connecting the semiconductor component to The pad electrically connects the semiconductor component to the terminal; and (13) thermally bonding the semiconductor component to the cover, thereby thermally bonding the semiconductor component to the pedestal.

Providing the bump may include mechanically stamping a metal plate to form the bump on the metal plate and forming the recess in the bump. In this case, the bump is a stamped portion of the metal sheet, and the overhanging platform is an unpunched portion of the metal sheet.

Providing the adhesive layer can comprise: providing a film of uncured epoxy. Flowing the adhesive layer can include melting the uncured epoxy resin and extruding the uncured epoxy resin between the overhanging platform and the conductive layer. Curing the adhesive layer can include curing the melted uncured epoxy resin.

Providing the bond pad can include removing selected portions of the conductive layer after curing the adhesive layer. The removing may include wet chemical etching the conductive layer with a patterned etch stop layer defining the pad such that the pad includes a selected portion of the conductive layer.

Providing the cover may include removing selected portions of the conductive layer after curing the adhesive layer. The removing may include wet chemical etching the conductive layer with a patterned etch stop layer defining the cover such that the cover includes a selected portion of the conductive layer.

Providing the terminal can include removing a selected portion of the conductive layer after curing the adhesive layer. The removing may include wet chemical etching the conductive layer with a patterned etch stop layer defining the terminal such that the terminal includes a selected portion of the conductive layer.

Providing the terminal can include removing selected portions of the overhanging platform after curing the adhesive layer. The removing can include wet chemical etching the overhanging platform with a patterned etch stop layer defining the terminal such that the terminal includes a selected portion of the overhanging platform.

Providing the pedestal can include removing selected portions of the overhanging platform after curing the adhesive layer. The removing may include wet chemical etching the overhanging platform with a patterned etch stop layer defining the pedestal such that the pedestal includes a selected portion of the overhanging platform.

Providing the pad and the cover may include removing a selected portion of the conductive layer using a patterned etch stop layer defining the pad and the cover. In this way, the pad and the cover can be simultaneously formed by the same patterned etching resist in the same wet chemical etching step. Similarly, providing the pad and the terminal can include removing a selected portion of the conductive layer using a patterned etch stop layer that defines the pad and the terminal. In this way, the pad and the terminal can be simultaneously formed by the same patterned etching resist layer in the same wet chemical etching step. Similarly, providing the pad, the terminal and the cover may include removing a selected portion of the conductive layer by a patterned etch stop layer defining the pad, the terminal and the cover. In this way, the pad, the terminal and the cover can be simultaneously formed by the same patterned etching resist in the same wet chemical etching step.

Providing the pedestal and the terminal can include removing a selected portion of the overhanging platform using a patterned etch stop layer that defines the pedestal and the terminal. In this way, the susceptor and the terminal can be simultaneously formed by the same patterned etch resist layer in the same wet chemical etching step.

The pad may be formed before, after, or during formation of the terminal. Therefore, the pad and the terminal can be simultaneously formed or formed in the same wet chemical etching step by using different patterned etching resist layers. Likewise, the susceptor can be formed before, after, or during formation of the cover. Therefore, the pedestal and the cover can be formed simultaneously or sequentially by using different patterned etch resist layers in the same wet chemical etching step, or by using a patterned etch stop that can define the cover instead of the pedestal. The layer successively forms the base and the cover. Similarly, the pad, the terminal, the base and the cover may be formed simultaneously or sequentially.

Providing the bonding pad may include: after curing the adhesive layer, grinding the bump, the adhesive layer and the conductive layer, and causing the bump, the adhesive layer and the conductive layer to face the first vertical direction The lateral surfaces are laterally flush with each other; then selected portions of the conductive layer are removed using a patterned etch stop layer defining the pads such that the pads comprise selected portions of the conductive layer. The grinding may include grinding the adhesive layer without grinding the bump, and then grinding the bump, the adhesive layer, and the conductive layer. The removing may include: wet chemical etching the conductive layer with a patterned etch stop layer defining the pad.

Providing the bonding pad may include: depositing a conductive metal on the bump, the adhesive layer and the conductive layer to form a coating layer after the polishing is completed, and then removing selected portions of the conductive layer and the coating layer, The pad is provided with selected portions of both the conductive layer and the cover layer. Depositing the conductive metal to form the coating layer may include: disposing a thin coating layer on the bump, the adhesive layer and the conductive layer in an electroless plating manner, and then plating a thick coating layer on the thin coating layer . The removing may include wet chemical etching the conductive layer and the coating layer with a patterned etch stop layer defining the bonding pad.

Providing the cover body may include: depositing a conductive metal on the bump, the adhesive layer and the conductive layer to form a coating layer after the polishing is completed, and then removing selected portions of the conductive layer and the coating layer, The cover is provided with selected portions of both the conductive layer and the cover layer. Depositing the conductive metal to form the coating layer may include: disposing a thin coating layer on the bump, the adhesive layer and the conductive layer in an electroless plating manner, and then plating a thick coating layer on the thin coating layer . The removing may include wet chemical etching the conductive layer and the coating layer with a patterned etch stop layer defining the cover.

Providing the terminal may include: depositing a conductive metal on the bump, the adhesive layer and the conductive layer to form a coating layer after the polishing is completed, and then removing selected portions of the conductive layer and the coating layer, so that The terminal includes selected portions of both the conductive layer and the cover layer. Depositing the conductive metal to form the coating layer may include: disposing a thin coating layer on the bump, the adhesive layer and the conductive layer in an electroless plating manner, and then plating a thick coating layer on the thin coating layer . The removing may include wet chemical etching the conductive layer and the coating layer with a patterned etch stop layer defining the terminal.

Providing the terminal may include: depositing a conductive metal on the overhanging platform to form a coating layer after the grinding is completed, and then removing selected portions of both the overhanging platform and the covering layer such that the terminal includes the overhang A selected portion of both the platform and the overlay. Depositing the conductive metal to form the coating layer may include: disposing a thin coating layer on the overhanging plate in an electroless plating manner, and then plating a thick coating layer on the thin coating layer. The removing may include wet chemical etching the overhanging platform and the coating layer with a patterned etch stop layer defining the terminal.

Providing the pedestal may include: depositing a conductive metal on the overhanging platform to form a coating layer after the grinding is completed, and then removing selected portions of the overhanging platform and the covering layer to cause the pedestal to include the A selected portion of both the overhanging platform and the covering layer. Depositing the conductive metal to form the coating layer may include: disposing a thin coating layer on the overhanging plate in an electroless plating manner, and then plating a thick coating layer on the thin coating layer. The removing may include wet chemical etching the overhanging platform and the coating layer with a patterned etch stop layer defining the susceptor.

Providing the susceptor can include depositing a conductive metal on the overhanging platform and a filler in the recess to form a coating layer after the grinding is completed. Depositing the conductive metal to form the coating layer may include: disposing a thin coating layer on the overhanging platform and the filler in an electroless plating manner, and then plating a thick coating layer on the thin coating layer. Additionally, the pedestal can enclose the recess and cover the bump, the recess and the filler in the second vertical direction.

Providing the wire can include providing the pad, the terminal, and a routing line, wherein the routing line is on a conductive path between the pad and the terminal. The routing line can include a selected portion of the conductive layer and extend beyond the first vertical direction of the adhesive layer and the dielectric layer.

Providing the pad and the routing line can include removing a selected portion of the conductive layer using a patterned etch stop layer that defines the pad and the routing line. In this way, the pad and the routing line can be formed simultaneously using the same patterned etch stop layer in the same wet chemical etching step.

Providing the wire can include: providing the pad, the terminal, and a covered via, wherein the covered via is located on a conductive path between the pad and the terminal. The coated perforation may be formed first, and then the pad and the terminal are formed, wherein the covered via extends through the conductive layer, the adhesive layer, the dielectric layer and the overhanging platform.

Providing the pedestal, the cover, the bonding pad, the terminal and the covered perforation may include: after curing the adhesive layer, drilling through the conductive layer, the adhesive layer, the dielectric layer and the overhanging platform to form a hole; a conductive metal is deposited on the bump, the adhesive layer, the dielectric layer, the conductive layer and the overhanging platform, and the hole to form a coating layer, wherein the coating layer is on the bump Forming a first coating layer on the adhesive layer and the conductive layer, and forming a second coating layer on the overhanging platform, and forming the covered perforation in the hole; and then forming a definable on the first coating layer a first patterned etch stop layer of the pad and the cover, and a second patterned etch stop layer defining the pedestal and the terminal on the second cover layer; using the first patterned etch The resist layer etches the conductive layer and the first cladding layer to form a pattern defined by the first patterned etch resist layer; etching the overhanging platform and the second cladding layer by using the second patterned etch resist layer Forming the second patterned etch stop layer The pattern; and finally removing the etch resist layer patterned such.

a first coating layer on the bump, the adhesive layer and the conductive layer may contact the bump, the adhesive layer and the conductive layer, and cover the bump in the first vertical direction, and respectively form the solder pad And a part of the terminal, the routing line and the cover. Similarly, the second covering layer on the overhanging platform can contact the overhanging platform, contact the bump and/or one of the fillings in the recess, and cover the bump in the second vertical direction while A portion of the base and a portion of the terminal are formed separately. The routing line can contact the dielectric layer but maintain a distance from the adhesive layer. The coated via can contact the adhesive layer and the dielectric layer in the hole. Moreover, etching the conductive layer and the first cladding layer may include exposing the dielectric layer toward the first vertical direction, but not exposing the adhesive layer toward the first vertical direction. Etching the overhanging platform and the second covering layer may include exposing the adhesive layer toward the second vertical direction without exposing the dielectric layer toward the second vertical direction.

The pocket may be hollow or contain a filler. For example, after the semiconductor component is disposed, the recess may have a hollow space, and the hollow space extends across the majority of the bump along the vertical and lateral directions. In this case, the recess can be exposed toward the second vertical direction after the semiconductor element is disposed, and the bump is also exposed toward the second vertical direction. Alternatively, before the semiconductor component is disposed, the recess may be filled with a filler such as epoxy resin, polyimide or solder, and the filler extends across the bump in the vertical and lateral directions. Part and fill most or all of the pocket. For example, the filler may be first filled into the pocket and the adhesive layer disposed. As another example, the step of filling the filler in the recess can be performed after curing the adhesive layer and before providing the wire. In this case, the filler may be first filled into the recess, and the second coating layer may be disposed on the overhanging platform and the filler; or the second coating layer may be first disposed on the filler layer. The bump and the overhanging platform are filled into the recess. In addition, the filler can be ground after the filling is completed, so that the filler is not only accommodated in the pocket, but also laterally facing the second vertical direction of the overhanging platform or the second covering layer. It is laterally aligned on the plane.

Flowing the adhesive layer can include filling the gap with the adhesive layer. Flowing the adhesive layer may further include: pressing the adhesive layer through the notch and extending along the first vertical direction to the bump and the conductive layer, and finally reaching both the bump and the conductive layer a surface portion, wherein the surface portions abut the notch and face the first vertical direction, and therefore, the adhesive layer extends to the outer side of the bump and the conductive layer along the first vertical direction.

Curing the adhesive layer can include mechanically bonding the bump to the overhanging platform to the conductive layer.

The disposing the semiconductor device on the bump may include: disposing the semiconductor device on the cover, and thus disposing the semiconductor device on the bump. The disposing the semiconductor device may further include positioning the semiconductor device in a periphery of the cover and outside a periphery of the bonding pad, or positioning the semiconductor device in a periphery of the cover and the periphery of the bonding pad and outside the periphery. The semiconductor component may also be located in or around the periphery of the bump and the periphery of the recess and outside the circumference of the lead or extending beyond the circumference of the lead and beyond the circumference. Additionally, the semiconductor component can be located within the perimeter of the pedestal. Regardless of the arrangement, the semiconductor component extends laterally within the periphery of the recess.

The disposing the semiconductor device may include: providing a first solder and a second solder, wherein the first solder is located between an LED package including an LED chip and the bonding pad, and the second solder is located in the LED package Between the covers. Electrically connecting the semiconductor component can include providing the first solder between the LED package and the pad. Thermally bonding the semiconductor component can include providing the second solder between the LED package and the cover.

Providing the semiconductor device can include providing a die bond material between a semiconductor wafer (such as an LED chip) and the cover. Electrically bonding the semiconductor component can include providing a wire between the wafer and the pad. Thermally bonding the semiconductor component can include providing the die attach material between the wafer and the cover.

The adhesive layer may contact the bump, the base, the cover and the dielectric layer, and cover the wire and the substrate in the second vertical direction, and cover and surround one of the bumps in the lateral direction The side wall extends to the peripheral edge formed by the separation of the other components of the same batch after the assembly is completed.

The pedestal can support the bump, the substrate and the adhesive layer, extending laterally to the outside of the cover, and extending to the periphery of the set after the assembly is manufactured and separated from other groups produced in the same batch The edge or distance from the peripheral edge of the group.

The invention has several advantages. The heat sink can provide excellent heat dissipation and prevent thermal energy from flowing through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not easily delaminated. The heat sink can provide a relatively large surface area with relatively thin metal, thereby helping to reduce weight and cost. The bump and the recess can be mechanically stamped, thereby improving precision, and the bump and the base can be integrally formed to improve reliability. The cover body can be tailored to the semiconductor component to enhance the effect of thermal bonding. The filler can provide mechanical support for the bump to increase strength. The bonding pad and the cover may include a selected portion of the conductive layer superposed on the adhesive layer or superposed on the dielectric layer, thereby improving reliability. The adhesive layer may be located between the bump and the substrate, between the base and the substrate, and between the cover and the substrate, thereby providing a strong mechanical connection between the heat sink and the substrate. The wires can form a simple circuit pattern to provide signal routing or to form complex circuit patterns for flexible multilayer signal routing. The wire may also utilize a coated via extending through the adhesive layer and the dielectric layer to provide a vertical signal routing between the bond pad and the terminal. In addition, the coated perforation may be formed after the adhesive layer is cured, and maintain a hollow tubular shape, or be cleaved at the peripheral edge of the assembly, so that the solder that is subsequently reflowed to the surface of the terminal is wetted and flows into the covered perforation. Therefore, the void is formed in the solder because the covered perforation is filled with the adhesive layer or other non-wettable insulating material, and this design contributes to the improvement of reliability. The pedestal provides mechanical support for the substrate to prevent it from bending and deforming. The assembly can be manufactured by a low temperature process, which not only reduces stress but also improves reliability. The assembly can also be fabricated using high control procedures that can be easily implemented by circuit boards, lead frames, and tape and roll substrate manufacturers.

The above and other features and advantages of the present invention will be further described hereinafter by way of various embodiments.

1A and 1B are cross-sectional views showing a method of manufacturing a bump and an overhanging platform according to an embodiment of the present invention, wherein FIG. 1C is an enlarged cross-sectional view of FIG. 1B, and FIGS. 1D and 1E are respectively FIG. 1B. Top view and bottom view.

1A is a cross-sectional view of a metal plate 10 that includes opposing major surfaces 12 and 14. The illustrated metal plate 10 is a copper plate having a thickness of 150 microns. Copper has the advantages of high thermal conductivity, good bonding and low cost. The metal plate 10 can be made of a variety of metals such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold, mixtures thereof, and alloys thereof.

1B, 1C, 1D, and 1E are a cross-sectional view, an enlarged cross-sectional view, a plan view, and a bottom view, respectively, of the metal plate 10 forming the bump 16, the overhanging platform 18, and the recess 20. The bump 16, the recess 20 and the bent corners 22, 24 are mechanically stamped from the metal plate 10, wherein the bump 16 is a portion of the metal plate 10 that is stamped, and the overhanging platform 18 is a metal plate 10 that is not stamped. The bent portions 22 and 24 are the bent portions of the metal plate 10.

The projection 16 abuts the overhanging platform 18, is integral with the overhanging platform 18, and extends from the overhanging platform 18 in an upward direction, and the overhanging platform 18 is oriented along a side perpendicular to the upward and downward directions (eg, Left and right) extend from the side of the bump 16.

The bump 16 includes bent corners 22 and 24, side walls 26 and a top plate 28. The bent corners 22 and 24 are bent by stamping and cause the side walls 26 to also have a stamped shape and slope. The bend corners 22 abut the top panel 28 and extend laterally inwardly, and the bend corners 24 abut the overhanging platform 18 and extend laterally outward. The side walls 26 extend vertically between the bend corners 22 and 24 in the upward and downward directions, while the top plate 28 extends laterally inwardly from the bend corners 22. Further, the bent corner 22 has an angle θ ₁ which is 90 degrees, and the bent corner 24 has an angle θ ₂ which is the same as 90 degrees (see FIG. 1C). Thus, the angle θ ₁ of the side wall 26 relative to the top plate 28 is 90 degrees, and the angle θ _{2 of the} side wall 26 relative to the overhanging platform 18 is also 90 degrees.

The bumps 16 are cylindrical and have a diameter that is fixed in the vertical direction between the bent corners 22 and 24. The height of the bumps 16 (relative to the overhanging platform 18) is 600 microns and the diameter is 1000 microns. Further, the bumps 16 have an irregular thickness due to the stamping. For example, the side wall 26 elongated by stamping is thinner than the top plate 28. However, for ease of illustration, the bumps 16 have a uniform thickness in the figures.

The recess 20 extends into the projection 16 and is covered by the projection 16 from above while the face faces downward. Further, the recess 20 is exposed outwardly downward, and the portion of the projection 16 forming the recess 20 is also oriented downward. Exposed. Therefore, the recess 20 is hollow, its entrance at the overhanging platform 18 is not closed, and the projection 16 does not cover the recess 20 from below. Since the shape of the recess 20 coincides with the projection 16, the recess 20 also has a cylindrical shape with a fixed diameter. Furthermore, the pockets 20 extend across the majority of the bumps 16 in the vertical and side directions.

2A and 2B are cross-sectional views illustrating a method of making an adhesive layer in an embodiment of the present invention. The 2C and 2D drawings are a plan view and a bottom view, respectively, which are drawn according to FIG. 2B.

2A is a cross-sectional view of the adhesive layer 30, wherein the adhesive layer 30 is a B-stage uncured epoxy film which is an uncured and unpatterned sheet having a thickness of 250 microns.

Adhesive layer 30 can be a variety of dielectric films or films made from a variety of organic or inorganic electrical insulators. For example, the adhesive layer 30 may initially be a film in which a resin-type thermosetting epoxy resin is partially cured to a medium stage after being immersed in a reinforcing material. The epoxy resin may be FR-4, but other epoxy resins such as polyfunctional and bismaleimide-triazabenzene (BT) resins may also be used. Cyanate esters, polyimine and polytetrafluoroethylene (PTFE) are also suitable materials for specific applications. The reinforcing material may be an electronic grade glass, or may be other reinforcing materials such as high-strength glass, low-induced glass, quartz, kevlar aramid, and paper. The reinforcing material may also be a woven fabric, a non-woven fabric or a non-directional microfiber. Fillers such as enamel (melt fused silica) can be added to the film to improve thermal conductivity, thermal shock resistance and thermal expansion matching. Commercially available prepregs can be utilized, such as the SPEEDBOARD C film from W. L. Gore & Associates of Oakley, Wisconsin, USA.

The 2B, 2C, and 2D drawings are a cross-sectional view, a top view, and a bottom view, respectively, of the adhesive layer 30 having the opening 32. The opening 32 is a window that extends through the adhesive layer 30 and has a diameter of 1050 microns. The opening 32 is formed by mechanically drilling through the film, but may be fabricated by other techniques such as stamping and stamping.

3A and 3B are cross-sectional views illustrating a method of fabricating a substrate in an embodiment of the present invention, and FIGS. 3C and 3D are respectively a plan view and a bottom view, which are drawn according to FIG. 3B.

3A is a cross-sectional view of the substrate 34. The substrate 34 includes a conductive layer 36 and a dielectric layer 38. Conductive layer 36 is an electrical conductor that contacts dielectric layer 38 and extends over dielectric layer 38. Dielectric layer 38 is an electrical insulator. For example, the conductive layer 36 is a copper plate having no pattern and a thickness of 50 μm, and the dielectric layer 38 is an epoxy resin having a thickness of 350 μm.

3B, 3C, and 3D are respectively a cross-sectional view, a plan view, and a bottom view of the substrate 34 having the through holes 40. The through hole 40 is a window that penetrates the substrate 34 and has a diameter of 1050 microns. The through hole 40 is formed by mechanically drilling through the conductive layer 36 and the dielectric layer 38, but may be fabricated by other techniques such as punching and stamping. The opening 32 has the same diameter as the through hole 40. Further, the drill having the same opening 32 as the through hole 40 may be formed in the same manner on the same drill stand, or may be formed in the same manner on the same punch by the same punch.

The substrate 34 is illustrated herein as a laminate structure, but the substrate 34 can also be other electrical interconnect structures such as ceramic plates or printed circuit boards. Similarly, the substrate 34 can further comprise a plurality of layers of embedded circuits.

4A to 4L are cross-sectional views illustrating a method of fabricating a thermally conductive plate in accordance with an embodiment of the present invention, the thermally conductive plate comprising a bump 16, an adhesive layer 30, and a substrate 34. The 4M and 4N drawings are a plan view and a bottom view of the 4th L, respectively.

The structures in Figs. 4A and 4B are in a state in which the recesses are downwardly disposed so that the adhesive layer 30 and the substrate 34 are placed on the overhanging platform 18 by gravity. The structure in Figures 4C to 4L still maintains the state of the pocket down. In other words, the pocket 20 is facing downward and is covered by the bump 16 from above. However, regardless of where the pocket 20 is facing, the relative orientation of the structure is unchanged. In particular, regardless of whether the structure is inverted, rotated or tilted, the pockets 20 are always covered by the bumps 16 in a first vertical direction. Likewise, regardless of whether the structure is inverted, rotated or tilted, the bumps 16 extend all the way out of the overhanging platform 18 in the first vertical direction and extend beyond the substrate 34 in a second vertical direction. The first and second vertical directions are opposite to each other with respect to the direction of the structure, and are perpendicular to the aforementioned side direction.

4A is a cross-sectional view of the adhesive layer 30 disposed on the overhanging platform 18. The adhesive layer 30 is lowered onto the overhanging platform 18 such that the bumps 16 are inserted upwardly through the opening 32, and finally the adhesive layer 30 is contacted and positioned on the overhanging platform 18. Preferably, the bump 16 is aligned with the opening 32 after insertion and penetration through the opening 32 and is located centrally within the opening 32 without contacting the adhesive layer 30.

In the structure shown in Fig. 4B, the substrate 34 has been placed on the adhesive layer 30. The substrate 34 is lowered onto the adhesive layer 30, and the bumps 16 are inserted upward into the through holes 40, and finally the substrate 34 is brought into contact with and positioned on the adhesive layer 30.

The bump 16 is aligned with the through hole 40 after being inserted (but not penetrating) through the through hole 40 and located at a central position within the through hole 40 without contacting the substrate 34. Therefore, the notch 42 is located in the through hole 40 and between the bump 16 and the substrate 34. The notch 42 laterally surrounds the bump 16 while being laterally surrounded by the substrate 34. Further, the opening 32 and the through hole 40 are aligned with each other and have the same diameter.

At this time, the substrate 34 is disposed on and in contact with the adhesive layer 30 and extends over the adhesive layer 30. After extending through the opening 32, the bump 16 enters the via 40 and reaches the dielectric layer 38. The bump 16 is 50 microns lower than the top surface of the conductive layer 36 and is exposed outwardly through the through hole 40. The adhesive layer 30 contacts the overhanging platform 18 and the substrate 34 and is located between the two. Adhesive layer 30 contacts dielectric layer 38 but is at a distance from conductive layer 36. At this stage, the adhesive layer 30 is still a film of B-stage uncured epoxy, while the gap 42 is air.

FIG. 4C shows that the adhesive layer 30 flows into the notch 42 after being heated and pressurized. In this figure, the method of forcing the adhesive layer 30 into the notch 42 is to apply downward pressure to the conductive layer 36 and/or to apply upward pressure to the outwardly extending platform 18, that is, to press the overhanging platform 18 against the substrate 34. The adhesive layer 30 is pressed; at the same time, the adhesive layer 30 is also heated. The heated adhesive layer 30 can be arbitrarily shaped under pressure. Therefore, after the adhesive layer 30 between the overhanging platform 18 and the substrate 34 is pressed, its original shape is changed and flows upward into the notch 42. The overhanging platform 18 and the substrate 34 are continuously pressed toward each other until the adhesive layer 30 fills the notch 42. In addition, after the gap between the overhanging platform 18 and the substrate 34 is reduced, the adhesive layer 30 still fills the reduced gap.

For example, the overhanging platform 18 and the conductive layer 36 can be disposed between a press machine and a lower pressing table (not shown). In addition, an upper baffle and an upper cushioning paper (not shown) may be interposed between the conductive layer 36 and the upper pressing table, and the lower baffle and the lower cushioning paper (not shown) are placed on the overhanging platform. 18 between the lower pressing table. The stacked body thus constructed is, in order from top to bottom, an upper pressing table, an upper baffle, an upper cushioning paper, a substrate 34, an adhesive layer 30, an overhanging platform 18, a lower cushioning paper, a lower baffle plate, and a lower pressing table. Further, the stacked body may be positioned on the lower pressing table by a tool pin (not shown) extending upward from the lower pressing table and passing through a registration hole (not shown) of the metal plate 10.

The upper and lower press tables are then heated and pushed toward each other, whereby the adhesive layer 30 is heated and pressed. The baffle disperses the heat of the platen to apply heat evenly to the overhanging platform 18 and the substrate 34 or even the adhesive layer 30. The cushioning paper disperses the pressure of the platen so that the pressure is uniformly applied to the overhanging platform 18 and the substrate 34 or even the adhesive layer 30. Initially, the dielectric layer 38 contacts and is pressed against the adhesive layer 30. As the platen continues to operate and continues to heat, the adhesive layer 30 between the overhanging platform 18 and the substrate 34 is squeezed and begins to melt, thereby flowing upward into the notch 42 and through the dielectric layer 38 and the conductive layer 36. For example, the uncured epoxy resin is melted into the gap 42 after being melted by heat, but the reinforcing material and the filler remain between the overhanging platform 18 and the substrate 34. The adhesive layer 30 rises faster in the through hole 40 than the bump 16 and ends up filling the gap 42. The adhesive layer 30 also rises slightly above the notch 42 and overflows to the top surface of the bump 16 and the top surface of the conductive layer 36 adjacent the notch 42 before the platen stops operating. This can happen if the film thickness is slightly larger than actually needed. As a result, the adhesive layer 30 forms a thin layer of cover on the top surface of the bump 16 and the top surface of the conductive layer 36. The pressing table stops after touching the bumps 16, but continues to heat the adhesive layer 30.

The direction in which the adhesive layer 30 flows upward in the notch 42 is as shown by the upward bold arrow in the figure, and the upward movement of the bump 16 and the overhanging platform 18 with respect to the substrate 34 is as shown by the upward fine arrow, and the substrate 34 is opposed to the convex The downward movement of the block 16 and the overhanging platform 18 is as indicated by the downwardly fine arrow.

The adhesive layer 30 in Fig. 4D has been cured.

For example, after the platen stops moving, the bump 16 and the overhanging platform 18 are continuously clamped and heated, thereby converting the melted B-stage epoxy resin into C-stage curing or Hardened epoxy resin. Therefore, the epoxy resin is cured in a manner similar to conventional lamination. After the epoxy resin is cured, the platen is separated to remove the structure from the press.

The cured adhesive layer 30 provides a secure mechanical bond between the bumps 16 and the substrate 34 and between the overhanging platform 18 and the substrate 34. The adhesive layer 30 can withstand normal operating pressure without deformation and damage, and is only temporarily distorted when excessive pressure is applied. Furthermore, the adhesive layer 30 can absorb thermal expansion mismatch between the bump 16 and the substrate 34 and between the overhanging platform 18 and the substrate 34.

At this stage, the bumps 16 are substantially coplanar with the conductive layer 36, and the adhesive layer 30 and the conductive layer 36 extend to the top surface of the upward direction. For example, the adhesive layer 30 between the overhanging platform 18 and the dielectric layer 38 is 200 microns thick, which is 50 microns smaller than its initial thickness of 250 microns; that is, the bumps 16 are raised by 50 microns in the through holes 40, while the substrate 34 is relatively The bump 16 is lowered by 50 microns. The height of the bumps 16 of 600 microns is substantially equivalent to the combined height of the conductive layer 36 (50 microns), the dielectric layer 38 (350 microns) and the underlying adhesive layer 30 (200 microns). In addition, the bumps 16 are still located at the center of the openings 32 and the through holes 40 and are spaced apart from the substrate 34, and the adhesive layer 30 fills the space between the overhanging platform 18 and the substrate 34 and fills the gaps 42. For example, the width of the notch 42 (and the adhesive layer 30 between the bump 16 and the substrate 34) is 25 microns ((1050-1000)/2). Adhesive layer 30 extends across dielectric layer 38 within indentation 42. In other words, the adhesive layer 30 in the notch 42 extends in the upward and downward directions and across the thickness of the dielectric layer 38 of the outer sidewall of the indentation 42. The adhesive layer 30 also includes a thin top portion over the indentation 42 that contacts the top surface of the bump 16 and the top surface of the conductive layer 36 and extends 10 microns above the bump 16.

In the structure shown in Fig. 4E, the bumps 16, the adhesive layer 30, and the top of the conductive layer 36 are removed.

The tops of the bumps 16, the adhesive layer 30 and the conductive layer 36 are removed by grinding, for example, by rotating the diamond wheel and the top of the structure with distilled water. Initially, the diamond wheel only scratches the adhesive layer 30. With continuous grinding, the adhesive layer 30 becomes thinner as the surface to be worn is moved downward. The diamond wheel will eventually contact the bump 16 and the conductive layer 36 (not necessarily simultaneously), thus beginning to grind the bump 16 and the conductive layer 36. After continuous grinding, the bumps 16, the adhesive layer 30, and the conductive layer 36 are all thinned by the worn surface being moved down. The grinding is continued until the desired thickness is removed, and then the structure is rinsed with distilled water to remove dirt.

The above grinding step abrades the top of the adhesive layer 30 by 25 microns, the top of the bump 16 by 15 microns, and the top of the conductive layer 36 by 15 microns. The thickness reduction has no significant effect on the bumps 16 or the adhesive layer 30, but the thickness of the conductive layer 36 is greatly reduced from 50 micrometers to 35 micrometers.

So far, the bumps 16, the adhesive layer 30 and the conductive layer 36 are collectively located on the smooth top side of the upper surface of the dielectric layer 38 in the upward direction.

The structure shown in Fig. 4F has coating layers 44 and 46. The covering layer 44 is formed on the bump 16, the adhesive layer 30, and the conductive layer 36, and the covering layer 46 is formed on the bump 16 and the overhanging platform 18.

The coating layer 44 is deposited on the lateral top surface of the bump 16, the adhesive layer 30 and the conductive layer 36 which are exposed upward and outward, while contacting and covering the three from above. The cover layer 44 is an unpatterned copper layer having a thickness of 25 microns.

The covering layer 46 is deposited on the bottom surface of the bump 16 and the overhanging platform 18 which is outwardly exposed downward, while contacting and covering the two from below. The cover layer 46 is an unpatterned copper layer having a thickness of 25 microns.

For example, the structure can be immersed in an activator solution such that the adhesive layer 30 can react with electroless copper to produce a catalyst. Then, an upper electroless copper plating layer is provided on the bump 16, the adhesive layer 30 and the conductive layer 36 in an electroless plating manner, and the lower electroless copper plating layer is provided on the bump 16 and the overhang in an electroless plating manner. On platform 18. An upper electroplated copper layer is then electroplated on the upper electroless copper layer to form a cladding layer 44, and a lower electroplated copper layer is electroplated on the lower electroless copper layer to form a cladding layer 46. Wherein, the thickness of the electroless copper plating layer is about 2 micrometers, and the thickness of the electroplated copper layer is about 23 micrometers, so that the thickness of the coating layers 44 and 46 is about 25 micrometers. As a result, the thickness of the bump 16 and the overhanging platform 18 increases substantially in the downward direction, and the thickness of the conductive layer 36 substantially increases in the upward direction. In addition, the recess 20 is still hollow, and is still exposed downward toward the bottom, and the bump 16 is still exposed downward toward the bottom, and still extends across the majority of the bump 16 in the vertical and lateral directions.

The cover layer 44 serves as a cover layer for one of the bumps 16, a thickened layer of the conductive layer 36, and a bridge structure between the bumps 16 and the conductive layer 36. The cover layer 46 serves as a thickened layer of the bump 16 and the overhanging platform 18.

For convenience of illustration, the bumps 16, the conductive layer 36, and the cover layer 44 are shown in a single layer. Similarly, for ease of illustration, the bumps 16, the overhanging platform 18, and the cover layer 46 are also shown in a single layer. Since copper is a homogeneous coating, the boundary between the bump 16 and the covering layer 44, the boundary between the conductive layer 36 and the covering layer 44, the boundary between the bump 16 and the covering layer 46, and the boundary between the overhanging platform 18 and the covering layer 46 (both shown in dotted lines) may be difficult to detect or even detect. However, the boundary between the adhesive layer 30 and the cover layer 44 is clearly visible.

The etching resist layers 50 and 52 are provided on the coating layers 44 and 46 of the structure shown in Fig. 4G, respectively.

The illustrated etch stop layers 50, 52 are respectively deposited on the coating layers 44, 46 in a photoresist layer, which is formed by a dry stamping technique using a hot roller to simultaneously press the photoresist layers to the cladding layers 44, 46, respectively. . Wet spin coating and curtain coating are also suitable photoresist forming techniques. The etch stop layer 50 is a patterned photoresist layer, and the etch stop layer 52 is an unpatterned photoresist layer, which can serve as a etch stop layer that is completely covered.

A photomask (not shown) is placed on the photoresist layer 50, and then light is selectively passed through the mask according to the prior art, so that the light-receiving portion of the light is insoluble, and then removed by the developer. The photoresist layer 50 is patterned by receiving a portion of the photoresist that is still soluble. Therefore, the photoresist layer 50 has a pattern in which a selected portion of the cladding layer 44 is exposed outwardly, and the photoresist layer 52 is maintained in a state of no pattern, and the cladding layer 46 is covered from below. Further, the photoresist layers 50 and 52 cover the bumps 16 from below and from below, respectively.

In the structure shown in FIG. 4H, the conductive layer 36 and the cladding layer 44 have been removed by etching to select a portion thereof to form a pattern defined by the etch stop layer 50.

The etch is a front wet chemical etch. For example, the structure may be inverted such that the etch stop layer 50 faces downward, and the etch stop layer 52 faces upward, and then the chemical etchant is sprayed onto the cover with a bottom nozzle (not shown) facing upward and facing the etch stop layer 50. Layer 44 and etch stop layer 50. At the same time, a top nozzle (not shown) facing the etch stop layer 52 is not activated. In this way, the by-product of the etching can be removed by gravity. Alternatively, the back side protection is provided by the etching resist layer 52, and the structure may be immersed in the chemical etching liquid. The chemical etching solution can etch the cladding layer 44 and the conductive layer 36 to expose the dielectric layer 38 to the upper side, thereby converting the originally unpatterned conductive layer 36 and the coating layer 44 into a pattern layer. However, the bumps 16, the overhanging platform 18 and the covering layer 46 are not affected by the chemical etching solution, and the overhanging platform 18 and the covering layer 46 are still unpatterned layers. Therefore, the adhesive layer 30 is maintained in a state of being covered from above and covered from below, and the dielectric layer 38 is exposed only outward toward the outside without being exposed outward.

A chemical etching solution suitable for the above etching operation and highly selective to copper may be an alkali ammonia-containing solution or a diluted mixture of nitric acid and hydrochloric acid. In other words, the chemical etching solution can be acidic or alkaline. The ideal etching time sufficient to form a pattern without excessively exposing the conductive layer 36 and the coating layer 44 to the chemical etching solution can be determined by trial and error.

In Fig. 41, the etching resist layers 50 and 52 on the structure are removed. The photoresist layers are removed by solvent treatment. For example, the solvent used may be a strong alkaline potassium hydroxide solution having a pH of 14.

The etched conductive layer 36 and the cladding layer 44 include a pad 54, a routing line 56, a terminal 58 and a cover 64. Therefore, the conductive layer 36 and the cladding layer 44 are a pattern layer including the pad 54, the routing line 56, the terminal 58 and the cover 64. Similarly, pad 54, routing line 56, terminal 58 and cover 64 are selected portions of etch stop layer 50 defined on conductive layer 36 and cladding layer 44.

The pad 54 is a portion of the conductive layer 36 and the cladding layer 44 that is protected from the etch stop layer 50 and is not etched, which abuts the routing line 56 but is spaced from the terminal 58. The routing line 56 is a portion of the conductive layer 36 and the coating layer 44 that is protected by the etch resist layer 50 and is not etched. The routing line 56 is adjacent to the pad 54 and the terminal 58 and extends laterally from the pad 54 and the terminal 58 while electrically bonding. Pad 54 and terminal 58. The terminal 58 is a portion of the conductive layer 36 and the cladding layer 44 that is protected by the etch stop layer 50 and is not etched, which abuts the routing line 56 but is spaced from the pad 54. The cover 64 is also a portion of the conductive layer 36 and the cover layer 44 which is protected by the etch stop layer 50 and is not etched. The abutting portion 16 abuts the bump 16 and protrudes from the side of the bump 16 and is thermally coupled to the bump 16 while The bumps 16 are covered above but are spaced from the pads 54, routing lines 56 and terminals 58.

The thickness of pad 54, routing line 56 and terminal 58 are both 60 microns (35 + 25). The thickness of the cover 64 is 25 microns at the abutment bump 16 (which does not contain the conductive layer 36) and 60 microns (35+25) at the adjacent dielectric layer 38 (which includes a selected portion of the conductive layer 36). . The thickness of the cover 64 is also 25 micrometers at the contact adhesive layer 30 (this portion is spaced from the dielectric layer 38 and covers the opening 32 and the via 40 from above), and is 60 at the contact dielectric layer 38. Micron (35+25).

The bump 16 thickened by the covering layer 46 includes a portion of the covering layer 46 located in the recess 20. Similarly, the overhanging platform 18 is thickened by the cover layer 46 and includes a portion of the cover layer 46 that is outside the recess 20.

The base 62 includes a portion of the outwardly extending platform 18 made of sheet metal 10 that abuts the projections 16 and is integral with the projections 16 and extends from the sides of the projections 16. The base 62 also includes a portion of the cover layer 46 that covers the aforementioned portion of the overhanging platform 18 from below. Thus, the pedestal 62 abuts the bump 16 and is integral with the bump 16 while extending from the side of the bump 16 to a thickness of 175 microns (150+25).

Pad 54, routing line 56 and terminal 58 together form conductor 70. Thus, the wire 70 includes selected portions of both the conductive layer 36 and the cover layer 44, and the selected portions are all at a distance from the bump 16, the pedestal 62, and the cover 64. The wire 70 is located outside of the pocket 20. In addition, routing line 56 forms a conductive path between pad 54 and terminal 58.

Wire 70 provides horizontal (lateral) routing from pad 54 to terminal 58 via routing line 56. The wire 70 is not limited to this configuration. For example, the conductive path may include conductive vias through the adhesive layer 30 and/or the dielectric layer 38, additional routing lines (which are above and/or below the adhesive layer 30 and/or the dielectric layer 38), and passive Components (such as resistors and capacitors placed on other pads).

The bump 16, the base 62 and the cover 64 together form a heat sink 72. Thus, the heat sink 72 includes selected portions of the metal plate 10, the conductive layer 36, and the cover layers 44, 46, and the selected portions are all spaced from the wire 70. In addition, the bumps 16 form a thermally conductive path between the pedestal 62 and the cover 64.

The heat sink 72 is substantially an inverted T-shaped heat sink block comprising a pillar portion (bump 16), a relatively large lower wing portion (base 62) and a relatively smaller upper wing portion (cover body) 64).

The structure shown in Fig. 4J is provided with a solder resist green paint 74 on the substrate 34, the wires 70, and the heat sink 72.

The solder resist green paint 74 is an electrically insulating layer having a selected pattern so that the pad 54, the terminal 58 and the cover 64 are exposed outwardly, and the routing line 56 is covered from above while covering the dielectric layer. 38 originally exposed to the upper part. The solder resist green lacquer 74 has a thickness of 25 microns above the pads 54, routing lines 56, terminals 58 and the cover 64, and the solder resist green lacquer 74 extends 85 microns (60+25) above the dielectric layer 38.

The solder resist green paint 74 was originally a light-developing liquid resin coated on the structure. Then, a pattern is formed on the solder resist green paint 74, and the method is to selectively pass the light through the mask (not shown), so that the portion of the light-shielded green paint becomes insoluble, and then remove the un-lighted by a developing solution. And some of the solder resist green paint that is still soluble, and finally hard baked, the above steps are known techniques.

The conductor 70 and the heat sink 72 of the structure shown in Fig. 4K are provided with covered contacts 78.

The coated contact 78 is a multilayer metal coating that contacts the exposed copper surface. Therefore, the covered contact 78 contacts the pad 54, the terminal 58 and the cover 64, and covers the exposed portions of the three from above. The covered contact 78 also contacts the bump 16 and the pedestal 62 and covers the exposed portions of the two from below. For example, a nickel layer is provided on the exposed copper surface in an electroless plating manner, and then a silver layer is provided on the nickel layer in an electroless plating manner, wherein the inner nickel layer is about 3 micrometers thick, silver. The surface layer is about 0.5 microns thick, so the thickness of the coated contact 78 is about 3.5 microns.

The surface treatment with the covered contacts 78 as the bumps 16, pads 54, terminals 58, the pedestal 62 and the cover 64 has a number of advantages. The inner nickel layer provides primary mechanical and electrical bonding and/or thermal bonding, while the silver surface layer provides a wettable surface for solder reflow to match solder and wire. The covered contacts 78 also protect the wires 70 from the heat sink 72 from corrosion. The coated contacts 78 can comprise a variety of metals to meet the needs of externally coupled media. For example, a gold layer may be coated on the inner nickel layer, or a nickel surface layer may be used alone.

For convenience of illustration, the bumps 16 provided with the covered contacts 78, the pads 54, the terminals 58, the pedestal 62 and the cover 64 are shown as a single layer. The boundary between the covered contact 78 and the bump 16, the pad 54, the terminal 58, the pedestal 62, and the cover 64 is a copper/nickel interface.

The fabrication of the heat conducting plate 80 is thus completed.

The 4L, 4M, and 4N drawings are respectively a cross-sectional view, a top view, and a bottom view of the heat conducting plate 80. The edges of the heat conducting plate 80 are separated along the cutting line from the support frame and/or the adjacent heat conductive plates produced in the same batch.

The heat conducting plate 80 includes an adhesive layer 30, a substrate 34, a wire 70, a heat sink 72, and a solder resist green paint 74. Substrate 34 includes a dielectric layer 38. Wire 70 includes pad 54, routing line 56, and terminal 58. The heat sink 72 includes a bump 16 , a base 62 , and a cover 64 .

The bump 16 abuts the base 62 at the bend corner 24 and abuts the cover 64 at the bend corner 22 and the top plate 28. On the one hand, the projection 16 extends upward from the base 62, and on the other hand, extends from the cover 64 in the downward direction and is formed integrally with the base 62. After the bump 16 extends into the opening 32 and the through hole 40, it is still located at a central position within the opening 32 and the through hole 40. In addition, the bumps 16 extend above and below the dielectric layer 38 and the vias 40 and are coplanar with the adhesive layer 30 at the cover 64. The bump 16 still forms a recess 20 and covers the recess 20 from above and has a stamped special irregular thickness. The bumps 16 also contact the adhesive layer 30 and are spaced from the dielectric layer 38 while maintaining a cylindrical shape, i.e., the bumps 16 extend from the pedestal 62 up to the cover 64 and have a constant diameter. In addition, the bent corners 22 are still bent laterally inwardly at an angle of about 90 degrees adjacent the cover 64, while the bent corners 24 are still laterally outward at an angle of about 90 degrees adjacent the base 62. The bends, and the side walls 26 still vertically separate the bend corners 22 and 24.

The pocket 20 extends into the bump 16 and is covered by the bump 16 from above. The recess 20 faces downwardly and outwardly toward the lower side, so that the portion of the projection 16 constituting the recess 20 is also exposed downward toward the outside. Therefore, the recess 20 is hollow, the entrance is not closed, and is not covered by the bump 16 from below. The pocket 20 also extends into the opening 32 and the through hole 40, and the pocket 20 is separated from the cover 64 by the projection 16. The shape of the pocket 20 conforms to the projection 16, that is, both are cylindrical in shape. In addition, the pockets 20 extend across the majority of the bumps 16 in the vertical and side directions.

The pedestal 62 is located below the adhesive layer 30, the substrate 34, and the wires 70. The susceptor 62 contacts the adhesive layer 30, but is spaced apart from the substrate 34 and the cover 64. The pedestal 62 extends from the side of the bump 16 beyond the cover 64 and the wire 70, and extends on the outer side of the adhesive layer 30 and the substrate 34 in the downward direction, and covers the wire 70 from below, thereby supporting the bump 16 The adhesive layer 30, the substrate 34 and the wires 70.

The cover 64 contacts the adhesive layer 30 and the dielectric layer 38 and extends over the two. The cover 64 has a first thickness adjacent to the bump 16 and the cover 64 has a second thickness greater than the first thickness adjacent to the dielectric layer 38. The cover 64 also has a flat surface with one side facing upward. In addition, the portion of the cover 64 that abuts the adhesive layer 30 and is spaced apart from the dielectric layer 38 has the first thickness, and the portion of the cover 64 that abuts the dielectric layer 38 and is spaced from the adhesive layer 30 has the second thickness.

The adhesive layer 30 is disposed on the base 62 and extends above the base 62. The adhesive layer 30 is in contact between the bumps 42 and between the bumps 16 and the dielectric layer 38 and fills the space between the bumps 16 and the dielectric layer 38. The adhesive layer 30 is in contact with the outside of the notch 42 and is located between the pedestal 62 and the dielectric layer 38 and fills the space between the pedestal 62 and the dielectric layer 38. Adhesive layer 30 is also in contact and is located between base 62 and cover 64, but is spaced from conductor 70. The adhesive layer 30 extends not only across the dielectric layer 38 within the indentation 42 but also between the pedestal 62 and the pads 54, between the pedestal 62 and the routing line 56, and between the pedestal 62 and the terminal 58. Adhesive layer 30 also extends laterally from bump 16 and over wire 70. At this time, the adhesive layer 30 has solidified.

The adhesive layer 30 covers in the lateral direction and surrounds the side wall 26 of the bump 16, covering the portion of the base 62 outside the periphery of the bump 16 from above, covering the portion of the cover 64 outside the periphery of the bump 16 from below, and covering from below Substrate 34. The adhesive layer 30 is also applied to the side wall 26 of the bump 16, the bottom surface of one of the dielectric layers 38, the top surface of the base 62 outside the periphery of the bump 16, and the bottom surface of the cover 64 at a portion outside the periphery of the bump 16.

The adhesive layer 30 can pass through an imaginary horizontal line between the bump 16 and the dielectric layer 38, an imaginary horizontal line between the bump 16 and the cover 64, an imaginary vertical line between the pedestal 62 and the dielectric layer 38, and An imaginary vertical line between the base 62 and the cover 64. However, the adhesive layer 30 does not individually pass through an imaginary line between the pedestal 62 and the wire 70. Therefore, although an imaginary horizontal line extending from the bump 16 to the dielectric layer 38 passes only through the adhesive layer 30, there is no imaginary line between the pedestal 62 and the wire 70 that is horizontal, vertical or otherwise oriented. The adhesive layer 30 is over-adhered because the imaginary line passes through the dielectric layer 38 in addition to passing through the adhesive layer 30 between the pedestal 62 and the wire 70.

The substrate 34 is disposed on the adhesive layer 30 and extends above the pedestal 62 and includes a wire 70. The dielectric layer 38 is in contact with and between the adhesive layer 30 and the pad 54, between the adhesive layer 30 and the routing line 56, and between the adhesive layer 30 and the terminal 58. The dielectric layer 38 also contacts the cover 64 but is spaced from the bump 16 and the pedestal 62.

The pad 54 , the routing line 56 and the terminal 58 both contact the dielectric layer 38 and are both spaced from the adhesive layer 30 while extending over the adhesive layer 30 and the dielectric layer 38 . The pad 54 has the same thickness as the terminal 58 and is co-located on the top surface of the side facing upward. In addition, the pad 54 and the cover 64 have the same thickness adjacent to each other, but the thickness of the cover 64 adjacent to the bump 16 is different from that of the pad 54. The pad 54 and the cover 64 are co-located on the top surface of the one surface facing upward.

After the same batch of thermally conductive plates 80 are cut, the adhesive layer 30, the dielectric layer 38, the pedestal 62 and the solder resist green lacquer 74 extend to the cut vertical edges.

The pad 54 is an electrical interface tailored for semiconductor components such as LED chips, which will be disposed on the cover 64 in a subsequent process. Terminal 58 is an electrical interface tailored to the next layer of components (e.g., solderable wires or contacts from a printed circuit board). The cover 64 is a thermal interface tailored specifically for the semiconductor component. The pedestal 62 is a thermal interface tailored for the next layer of components, such as the aforementioned printed circuit board or a heat sink for an electronic device.

The pad 54 and the terminal 58 are offset from each other in the horizontal direction and are exposed on the top surface of the heat conducting plate 80 to provide horizontal signal routing between the semiconductor component and the next layer.

For ease of illustration, the wire 70 is depicted as a continuous circuit trace in a cross-sectional view. However, the wires 70 can simultaneously provide horizontal signal routing in the X and Y directions, that is, the pads 54 and the terminals 58 can be laterally misaligned in the X and Y directions.

The wire 70 and the heat sink 72 are spaced apart from each other, and thus, the wire 70 is mechanically coupled to the heat sink 72 and electrically isolated from each other.

The heat sink 72 can diffuse the thermal energy generated by the semiconductor component subsequently disposed on the cover 64 to a lower group to which the heat conducting plate 80 is connected. After the thermal energy generated by the semiconductor element flows into the cover 64, it flows into the bump 16 from the cover 64, enters the pedestal 62 via the bump 16, and finally scatters from the pedestal 62 in a downward direction, for example, diffuses to a lower heat dissipation. Device.

The bumps 16, the pads 54, the terminals 58, the pedestal 62 and the cover 64 are all of the same metal, that is, copper/nickel/silver. The bump 16, the pad 54, the terminal 58, the pedestal 62 and the cover 64 are composed of a silver surface layer, an inner copper core and an inner nickel layer, wherein the inner nickel layer is in contact with and located on the silver surface layer. Between this internal copper core. The inner copper core of the bump 16, the pad 54, the terminal 58, the pedestal 62 and the cover 64 is mainly copper. The silver surface layer and the inner nickel layer are provided by a covered joint 78, and the inner copper core is provided by a plurality of combinations of the metal plate 10, the conductive layer 36, and the cover layers 44,46.

The wire 70 includes an inner copper core shared by the pad 54 and the routing line 56 and the terminal 58. The heat sink 72 includes an inner copper core shared by the bump 16, the base 62 and the cover 64. In addition, the wire 70 includes a covered contact 78 disposed on the pad 54 and another covered contact disposed on the terminal 58. The heat sink 72 includes a covered contact disposed on the bump 16 and the base 62. (the distance from the cover 64), and another covered contact 78 (which is spaced from the bump 16 and the base 62) provided on the cover 64. In addition, the wire 70 and the heat sink 72 are composed of copper/nickel/silver, and the inner copper core is mainly copper.

Both the bumps 16 of the heat conducting plate 80 and the routing wires 56 are not exposed outwardly. For ease of illustration, the bumps 16 and routing lines 56 are shown in dashed lines in Figure 4M.

The thermally conductive plate 80 can include a plurality of wires 70 comprised of pads 54, routing lines 56, and terminals 58. For ease of illustration, only a single wire 70 is described and labeled herein. In such conductors 70, pads 54 and terminals 58 generally have similar shapes and sizes, while routing lines 56 may (but are not necessarily) have different routing configurations. For example, the partial wires 70 are spaced apart from each other and electrically isolated, and the partial wires 70 are staggered or directed to the same pad 54, routing line 56 or terminal 58 and electrically connected to each other. Similarly, a portion of the pads 54 can be used to receive independent signals, while a portion of the pads 54 share a signal, power supply, or ground.

The heat conducting plate 80 is suitable for an LED package having blue, green and red LED chips, wherein each LED chip comprises an anode and a cathode, and each LED package comprises a corresponding anode terminal and cathode terminal. In this example, the thermally conductive plate 80 can include six pads 54 and four terminals 58 for directing each anode from a separate pad 54 to a separate terminal 58 and directing each cathode from a separate pad 54 A common ground terminal 58.

A simple cleaning step can be used at each stage of manufacture to remove oxides and residues from the exposed metal. For example, a short oxygen plasma cleaning step can be applied to the structure of the present invention. Alternatively, the structure of the present invention can be subjected to a brief wet chemical cleaning step using a potassium permanganate solution. Similarly, the structure can be rinsed with distilled water to remove dirt. This cleaning step cleans the desired surface without causing significant damage or damage to the structure.

The advantage of the present invention is that there is no need to separate or separate the confluence points or associated circuitry from the wires 70 after they are formed. The sink points can be separated during the wet chemical etching step of forming the wires 70.

The heat conducting plate 80 may include a counter hole (not shown) formed by drilling or cutting through the adhesive layer 30, the dielectric layer 38, the base 62 and the solder resist green paint 74. In this way, when the heat conducting plate 80 needs to be disposed on a lower carrier in a subsequent process, the tool pin can be inserted into the alignment hole to position the heat conducting plate 80.

The heat conducting plate 80 can accommodate a plurality of semiconductor components, rather than a single bump or a plurality of bumps can accommodate only a single semiconductor component. Therefore, one can arrange a plurality of semiconductor elements on a single bump or a plurality of semiconductor elements on different bumps.

If a single bump of the thermally conductive plate 80 is to accommodate a plurality of semiconductor components, the etch stop layer 50 can be adjusted to define more wires 70. The lateral positions of the wires 70 can be readjusted to provide a 2x2 array for the four semiconductor components. In addition, the cross-sectional shape and height (i.e., side shape) of the wire 70 can also be adjusted.

If a plurality of bumps are to be formed on the heat conducting plate 80 to accommodate a plurality of semiconductor components, additional bumps 16 may be stamped on the metal plate 10, the adhesive layer 30 may be adjusted to include more openings 32, and the substrate 34 may be adjusted to include more Multiple vias 40 are simultaneously etched to define more caps 64 and wires 70. The lateral position of bump 16, cover 64 and wire 70 can be readjusted to provide a 2x2 array of four semiconductor components. In addition, the cross-sectional shape and height (ie, the side shape) of the bump 16, the cover 64, and the wire 70 may be adjusted. Furthermore, the plurality of bumps 16 may have separate pedestals 62 or a common pedestal 62, depending on the design of the etch stop layer 52.

5A, 5B, and 5C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, the wires of the heat conducting plate being in contact with the adhesive layer.

In this embodiment, the substrate is provided only by the conductive layer, and no dielectric layer is provided. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used.

The heat conducting plate 82 includes an adhesive layer 30, a wire 70, a heat sink 72, and a solder resist green paint 74. Wire 70 includes pad 54, routing line 56 and terminal 58. The heat sink 72 includes a bump 16, a base 62 and a cover 64.

The conductive layer 36 in this embodiment is thicker than the conductive layer 36 in the previous embodiment. For example, the thickness of the conductive layer 36 is increased from 50 micrometers to 150 micrometers, thereby preventing the conductive layer 36 from being bent or shaken during handling, and the pad 54, the routing line 56, the terminal 58 and the cover 64 are thus thickened. . In addition, since the dielectric layer 38 is omitted in the present embodiment, the pad 54, the routing line 56, and the terminal 58 are both in contact with the adhesive layer 30.

The adhesive layer 30 is in contact with and is located between the pedestal 62 and the wire 70 while filling the space between the pedestal 62 and the wire 70. Thus, the adhesive layer 30 can pass through an imaginary vertical line between the pedestal 62 and the pad 54 alone, an imaginary vertical line between the pedestal 62 and the routing line 56, and an imaginary vertical line between the pedestal 62 and the terminal 58. . Moreover, the adhesive layer 30 has been thickened to fill the gap of the dielectric layer 38. In addition, in response to the increase in the thickness of the pad 54, the routing line 56, the terminal 58 and the cover 64, the solder resist green paint 74 is also thickened.

The heat conducting plate 82 is fabricated in a manner similar to the heat conducting plate 80, but the conductive layer 36 must be properly adjusted. For example, the metal sheet 10 is stamped to form the bumps 16, the overhanging platform 18, and the recesses 20, and then the adhesive layer 30 is placed on the overhanging platform 18, and the conductive layer 36 is separately disposed on the adhesive layer 30. The adhesive layer 30 is then heated and pressurized to cause the adhesive layer 30 to flow and solidify. The bumps 16, the adhesive layer 30, and the top surface of the conductive layer 36 are then polished to planarize. Next, the covering layers 44 and 46 are placed on the structure. The above steps have been explained in the foregoing. Conductive layer 36 and cladding layer 44 are then etched to form pads 54, routing lines 56, terminals 58 and cover 64 while leaving overhanging platform 18 and cladding layer 46 in a non-patterned state. Next, a solder resist green paint 74 is formed on the top surface, and the bumps 78, the pads 54, the terminals 58, the pedestal 62, and the lid 64 are surface-treated by the covered contacts 78. Finally, the adhesive layer 30, the pedestal 62 and the solder resist green paint 74 are cut or cleaved at the peripheral edge of the heat conducting plate 82 to separate the heat conducting plate 82 from the other heat conducting plates produced in the same batch.

6A, 6B, and 6C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, which can provide vertical signal routing.

In this embodiment, the terminal extends below the adhesive layer and electrically connects the routing line and the terminal by the covered via. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used.

The heat conducting plate 84 includes an adhesive layer 30, a wire 70, a heat sink 72, and solder resist green paints 74 and 76. Conductor 70 includes pad 54, routing line 56, terminal 58 and coated vias 60. The heat sink 72 includes a bump 16, a base 62 and a cover 64.

The wire 70 can provide not only horizontal (lateral) routing from the pad 54 to the covered via 60 via the routing line 56, but also vertical (top to bottom) routing from the routing line 56 to the terminal 58 through the covered via 60. Therefore, the routing line 56 forms a conductive path between the pad 54 and the covered via 60. The covered via 60 forms a conductive path between the routing line 56 and the terminal 58, and the routing line 56 and the covered via 60 together form a pad 54 and One of the conductive paths between the terminals 58.

The pad 54 and the routing line 56 both contact the dielectric layer 38, both at a distance from the adhesive layer 30, and both extend above the adhesive layer 30 and the dielectric layer 38. The terminal 58 contacts the adhesive layer 30, is spaced from the dielectric layer 38, and extends below the adhesive layer 30 and the dielectric layer 38. The coated vias 60 are in contact and extend through the adhesive layer 30 and the dielectric layer 38. The pedestal 62 is spaced from the peripheral edge of the thermally conductive plate 84 and does not cover the adhesive layer 30, the substrate 34, the routing lines 56, the terminals 58, the coated perforations 60 or the solder resist green paint 74 from below. In addition, terminal 58 and base 62 include selected portions of overhanging platform 18 having the same thickness and co-located on the underside of the structure.

The solder resist green paint 74 is an electrically insulating layer having a selected pattern, so that the solder pad 54, the covered vias 60 and the cover 64 are exposed outwardly, and the dielectric layer 38 is exposed to the outside. section. The solder resist green paint 76 is also an electrically insulating layer having a selected pattern, so that the bumps 16, the terminals 58 and the pedestal 62 are exposed outwardly and cover the portion of the adhesive layer 30 that is originally exposed downward. .

The heat conducting plate 84 is fabricated in a manner similar to the heat conducting plate 80, but must be suitably adjusted for the wire 70, the heat sink 72, and the solder resist green paints 74 and 76. For example, the metal sheet 10 is stamped to form the bumps 16, the overhanging platform 18, and the recesses 20, and then the adhesive layer 30 is placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30. The adhesive layer 30 is then heated and pressurized to cause the adhesive layer 30 to flow and solidify. The bumps 16, the adhesive layer 30, and the top surface of the conductive layer 36 are then polished to planarize. The above steps have been explained in the foregoing.

Next, the overhanging platform 18, the adhesive layer 30, the conductive layer 36, and the dielectric layer 38 are drilled to form holes, and then conductive metal is deposited on the structure, thereby forming a coating layer 44 on the top surface of the structure. A coating layer 46 is formed on the bottom surface, and a covered perforation 60 is formed in the hole.

An etch stop layer 50 is then formed over the cladding layer 44 to form a pattern defining the pads 54, the routing lines 56, and the cover 64 to expose selected portions of the cladding layer 44. An etch stop layer 52 is also formed over the cladding layer 46 to form a pattern defining the terminals 58 and the pedestals 62 to expose selected portions of the cladding layer 46. Then, the conductive layer 36 and the cladding layer 44 are etched to form the pad 54, the routing line 56 and the cover 64 defined by the etch stop layer 50, thereby exposing the dielectric layer 38 outwardly but not exposing the adhesive layer 30 upward. . The overhanging platform 18 and the cladding layer 46 are further etched to form the terminal 58 and the pedestal 62 defined by the etch stop layer 52, thereby further exposing the adhesive layer 30 downwardly without exposing the dielectric layer 38 downward. Terminal 58 and pedestal 62 include selected portions of both the overhanging platform 18 and the cladding layer 46 that are protected from etching by the etch stop layer 52, the selected portions being spaced apart from each other and at a distance from each other. In detail, the terminal 58 includes a portion of the overhanging platform 18 that is spaced apart from the bump 16 and maintains a distance; the base 62 also includes a portion of the overhanging platform 18, but this portion is adjacent to the bump 16, with the bump 16 is formed integrally and protrudes from the side of the bump 16.

Then, a solder resist green paint 74 is formed on the top surface of the structure, and a solder resist green paint 76 is formed on the bottom surface of the structure. The solder resist green paints 74 and 76 are initially applied to the light-developing liquid resin on the top and bottom surfaces of the structure, respectively, and then patterned to form a pattern such that the light is selectively transmitted through the mask (not shown). The portion of the light-retaining solder resist green paint is rendered insoluble, and then a developing solution is used to remove a portion of the solder resist green paint that is not exposed to light and still soluble, and finally hard baked. The above steps are conventional techniques.

Next, the bumps 78 are used as the bumps 16, the pads 54, the terminals 58, the covered vias 60, the pedestals 62, and the lid 64 for surface treatment. Finally, the adhesive layer 30, the dielectric layer 38 and the solder resist green paints 74 and 76 are cut or cleaved at the peripheral edge of the heat conducting plate 84 to separate the heat conducting plate 84 from the other heat conducting plates produced in the same batch.

7A, 7B, and 7C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, which can provide vertical signal routing.

In this embodiment, the terminal extends below the adhesive layer and omits the routing line, but is additionally provided with a covered via to provide an electrical connection between the pad and the terminal. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used.

The heat conducting plate 86 includes an adhesive layer 30, a wire 70, and a heat sink 72. The wire 70 includes a pad 54, a terminal 58 and a covered perforation 60. The heat sink 72 includes a bump 16, a base 62 and a cover 64.

The wire 70 can provide not only horizontal (lateral) routing from the pad 54 to the coated via 60, but also vertical (top to bottom) routing from the pad 54 to the terminal 58 through the covered via 60. Thus, the covered vias 60 form a conductive path between the pads 54 and the terminals 58.

The pad 54 contacts the dielectric layer 38, is spaced from the adhesive layer 30, and extends over the adhesive layer 30 and the dielectric layer 38. The terminal 58 contacts the adhesive layer 30, is spaced from the dielectric layer 38, and extends below the adhesive layer 30 and the dielectric layer 38. The coated vias 60 are in contact and extend through the adhesive layer 30 and the dielectric layer 38. The pedestal 62 is spaced from the peripheral edge of the thermally conductive plate 86 and does not cover the adhesive layer 30, the substrate 34, the pads 54, the terminals 58, or the covered perforations 60 from below. In addition, terminal 58 and base 62 include selected portions of overhanging platform 18 having the same thickness and co-located on the underside of the structure.

Since the embodiment does not have the solder resist green paint 74, the covered contact 78 occupies 85% to 95% of the top surface of the heat conducting plate 86. The coated contact 78 also provides a highly reflective top surface that reflects the light emitted by one of the LED chips that is subsequently disposed on the cover 64.

The heat conducting plate 86 is fabricated in a manner similar to the heat conducting plate 80, but must be appropriately adjusted for the wire 70 and the heat sink 72. For example, the metal sheet 10 is stamped to form the bumps 16, the overhanging platform 18, and the recesses 20, and then the adhesive layer 30 is placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30. The adhesive layer 30 is then heated and pressurized to cause the adhesive layer 30 to flow and solidify. The bumps 16, the adhesive layer 30, and the top surface of the conductive layer 36 are then polished to planarize. The above steps have been explained in the foregoing.

Next, the overhanging platform 18, the adhesive layer 30, the conductive layer 36, and the dielectric layer 38 are drilled to form holes, and then conductive metal is deposited on the structure, thereby forming a coating layer 44 on the top surface of the structure. A coating layer 46 is formed on the bottom surface, and a covered perforation 60 is formed in the hole.

An etch stop layer 50 is then formed over the cap layer 44 to form a pattern defining the pad 54 and the cap 64 to expose selected portions of the cap layer 44. An etch stop layer 52 is also formed over the cladding layer 46 to form a pattern defining the terminals 58 and the pedestals 62 to expose selected portions of the cladding layer 46. Then, the conductive layer 36 and the cladding layer 44 are etched to form the pad 54 and the cap 64 defined by the etch stop layer 50, thereby further exposing the dielectric layer 38 outwardly without exposing the adhesive layer 30 upward. The overhanging platform 18 and the cladding layer 46 are further etched to form the terminal 58 and the pedestal 62 defined by the etch stop layer 52, thereby exposing the adhesive layer 30 outwardly without exposing the dielectric layer 38 downward. Terminal 58 and pedestal 62 include selected portions of both the overhanging platform 18 and the cladding layer 46 that are protected from etching by the etch stop layer 52, the selected portions being spaced apart from each other and at a distance from each other. In detail, the terminal 58 includes a portion of the overhanging platform 18 that is spaced apart from the bump 16 and maintains a distance; the base 62 also includes a portion of the overhanging platform 18, but this portion is adjacent to the bump 16, with the bump 16 is formed integrally and protrudes from the side of the bump 16.

Next, the bumps 78 are used as the bumps 16, the pads 54, the terminals 58, the covered vias 60, the pedestals 62, and the lid 64 for surface treatment. Finally, the adhesive layer 30 and the dielectric layer 38 are cut or cleaved at the peripheral edge of the heat conducting plate 86 to separate the heat conducting plate 86 from the other heat conducting plates produced in the same batch.

8A, 8B, and 8C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a sealed recess containing a filler.

In this embodiment, a filler is first filled into the pocket, and then the adhesive layer is placed on the overhanging platform and the recess is closed by the pedestal. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used.

The heat conducting plate 88 includes an adhesive layer 30, a substrate 34, a filler 48, a wire 70, a heat sink 72, and a solder resist green paint 74. Substrate 34 includes a dielectric layer 38. Wire 70 includes pad 54, routing line 56 and terminal 58. The heat sink 72 includes a bump 16, a base 62 and a cover 64.

The filler 48 is an electrically insulating epoxy that is located within the pocket 20 and fills the pocket 20, and the pocket 20 is no longer hollow once loaded into the filler 48. The filler 48 contacts the bumps 16 within the pockets 20 and extends across the majority of the bumps 16 in the vertical and lateral directions. The filler 48 also covers the recess 20 from below and is spaced from the adhesive layer 30, the substrate 34, the cover 64, and the wires 70 while providing mechanical support for the bumps 16. In addition, the base 62 seals the pocket 20. Therefore, the filler 48 contacts the bump 16 and the pedestal 62 and is surrounded by the bump 16 and the pedestal 62. The pedestal 62 further covers the bump 16, the recess 20, the filler 48, and the cover 64 from below.

The heat conducting plate 88 is fabricated in a manner similar to the heat conducting plate 80, but must be suitably adjusted for the filler 48. For example, the metal sheet 10 is first stamped to form the bumps 16, the overhanging platform 18, and the pockets 20.

The filler 48 is then shaped within the pocket 20. The filler 48 is originally an epoxy resin paste and is selectively printed in the pockets 20 by screen printing. The epoxy paste is then heated to harden at a relatively low temperature (e.g., 190 ° C). The filler 48 is then milled to form a flat surface. For example, the bottom of the structure is treated with a rotating diamond wheel and distilled water. Initially, the diamond wheel only grinds the filler 48. With continuous grinding, the filler 48 becomes thinner as the surface to be abraded moves up. The diamond wheel will eventually contact the overhanging platform 18 and will also begin to grind the overhanging platform 18. After continuous grinding, the overhanging platform 18 and the filler 48 are both thinned by the upward movement of the abraded surface. The grinding is continued until the desired thickness is removed, and then the structure is rinsed with distilled water to remove dirt. At this time, the overhanging platform 18 and the filler 48 are located on the side of the smooth splicing side of the side in the downward direction.

The adhesive layer 30 is then placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30. The adhesive layer 30 is then heated and pressurized to cause the adhesive layer 30 to flow and solidify. The bumps 16, the adhesive layer 30, and the top surface of the conductive layer 36 are then polished to planarize. A conductive metal is then deposited over the structure to form cladding layers 44 and 46, wherein the cladding layer 46 is attached to the filler 48 and the filler 48 is covered from below. As such, the cover layer 46 (and even the pedestal 62) closes the pocket 20 and seals the filler 48 within the pocket 20.

The conductive layer 36 and the cladding layer 44 are then etched to form the pads 54, the routing lines 56, the terminals 58 and the cover 64, while the overhanging platform 18 and the cladding layer 46 remain unpatterned. Next, a solder resist green paint 74 is formed on the top surface of the structure, and the coated bumps 78 are used as the pad 54, the terminal 58, the base 62, and the lid 64 for surface treatment. Finally, the adhesive layer 30, the dielectric layer 38, the pedestal 62 and the solder resist green lacquer 74 are cut or cleaved at the peripheral edge of the heat conducting plate 88 to separate the heat conducting plate 88 from the other heat conducting plates produced in the same batch.

9A, 9B, and 9C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a closed recess containing a filler.

In this embodiment, a filler is filled into the cavity after the adhesive layer is cured, and the cavity is closed by the susceptor. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used.

The heat conducting plate 90 includes an adhesive layer 30, a substrate 34, a filler 48, a wire 70, a heat sink 72, and a solder resist green paint 74. Substrate 34 includes a dielectric layer 38. Wire 70 includes pad 54, routing line 56 and terminal 58. The heat sink 72 includes a bump 16, a base 62 and a cover 64.

The filler 48 is an electrically insulating epoxy that is located within the pocket 20 and fills the pocket 20, and the pocket 20 is no longer hollow once loaded into the filler 48. The filler 48 contacts the bumps 16 within the pockets 20 and extends across the majority of the bumps 16 in the vertical and lateral directions. The filler 48 also covers the recess 20 from below and is spaced from the adhesive layer 30, the substrate 34, the cover 64, and the wires 70 while providing mechanical support for the bumps 16. In addition, the base 62 seals the pocket 20. Therefore, the filler 48 contacts the bump 16 and the pedestal 62 and is surrounded by the bump 16 and the pedestal 62. The pedestal 62 further covers the bump 16, the recess 20, the filler 48, and the cover 64 from below.

The heat conducting plate 90 is fabricated in a manner similar to the heat conducting plate 80, but must be suitably adjusted for the filler 48. For example, the metal sheet 10 is stamped to form the bumps 16, the overhanging platform 18, and the recesses 20, and then the adhesive layer 30 is placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30, followed by the adhesive layer 30. The heat and pressure are applied to cause the adhesive layer 30 to flow and solidify.

The filler 48 is then shaped within the pocket 20. The filler 48 is originally an epoxy resin paste and is selectively printed in the pockets 20 by screen printing. The epoxy paste is then heated to harden at a relatively low temperature (e.g., 190 ° C). The filler 48 is then ground to form a flat surface. For example, the bottom of the structure is treated with a rotating diamond wheel and distilled water. Initially, the diamond wheel only grinds the filler 48. With continuous grinding, the filler 48 becomes thinner as the surface to be abraded moves up. The diamond wheel will eventually contact the overhanging platform 18 and will also begin to grind the overhanging platform 18. After continuous grinding, the overhanging platform 18 and the filler 48 are both thinned by the upward movement of the abraded surface. The grinding is continued until the desired thickness is removed, and then the structure is rinsed with distilled water to remove dirt. At this time, the overhanging platform 18 and the filler 48 are located on the side of the smooth splicing side of the side in the downward direction.

A grinding operation is also applied to the top surfaces of the bumps 16, the adhesive layer 30, and the conductive layer 36 to planarize them.

A conductive metal is then deposited over the structure to form cladding layers 44 and 46, wherein the cladding layer 46 is attached to the filler 48 and the filler 48 is covered from below. As such, the cover layer 46 (and even the pedestal 62) closes the pocket 20 and seals the filler 48 within the pocket 20.

The conductive layer 36 and the cladding layer 44 are then etched to form the pads 54, the routing lines 56, the terminals 58, and the cover 64. At the same time, the overhanging platform 18 and the cladding layer 46 remain unpatterned. Next, a solder resist green paint 74 is formed on the top surface of the structure, and the coated bumps 78 are used as the pad 54, the terminal 58, the pedestal 62, and the lid 64 for surface treatment. Finally, the adhesive layer 30, the dielectric layer 38, the pedestal 62 and the solder resist green lacquer 74 are cut or cleaved at the peripheral edge of the heat conducting plate 90 to separate the heat conducting plate 90 from the other heat conducting plates produced in the same batch.

10A, 10B and 10C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a non-closed recess containing a filler.

In this embodiment, a conductive metal is deposited on the structure to form a coating layer, and a filler is filled into the cavity, and the cavity remains unsealed. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used.

The heat conducting plate 92 includes an adhesive layer 30, a substrate 34, a filler 48, a wire 70, a heat sink 72, and a solder resist green paint 74. Substrate 34 includes a dielectric layer 38. Wire 70 includes pad 54, routing line 56 and terminal 58. The heat sink 72 includes a bump 16, a base 62 and a cover 64.

The filler 48 is an electrically insulating epoxy that is located within the pocket 20 and fills the pocket 20, and the pocket 20 is no longer hollow once loaded into the filler 48. The filler 48 contacts the bumps 16 within the pockets 20 and extends across the majority of the bumps 16 in the vertical and lateral directions. The filler 48 also covers the recess 20 from below and is spaced from the adhesive layer 30, the substrate 34, the cover 64, and the wires 70 while providing mechanical support for the bumps 16. In addition, the pockets 20 remain unsealed, exposing the filler 48 outwardly.

The heat conducting plate 92 is fabricated in a manner similar to the heat conducting plate 80, but must be suitably adjusted for the filler 48. For example, the metal sheet 10 is stamped to form the bumps 16, the overhanging platform 18, and the recesses 20, and then the adhesive layer 30 is placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30. The adhesive layer 30 is then heated and pressurized to cause the adhesive layer 30 to flow and solidify. The bumps 16, the adhesive layer 30, and the top surface of the conductive layer 36 are then polished to planarize. Conductive metal is then deposited over the structure to form cladding layers 44 and 46. The above steps have been explained in the foregoing.

The filler 48 is then shaped within the pocket 20. The filler 48 was originally an epoxy resin paste and was selectively printed in the pockets 20 by screen printing. The epoxy paste is then heated to harden at a relatively low temperature (e.g., 190 ° C). The filler 48 is then ground to form a flat surface. For example, the bottom of the structure is treated with a rotating diamond wheel and distilled water. Initially, the diamond wheel only grinds the filler 48. With continuous grinding, the filler 48 becomes thinner as the surface to be abraded moves up. The diamond wheel will eventually contact the cover layer 46 and will also begin to grind the cover layer 46. After continuous grinding, both the coating layer 46 and the filler 48 are thinned by the upward movement of the surface to be abraded. The grinding is continued until the desired thickness is removed, and then the structure is rinsed with distilled water to remove dirt. At this time, the covering layer 46 and the filler 48 are located on the side of the smooth splicing side of the side in the downward direction.

The conductive layer 36 and the cladding layer 44 are then etched to form the pads 54, the routing lines 56, the terminals 58, and the cover 64. At the same time, the overhanging platform 18 and the cladding layer 46 remain unpatterned. Next, a solder resist green paint 74 is formed on the top surface of the structure, and the coated bumps 78 are used as the pad 54, the terminal 58, the pedestal 62, and the lid 64 for surface treatment. Finally, the adhesive layer 30, the dielectric layer 38, the pedestal 62 and the solder resist green lacquer 74 are cut or cleaved at the peripheral edge of the heat conducting plate 92 to separate the heat conducting plate 92 from the other heat conducting plates produced in the same batch.

11A, 11B and 11C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a raised edge.

In this embodiment, a raised edge is disposed on the solder resist green paint. For the sake of brevity, the description of the heat conducting plate 80 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the heat conducting plate of this embodiment are similar to those of the heat conducting plate 80, and corresponding reference numerals are used.

The heat conducting plate 94 includes an adhesive layer 30, a substrate 34, a raised edge 68, a wire 70, a heat sink 72, and a solder resist green paint 74. Substrate 34 includes a dielectric layer 38. Wire 70 includes pad 54, routing line 56 and terminal 58. The heat sink 72 includes a bump 16, a base 62 and a cover 64.

The raised edge 68 is a square frame that contacts the solder resist green paint 74 and extends over the solder resist green paint 74. Both the projection 16 and the cover 64 are centrally located within the periphery of the raised edge 68, while the terminal 58 is located outside of the periphery of the raised edge 68. For example, the raised edge 68 has a height of 600 microns, the width (distance between the inner and outer sidewalls) is 500 microns, and the lateral spacing of the raised edge 68 from the pad 54 is also 500 microns.

The raised edge 68 comprises a solder resist green lacquer, a laminate and a film adhesive; however, for ease of illustration, the raised edge 68 is shown in a single layer in the Figure. The solder resist green paint contacts the laminate and extends over it, thereby forming a top surface. The film-like adhesive contacts the laminate and extends below it, thereby forming a bottom surface. The laminate is in contact with and is pressed between the solder resist green paint and the film adhesive. The solder resist green paint, the laminate and the film adhesive are all electrical insulators. For example, the solder resist green paint is 50 microns thick, the laminate is 500 microns thick, and the film adhesive is 50 microns thick, so the height of the raised edge 68 is 600 microns (50+500+50).

The laminate can be a variety of dielectric films made of a variety of organic and inorganic electrical insulators. For example, the laminate may be a polyimine or an FR-4 epoxy resin, but other epoxy resins such as polyfunctional and bismaleimide-triazabenzene (BT) may also be used. Alternatively, the raised edge 68 can comprise a metal ring disposed on the film-like adhesive.

The heat conducting plate 94 is fabricated in a manner similar to the heat conducting plate 80, but must be suitably adjusted for the raised edge 68. For example, the metal sheet 10 is stamped to form the bumps 16, the overhanging platform 18, and the recesses 20, and then the adhesive layer 30 is placed on the overhanging platform 18, and the substrate 34 is placed on the adhesive layer 30. The adhesive layer 30 is then heated and pressurized to cause the adhesive layer 30 to flow and solidify. The bumps 16, the adhesive layer 30, and the top surface of the conductive layer 36 are then polished to planarize. Conductive metal is then deposited over the structure to form cladding layers 44 and 46. The above steps are all explained in the previous section. The conductive layer 36 and the cladding layer 44 are then etched to form the pads 54, the routing lines 56, the terminals 58, and the cover 64. At the same time, the overhanging platform 18 and the cladding layer 46 remain unpatterned. Then, a solder resist green paint 74 is formed on the top surface of the structure, and a raised edge 68 is disposed on the solder resist green paint 74, and then the bump contact 78 is used as the bump 16, the pad 54, the terminal 58, and the base 62. The cover 64 is subjected to surface treatment. Finally, the adhesive layer 30, the dielectric layer 38, the pedestal 62 and the solder resist green lacquer 74 are cut or cleaved at the peripheral edge of the heat conducting plate 94 to separate the heat conducting plate 94 from the other heat conducting plates produced in the same batch.

12A, 12B and 12C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer package according to an embodiment of the present invention, the semiconductor wafer package comprising a heat conducting plate, a semiconductor component and a packaging material.

In this embodiment, the semiconductor component is a blue-emitting LED chip that is disposed on the cover, electrically connected to the pad by a wire, and thermally bonded to the cover by a die bonding material. The LED chip is covered by a packaging material that converts blue light into white light.

The semiconductor wafer package 100 includes a heat conductive plate 80, an LED wafer 102, a wire 104, a die bonding material 106, and an encapsulation material 108. The LED wafer 102 includes a top surface 110, a bottom surface 112, and a wire bonding pad 114. The top surface 110 is an active surface and includes a wire bonding pad 114, and the bottom surface 112 is a thermal contact surface.

The LED chip 102 is disposed on the heat sink 72, electrically connected to the wire 70, and thermally coupled to the heat sink 72. In detail, the LED chip 102 is disposed on the cover 64 (or even the bump 16) on the opposite side of the recess 20 and extends over the cover 64 (or even the bumps 16 and the recesses 20). And overlapping the bump 16, the recess 20 and the cover 64 (ie, extending laterally in the periphery of the bump 16, the recess 20 and the cover 64), but not overlapping the substrate 34 and the wire 70 (ie, The LED chip 102 is located outside the periphery of the substrate 34 and the wire 70). The LED chip 102 is electrically connected to the pad 54 via the bonding wire 104, and is thermally coupled via the die bonding material 106 and mechanically adhered to the cap 64. In addition, the cover 64 covers the LED wafer 102 from below and provides a recessed wafer holder and a reflector for the LED wafer 102.

For example, the bonding wires 104 are electrically connected to the bonding pads 54 and the bonding pads 114 , thereby electrically connecting the LED chips 102 to the terminals 58 . The die bonding material 106 is in contact with and located between the cover 64 and the thermal contact surface 112 while thermally bonding and mechanically bonding the cover 64 to the thermal contact surface 112, thereby thermally bonding the LED wafer 102 to the bumps 16, thereby LED Wafer 102 is thermally coupled to pedestal 62.

The encapsulating material 108 is a solid-state electrically insulating protective covering for converting color, which can provide environmental protection against moisture and anti-particles for the LED chip 102 and the wire 104. The encapsulating material 108 contacts the bonding pad 54, the routing line 56, the cover 64, the solder resist green paint 74, the LED chip 102, the bonding wire 104 and the die bonding material 106, but with the bump 16, the adhesive layer 30, the dielectric layer 38, the terminal 58 and base 62 maintain a distance. In addition, the encapsulating material 108 covers the bumps 16 , the pads 54 , the cover 64 , the LED chips 102 , the wires 104 , and the die bonding material 106 from above. The encapsulating material 108 is transparent in the figure for convenience of illustration.

The pad 54 is provided with a nickel/silver coated metal pad to securely engage the wire 104, thereby improving signal transmission from the wire 70 to the LED chip 102. A nickel/silver coated metal pad is also provided on the cover 64 to facilitate solid bonding with the die bond material 106, thereby improving heat transfer from the LED die 102 to the heat sink 72. The cover 64 also provides a highly reflective surface that reflects the light from the LED wafer 102 toward the silver surface layer, thereby increasing the amount of light exiting in the upward direction. Moreover, since the shape and size of the cover 64 are adapted to the thermal contact surface 112, the shape and size of the bump 16 need not be designed to match the thermal contact surface 112.

The LED chip 102 is a compound semiconductor which emits blue light and has high luminous efficiency and forms a p-n junction. Suitable compound semiconductors include gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), gallium arsenide (GaAsP), gallium phosphide (GaAlP), gallium arsenide (GaAlAs), Indium phosphide (InP) and indium gallium phosphide (InGaP). In addition, the amount of light emitted by the LED chip 102 is high but also produces considerable thermal energy.

The encapsulating material 108 comprises a transparent epoxy resin and a yellow phosphor (shown as black dots in Figure 12A). For example, the enamel resin may be a polydecane resin, and the yellow phosphor may be a yttrium-doped yttrium aluminum garnet (Ce: YAG) phosphor powder. The yellow phosphor emits yellow light when illuminated by blue light, and the blue and yellow light mix to form white light. Therefore, the encapsulation material 108 can convert the blue light emitted by the LED chip 102 into white light, so that the group 100 becomes a white light source. In addition, the encapsulating material 108 is in the shape of a hemispherical dome, which provides a convex refractive surface to concentrate the white light in the upward direction.

If the semiconductor wafer package 100 is to be fabricated, the LED wafer 102 can be placed on the cover 64 by using the die bonding material 106, and then the bonding pads 54 and the bonding pads 114 can be bonded, and finally the sealing material 108 can be formed.

For example, the die bonding material 106 is originally a silver-containing epoxy resin paste having high thermal conductivity and is selectively printed on the cover 64 by screen printing. The LED wafer 102 is then placed on the epoxy silver paste in a step-and-repeat manner using a grab head and an automated pattern recognition system. The epoxy silver paste is then heated and hardened at a relatively low temperature (e.g., 190 ° C) to complete the die bond 106. The wire 104 is a gold wire which is then connected to the wire bonding pad 54 and the wire bonding pad 114 by thermal ultrasonic waves. Finally, the encapsulation material 108 is molded onto the structure.

The LED chip 102 can be electrically connected to the bonding pad 54 through a plurality of bonding media, thermally bonded by a plurality of thermal adhesives and mechanically adhered to the heat sink 72, and packaged in a plurality of packaging materials.

The semiconductor wafer package 100 is a first-level single crystal package.

13A, 13B, and 13C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package including a heat conductive plate for providing vertical signal routing, a semiconductor device, and a package. material.

In this embodiment, the terminal extends below the adhesive layer and omits the routing line, but is additionally provided with a covered via to provide an electrical connection between the pad and the terminal. For the sake of brevity, the description of the assembly 100 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the assembly of this embodiment are similar to those of the component 100, and the corresponding reference numerals are used, but the base number of the coding is changed from 100 to 200. For example, LED chip 202 corresponds to LED wafer 102, wire 204 corresponds to wire 104, and so on.

The semiconductor wafer package 200 includes a thermally conductive plate 86, an LED wafer 202, a wire 204, a die bonding material 206, and an encapsulation material 208. The LED chip 202 includes a top surface 210, a bottom surface 212, and a wire bonding pad 214. The top surface 210 is an active surface and includes a wire bond pad 214, and the bottom surface 212 is a thermal contact surface.

The LED chip 202 is disposed on the heat sink 72, electrically connected to the wire 70, and thermally coupled to the heat sink 72. In detail, the LED chip 202 is disposed on the cover 64 , electrically connected to the pad 54 via the wire 204 , and thermally coupled via the die bonding material 206 and mechanically adhered to the cover 64 .

The encapsulating material 208 contacts the dielectric layer 38, the pad 54, the cover 64, the LED chip 202, the wire 204, and the die bonding material 206, but remains with the bump 16, the adhesive layer 30, the terminal 58, the covered via 60, and the pedestal 62. distance. In addition, the encapsulation material 208 covers the bumps 16 , the cover 64 , the LED chips 202 , the bonding wires 204 , and the die bonding material 206 from above.

The LED chip 202 can emit blue light, and the encapsulating material 208 can convert the blue light into white light, so that the assembly 200 becomes a white light source.

If the semiconductor wafer assembly 200 is to be fabricated, the LED wafer 202 can be placed on the cover 64 by using the die bonding material 206, and then the bonding pads 54 and the bonding pads 214 can be bonded, and finally the encapsulating material 208 can be formed.

The semiconductor wafer package 200 is a first-level single crystal package.

14A, 14B and 14C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer package according to an embodiment of the present invention, the semiconductor wafer package comprising a heat conducting plate having a raised edge, a semiconductor component and an upper cover.

In this embodiment, the upper cover is placed on the raised edge while omitting the encapsulating material. For the sake of brevity, the description of the assembly 100 is applicable to this embodiment, and the same description will not be repeated. Similarly, the components of the assembly of this embodiment are similar to those of the component 100, and the corresponding reference numerals are used, but the base number of the coding is changed from 100 to 300. For example, LED wafer 302 corresponds to LED wafer 102, wire 304 corresponds to wire 104, and so on.

The semiconductor wafer package 300 includes a heat conductive plate 94, an LED wafer 302, a wire bonding 304, a die bonding material 306, and an upper cover 316. The LED wafer 302 includes a top surface 310, a bottom surface 312, and a wire bonding pad 314. The top surface 310 is an active surface and includes a wire bonding pad 314, and the bottom surface 312 is a thermal contact surface.

The LED chip 302 is disposed on the heat sink 72, electrically connected to the wire 70, and thermally coupled to the heat sink 72. In detail, the LED chip 302 is disposed on the cover 64 and electrically connected to the pad 54 via the wire 304, and is thermally coupled via the die bonding material 306 and mechanically adhered to the cover 64.

The upper cover 316 is a glass plate and is disposed on the raised edge 68, thereby forming a sealing enclosure on the opposite side of the recess 20 to enclose the LED chip 302 and the wire 304, and the LED chip 302 and the wire. 304 provides environmental protection against moisture and particulates. Further, the upper cover 316 is transparent and cannot convert light color.

The LED chip 302 emits white light, which can pass through the upper cover 316 to emit light, so that the assembly 300 becomes a white light source.

If the semiconductor wafer assembly 300 is to be fabricated, the LED wafer 302 can be disposed on the cover 64 by using the die bonding material 306, then the bonding pads 54 and the bonding pads 314 are wire bonded, and finally the upper cover 316 is disposed on the raised edge 68.

The semiconductor wafer package 300 is a first-level single crystal package.

15A, 15B, and 15C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package including a heat conducting plate and a semiconductor component having a back contact.

The semiconductor component in this embodiment is an LED package instead of an LED wafer. In addition, the semiconductor component is disposed on the heat sink and the wire, overlaps the heat sink and the wire, is electrically connected to the pad through the solder, and is thermally coupled to the cover through another solder.

The semiconductor wafer package 400 includes a heat conductive plate 80, an LED package 402, and solders 404, 406. The LED package 402 includes an LED wafer 408, a pedestal 410, a wire 412, electrical contacts 414, thermal contacts 416, and encapsulation material 418. The LED chip 408 includes a wire bonding pad (not shown) electrically connected to one of the conductive holes (not shown) of the pedestal 410 via the wire 412, thereby electrically connecting the LED chip 408 to the electrical connection. Point 414. The LED chip 408 is disposed on the pedestal 410 through a die attach material (not shown) while being thermally bonded and mechanically adhered to the pedestal 410 to thermally bond the LED chip 408 to the thermal contact 416. The pedestal 410 is a ceramic block having low conductivity and high thermal conductivity, and the contacts 414 and 416 are coated on the back surface of the pedestal 410 and protrude downward from the back surface of the pedestal 410. In addition, LED die 408 is similar to LED die 102, wire bond 412 is similar to wire bond 104, and package material 418 is similar to package material 108.

The LED package 402 is disposed on the wire 70 and the heat sink 72, electrically connected to the wire 70, and thermally coupled to the heat sink 72. In detail, the LED package 402 is disposed on the pad 54 (or even the substrate 34) and the cover 64 (or the bump 16), and extends over the pad 54 (or the substrate 34) and the cover 64 (or even Above the bumps 16 and the recesses 20), the bumps 16, the recesses 20, the pads 54 and the cover 64 are covered from above (ie, laterally extending from the bumps 16, the recesses 20, the pads 54 and The periphery of the cover 64 does not overlap the terminal 58 (ie, the LED package 402 is located outside the periphery of the terminal 58). The LED package 402 is electrically connected to the pad 54 via solder 404 and thermally coupled to the cover 64 via solder 406.

For example, the solder 404 contacts and is located between the pad 54 and the electrical contact 414 , and electrically and mechanically bonds the pad 54 and the electrical contact 414 , thereby electrically connecting the LED chip 408 to the terminal 58 . Similarly, the solder 406 is in contact with and located between the cover 64 and the thermal contact 416, while thermally bonding and mechanically bonding the cover 64 to the thermal contact 416, thereby thermally bonding the LED chip 408 to the bump 16, thereby The LED chip 408 is thermally coupled to the pedestal 62.

The pad 54 is provided with a nickel/silver coated metal pad for stable bonding with the solder 404, thereby improving signal transmission from the wire 70 to the LED chip 408. A nickel/silver coated metal pad is also provided on the cover 64 to provide a secure bond with the solder 406 and thereby improve heat transfer from the LED die 408 to the heat sink 72. In addition, since the shape and size of the cover 64 are designed to match the hot contacts 416, the shape and size of the bumps 16 need not be matched with the hot contacts 416.

If the semiconductor wafer assembly 400 is to be fabricated, solder may be deposited on the pad 54 and the cover 64, and then the contacts 414 and 416 are placed on the solder on the pad 54 and the cover 64, respectively, and then the solder is reflowed. To form the next solder 404 and 406.

For example, the solder paste is selectively printed on the pad 54 and the cover 64 by screen printing, and then the LED package 402 is placed in a step-and-repeat manner using a grab head and an automated pattern recognition system. On the heat conducting plate 80. The pick-up head of the reflow machine places contacts 414 and 416 on the solder paste 54 and the solder paste over the cover 64, respectively. The solder paste is then heated to reflow at a relatively low temperature (e.g., 190 ° C), and then the heat source is removed, and the solder paste is allowed to cool and solidify to form hardened solders 404 and 406. Alternatively, a solder ball may be placed on the pad 54 and the cover 64, and then the contacts 414 and 416 are respectively placed on the solder balls above the pad 54 and the cover 64, and then the solder balls are heated to be reflowed to form Next, solders 404 and 406.

The solder may initially be deposited on the thermally conductive plate 80 or the LED package 402 via coating, printing or placement techniques such that it is positioned between the thermally conductive plate 80 and the LED package 402 and then solder reflowed. Solder may also be placed on terminal 58 and pedestal 62 for use in the next layer if desired. In addition, a conductive adhesive (for example, a silver-containing epoxy resin) or other bonding medium may be used instead of the solder, and the bonding pads on the pad 54, the terminal 58, the pedestal 62 and the cover 64 are not necessarily the same.

The semiconductor wafer package 400 is a second-level single crystal module.

The semiconductor wafer package and the heat conductive plate described above are merely illustrative examples, and the present invention can be implemented by other various embodiments. In addition, the above embodiments may be used in combination with other embodiments or in combination with other embodiments in consideration of design and reliability. For example, the substrate can comprise a complex array of single layer conductors and a complex array of multilayer conductors. The thermally conductive plate may comprise a plurality of bumps, wherein the bumps are arranged in an array for use with a plurality of semiconductor components; and in conjunction with additional semiconductor components, the thermally conductive plate may comprise more wires. The heat conducting plate may also include a wire that only contacts the adhesive layer and provides vertical signal routing. The heat conducting plate may also include a wire that only contacts the adhesive layer, and a filler is provided in the cavity. The heat conducting plate may also include a wire for providing vertical signal routing and a filler in the recess. The heat conducting plate may also include a wire that provides vertical signal routing through the covered perforations provided at the peripheral edge of the heat conducting plate. The heat conducting plate may also include a raised edge disposed on the solder resist green paint and a filler is disposed in the recess. The semiconductor component of the present invention may be covered by a transparent, translucent or opaque encapsulating material in a first vertical direction and/or covered by a transparent, translucent or opaque overlying cover. For example, the semiconductor component of the present invention may be a blue LED chip and covered by a transparent encapsulating material or an upper cover to make the group a blue light source; or the LED chip is packaged by a color conversion color. The material or cover is covered to make the group a green, red or white light source. Similarly, the semiconductor component of the present invention can be an LED package having a plurality of LED chips, and the heat conductive plate can include more wires to match the additional LED chips.

The semiconductor component of the present invention can use a heat sink alone or share a heat sink with other semiconductor components. For example, a single semiconductor component can be disposed on a heat sink or a plurality of semiconductor components can be disposed on the same heat sink. For example, four small wafers arranged in a 2x2 array can be attached to the cover and additional wires can be placed on the thermal plate to match the electrical connections of the wafers. This practice is far more economical than placing a tiny bump on each wafer.

The semiconductor wafer of the present invention may be optical or non-optical. For example, the wafer can be an LED, an infrared (IR) detector, a solar cell, a microprocessor, a controller, a dynamic random access memory (DRAM), or a radio frequency (RF) power amplifier. Similarly, the semiconductor package of the present invention can be an LED package or a radio frequency module. Thus, the semiconductor component of the present invention can be an optical or non-optical wafer that is packaged or unpackaged. In addition, a plurality of bonding media can be used to mechanically, electrically, and thermally bond the semiconductor components to the heat conducting plate, including by soldering and using conductive and/or thermally conductive adhesives.

The heat sink of the present invention can quickly, efficiently and uniformly dissipate the heat generated by the semiconductor component to the next layer assembly, and does not allow heat to flow through the adhesive layer, the substrate or the heat conducting plate elsewhere. In this way, an adhesive layer having a lower thermal conductivity can be used, thereby greatly reducing the cost. The heat sink can include an integrally formed bump and a base, and a cover that is metallurgically bonded and thermally coupled to the bump, thereby improving reliability and reducing cost. The cover body may be coplanar with the solder pad for electrical connection, thermal connection, and mechanical connection with the semiconductor component.

The cover body can be tailored to the semiconductor component, and the base can be tailored to the next layer to enhance the thermal connection from the semiconductor component to the next layer. For example, the cover may be square or rectangular on one side of the plane and have the same or similar side shape as the thermal contacts of the semiconductor component; the pedestal may be square or rectangular on one side of the plane, and with a heat dissipation The devices have the same or similar side shapes. In addition, if the opening and the through hole of the present case are not formed by drilling, and are square or rectangular instead of circular, the convex piece may be square or rectangular on one side of the plane, and has the opening And the side shape similar to the through hole, and the side shape which is the same as or similar to the thermal contact of the semiconductor element. In either of the above designs, the heat sink can be constructed with a variety of different thermally conductive structures.

The heat sink can be electrically or electrically isolated from the wires. For example, a routing line extending from the outer side of the adhesive layer and the dielectric layer along the first vertical direction can electrically connect the bonding pad and the cover body, and a routing line extending from the outer side of the adhesive layer and the dielectric layer along the second vertical direction. The base and the terminal can be electrically connected, or the pad can be integrated with the cover. The terminal can be further electrically grounded to electrically ground the cover.

The bumps can be integrally formed with the base and thus become a single metal body (such as copper or aluminum). The bumps may also be integrally formed with the base such that the interface between the two comprises a single metal body (e.g., copper), while other locations include other metals (e.g., a covered contact). The bumps may also be integrally formed with the base, and the interface between the two may comprise a plurality of single metal bodies (for example, a nickel buffer layer on an aluminum core peripheral and a copper layer on the nickel buffer layer).

The pedestal provides mechanical support for the bumps, substrate and adhesive layer. For example, the pedestal prevents bending deformation of the substrate during metal grinding, wafer placement, wire bonding, and molding of the packaging material. Additionally, the back side of the base may include fins that project toward the second vertical direction. For example, a rig can be used to cut the exposed lateral surfaces of the pedestal to form lateral grooves, and such lateral grooves can form fins to increase the surface area of the pedestal. Therefore, if the fins are exposed to the air instead of being disposed on a heat sink, the thermal conductivity of the susceptor via thermal convection can be improved.

The cover can be formed by a variety of deposition techniques after the adhesive layer is cured, including single or multi-layer structures by electroplating, electroless plating, evaporation, and sputtering. The cover body may be made of the same or different metal material as the bump. In addition, the cover may span the through hole and extend to the substrate or be located within the periphery of the through hole. Therefore, the cover can contact or remain at a distance from the substrate. Regardless of any of the above designs, the cover abuts the projection and extends perpendicularly from the projection to the opposite side of the pocket while extending from the side of the projection.

The adhesive layer provides a strong mechanical bond between the heat sink and the substrate. For example, the adhesive layer can extend laterally from the bump, over the wire, and to the peripheral edge of the assembly. The adhesive layer fills the space between the heat sink and the substrate, and is a non-porous structure with a uniform distribution of bonding wires. The adhesive layer also absorbs the mismatch caused by thermal expansion between the heat sink and the substrate. The material of the adhesive layer may be the same as or different from the dielectric layer. In addition, the adhesive layer can be a low cost dielectric and does not require high thermal conductivity. Furthermore, the adhesive layer of this case is not easily delaminated.

We can adjust the thickness of the adhesive layer so that the adhesive layer substantially fills the gap and allows almost all of the adhesive to be located within the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error. Similarly, we can also adjust the thickness of the dielectric layer to achieve this effect.

The substrate can be a low cost laminate structure and does not require high thermal conductivity. Further, the substrate may comprise a single conductive layer or a plurality of conductive layers. Furthermore, the substrate may comprise or consist of a conductive layer.

The conductive layer can be separately disposed on the adhesive layer. For example, a through hole may be formed on the conductive layer, and then the conductive layer is disposed on the adhesive layer, so that the conductive layer contacts the adhesive layer and is exposed to the first vertical direction. At the same time, the bump extends into the through hole and penetrates through The through hole is exposed in the first vertical direction. In this case, the thickness of the conductive layer may be from 100 to 200 micrometers, for example, 150 micrometers. This thickness is thick enough on the one hand, so that it does not bend when transported, and is thin enough on the other hand, so that a pattern can be formed without excessive etching.

The conductive layer may also be disposed on the adhesive layer together with the dielectric layer. For example, the conductive layer may be first disposed on the dielectric layer, then a via hole is formed on the conductive layer and the dielectric layer, and then the conductive layer and the dielectric layer are disposed on the adhesive layer to expose the conductive layer to the first vertical direction. And contacting the dielectric layer between the conductive layer and the adhesive layer, thereby separating the conductive layer from the adhesive layer, and at the same time, the bump extends into the through hole and is exposed through the through hole toward the first vertical direction. In this case, the conductive layer may have a thickness of 10 to 70 microns, for example 50 microns, which is thick enough to provide reliable signal transmission and, on the other hand, thin enough to reduce weight and cost. In addition, the dielectric layer is always part of the heat conducting plate.

The conductive layer and the carrier may also be disposed on the adhesive layer at the same time. For example, a thin film may be first adhered to a carrier such as a bi-directional polyethylene terephthalate film (Mylar), and then only on the conductive layer without forming a via hole on the carrier, followed by conducting The layer and the carrier are disposed on the adhesive layer, so that the carrier covers the conductive layer and is exposed toward the first vertical direction, and the film is in contact with and located between the carrier and the conductive layer, and the conductive layer contacts and is located between the film and the adhesive layer. At the same time, the bumps are aligned with the through holes, and the bumps are covered by the carrier in the first vertical direction. After the adhesive layer is cured, the film may be decomposed by ultraviolet light to strip the carrier from the conductive layer, thereby exposing the conductive layer to the first vertical direction, and then the conductive layer may be ground and patterned to form a pad and a cover. . In this case, the conductive layer may have a thickness of 10 to 70 micrometers, for example, 50 micrometers, which is thick enough to provide reliable signal transmission, and on the other hand is thin enough to reduce weight and cost; thickness of the carrier It can be 300 to 500 microns. This thickness is thick enough on the one hand, so it does not bend and shake when transported, and is thin enough on the other hand to help reduce weight and cost. The carrier is only a temporary fixture and is not permanently part of the heat conducting plate.

The pads and terminals are available in a variety of packages depending on the needs of the semiconductor component and the next layer of the package.

The pads and terminals can be formed by a variety of deposition techniques, including electroplating, electroless plating, evaporation, and sputtering, to form a single or multi-layer structure when the substrate has not been or has been disposed on the adhesive layer. For example, a pattern of a conductive layer may be formed on the substrate when the substrate is not disposed on the adhesive layer or after the substrate has adhered to the bump and the overhanging platform by the adhesive layer, thereby forming a wire. Likewise, the overhanging platform can be patterned to form the pedestal and the terminals prior to forming the coated perforations.

The step of surface treatment with the covered contacts can be performed before or after the pads and terminals are formed. For example, the conductive layer may be etched first to form a pad and a terminal, and then the covered contact is deposited on the structure; or the covered contact is first deposited on the structure, and then the conductive layer is etched to form a pad and a terminal.

The bonding pad and the cover body can be co-located on the first surface facing the first vertical direction, so that the soldering between the semiconductor component and the heat conducting plate can be strengthened by controlling the degree of collapse of the solder ball. Similarly, the base and the terminal may be co-located on a second surface facing the second vertical direction to enhance the soldering between the heat conducting plate and the next layer assembly by controlling the degree of collapse of the solder ball.

The raised edges of the present case may or may not be reflective and may be transparent or opaque. For example, the raised edge may comprise a highly reflective metal such as silver or aluminum and has an inclined inner side surface for reflecting light impinging on the inner side surface toward the first vertical direction, thereby increasing the amount of light emitted in the first vertical direction. Likewise, the raised edges may comprise a transparent material such as glass, or a non-reflective, opaque, and low cost material such as an epoxy. In addition, reflective ridges can be used regardless of whether the raised edge contacts the encapsulating material or limits the extent of the encapsulating material.

The encapsulating material of the present invention can be a variety of transparent, translucent or opaque materials, and can have different shapes and sizes. For example, the encapsulating material can be a transparent epoxy resin, an epoxy resin, or a combination thereof. In terms of the stability of heat conduction and color conversion, the epoxy resin is superior to the epoxy resin, but the cost of the epoxy resin is higher, the hardness is lower, and the adhesion is poor.

The cover on the case can cover or replace the packaging material. The upper cover provides environmental protection such as moisture resistance and anti-particles for wafers and wires in a confined space. The upper cover can be made from a variety of transparent, translucent or opaque materials and can have different shapes and sizes. For example, the upper cover can be a transparent glass or cerium oxide.

We can also use a lens to cover or replace the packaging material. The lens provides environmental protection such as moisture resistance and particle resistance for wafers and wires in a confined space. The lens can also provide a convex refractive surface whereby the light is concentrated in a first vertical direction. The lens can be made from a variety of transparent, translucent or opaque materials and can have different shapes and sizes. For example, a hollow hemispherical dome-shaped glass lens can be placed on the thermally conductive plate and the lens can be kept at a distance from the encapsulating material. Alternatively, a solid hemispherical dome shaped plastic lens can be placed over the encapsulating material and the lens is placed at a distance from the thermally conductive plate.

The wires of this case may include additional pads, terminals, routing wires, coated vias, conductive vias, and passive components, and may be of different configurations. The wires can be used as signal layers, power layers or ground planes depending on the purpose of their respective semiconductor component pads. The wires may also contain various conductive metals such as copper, gold, nickel, silver, palladium, tin, mixtures thereof, and alloys thereof. The ideal composition depends both on the nature of the externally connected medium and on the design and reliability considerations. In addition, those skilled in the art should be able to understand that the copper used in the semiconductor wafer package of the present invention may be pure copper, but is usually a copper-based alloy such as copper-zirconium (99.9% copper), copper-silver-phosphorus. - Magnesium (99.7% copper) and copper-tin-iron-phosphorus (99.7% copper) to improve mechanical properties such as tensile strength and ductility.

In general, it is preferred to provide the cover, routing wires, coated perforations, dielectric layers, fillers, coatings, coated contacts, solder resist green paint, and encapsulating materials, but in some embodiments Can be omitted. For example, if a large pad is used, the routing line can be omitted. If only single layer signal routing is used, the coated perforation can be omitted. If a thicker adhesive layer is used, the dielectric layer can be omitted. If the shape and size of the bump are designed according to the thermal contact surface of the semiconductor element, the cover can be omitted.

The heat conducting plate of the present invention may include a heat conducting hole which is spaced apart from the bump and extends through the adhesive layer and the dielectric layer outside the opening and the through hole while adjoining and thermally connecting the base and the cover body. This enhances the heat dissipation from the cover to the base and promotes the diffusion of thermal energy within the base.

The group of the case can provide horizontal or vertical single layer or multi-layer signal routing.

U.S. Patent Application Serial No. 12/616,773, filed on Jan. The structure of the pad, the terminal and the routing line are all located above the dielectric layer, the contents of which are incorporated herein by reference.

U.S. Patent Application Serial No. 12/616,775, filed on Nov. 11, 2009, the disclosure of which is incorporated herein in The structure of the routing in which the pads, terminals and routing wires are located above the adhesive layer, and the structure is not provided with a dielectric layer, the contents of which are incorporated herein by reference.

U.S. Patent Application Serial No. 12/557,540, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire content a routing structure in which pads and terminals above the dielectric layer are electrically connected by using first and second conductive vias through the dielectric layer and routing lines under the dielectric layer. US Patent Application The content is hereby incorporated by reference.

U.S. Patent Application Serial No. 12/557,541, the entire disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire content The structure of the signal routing, wherein the pads above the dielectric layer and the terminals under the adhesive layer utilize a first conductive via passing through the dielectric layer, a routing line under the dielectric layer, and a second through the adhesive layer The conductive vias are electrically connected, the contents of which are incorporated herein by reference.

The working format of the heat conducting plate of the present case can be single or multiple heat conducting plates, depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a plurality of thermally conductive plates can be fabricated in batches using a single metal sheet, a single adhesive layer, a single substrate, and a single solder resist green paint, and then separated. Similarly, for each thermal plate in the same batch, we can also use a single metal plate, a single adhesive layer, a single substrate and a single solder mask green paint to simultaneously manufacture multiple sets of heat sinks and wires for a single semiconductor component. .

For example, a plurality of bumps may be punched out on a metal plate, and then an uncured adhesive layer having openings corresponding to the bumps is disposed on the overhanging platform such that each of the bumps extends through a corresponding opening; Then, a substrate (having a single conductive layer, a single dielectric layer, and a through hole corresponding to the bumps) is disposed on the adhesive layer, so that each of the bumps extends through a corresponding opening and enters a corresponding pass. a hole; and then the pressing platform is used to make the overhanging platform and the substrate abut each other, forcing the adhesive layer to enter a gap between the bumps and the substrate in the through holes; then curing the adhesive layer, and then grinding the same a bump, the adhesive layer and the conductive layer to form a lateral surface; then coating the coating layer on the structure, and then etching the conductive layer and the coating layer thereon to form a plurality of corresponding corresponding bumps a solder pad, a routing line, a terminal and a cover; and then depositing a solder resist green paint on the structure to form a pattern of the solder resist green paint, so that the pads, the terminals and the cover are exposed to the outside; Then, the covered contacts are the bumps, and the The pad, the terminals, the terminals and the cover are surface-treated; finally, the pedestal, the adhesive layer, the dielectric layer and the solder resist are cut or split at appropriate positions on the peripheral edge of each of the heat-conducting plates Green paint, which separates individual heat-conducting plates from each other.

The working format of the semiconductor wafer package of the present invention may be a single group or a plurality of groups, depending on the manufacturing design. For example, a single group may be separately manufactured, or a plurality of groups may be simultaneously manufactured in batches, and then the heat conducting plates may be separated one by one. Similarly, a plurality of semiconductor elements may be electrically connected, thermally coupled, and mechanically coupled to each of the heat conducting plates in mass production.

For example, a plurality of solid crystal materials may be separately deposited on a plurality of covers, and then a plurality of wafers are respectively placed on the solid crystal materials, and then the solid crystal materials are simultaneously heated to harden and form a plurality of solids. crystal. Then, the wafers are wire bonded to the corresponding pads, and then a plurality of package materials are simultaneously molded on the wafers and wires, and then the heat transfer plates are separated one by one.

We can separate the heat conducting plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be batched into a flat plate, and then a plurality of semiconductor elements are disposed on the flat plate, and then the plurality of semiconductor wafer assemblies formed by the flat plates are separated one by one. Alternatively, a plurality of heat conducting plates can be batched into a flat plate, and then the plurality of heat conducting plates formed by the flat plate are slit into a plurality of heat conducting strips, and then a plurality of semiconductor elements are respectively disposed on the heat conducting strips. Finally, the plurality of semiconductor wafer assemblies formed by the heat conducting strips are separated into individual parts. In addition, mechanical cutting, laser cutting, bifurcation or other suitable techniques may be utilized in splitting the thermally conductive plates.

As used herein, the term "adjacent" means that the elements are integrally formed (forming a single individual) or in contact with one another (with or without separation from one another). For example, the bump abuts the base and the cover but does not abut the dielectric layer.

The term "overlapping" means located above and extending within the perimeter of a lower element. "Overlap" includes extending within, outside of, or within the circumference of the circumference. For example, in a state in which the recess is facing downward, the semiconductor component of the present invention is overlapped with the bump, because an imaginary vertical line can simultaneously penetrate the semiconductor component and the bump, regardless of whether the semiconductor component and the bump exist. There is another element (such as a die-bonding material) that is also the imaginary vertical line, and whether or not another imaginary vertical line only penetrates the bump and does not penetrate the semiconductor element (ie, is located outside the periphery of the semiconductor element) . Similarly, the cover overlaps the bump and the pad overlaps the adhesive layer. In addition, "overlap" is synonymous with "below" and "overlap" is synonymous with "below".

The term "contact" means direct contact. For example, the dielectric layer contacts the pads but does not contact the bumps.

The term "covering" means completely covering in a vertical and/or lateral direction. For example, in a state where the pocket is facing downward, the cover system covers the bump from above, but the bump does not cover the cover from below.

The "layer" word contains a layer with or without a pattern. For example, when the substrate is disposed on the adhesive layer, the conductive layer may be a blank unpatterned flat plate on the dielectric layer; and after the semiconductor component is disposed on the heat sink, the conductive layer may be a spacer having a spacer on the dielectric layer. Circuit pattern. In addition, a "layer" may comprise a plurality of superposed layers.

The term "pad" as used in connection with a conductor means a connection area for connecting and/or bonding an external connection medium (such as solder or wire), and the external connection medium electrically connects the wire to the semiconductor element. .

The term "terminal" when used in conjunction with a conductor means a connected area that can be contacted and/or joined to an externally connected medium (such as solder or wire) that electrically connects the conductor to the next layer. One of the external devices (such as a printed circuit board or a wire connected to it).

The term "coated perforation" when used in conjunction with a conductor means an electrical interconnection structure formed in a hole in a covered manner. For example, a coated perforation may remain intact and remain at a distance from the peripheral edge of the assembly, or may be cleaved or trimmed into a groove in a subsequent process such that the remainder of the coated perforation is in the group In the groove of the outer edge of the body. However, the presence of the coated perforations is independent of which configuration is employed.

When the term "dent" is used in conjunction with a bump, it refers to a closed or non-closed space within the bump. For example, the recess in the bump can be covered by the pedestal in the second vertical direction, thereby forming a closed space; or the recess in the bump can be exposed in the second vertical direction, thereby forming a non-closed space. Similarly, the recess in the bump can be hollow or contain a filler such as epoxy, polyimide or solder.

When the word "about" is used in conjunction with an angle, it means within ±2 degrees.

The words "opening", "through hole" and "hole" refer to the through hole. For example, the bump is inserted into the opening of the adhesive layer with the recess facing downward, and is exposed from the adhesive layer in the upward direction. Similarly, after the bump is inserted into the through hole of the substrate, it is exposed from the substrate in the upward direction.

The term "insertion" means the relative movement between components. For example, "inserting the bump into the through hole" includes: the substrate is fixed and moved by the overhanging platform toward the substrate; the overhanging platform is fixed and moved by the substrate toward the overhanging platform; and the substrate and the overhanging platform abut each other. For another example, "inserting (or extending into) the through hole" includes: a through hole (through and through) of the through hole, and a through hole that is inserted but not penetrated (penetrated but not worn out).

The phrase "together with each other" also refers to the relative movement between components. For example, "the substrate and the overhanging platform abut each other" include: the substrate is fixed and moved by the overhanging platform toward the substrate; the overhanging platform is fixed and moved by the substrate toward the overhanging platform; and the substrate and the overhanging platform are close to each other.

The term "aligned" means the relative position between components. For example, in the case where the recess is facing down, when the adhesive layer has been placed on the base, the substrate has been placed on the adhesive layer, the bump has been inserted and aligned with the opening and the through hole has been aligned with the opening, regardless of the bump system Insert the through hole or under the through hole and keep it away from the through hole.

The term "set in" encompasses contact and non-contact with a single or multiple support elements. For example, a semiconductor component is disposed on the cover, whether the semiconductor component is actually in contact with the cover or is separated from the cover by a solid crystal material.

The term "adhesive layer...in the gap" means the adhesive layer located in the gap. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer within the gap extends across the dielectric layer. Similarly, "the adhesive layer contacts the gap and is located between the bump and the dielectric layer" means that the adhesive layer in the gap contacts and is located between the bump of the inner sidewall of the notch and the dielectric layer of the outer sidewall of the notch.

The term "upper" is intended to mean an upward extension and encompasses contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, in a state where the pocket is facing downward, the cover system extends over the bump while adjoining, overlapping the bump and projecting out of the bump. Likewise, the bumps may extend over the dielectric layer even if they are not adjacent or overlapping the dielectric layer.

The word "below" is intended to mean a downward extension and includes contiguous and non-contiguous elements as well as overlapping and non-overlapping elements. For example, in a state in which the pocket is facing downward, the bump extends below the lid body, abuts the lid body, is overlapped by the lid body, and protrudes from the lid body in a downward direction. Similarly, the bumps may extend below the pads even if they are not adjacent to the pads or overlapped by the pads.

The "first vertical direction" and the "second vertical direction" do not depend on the orientation of the semiconductor wafer package (or the heat conduction plate), and those skilled in the art can easily understand the direction in which they actually refer. For example, the bumps extend vertically on the outer side of the susceptor along the first vertical direction, and extend perpendicularly to the outer side of the cover body along the second vertical direction, whether the assembly is inverted and/or the assembly is disposed in a heat dissipation manner. Not relevant on the device. Similarly, the cover system projects "laterally" from the bump along a lateral plane, regardless of whether the assembly is inverted, rotated or tilted. Therefore, the first and second vertical directions are opposite to each other and perpendicular to the side direction. Furthermore, the laterally aligned elements are coplanar with one another in a lateral plane perpendicular to the first and second perpendicular directions. Furthermore, when the pocket is downward, the first vertical direction is the upward direction and the second vertical direction is the downward direction; when the pocket is upward, the first vertical direction is the downward direction and the second vertical direction is the upward direction.

The semiconductor wafer package of the present invention has a number of advantages. The group's reliability is high, the price is flat and it is very suitable for mass production. This group is especially suitable for high-power semiconductor components (such as LED chips and large semiconductor wafers) and multiple semiconductor components used simultaneously (e.g., arrayed) that are prone to high heat and require excellent heat dissipation to operate efficiently and reliably. Small semiconductor wafer).

The manufacturing process of this case is highly applicable, and combines various mature electrical connections, thermal connections and mechanical joining technologies in a unique and progressive manner. In addition, the manufacturing process of this case can be implemented without expensive tools. As a result, this manufacturing process can significantly increase the yield, yield, performance and cost effectiveness of traditional packaging technologies. Furthermore, the group in this case is extremely suitable for copper wafers and lead-free environmental requirements.

The embodiments described herein are illustrative, and the elements or steps of the present invention are either simplified or omitted to avoid obscuring the features of the present invention. Similarly, in the drawings, the repeated or non-essential elements and reference numerals may be omitted.

Those skilled in the art will be able to readily appreciate various changes and modifications to the embodiments described herein. For example, the foregoing materials, dimensions, shapes, sizes, steps, and order of steps are merely examples. Such changes, modifications and equalizations may be made by those skilled in the art without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Metal plate

12, 14. . . surface

16. . . Bump

18. . . Outreach platform

20. . . Pocket

22, 24. . . Bent corner

26. . . Side wall

28. . . roof

θ ₁ , θ ₂ . . . angle

30. . . Adhesive layer

32. . . Opening

34. . . Substrate

36. . . Conductive layer

38. . . Dielectric layer

40. . . Through hole

42. . . gap

44, 46. . . Coating

48. . . Filler

50, 52. . . Etch resist

54. . . Solder pad

56. . . Routing line

58. . . Terminal

60. . . Covered perforation

62. . . Pedestal

64. . . Cover

68. . . Rising edge

70. . . wire

72. . . Heat sink

74, 76. . . Anti-weld green paint

78. . . Covered joint

80, 82, 84, 86, 88, 90, 92, 94. . . Thermal plate

100, 200, 300, 400. . . Semiconductor wafer package

102, 202, 302, 408. . . LED chip

104, 204, 304, 412. . . Line

106, 206, 306. . . Solid crystal material

108, 208, 418. . . Packaging material

110, 210, 310. . . Top surface

112, 212, 312. . . Bottom

114, 214, 314. . . Wire mat

316. . . Upper cover

402. . . LED package

404, 406. . . Solder

410. . . Pedestal

414. . . Electric contact

416. . . Hot junction

1A and 1B are cross-sectional views illustrating a method for fabricating a bump and an overhanging platform in accordance with an embodiment of the present invention.

1C, 1D, and 1E are enlarged cross-sectional, top, and bottom views, respectively, of FIG. 1B.

2A and 2B are cross-sectional views illustrating a method for making an adhesive layer in an embodiment of the present invention.

The 2C and 2D drawings are a plan view and a bottom view of FIG. 2B, respectively.

3A and 3B are cross-sectional views illustrating a method for fabricating a substrate in an embodiment of the present invention.

The 3C and 3D drawings are a plan view and a bottom view, respectively, of FIG. 3B.

4A to 4L are cross-sectional views illustrating a method for fabricating a heat conducting plate in accordance with an embodiment of the present invention.

The 4M and 4N drawings are a plan view and a bottom view of the 4th L, respectively.

5A, 5B, and 5C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a wire in contact with the adhesive layer.

6A, 6B, and 6C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, which can provide vertical signal routing.

7A, 7B, and 7C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, which can provide vertical signal routing.

8A, 8B, and 8C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a sealed recess containing a filler.

9A, 9B, and 9C are respectively a cross-sectional view, a top view, and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a closed recess containing a filler.

10A, 10B and 10C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a non-closed recess containing a filler.

11A, 11B and 11C are respectively a cross-sectional view, a top view and a bottom view of a heat conducting plate according to an embodiment of the present invention, the heat conducting plate having a raised edge.

12A, 12B and 12C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer package according to an embodiment of the present invention, the semiconductor wafer package comprising a heat conducting plate, a semiconductor component and a packaging material.

13A, 13B, and 13C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package including a heat conductive plate for providing vertical signal routing, a semiconductor device, and a package. material.

14A, 14B and 14C are respectively a cross-sectional view, a top view and a bottom view of a semiconductor wafer package according to an embodiment of the present invention, the semiconductor wafer package comprising a heat conducting plate having a raised edge, a semiconductor component and an upper cover.

15A, 15B, and 15C are respectively a cross-sectional view, a top view, and a bottom view of a semiconductor wafer package including a heat conducting plate and a semiconductor component having a back contact.

16. . . Bump

20. . . Pocket

30. . . Adhesive layer

34. . . Substrate

38. . . Dielectric layer

54. . . Solder pad

56. . . Routing line

58. . . Terminal

62. . . Pedestal

64. . . Cover

70. . . wire

72. . . Heat sink

74. . . Anti-weld green paint

80. . . Thermal plate

400. . . Semiconductor wafer package

402. . . LED package

404. . . Solder

406. . . Solder

408. . . LED chip

412. . . Line

410. . . Pedestal

414. . . Electric contact

416. . . Hot junction

418. . . Packaging material

Claims (85)

A semiconductor wafer assembly comprising at least: a semiconductor component; an adhesive layer having at least one opening; a heat sink having at least one bump and a pedestal, wherein (i) the bump abuts the pedestal Forming an integral with the base and extending from the base in a first vertical direction; (ii) the base extends from the side of the protrusion in a side direction perpendicular to the first vertical direction; Iii) the bump has a recess, the recess being covered by the bump in the first vertical direction, but the recess is not in the second vertical direction opposite to the first vertical direction a bump covering; and a wire comprising a pad and a terminal; wherein the semiconductor component is disposed on the bump, extending beyond the first vertical direction of the bump, outside the cavity, and Extending laterally in a periphery of the recess, the semiconductor component is electrically connected to the solder pad to be electrically connected to the terminal, and the semiconductor component is also thermally coupled to the bump to be thermally coupled to the pedestal Where the adhesive layer contacts the bump and the base, and from the bump Extends across the terminals or to the terminals; wherein the wire is located outside the cavity; and wherein the protrusion enters the recess extending to the opening. The assembly of claim 1, wherein the semiconductor component is an LED chip. The assembly of claim 1, wherein the semiconductor component is electrically connected to the pad by a wire and thermally bonded to the bump by a die bonding material. The assembly of claim 1, wherein the semiconductor component is electrically connected to the pad by a first solder and thermally coupled to the bump by a second solder. The assembly of claim 1, wherein the adhesive layer contacts the pad and the terminal. The assembly of claim 1, wherein the adhesive layer is at a distance from the bonding pad and the terminal, a dielectric layer is in contact between the bonding pad and the adhesive layer, and the terminal is adhered to the terminal. Between the layers, but keeping a distance from the bump and the pedestal. The assembly of claim 1, wherein the adhesive layer is laterally covered, surrounded and conformally coated on one side wall of the bump. The group of claim 1, wherein the adhesive layer extends to a peripheral edge of the group. The assembly of claim 1, wherein the bump comprises a bent corner extending to the base. The assembly of claim 1, wherein the protrusion is bent laterally outwardly adjacent to the base. The assembly of claim 1, wherein the bump has a stamped special irregular thickness. The group of claim 1, wherein the pocket is exposed in the second vertical direction. The group of claim 1, wherein the pocket is covered in the second vertical direction. The group of claim 1, wherein the pocket is not sealed and contains a filler that fills most or all of the pocket. The group of claim 1, wherein the pocket is in a sealed state and contains a filler that fills most or all of the pocket. The assembly of claim 1, wherein the recess extends across the majority of the bumps in the vertical direction and the lateral directions. The assembly of claim 1, wherein the base extends to a peripheral edge of the set. The assembly of claim 1, wherein the bonding pad and the terminal extend outside the first vertical direction of the adhesive layer. The assembly of claim 1, wherein the bonding pad extends on an outer side of the adhesive layer along the first vertical direction, and the terminal extends on an outer side of the adhesive layer along the second vertical direction. The group of claim 1, wherein the pad is coplanar with the terminal. The assembly of claim 1, wherein the base is coplanar with the terminal. The assembly of claim 1, wherein the susceptor, the pad and the terminal are the same metal. The group of claim 1, wherein the susceptor, the pad and the terminal comprise a gold, silver or nickel surface layer and an inner copper core, but mainly copper, the bump is mainly It is copper or all copper. The assembly of claim 1, wherein the heat sink comprises a copper core shared by the bump and the base. The assembly of claim 1, wherein the wire comprises a copper core shared by the pad and the terminal. A semiconductor wafer package comprising: at least one semiconductor component; an adhesive layer having at least one opening; and a heat sink comprising at least one bump, a base and a cover, wherein (i) the bump abuts The base is integrally formed with the base and protrudes from the base in a first vertical direction, the protrusion also abuts the cover body, and the cover body is opposite to the first vertical direction Extending in a vertical direction; (ii) the base extends from the side of the bump in a side direction perpendicular to the vertical direction; (iii) the cover covers the bump in the first vertical direction, and Extending from the side of the bump; and (iv) the bump has a recess, the recess being covered by the bump in the first vertical direction, but the recess is in the second vertical direction Not being covered by the bump, the bump separating the recess from the cover, and the recess extends across the majority of the bump in the vertical direction and the lateral directions; and a wire including a solder pad and a terminal; wherein the semiconductor component is disposed on the cover body and extends along the first vertical side of the cover body The semiconductor element is electrically connected to the terminal, and the semiconductor element is also thermally coupled to the outer side of the recess, and extends laterally in the periphery of the recess. The cover is thermally coupled to the base; wherein the adhesive layer contacts the bump, the base and the cover, and is located between the base and the pad and between the base and the cover And extending laterally from the bump to the terminal or past the terminal; wherein the wire is outside the recess; and wherein the bump and the recess extend into the opening. The assembly of claim 26, wherein the semiconductor component is an LED chip. The assembly of claim 26, wherein the semiconductor component is electrically connected to the pad by a wire and thermally bonded to the cover by a die bonding material. The assembly of claim 26, wherein the semiconductor component is electrically connected to the pad by a first solder and thermally coupled to the cover by a second solder. The assembly of claim 26, wherein the adhesive layer contacts the pad and the terminal. The assembly of claim 26, wherein the adhesive layer is at a distance from the bonding pad and the terminal, a dielectric layer is in contact and is located between the bonding pad and the adhesive layer, and the terminal is adhered to the terminal. Between the layers, but keeping a distance from the bump and the pedestal. The assembly of claim 26, wherein the adhesive layer is laterally covered, circumferentially and conformally coated on one of the side walls of the projection while extending to a peripheral edge of the assembly. The assembly of claim 26, wherein the bump is coplanar with the adhesive layer at the cover. The assembly of claim 26, wherein the bump comprises a first bent corner extending to the base, and a second bent corner extending to the cover, the bent corner Separate from each other vertically. The assembly of claim 26, wherein the protrusion is bent laterally outwardly adjacent to the base, and the protrusion is bent laterally inwardly adjacent to the cover. The assembly of claim 26, wherein the projection is bent laterally outwardly at an angle of about 90 degrees adjacent to the base, the projection being adjacent to the cover at about 90 degrees. The angle is bent inwardly and laterally. The assembly of claim 26, wherein the bump has a stamped special irregular thickness. The assembly of claim 26, wherein the recess is hollow and exposed toward the second vertical direction and exposes the projection toward the second vertical direction. The assembly of claim 26, wherein the pocket is not sealed and contains a filler, the filler contacting the bump, limited by the recess, filling the recess Part or all, and exposed to the second vertical direction. The assembly of claim 26, wherein the recess is in a sealed state and contains a filler, the filler contacts the bump, and is limited by the recess to fill the recess. Part or all, and covered in the second vertical direction. The assembly of claim 26, wherein the recess contains a filler, the filler contacting the bump and extending across the plurality of the bumps in the vertical direction and the lateral directions The filler is confined to the pocket, filling most or all of the pocket and exposing toward the second vertical direction. The assembly of claim 26, wherein the recess includes a filler, the filler contacting the bump and the base, and extending across the convex in the vertical direction and the lateral directions Most of the block, the filler is confined to the pocket, filling most or all of the pocket and being covered by the pedestal in the second vertical direction. The assembly of claim 26, wherein the base covers the wire in the second vertical direction and extends laterally outside the cover to the peripheral edge of the assembly. The assembly of claim 26, wherein the bonding pad and the terminal extend on the outer side of the adhesive layer along the first vertical direction, and are co-located on a surface facing the first vertical direction, the wire A routing line is also included, the routing line being located on a conductive path between the pad and the terminal. The assembly of claim 26, wherein the bonding pad extends on an outer side of the adhesive layer along the first vertical direction, and the terminal extends on an outer side of the adhesive layer along the second vertical direction, the pedestal Cooperating with the terminal on a surface facing the second vertical direction, the wire further includes a covered through hole extending through the adhesive layer and located on a conductive path between the pad and the terminal. The assembly of claim 26, wherein the bonding pad and the cover have the same thickness adjacent to each other, but the thickness of the cover adjacent to the protruding portion is different from the bonding pad, The pad and the cover are co-located on a surface facing the first vertical direction. The assembly of claim 26, wherein the base, the cover, the pad and the terminal are the same metal. The assembly of claim 26, wherein the base, the cover, the pad and the terminal comprise a gold, silver or nickel surface layer and an inner copper core, but mainly copper. The bumps are mainly copper or all copper. The assembly of claim 26, wherein the heat sink comprises a copper core shared by the bump and the base. The assembly of claim 26, wherein the wire comprises a copper core shared by the pad and the terminal. A semiconductor wafer package comprising: at least one semiconductor component; an adhesive layer having at least one opening; and a heat sink comprising at least one bump, a base and a cover, wherein (i) the bump abuts The base is integrally formed with the base and protrudes from the base in a first vertical direction, the protrusion also abuts the cover body, and the cover body is opposite to the first vertical direction Extending in a vertical direction; (ii) the base extends from the side of the bump in a side direction perpendicular to the vertical direction; (iii) the cover covers the bump in the first vertical direction, and Extending from the side of the bump; and (iv) the bump has a recess, the recess being covered by the bump in the first vertical direction, but the recess is in the second vertical direction Not covering the bump, the bump separating the recess from the cover, and the recess extends across the majority of the bump along the vertical direction and the lateral directions; a substrate comprising a a dielectric layer, wherein a via extends through the substrate; and a wire comprising a pad and a terminal; wherein the semiconductor The body element is disposed on the cover body, extends on the outer side of the cover body along the first vertical direction, is located outside the cavity, and extends laterally in a periphery of one of the recesses, and the semiconductor component is electrically connected To the solder pad, electrically connected to the terminal, the semiconductor component is also thermally coupled to the cover to be thermally coupled to the base; wherein the adhesive layer contacts the bump, the base, the cover and the cover a dielectric layer, but maintaining a distance from the bonding pad, the adhesive layer being between the bump and the dielectric layer, between the pedestal and the bonding pad, between the pedestal and the cover, and the base Between the socket and the dielectric layer, and extending laterally from the bump to the terminal or over the terminal; wherein the substrate is disposed on the adhesive layer, the dielectric layer contacts the bonding pad and the cover, but Maintaining a distance from the bump and the base; wherein the wire is located outside the recess; and wherein the bump and the recess extend into the opening and the through hole, the bump extending in the vertical direction to the through hole Outside the hole, the cover covers the opening and the through hole in the first vertical direction. The assembly of claim 51, wherein the semiconductor component is an LED chip. The assembly of claim 51, wherein the semiconductor component is electrically connected to the pad by a wire and thermally bonded to the cover by a die bonding material. The assembly of claim 51, wherein the semiconductor component is electrically connected to the pad by a first solder and thermally coupled to the cover by a second solder. The assembly of claim 51, wherein the dielectric layer contacts and is located between the terminal and the adhesive layer. The assembly of claim 51, wherein the adhesive layer contacts and is located between the terminal and the dielectric layer. The assembly of claim 51, wherein the adhesive layer is laterally covered, circumferentially and conformally coated on one of the side walls of the projection while extending to a peripheral edge of the assembly. The assembly of claim 51, wherein the bump is coplanar with the adhesive layer at the cover. The assembly of claim 51, wherein the bump comprises a first bent corner extending to the base, and a second bent corner extending to the cover, the bent corner Separate from each other vertically. The assembly of claim 51, wherein the portion of the projection that extends to the base is bent laterally outwardly, and the portion of the projection that extends to the cover is bent laterally inward. fold. The assembly of claim 51, wherein the portion of the projection extending to the base is bent laterally outward at an angle of about 90 degrees, the projection extending to a portion of the cover Bend laterally inward at an angle of about 90 degrees. The assembly of claim 51, wherein the bump has a stamped special irregular thickness. The assembly of claim 51, wherein the recess is hollow and exposed toward the second vertical direction, and the bump is exposed toward the second vertical direction. The assembly of claim 51, wherein the recess is not sealed and contains a filler, the filler contacts the bump, and is limited by the recess to fill the recess. Part or all, and exposed to the second vertical direction. The assembly of claim 51, wherein the recess is in a sealed state and contains a filler, the filler contacting the bump, limited by the recess, filling the recess Part or all, and covered in the second vertical direction. The assembly of claim 51, wherein the recess includes a filler, the filler contacting the bump and extending across the plurality of the bumps in the vertical direction and the lateral directions The filler is confined to the pocket, filling most or all of the pocket and exposing toward the second vertical direction. The assembly of claim 51, wherein the recess includes a filler, the filler contacting the bump and the base, and extending across the convex in the vertical direction and the lateral directions Most of the block, the filler is confined to the pocket, filling most or all of the pocket and being covered by the pedestal in the second vertical direction. The assembly of claim 51, wherein the base supports the substrate and the adhesive layer, and covers the wire and the substrate in the second vertical direction while laterally extending to the outside of the cover until the The outer edge of the group. The assembly of claim 51, wherein the bonding pad and the terminal extend on the outer side of the adhesive layer along the first vertical direction, and are co-located on a surface facing the first vertical direction, the wire A routing line is also included, the routing line being located on a conductive path between the pad and the terminal. The assembly of claim 51, wherein the bonding pad extends on the outer side of the adhesive layer and the dielectric layer along the first vertical direction, and the terminal extends along the adhesive layer and the dielectric layer The outer surface of the second vertical direction, the base and the terminal are co-located on a surface facing the second vertical direction, the wire further includes a covered through hole extending through the adhesive layer and the dielectric layer, and Located on a conductive path between the pad and the terminal. The assembly of claim 51, wherein the bonding pad and the cover have the same thickness adjacent to each other, but the thickness of the cover adjacent to the protruding portion is different from the bonding pad, The pad and the cover are co-located on a surface facing the first vertical direction. The assembly of claim 51, wherein the base, the cover, the pad and the terminal are the same metal. The assembly of claim 51, wherein the base, the cover, the pad and the terminal comprise a gold, silver or nickel surface layer and an inner copper core, but mainly copper. The bumps are mainly copper or all copper. The assembly of claim 51, wherein the heat sink comprises a copper core shared by the bump and the base. The assembly of claim 51, wherein the wire comprises a copper core shared by the pad and the terminal. A semiconductor wafer package comprising: at least one semiconductor component; an adhesive layer having at least one opening; and a heat sink comprising at least one bump, a base and a cover, wherein (i) the bump abuts The base is integrally formed with the base and protrudes from the base in a first vertical direction, the protrusion also abuts the cover body, and the cover body is opposite to the first vertical direction Extending in a vertical direction, the bumps include first and second bent corners vertically separated from each other; (ii) the base extends from the side of the bump in a side direction perpendicular to the vertical direction; Iii) the cover covers the bump in the first vertical direction and protrudes from the side of the bump; and (iv) the bump has a recess, the recess is in the first vertical direction The bump covers, but the recess is not covered by the bump in the second vertical direction, the bump separates the recess from the cover, and the recess is along the vertical direction and the same a lateral direction extending across a majority of the bump; and a wire comprising a pad and a terminal; wherein the semiconductor component Is disposed on the cover body, extending on the outer side of the cover body along the first vertical direction, outside the recess, and extending laterally in a periphery of the recess, the semiconductor component is electrically connected to the cover a solder pad electrically connected to the terminal, the semiconductor component is also thermally coupled to the cover to be thermally coupled to the base; wherein the adhesive layer contacts the bump, the base and the cover, and is located Between the pedestal and the pad, and between the pedestal and the cover, extending laterally from the bump to the terminal or over the terminal and extending to a peripheral edge of the assembly; wherein the wire is located Outside the recess; wherein the pad and the cover are co-located on a surface facing the first vertical direction; and wherein the bump and the recess extend into the opening, and the cover is covered in the first vertical direction The opening. The assembly of claim 76, wherein the semiconductor component is an LED device and is electrically connected to the pad by a wire and thermally bonded to the cover by a die bonding material. The assembly of claim 76, wherein the bump is coplanar with the adhesive layer at the cover. The assembly of claim 76, wherein the bonding pad, the terminal and the cover are co-located on a surface facing the first vertical direction, and both extend along the first vertical direction of the adhesive layer. On the outside, the pedestal covers the wire in the second vertical direction and extends laterally outside the cover to the peripheral edge of the set. The assembly of claim 76, wherein the base, the cover, the pad and the terminal are the same metal, and each comprises a gold, silver or nickel surface layer, but mainly copper The bump is mainly copper or all copper. The heat sink includes a copper core shared by the bump and the base, and the wire includes a copper core shared by the solder pad and the terminal. . A semiconductor wafer package comprising: at least one semiconductor component; an adhesive layer having at least one opening; and a heat sink comprising at least one bump, a base and a cover, wherein (i) the bump abuts The base is integrally formed with the base and protrudes from the base in a first vertical direction, the protrusion also abuts the cover body, and the cover body is opposite to the first vertical direction Extending in a vertical direction, the bumps include first and second bent corners vertically separated from each other; (ii) the base extends from the side of the bump in a side direction perpendicular to the vertical direction; Iii) the cover covers the bump in the first vertical direction and protrudes from the side of the bump; and (iv) the bump has a recess, the recess is in the first vertical direction The bump cover is exposed in the second vertical direction, and the bump separates the recess from the cover body, and the recess extends across the convex block in the vertical direction and the lateral direction Partially, and hollow, and the portion of the protrusion forming the recess is also exposed toward the second vertical direction; and a guide a wire comprising a pad and a terminal; wherein the semiconductor component is disposed on the cover, extending on the outer side of the cover along the first vertical direction, outside the cavity, and extending laterally to the recess The semiconductor component is electrically connected to the pad, and is electrically connected to the terminal, and the semiconductor component is also thermally coupled to the cover to be thermally coupled to the pedestal; wherein the adhesive layer contacts The bump, the base and the cover body are located between the base and the soldering pad and between the base and the cover body, and extend from the lateral direction of the bump to the terminal or over the terminal. And extending to a peripheral edge of the group; wherein the wire is located outside the cavity; wherein the pad and the cover are co-located on a surface facing the first vertical direction; and wherein the bump and the cavity extend The opening is entered, and the cover covers the opening in the first vertical direction. The assembly of claim 81, wherein the semiconductor component is an LED device and is electrically connected to the pad by a wire and thermally bonded to the cover by a die bonding material. The assembly of claim 81, wherein the bump is coplanar with the adhesive layer at the cover. The assembly of claim 81, wherein the bonding pad, the terminal and the cover are co-located on a surface facing the first vertical direction, and both extend along the first vertical direction of the adhesive layer. On the outside, the pedestal covers the wire in the second vertical direction and extends laterally outside the cover to the peripheral edge of the set. The assembly of claim 81, wherein the bump, the base, the cover, the pad and the terminal are the same metal, and each comprises a gold, silver or nickel surface layer. But mainly copper, the heat sink includes a copper core shared by the bump, the base and the cover, and the wire includes a copper core shared by the pad and the terminal.