CN102130084A - Semiconductor chip assembly with post/base heat sink and signal post - Google Patents

Abstract

A semiconductor chip assembly at least comprises a semiconductor device, a heat sink, a wire and an adhesive layer. The semiconductor device is electrically connected to the wire and thermally connected to the heat sink. The heat sink at least comprises a heat-conducting protrusion and a base. The heat-conducting protrusion extends upward from the base into a first opening of the adhesive layer, and the base extends laterally from the heat-conducting protrusion. The wire at least comprises a pad, a terminal and a signal protrusion. The signal protrusion extends upward from the terminal into a second opening of the adhesive layer.

Description

Semiconductor chip assembly with post/pedestal heat sink and signal post

technical field

The invention relates to a semiconductor chip group body, in particular to a semiconductor chip group body composed of a semiconductor device, a wire, an adhesive layer and a heat sink and a manufacturing method thereof. Cross-references to related applications:

This application is a continuation-in-part of US Patent Application Serial No. 12/616,773, filed November 11, 2009, the contents of which are incorporated herein by reference. This application is also a continuation-in-part of US Patent Application No. 12/616,775 filed on November 11, 2009, the contents of which are also incorporated herein by reference. This application also claims priority to US Provisional Patent Application Serial No. 61/257,830, filed November 3, 2009, the contents of which are also incorporated herein by reference.

The aforementioned U.S. Patent Application No. 12/616,773 filed on November 11, 2009 and the aforementioned U.S. Patent Application No. 12/616,775 filed on November 11, 2009 were both filed on September 11, 2009 A continuation-in-part of US Patent Application Serial No. 12/557,540, which are also continuations-in-part of US Patent Application Serial No. 12/557,541, filed September 11, 2009.

The aforementioned U.S. Patent Application No. 12/557,540 filed on September 11, 2009 and the aforementioned U.S. Patent Application No. 12/557,541 filed on September 11, 2009 were both filed on March 18, 2009 Continuation-in-Part of U.S. Patent Application No. 12/406,510. This U.S. Patent Application No. 12/406,510 asserts U.S. Provisional Patent Application No. 61/071,589, filed May 7, 2008, U.S. Provisional Patent Application No. 61/071,588, filed May 7, 2008 , U.S. Provisional Patent Application No. 61/071,072, filed April 11, 2008, and U.S. Provisional Patent Application No. 61/064,748, filed March 25, 2008, the contents of which are Incorporated herein by reference. The aforementioned U.S. Patent Application No. 12/557,540 filed on September 11, 2009 and the aforementioned U.S. Patent Application No. 12/557,541 filed on September 11, 2009 also claim that the February 9, 2009 filing Priority to U.S. Provisional Patent Application No. 61/150,980, the contents of which are incorporated herein by reference.

Background technique

Semiconductor devices such as packaged and unpackaged semiconductor chips provide high-voltage, high-frequency, and high-efficiency applications; these applications consume a lot of power to perform specific functions, but the higher the power, the semiconductor device generates heat more and more. In addition, after the packaging density is increased and the size is reduced, the surface area available for heat dissipation is reduced, resulting in increased heat generation.

Semiconductor devices are prone to problems such as performance degradation and shortened service life under high temperature operation, and may even fail immediately. High heat not only affects chip performance, but may also cause thermal stress on the chip and its surrounding devices due to thermal expansion mismatch. Therefore, it is necessary to quickly and effectively dissipate heat from the chip to ensure its operating efficiency and reliability. A high thermal conductivity path typically conducts and dissipates thermal energy to an area with a larger surface area than the chip or die pad on which the chip resides.

Light-emitting diodes (LEDs) have recently become popular as an alternative to incandescent, fluorescent, and halogen light sources. LEDs can provide high energy efficiency and low-cost long-term lighting for applications such as medical, military, signage, signaling, aviation, marine, vehicles, portable devices, commercial and residential lighting. For example, LEDs can provide light sources for equipment such as lamps, flashlights, headlights, searchlights, traffic lights and displays.

The high-power chips in LEDs generate a lot of heat while providing high light output. However, under high-temperature operation, LEDs suffer from problems such as color shift, reduced brightness, shortened lifespan, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. Therefore, LEDs particularly highlight the market's demand for high-power chips with good heat dissipation.

The LED package usually includes an LED chip, a base, electrical contacts and a thermal contact. The base is thermally connected to the LED chip and used to support the LED chip. The electrical contacts are electrically connected to the anode and cathode of the LED chip. The thermal junction is thermally connected to the LED chip through the base, and the carrier below it can sufficiently dissipate heat to prevent the LED chip from overheating.

The industry is actively investing in the research and development of high-power chip packages and thermal pads with various design and manufacturing technologies in order to meet performance requirements in this extremely cost-competitive environment.

The plastic ball grid array (PBGA) package is to wrap a chip and a laminated substrate in a plastic case, and then adhere to a printed circuit board (PCB) with solder balls. The laminate substrate includes a dielectric layer, usually composed of glass fibers. The heat energy generated by the chip can be transferred to the solder ball through the plastic and dielectric layer, and then to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, PBGAs do not dissipate heat well.

Quad Flat No-Lead (QFN) packages place the chip on a copper die pad soldered to a printed circuit board. The heat energy generated by the chip can be transferred to the printed circuit board through the die pad. However, due to the limited routing capability of its lead frame interposer, the QFN package is not suitable for high input/output (I/O) chips or passive devices.

Thermally conductive plates provide functions such as electrical routing, thermal management, and mechanical support for semiconductor devices. A thermal pad usually consists of a substrate for signal routing, a heat sink or heat sink for heat removal, a solder pad for power connection to a semiconductor device, and a terminal for power connection to the next layer of assembly . The substrate can be a laminated structure with single or multi-layer routing circuitry and one or more dielectric layers. The heat sink can be a metal base, a metal block or a buried metal layer.

The thermally conductive plate joins the next layer of assembly. For example, the next layer of assembly can be a lamp holder with a printed circuit board and a heat dissipation device. In this example, an LED package is mounted on a heat conduction plate, the heat conduction plate is mounted on a heat sink, and the heat conduction plate/heat sink subassembly and printed circuit board are mounted in the lamp holder. In addition, the heat conducting plate is electrically connected to the printed circuit board via wires. The substrate guides electrical signals from the printed circuit board to the LED packaging body, and the heat dissipation seat dissipates and transfers the heat energy of the LED packaging body to the heat dissipation device. Therefore, the heat conducting plate can provide an important heat path for the LED chips.

US Patent No. 6,507,102 to Juskey et al. discloses an assembly in which a composite substrate of glass fibers and cured thermosetting resin includes a central opening. A heat slug having a square or rectangular shape similar to the aforementioned central opening is adhered to the sidewall of the central opening so as to be combined with the substrate. The upper and lower conductive layers are adhered to the top and the bottom of the substrate respectively, and are electrically connected to each other through the electroplating via holes penetrating the substrate. A chip is arranged on the heat dissipation block and bonded to the upper conductive layer by wire bonding, a packaging material is molded on the chip, and the lower conductive layer is provided with solder balls.

During manufacture, the substrate is originally a B-stage resin film placed on the lower conductive layer. The heat dissipation block is inserted in the central opening, thus located on the lower conductive layer, and separated from the substrate by a gap. The upper conductive layer is arranged on the substrate. After the upper and lower conductive layers are heated and pressed together, the resin is melted and flows into the aforementioned gap to solidify. The upper and lower conductive layers are patterned, thereby forming circuit wiring on the substrate, and exposing the resin flash on the heat dissipation block. The resin flash is then removed to expose the heat slug. Finally, the chip is placed on the heat dissipation block and then wire bonded and packaged.

Therefore, the heat energy generated by the chip can be transferred to the printed circuit board through the heat slug. However, in mass production, manually placing the heat sink in the central opening is extremely labor-intensive and expensive. Furthermore, due to the small lateral installation tolerance, it is not easy to accurately locate the heat dissipation block in the central opening, resulting in gaps and uneven wiring between the substrate and the heat dissipation block. As a result, the substrate is only partially adhered to the heat dissipation block, cannot obtain sufficient supporting force from the heat dissipation block, and is easy to delaminate. In addition, the chemical etching solution used to remove part of the conductive layer to expose the resin flash will also remove part of the heat sink that is not covered by the resin flash, making the heat sink uneven and difficult to bond, which will eventually lead to lower yield and lower reliability of the assembly. Insufficient and costly.

US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package, the substrate of which includes a metal core layer, and the chip is placed on the die pad area on the top surface of the metal core layer. An insulating layer is formed on the bottom surface of the metal core layer. The blind hole penetrates the insulating layer and directly leads to the metal core layer, and the hole is filled with heat-dissipating solder balls, and solder balls corresponding to the heat-dissipating solder balls are arranged on the substrate. The heat energy generated by the chip can flow to the heat dissipation solder ball through the metal core layer, and then flow to the printed circuit board. However, the insulating layer interposed between the metal core layer and the printed circuit board restricts the heat flow to the printed circuit board.

US Patent No. 6,670,219 to Lee et al. discloses a recessed down ball grid array (CDBGA) package in which a ground plate with a central opening is disposed on a heat sink to form a heat sink substrate. A substrate with a central opening is disposed on the ground plate through an adhesive layer with a central opening. A chip is installed in a groove formed by the central opening of the ground plate on the heat sink, and solder balls are arranged on the substrate. However, since the solder balls are located on the substrate, the heat sink cannot contact the printed circuit board, so the heat dissipation effect of the heat sink is limited to heat convection rather than heat conduction, thus greatly limiting its heat dissipation effect.

US Patent No. 7,038,311 to Woodall et al. provides a high heat dissipation BGA package with an inverted T-shaped heat sink comprising a post and a wide base. A substrate with a window-shaped opening is placed on the wide base, and an adhesive layer adheres the post and the wide base to the substrate. A chip is placed on the post and bonded to the substrate by wire bonding, a packaging material is molded on the chip, and solder balls are arranged on the substrate. The post extends through the window opening and supports the substrate by the wide base, and the solder balls are located between the wide base and the periphery of the substrate. The heat energy generated by the chip can be transmitted to the wide base through the pillars, and then to the printed circuit board. However, the wide base protrudes below the substrate only at a position corresponding to the position between the central window and the innermost solder ball, since there must be room on the wide base to accommodate the solder balls. As a result, the substrate is unbalanced during the manufacturing process, and is easy to shake and bend, which leads to difficulties in chip mounting, wire bonding, and packaging material molding. In addition, the wide base may bend due to the molding of the packaging material, and once the solder balls collapse, it may prevent the package from being soldered to the next layer of assembly. Therefore, the package has low yield, insufficient reliability and high cost.

U.S. Patent Application Publication No. 2007/0267642 of Erchak et al. proposes a light-emitting device assembly, wherein an inverted T-shaped base includes a substrate, a protruding portion, and an insulating layer with a through hole, and on the insulating layer are With electrical contacts. A packaging body with a through hole and a transparent upper cover is arranged on the electrical contact. An LED chip is arranged on the protruding part and connected to the substrate by wire bonding. The protruding portion is adjacent to the substrate and extends through the insulating layer and the through hole on the package body to enter the package body. The insulating layer is arranged on the substrate, and the insulating layer is provided with electric contacts. The packaging body is arranged on the electrical contact and keeps a distance from the insulating layer. The heat energy generated by the chip can be transferred to the substrate through the protruding part, and then reaches a heat dissipation device. However, the electrical contacts are not easy to be disposed on the insulating layer, difficult to be electrically connected to the next layer assembly, and cannot provide multi-layer routing.

Existing packages and thermal pads have significant disadvantages. For example, electrical insulating materials with low thermal conductivity, such as epoxy resin, limit the heat dissipation effect, while electrical insulating materials with higher thermal conductivity, such as epoxy resin filled with ceramic or silicon carbide, have low adhesion and The disadvantage of high mass production cost. The electrically insulating material may delaminate due to heat during fabrication or early in operation. If the substrate is a single-layer circuit system, the routing capability is limited, but if the substrate is a multi-layer circuit system, the over-thick dielectric layer will reduce the heat dissipation effect. In addition, the previous technology still has problems such as insufficient performance of the heat sink, too large volume, or difficult thermal connection to the next layer of assembly. The manufacturing process of the prior art is also not suitable for low-cost mass production.

In view of the various development situations and related limitations of existing high-power semiconductor device packages and heat-conducting plates, the industry really needs a cost-effective, reliable performance, suitable for mass production, multi-functional, flexible signal routing and excellent heat dissipation Sexual semiconductor chipsets.

Contents of the invention

The object of the present invention is to provide a semiconductor chip assembly.

Another object of the present invention is to provide a method for manufacturing a semiconductor chip assembly.

The semiconductor chip assembly of the present invention at least includes a semiconductor device, a heat sink, a wire and an adhesive layer. The semiconductor device is electrically connected to the wire and thermally connected to the heat sink. The heat sink at least includes a heat conduction boss and a base. The heat conduction protrusion extends upward from the base and enters a first opening of the adhesive layer, and the base extends laterally from the heat conduction protrusion. The wire at least includes a welding pad, a terminal and a signal stud. The signal stud extends upward from the terminal and enters a second opening of the adhesive layer.

According to an aspect of the present invention, a semiconductor chip assembly at least includes a semiconductor device, an adhesive layer, a heat sink and a wire. The adhesive layer has at least a first opening and a second opening. The heat sink at least includes a heat conduction protrusion and a base, wherein the heat conduction protrusion is adjacent to the base and extends above the base along an upward direction, and the base is downward along a direction opposite to the upward direction. The direction extends below the heat conduction protrusion, and extends laterally from the heat conduction protrusion along a side direction perpendicular to the upward and downward directions. The wire at least includes a pad, a terminal and a signal stud, wherein the signal stud extends below the pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud .

The semiconductor device is located above the heat conduction protrusion and overlaps the heat conduction protrusion. The semiconductor device is electrically connected to the welding pad, thereby electrically connected to the terminal; and thermally connected to the heat-conducting stud, thereby thermally connected to the base. The adhesive layer is arranged on the base, extends above the base, and extends laterally from the heat conducting post to the terminal or beyond the terminal. The pad extends above the adhesive layer, and the terminal extends below the adhesive layer. The heat conduction protrusion extends into the first opening, and the signal protrusion extends into the second opening. In addition, the protrusions have the same thickness and are coplanar with each other, and the base and the terminal also have the same thickness and are coplanar with each other.

The wire can include the welding pad, the terminal, the signal stud and a routing line. The routing line may adjoin the pad. The signal stud can be adjacent to the routing line and the terminal, extend below the pad and the routing line, and extend above the terminal. The pad and the routing line can overlap the adhesive layer. The terminal can be overlapped by the adhesive layer. The signal stud can extend through the adhesive layer. The welding pad, the terminal, the signal stud and the routing line can contact the adhesive layer. A conductive path between the pad and the terminal may include the signal stud and the routing line.

According to another aspect of the present invention, a semiconductor chip assembly at least includes a semiconductor device, an adhesive layer, a heat sink, a substrate and a wire. The adhesive layer has at least a first opening and a second opening. The heat sink at least includes a heat conduction protrusion and a base, wherein the heat conduction protrusion is adjacent to the base and extends above the base along an upward direction, and the base is downward along a direction opposite to the upward direction. The direction extends below the heat conduction protrusion, and extends laterally from the heat conduction protrusion along a side direction perpendicular to the upward and downward directions. The substrate at least includes a pad and a dielectric layer, and the first and second through holes extend through the substrate. The wire at least includes the pad, a terminal and a signal stud, wherein the signal stud extends below the pad and above the terminal, and a conductive path between the pad and the terminal includes the signal stud .

The semiconductor device is located above the heat conduction protrusion and overlaps the heat conduction protrusion. The semiconductor device is electrically connected to the welding pad, thereby electrically connected to the terminal; and thermally connected to the heat-conducting stud, thereby thermally connected to the base. The adhesive layer is arranged on the base, extends above the base, and extends into a first notch in the first through hole between the heat conducting post and the substrate, and at the same time extends into the second through hole. A second notch in the hole is between the signal stud and the substrate, and extends across the dielectric layer in the notch. The adhesive layer extends laterally from the heat-conducting post to the terminal or crosses the terminal, and is between the heat-conducting post and the dielectric layer, between the signal post and the dielectric layer, and the base between the dielectric layer. The substrate is arranged on the adhesive layer and extends above the base.

The pad extends above the dielectric layer, and the terminal extends below the adhesive layer.

The heat conduction protrusion extends into the first opening and the first through hole, and the signal protrusion extends into the second opening and the second through hole. In addition, the protrusions have the same thickness and are coplanar with each other, and the base and the terminal also have the same thickness and are coplanar with each other.

The heat sink may include a cover, the cover is located above the top of the heat conduction protrusion, adjacent to the top of the heat conduction protrusion, while covering the top of the heat conduction protrusion from above, and conducts heat from the heat conduction protrusion along the side direction. The top of the boss extends laterally. For example, the cover body can be rectangular or square, and the top of the heat conducting post can be circular. In this case, the size and shape of the cover can be designed to match the thermal contact surface of the semiconductor device, while the size and shape of the top of the thermally conductive post is not designed according to the thermal contact surface of the semiconductor device. The cover can also contact and cover a portion of the adhesive layer that is adjacent to the heat conduction protrusion and coplanar with the heat conduction protrusion. The cap can also be coplanar with the pad over the dielectric layer. In addition, the heat-conducting post can thermally connect the base and the cover. The heat sink can be composed of the heat conduction protrusion and the base, or the heat conduction protrusion, the base and the cover. The heat sink can also be made of copper, aluminum or copper/nickel/aluminum alloy. No matter which composition method is used, the heat sink can provide heat dissipation, and the heat energy of the semiconductor device can be diffused to the next layer of assembly.

The semiconductor device can be arranged on the heat sink. For example, the semiconductor device can be disposed on the heat sink and the substrate, overlap the heat conduction stud and the pad, be electrically connected to the pad through a first solder, and be thermally connected to the pad through a second solder. heat sink. Alternatively, the semiconductor device can be disposed on the heat sink instead of the substrate, overlap the heat-conducting stud instead of the substrate, be electrically connected to the pad through a bonding wire, and be thermally connected to the pad through a die-bonding material. heat sink.

The semiconductor device can be a packaged or unpackaged semiconductor chip. For example, the semiconductor device can be an LED package including an LED chip, which is disposed on the heat sink and the substrate, overlaps the heat-conducting stud and the solder pad, and is electrically connected to the solder pad through a first solder. pad, and is thermally connected to the heat sink via a second solder. Alternatively, the semiconductor device can be a semiconductor chip, which is arranged on the heat sink instead of the substrate, overlaps the heat conduction stud instead of the substrate, is electrically connected to the solder pad through a bonding wire, and is connected to the solder pad through a bonding wire. The die-bonding material is thermally connected to the heat sink.

The adhesive layer can contact the heat conduction stud and the dielectric layer in the first notch, contact the signal stud and the dielectric layer in the second notch, and contact the base outside the notch , the terminal and the dielectric layer. The adhesive layer can also cover and surround the protruding post in the side direction, and is conformally coated on the side wall of the protruding post. The adhesive layer can be coplanar with the top and bottom of the protrusion.

The adhesive layer can extend laterally from the heat conducting post to the terminal or beyond the terminal. For example, the adhesive layer and the terminal can extend to the peripheral edge of the assembly; in this example, the adhesive layer extends laterally from the heat conducting post to the terminal. Alternatively, the adhesive layer may extend to the peripheral edge of the assembly, while the terminal is kept at a distance from the peripheral edge of the assembly; in this case, the adhesive layer extends laterally from the thermally conductive post and beyond the terminal .

The heat conduction boss can be integrally formed with the base. For example, the heat conduction stud and the base can be a single metal body or include a single metal body at their interface, wherein the single metal body can be copper. The heat conducting post can also extend through the first opening. The thermally conductive protrusion can also be coplanar with the adhesive layer above the dielectric layer. The heat-conducting post can also be in the shape of a flat-topped cone, and its diameter decreases upwards from the base to the flat top adjacent to the cover.

The signal stud can be integrally formed with the terminal. For example, the signal stud and the terminal can be a single metal body or include a single metal body at their interface, wherein the single metal body can be copper. The signal stud can also extend through the second port. The signal bump can also be coplanar with the adhesive layer above the dielectric layer. The signal post can also be in the shape of a flat-topped cone, and its diameter decreases upward from the terminal to the flat top of the adjacent routing line.

The base can cover the heat-conducting protrusion from below, support the substrate, and keep a distance from the peripheral edge of the assembly.

The substrate can keep a distance from the heat conduction protrusion and the base. The substrate can also be a laminated structure.

The wire can keep a distance from the heat sink. The welding pad can contact the dielectric layer, the terminal can contact the adhesive layer, and the signal stud can contact the adhesive layer and the dielectric layer. In addition, the terminal can be adjacent to the signal stud, extend below the signal stud, and extend laterally from the signal stud.

The pad can be used as an electrical contact of the semiconductor device, the terminal can be used as an electrical contact of the next layer assembly, and the pad and the terminal can provide vertical signals between the semiconductor device and the next layer assembly routing.

The assembly can be a first level or second level monocrystalline or polycrystalline device. For example, the assembly can be a first-level package including a single chip or multiple chips. Alternatively, the assembly can be a second-level module comprising a single LED package or multiple LED packages, wherein each LED package can comprise a single LED chip or multiple LED chips.

The method for manufacturing a semiconductor chip assembly of the present invention includes: providing a heat conduction protrusion, a signal protrusion and a base; setting an adhesive layer on the base, and this step includes inserting the heat conduction protrusion into the adhesive layer, and insert the signal stud into a second opening of the adhesive layer; disposing a conductive layer on the adhesive layer, this step includes aligning the thermally conductive stud with a first opening of the conductive layer through holes, and align the signal studs with a second through hole of the conductive layer; make the adhesive layer flow upward into a first gap between the heat conduction studs and the conductive layer in the first through hole; A second gap between the signal stud and the conductive layer in the second through hole; curing the adhesive layer; providing a wire, the wire at least includes a pad, a terminal, the signal stud and the conductive layer a selected portion of the layer; disposing a semiconductor device on a heat sink, wherein the heat sink includes at least the heat conduction stud and the base; electrically connecting the semiconductor device to the wire; and thermally connecting the semiconductor device to the heat sink.

According to an aspect of the present invention, a method of manufacturing a semiconductor chip assembly includes: (1) providing a thermally conductive stud, a signal stud, a base, an adhesive layer, and a conductive layer, wherein (a) the The heat conduction protrusion is adjacent to the base, extends above the base in an upward direction, extends into a first opening of the adhesive layer, and aligns with a first through hole of the conductive layer, (b) the signal protrusion the post is adjacent to the base, extends above the base in the upward direction, extends into a second opening of the adhesive layer, and is aligned with a second through hole of the conductive layer, (c) the base is along A downward direction opposite to the upward direction extends below the boss and extends laterally from the boss in a side direction perpendicular to the upward and downward directions, (d) the adhesive layer is provided on the base, extending above the base, between the base and the conductive layer, and uncured, and (e) the conductive layer is disposed on the adhesive layer and extends over the adhesive layer (2) Make the adhesive layer flow upward into the first through hole, a first gap between the heat conduction stud and the conductive layer, and a gap between the signal stud and the conductive layer in the second through hole. (3) curing the adhesive layer; (4) providing a wire, the wire at least including a pad, a terminal, the signal stud and a selected portion of the conductive layer; (5 ) arranging a semiconductor device on a heat sink including at least the heat conduction stud and the base, wherein the semiconductor device overlaps the heat conduction stud; (6) electrically connecting the semiconductor device to the pad, thereby electrically (7) thermally connecting the semiconductor device to the thermally conductive stud, thereby thermally connecting the semiconductor device to the terminal, wherein a conductive path between the pad and the terminal includes the signal stud; the base.

According to another aspect of the present invention, a method of manufacturing a semiconductor chip assembly includes: (1) providing a heat conduction stud, a signal stud and a base, wherein the heat conduction stud is adjacent and integrally formed on the base, and extends above the base along an upward direction, the signal boss is adjacent to and integrally formed on the base, and extends above the base along the upward direction, and the base is along a line with the base The downward direction opposite to the upward direction extends below the boss, and extends laterally from the boss in a side direction perpendicular to the upward and downward directions; (2) providing an adhesive layer, wherein the first The opening and the second opening extend through the adhesive layer; (3) providing a conductive layer, wherein the first and second via holes extend through the conductive layer; (4) setting the adhesive layer on the base, this step includes inserting the heat-conducting post into the first opening, and inserting the signal post into the second opening, wherein the adhesive layer extends above the base, the heat-conducting post extends into the first opening, and the signal post extends into the first opening. Then extend into the second opening; (5) disposing the conductive layer on the adhesive layer, this step includes aligning the heat conduction stud with the first through hole, and aligning the signal stud with the second through hole , wherein the conductive layer is extended above the adhesive layer, and the adhesive layer is between the base and the conductive layer and is uncured; (6) heating and melting the adhesive layer; (7) making the base and the The conductive layers are attached to each other, so that the heat conduction stud moves upward in the first through hole, and the signal stud moves upward in the second through hole, and at the same time, the gap between the base and the conductive layer is The melted adhesive layer exerts pressure, and the pressure forces the melted adhesive layer to flow upward into the first through hole, a first gap between the thermally conductive post and the conductive layer, and a first gap between the heat conduction bump and the conductive layer, and a gap between the signal bump in the second through hole. a second gap between the post and the conductive layer; (8) heating and solidifying the melted adhesive layer, thereby mechanically adhering the boss and the base to the conductive layer; (9) providing a wire, the wire At least including a pad, a terminal, a routing line and the signal stud, wherein the wire includes a selected portion of the conductive layer, and a conductive path between the pad and the terminal includes the routing line and the signal stud Signal studs; (10) setting a semiconductor device on a heat sink, the heat sink at least includes the heat conduction studs and the base, wherein the semiconductor device overlaps the heat conduction studs; (11) electrically connects the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and (12) thermally connecting the semiconductor device to the heat-conducting stud, thereby thermally connecting the semiconductor device to the base.

Disposing the conductive layer may include: separately disposing the conductive layer on the adhesive layer, or first adhering the conductive layer to a carrier, and then disposing the conductive layer together with the carrier on the adhesive layer, so that the The carrier overlaps the conductive layer, and the conductive layer contacts the adhesive layer and is interposed between the adhesive layer and the carrier. After the adhesive layer is cured, the carrier is removed first, and then the wire is provided.

According to another aspect of the present invention, a method of manufacturing a semiconductor chip assembly includes: (1) providing a thermally conductive stud, a signal stud, a base, an adhesive layer, and a substrate, wherein (a) the The substrate at least includes a conductive layer and a dielectric layer, (b) the thermally conductive stud is adjacent to the base, extends above the base in an upward direction, extends through a first opening of the adhesive layer, and extends into a first through hole of the substrate, (c) the signal stud is adjacent to the base, extends above the base in the upward direction, extends through a second opening of the adhesive layer, and extends into the A second through hole of the base plate, (d) the base extends below the boss along a downward direction opposite to the upward direction, and extends from the said post along a side direction perpendicular to the upward and downward direction. The protrusions extend laterally, (e) the adhesive layer is disposed on the base, extends above the base, and is located between the base and the substrate, and is uncured, (f) the substrate is disposed on the adhesive layer, extending above the adhesive layer, and the conductive layer extending above the dielectric layer, (g) a first gap is located in the first through hole, and is between the thermally conductive stud and the substrate, in addition, (h) a second notch is located in the second through hole and between the signal stud and the substrate; (2) making the adhesive layer flow upward into the notch; (3) curing the adhesive layer; (4) setting a semiconductor device on a heat sink including at least the heat conduction boss and the base, wherein the semiconductor device overlaps the heat conduction boss, and a wire includes at least one welding pad , a terminal, the signal stud and a selected portion of the conductive layer, and a conductive path between the pad and the terminal includes the signal stud; (5) electrically connecting the semiconductor device to the pad, thereby electrically connecting the semiconductor device to the terminal; and (6) thermally connecting the semiconductor device to the heat-conducting stud, thereby thermally connecting the semiconductor device to the base.

According to still another aspect of the present invention, a method of manufacturing a semiconductor chip assembly includes: (1) providing a heat conduction stud, a signal stud and a base, wherein the heat conduction stud is adjacent and integrally formed on the base, and extends above the base along an upward direction, the signal boss is adjacent to and integrally formed on the base, and extends above the base along the upward direction, the base is along an upward direction The opposite downward direction extends below the boss, and extends laterally from the boss in a side direction perpendicular to the upward and downward directions; (2) providing an adhesive layer, wherein the first opening and the second opening extends through the adhesive layer; (3) providing a substrate comprising at least one conductive layer and a dielectric layer, wherein the first and second via holes extend through the substrate; (4) disposing the adhesive layer on the On the base, this step includes passing the heat conducting post through the first opening, and passing the signal post through the second opening, wherein the adhesive layer extends above the base, and the heat conducting post extends through The first opening, the signal stud extends through the second opening; (5) disposing the substrate on the adhesive layer, this step includes inserting the heat conduction stud into the first through hole, and placing the signal stud Inserting the second through hole, wherein the substrate extends above the adhesive layer, the conductive layer extends above the dielectric layer, the heat conduction stud extends through the first opening and enters the first through hole, and the signal stud extending through the second opening and into the second through hole, the adhesive layer is between the base and the substrate and uncured, a first gap is located in the first through hole and between the heat conduction bump Between the post and the substrate, in addition, a second notch is located in the second through hole and between the signal post and the substrate; (6) heating and melting the adhesive layer; (7) making the base close to the substrate, so that the heat conduction protrusion moves upward in the first through hole, and the signal protrusion moves upward in the second through hole, and at the same time, the gap between the base and the substrate applying pressure to the melted adhesive layer, wherein the pressure forces the melted adhesive layer to flow upward into the gap, and the protrusions and the melted adhesive layer extend above the dielectric layer; (8) heating and solidifying the melted adhesive layer, Thereby mechanically adhering the boss and the base to the substrate; (9) disposing a semiconductor device on a heat dissipation seat, the heat dissipation seat at least includes the heat conduction boss and the base, wherein the semiconductor device overlaps In the stud, a conductive line includes at least a pad, a terminal, the signal stud and a selected portion of the conductive layer, and a conductive path between the pad and the terminal includes the signal stud; (10 ) electrically connecting the semiconductor device to the solder pad, thereby electrically connecting the semiconductor device to the terminal; and (11) thermally connecting the semiconductor device to the heat-conducting stud, thereby thermally connecting the semiconductor device to the base .

Providing the heat conduction stud, the signal stud and the base may include: providing a metal plate; forming a patterned etching resist layer on the metal plate, which selectively exposes the metal plate; etching the metal plate, so that It forms the pattern defined by the patterned etch stop layer, thereby forming a groove in the metal plate, which extends into but not through the metal plate; and then removes the patterned etch stop layer, wherein the thermally conductive bump The post includes a first unetched portion of the metal plate that protrudes above the base and is laterally surrounded by the groove, and the signal stud includes a first unetched portion of the metal plate. Two unetched portions, the second unetched portion protrudes above the base and is laterally surrounded by the groove, the base is also an unetched portion of the metal plate, the unetched portion It is located under the boss and the groove.

Providing the adhesive layer may include: providing a film of uncured epoxy resin. Flowing the adhesive layer may include: melting the uncured epoxy; and squeezing the uncured epoxy between the base and the substrate. Curing the adhesive layer may include: curing the melted uncured epoxy resin.

Providing the heat sink may include: after curing the adhesive layer and before disposing the semiconductor device, providing a cover on the heat conduction post, the cover is located above a top of the heat conduction post and adjacent to the heat conduction post The top part covers the top of the heat conduction protrusion from above and extends laterally from the top of the heat conduction protrusion along the side direction.

Providing the pad may include removing selected portions of the conductive layer after curing the adhesive layer.

Providing the pad may also include: after curing the adhesive layer, grinding the bump, the adhesive layer, and the conductive layer so that the bump, the adhesive layer, and the conductive layer are on a side facing the upward direction. The upper side surfaces are laterally flush with each other; and then removing a selected portion of the conductive layer so that the pad includes the selected portion of the conductive layer. The grinding may include: grinding the adhesive layer without grinding the protrusion; and then grinding the protrusion, the adhesive layer and the conductive layer. The removing may include wet chemical etching the conductive layer with a patterned etch stop defining the pad.

Providing the pad may also include: after grinding, depositing conductive metal on the bump, the adhesive layer, and the conductive layer to form a second conductive layer; and then removing selected portions of these conductive layers, so that The pad includes selected portions of the conductive layers. Depositing conductive metal to form the second conductive layer may include: disposing a first coating layer on the bump, the adhesive layer and the conductive layer in an electroless coating manner; and then electroplating a second coating layer The method is provided on the first covering layer. The removing can include wet chemical etching the conductive layers with a patterned etch stop layer that can define the pad.

Providing the terminal may include removing selected portions of the base after curing the adhesive layer. The removing may include wet chemical etching the pedestal with a patterned etch stop defining the terminal such that the terminal includes an unetched portion of the pedestal adjacent the signal bump. column, and is separated from the base, spaced apart from each other, so it is no longer part of the base. In this way, the pad and the terminal can be formed simultaneously in the same wet chemical etching step using different patterned etch resist layers.

Providing the cover may include removing selected portions of the second conductive layer. Providing the cover may also include performing the aforementioned grinding and then removing selected portions of the second conductive layer using a patterned etch stop that defines the cover, such that the cover includes selected portions of the second conductive layer. fixed part. In this way, the solder pad and the cover can be formed simultaneously through the same grinding process and the same wet chemical etching step using the same patterned etch stop layer.

Making the adhesive layer flow may include: filling the gap with the adhesive layer. Flowing the adhesive layer may also include: pressing the adhesive layer through the gap, reaching above the boss and the substrate, and adjoining the gap between the top surface of the boss and the top surface of the substrate part.

Curing the adhesive layer may include: mechanically combining the protrusion and the base with the substrate.

Setting the semiconductor device may include: setting the semiconductor device on the cover. Arranging the semiconductor device may also include: disposing the semiconductor device on the heat conducting post, the cover, the first opening and the first through hole, and making the semiconductor device overlap the heat conducting post, the cover , the first opening and the first through hole, but not overlapping the signal stud, the second opening and the second through hole.

Setting the semiconductor device may include: providing a first solder and a second solder, wherein the first solder is located between an LED package including an LED chip and the pad, and the second solder is located between the LED package and the pad. between the covers. Electrically connecting the semiconductor device may include: providing the first solder between the LED package and the pad. Thermally connecting the semiconductor device may include: providing the second solder between the LED package and the cover.

Setting the semiconductor device may include: providing a die-bonding material between a semiconductor chip and the cover. Electrically connecting the semiconductor device may include: providing a bonding wire between the chip and the bonding pad. Thermally connecting the semiconductor device may include: providing the die-bonding material between the chip and the lid.

The adhesive layer can contact the boss, the base, the cover and the dielectric layer, cover the substrate from below, cover and surround the boss in the side direction, and extend until the assembly is completed. The peripheral edge formed by separation from other groups produced in the same batch.

After the assembly is completed and separated from other assemblies produced in the same batch, the base can cover the semiconductor device, the heat-conducting studs and the cover from below, while supporting the substrate and connecting with the periphery of the assembly. Edges keep their distance.

The beneficial effects of the present invention are: the present invention has multiple advantages. The heat sink can provide excellent heat dissipation effect and prevent heat energy from flowing through the adhesive layer. Therefore, the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not prone to delamination. The heat conduction boss and the base can be integrally formed to improve reliability. The cover body can be customized for the semiconductor device to improve the effect of thermal connection. The adhesive layer can be interposed between the boss and the substrate and between the base and the substrate, so as to provide a strong mechanical connection between the heat sink and the substrate. The wires can form simple circuit patterns to provide signal routing, or form complex circuit patterns to realize flexible multi-layer signal routing. The wire can also provide vertical signal routing between the pad above the dielectric layer and the terminal below the adhesive layer. The base can provide mechanical support for the substrate and prevent it from being bent and deformed. The assembly can be manufactured using a low-temperature process, which not only reduces stress, but also improves reliability. The assembly can also be fabricated using a high-control process that can be easily implemented by circuit board, lead frame, and tape and reel fabrication plants.

The above and other features and advantages of the present invention will be further illustrated through various embodiments below.

Description of drawings

1 to 4 are cross-sectional views illustrating a method for manufacturing a boss and a base in an embodiment of the present invention;

Fig. 5 and Fig. 6 are respectively the top view and the bottom view of Fig. 4;

7 and 8 are cross-sectional views illustrating a method for making an adhesive layer in an embodiment of the present invention;

Fig. 9 and Fig. 10 are the top view and the bottom view of Fig. 8 respectively;

11 and 12 are cross-sectional views illustrating a method for fabricating a substrate in an embodiment of the present invention;

Figure 13 and Figure 14 are respectively the top view and the bottom view of Figure 12;

15 to 26 are cross-sectional views illustrating a method for manufacturing a heat conducting plate in an embodiment of the present invention, and the heat conducting plate is provided with a substrate on its adhesive layer;

Figure 27 and Figure 28 are respectively the top view and the bottom view of Figure 26;

Figures 29, 30 and 31 are respectively a sectional view, a top view and a bottom view of a heat conduction plate in an embodiment of the present invention, the heat conduction plate is provided with a wire on its adhesive layer;

32, 33 and 34 are respectively a cross-sectional view, a top view and a bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate and an LED package with back contacts;

35, 36 and 37 are respectively a cross-sectional view, a top view and a bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate and an LED package with side leads;

38, 39 and 40 are respectively a sectional view, a top view and a bottom view of a semiconductor chip assembly body in an embodiment of the present invention, the semiconductor chip assembly body includes a heat conducting plate and a semiconductor chip.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

1 to 4 are cross-sectional views illustrating a method of manufacturing a heat-conducting boss 22, a signal boss 24 and a base 26 in an embodiment of the present invention. Top view and bottom view.

FIG. 1 is a cross-sectional view of a metal plate 10 including opposing major surfaces 12 and 14 . The illustrated metal plate 10 is a copper plate having a thickness of 330 microns. Copper has the advantages of high thermal conductivity, good bonding and low cost. The metal plate 10 can be made of various metals such as copper, aluminum, iron-nickel alloy, iron, nickel, silver, gold, mixtures thereof and alloys thereof.

FIG. 2 is a cross-sectional view showing a patterned etch stop layer 16 and a fully covered etch stop layer 18 formed on the metal plate 10 . The patterned etch resist layer 16 and the fully covered etch resist layer 18 shown in the figure are the photoresist layers deposited on the metal plate 10, which are manufactured by pressing the photoresist layers separately with a hot roller simultaneously using a compression molding technique. Fits surfaces 12 and 14. Wet spin coating and curtain coating are also suitable photoresist forming techniques. A photomask (not shown) is attached to the photoresist layer, and then according to the prior art, light is selectively passed through the photomask, so that the part of the photoresist that receives light becomes insoluble; The portion of the photoresist that can still be dissolved, patterning the photoresist layer. Thus, the patterned etch stop layer 16 has a pattern that selectively exposes the surface 12 , while the full coverage etch stop layer 18 is patternless and covers the surface 14 .

FIG. 3 is a cross-sectional view showing a metal plate 10 formed with a groove 20 dug into but not penetrating the metal plate 10 . The groove 20 is formed by etching the metal plate 10 such that the metal plate 10 forms a pattern defined by the patterned etch stop layer 16 . The etch shown in the figure is a front wet chemical etch. For example, the structure can be reversed so that the patterned etch stop layer 16 faces downward and the fully covered etch stop layer 18 faces up, and then a bottom nozzle (not shown) facing the patterned etch stop layer 16 is used to inject The chemical etchant is sprayed upward on the metal plate 10 and the patterned etch stop layer 16. At the same time, the top nozzle (not shown) facing the full coverage of the etch stop layer 18 is not activated, so that Etching by-products are removed by gravity. Alternatively, the backside protection is provided by an etch stop layer 18 covering the entire surface, and the structure can also be immersed in a chemical etching solution to form the groove 20 . The chemical etchant is highly specific to copper and can etch into the metal plate 10 up to 300 microns. Thus, groove 20 extends from surface 12 into but not through metal plate 10 at a distance of 30 microns from surface 14 and a depth of 300 microns. The chemical etchant also causes lateral etching into the metal plate 10 below the patterned etch stop layer 16 . Applicable chemical etching solutions can be solutions containing alkaline ammonia or dilute mixtures of nitric acid and hydrochloric acid. In other words, the chemical etchant can be acidic or alkaline. The ideal etch time sufficient to form the grooves 20 without over-exposing the metal plate 10 to the chemical etchant can be determined by trial and error.

Fig. 4, 5 and Fig. 6 are respectively the sectional view, the top view and the bottom view of the metal plate 10 after removing the patterned etch stop layer 16 and the fully covered etch stop layer 18, wherein the patterned etch stop layer 16 and the fully covered etch stop layer The etch stop layer 18 has been removed by solvent treatment. For example, the solvent used may be a strongly alkaline potassium hydroxide solution at pH 14.

The etched metal plate 10 thus includes the heat conducting studs 22 , the signal studs 24 and the base 26 .

The thermally conductive stud 22 is a first unetched portion of the metal plate 10 protected by the patterned etch stop layer 16 . The heat conduction post 22 is adjacent to the base 26 , integrally formed with the base 26 , protrudes above the base 26 , and is surrounded by the groove 20 from the side. The heat conduction boss 22 is 300 microns high (equal to the depth of the groove 20), the diameter of its top surface (circular part of the surface 12) is 1000 microns, and the diameter of the bottom (the circular part adjacent to the base 26) is 1100 microns. Microns. Therefore, the heat-conducting protrusion 22 is in the shape of a flat-topped cone (similar to a frustum), its sidewalls are tapered, and its diameter gradually decreases from the base 26 toward its flat circular top surface. The tapered sidewall is formed by lateral etching of the chemical etchant under the patterned etch stop layer 16 . The top surface is concentric with the circumference of the bottom (as shown in Figure 5).

The signal stud 24 is a second unetched portion of the metal plate 10 protected by the patterned etch stop layer 16 . The signal post 24 is adjacent to the base 26 , integrally formed with the base 26 , protrudes above the base 26 , and is surrounded by the groove 20 from the side. The signal stud 24 is 300 microns high (equal to the depth of the groove 20), has a diameter of 300 microns at the top (the circular portion of the surface 12), and a diameter of 400 microns at the bottom (the circular portion adjacent to the base 26). Microns. Therefore, the signal post 24 is in the shape of a flat-topped cone (similar to a frustum), its sidewalls are tapered, and its diameter gradually decreases from the base 26 toward its flat circular top surface. The tapered sidewall is formed by lateral etching of the chemical etchant under the patterned etch stop layer 16 . The top surface is concentric with the circumference of the bottom (as shown in Figure 5).

The base 26 is an unetched part of the metal plate 10 below the heat conduction stud 22 and the signal stud 24, and extends from the heat conduction stud 22 and the signal stud 24 along one side to the plane (such as the left and right sides) Extended laterally, the thickness is 30 microns (ie 330-300).

The thermally conductive bumps 22 , the signal bumps 24 and the base 26 can be processed to enhance the bonding with epoxy resin and solder. For example, the thermally conductive studs 22 , the signal studs 24 and the base 26 may be chemically oxidized or micro-etched to produce a rougher surface.

The heat conduction stud 22 , the signal stud 24 and the base 26 are a single metal (copper) body formed by cutting method in the drawing. In addition, the metal plate 10 can also be stamped with a contact piece, wherein the contact piece has a first groove or hole that can define the heat conduction boss 22 and a second groove or hole that can define the signal boss 24, so that the heat conduction boss The column 22 , the signal boss 24 and the base 26 form a single metal body formed by stamping. Alternatively, the heat-conducting protrusion 22 and the signal protrusion 24 can be formed by using an additive method. The method is to deposit the heat-conducting protrusion 22 and the signal protrusion 24 by electroplating, chemical vapor deposition (CVD), physical vapor deposition (PVD) and other technologies. on the base 26. For example, the solder heat conduction boss 22 and the solder signal boss 24 can be electroplated on the copper base 26; in this case, the heat conduction boss 22 and the base 26 are connected by a metallurgical interface, adjacent to each other but not integrally formed, The signal stud 24 and the base 26 are connected by a metallurgical interface, adjacent to each other but not integrally formed. Alternatively, the heat conduction studs 22 and the signal studs 24 can be formed by a semi-additive method, for example, the upper parts of the heat conduction studs 22 and the signal studs 24 can be respectively deposited above the etched lower parts of the heat conduction studs 22 and the signal studs 24 . In addition, the heat conduction protrusion 22, the signal protrusion 24 and the base 26 can also be formed by a semi-additive method at the same time. The column 22 , the signal boss 24 and the upper part of the base 26 have the same shape. The heat conduction studs 22 and the signal studs 24 can also be sintered on the base 26 .

7 and 8 are cross-sectional views illustrating a method for manufacturing the adhesive layer 28 in an embodiment of the present invention. 9 and 10 are respectively a top view and a bottom view drawn according to FIG. 8 .

7 is a cross-sectional view of the adhesive layer 28, wherein the adhesive layer 28 is a B-stage (B-stage) uncured epoxy film, which is an uncured and patternless sheet with a thickness of 180 microns.

The adhesive layer 28 can be various dielectric films or films made of various organic or inorganic electrical insulators. For example, the adhesive layer 28 may initially be a film in which a thermosetting epoxy resin in resin form is impregnated into a reinforcing material and then partially cured to a medium term. The epoxy resin may be FR-4, but other epoxy resins such as multifunctional and bismaleimide-triazine (BT) resins may also be used. Cyanate esters, polyimides, and polytetrafluoroethylene (PTFE) are also useful epoxy resins in certain applications. The reinforcing material can be electronic-grade glass, or other reinforcing materials, such as high-strength glass, low-dielectric glass, quartz, kevlar aramid, and paper. The reinforcing material may also be woven, non-woven or non-directional microfibres. Fillers such as silicon (powdered fused silica) can be added to the film to improve thermal conductivity, thermal shock resistance, and thermal expansion matching. Commercially available prepregs can be used, such as the SPEEDBOARD C film of W.L. Gore & Associates in Oakley, Wisconsin, USA, as an example.

8 , 9 and 10 are respectively a cross-sectional view, a top view and a bottom view of the adhesive layer 28 with openings 30 and 32 . The opening 30 is a first window, which penetrates the adhesive layer 28 and has a diameter of 1150 microns. The opening 32 is a second window, which penetrates the adhesive layer 28 and has a diameter of 450 microns. The openings 30, 32 are mechanically drilled through the film, but can also be made by other techniques, such as stamping and punching.

11 and 12 are cross-sectional views illustrating a method for manufacturing the substrate 34 in an embodiment of the present invention, while FIGS. 13 and 14 are top and bottom views drawn according to FIG. 12 , respectively.

FIG. 11 is a cross-sectional view of the substrate 34 . The substrate 34 includes a conductive layer 36 and a dielectric layer 38 . Conductive layer 36 is an electrical conductor that contacts dielectric layer 38 and extends over dielectric layer 38 . The dielectric layer 38 is an electrical insulator. For example, the conductive layer 36 is an unpatterned copper plate with a thickness of 30 microns, and the dielectric layer 38 is epoxy resin with a thickness of 150 microns.

12 , 13 and 14 are respectively a cross-sectional view, a top view and a bottom view of the substrate 34 having through holes 40 and 42 . The through hole 40 is a first window, which penetrates the substrate 34 and has a diameter of 1150 microns. The through hole 42 is a second window, which penetrates the substrate 34 and has a diameter of 450 microns. The via holes 40 and 42 are formed by mechanically drilling through the conductive layer 36 and the dielectric layer 38 , but they can also be made by other techniques, such as punching and stamping. Preferably, the opening 30 and the through hole 40 have the same diameter, and are formed in the same way on the same drill floor with the same drill bit; The drill floor is formed in the same way.

The substrate 34 is shown here as a laminated structure, but the substrate 34 can also be other electrically connected objects, such as a ceramic board or a printed circuit board. Likewise, the substrate 34 may further include a plurality of layers embedded with circuits.

15 to 26 are cross-sectional views illustrating a method of manufacturing a heat conduction plate 74 in an embodiment of the present invention. The heat conduction plate 74 includes a heat conduction boss 22, a signal boss 24, a base 26, an adhesive layer 28 and a substrate. 34. 27 and 28 are a top view and a bottom view of FIG. 26, respectively.

FIG. 15 is a cross-sectional view of the adhesive layer 28 disposed on the base 26 . The adhesive layer 28 descends onto the base 26 , so that the heat conduction post 22 is inserted upwards and passes through the opening 30 , while the signal post 24 is inserted upwards and passes through the opening 32 , and finally the adhesive layer 28 contacts and is positioned on the base 26 . Preferably, the heat conduction post 22 is aligned with the opening 30 after being inserted into and penetrated through the opening 30 and is located at the center of the opening 30 without contacting the adhesive layer 28; and the signal post 24 is also aligned after being inserted into and through the opening 32 The opening 32 is located at the center of the opening 32 but does not touch the adhesive layer 28 .

In the structure shown in FIG. 16 , the substrate 34 is disposed on the adhesive layer 28 . The substrate 34 descends onto the adhesive layer 28 , so that the heat conduction protrusion 22 is inserted upward into the through hole 40 , and the signal protrusion 24 is upwardly inserted into the through hole 42 , and finally the substrate 34 is contacted and positioned on the adhesive layer 28 .

After being inserted into (but not penetrating through) the through hole 40 , the heat conduction protrusion 22 is aligned with the through hole 40 and is located at the center of the through hole 40 without contacting the substrate 34 . Therefore, the notch 44 is located in the through hole 40 and interposed between the heat conduction protrusion 22 and the substrate 34 . The notch 44 laterally surrounds the heat-conducting protrusion 22 and is laterally surrounded by the substrate 34 . In addition, the opening 30 and the through hole 40 are aligned with each other and have the same diameter.

After the signal stud 24 is inserted into (but not penetrated through) the through hole 42 , it is aligned with the through hole 42 and is located in the center of the through hole 42 without contacting the substrate 34 . Therefore, the notch 46 is located in the through hole 42 and between the signal stud 24 and the substrate 34 . The notch 46 laterally surrounds the signal stud 24 and is laterally surrounded by the substrate 34 . In addition, the opening 32 and the through hole 42 are aligned with each other and have the same diameter.

At this time, the substrate 34 is disposed on and in contact with the adhesive layer 28 , and extends above the adhesive layer 28 . After extending through the opening 30 , the heat conducting post 22 enters the through hole 40 and reaches the dielectric layer 38 . The thermally conductive bump 22 is 60 microns lower than the top surface of the conductive layer 36 and is exposed in an upward direction through the through hole 40 . After the signal stud 24 extends through the opening 32 , enters the via hole 42 and reaches the dielectric layer 38 . The signal stud 24 is 60 microns lower than the top surface of the conductive layer 36 , and is exposed in the upward direction through the via hole 42 . The adhesive layer 28 is in contact with and interposed between the base 26 and the substrate 34 . Adhesive layer 28 contacts dielectric layer 38 but is spaced from conductive layer 36 . At this stage, the adhesive layer 28 is still a B-stage film of uncured epoxy resin, and the gaps 44, 46 are filled with air.

FIG. 17 shows that the adhesive layer 28 flows into the gaps 44 and 46 after being heated and pressed. In this figure, the method of forcing the adhesive layer 28 to flow into the gaps 44, 46 is to exert downward pressure on the conductive layer 36 and/or exert upward pressure on the base 26, that is to say, press the base 26 against the substrate 34. together, so as to apply pressure to the adhesive layer 28; at the same time, the adhesive layer 28 is also heated. The heated adhesive layer 28 can be shaped arbitrarily under pressure. Therefore, the adhesive layer 28 located between the base 26 and the substrate 34 changes its original shape and flows upward into the notches 44 , 46 after being squeezed. The base 26 and the substrate 34 continue to be pressed against each other until the adhesive layer 28 fills the gaps 44 , 46 . In addition, after the gap between the base 26 and the substrate 34 is narrowed, the adhesive layer 28 still fills up the narrowed gap.

For example, the base 26 and the conductive layer 36 may be disposed between the upper and lower press tables (not shown) of a laminating machine. In addition, an upper baffle and upper buffer paper (not shown) can be sandwiched between the conductive layer 36 and the upper pressing table, and a lower baffle and lower buffer paper (not shown) can be sandwiched between the base 26 and Press down the room. From top to bottom, the composite body thus constituted is an upper press table, an upper baffle plate, an upper buffer paper, a substrate 34, an adhesive layer 28, a base 26, a lower buffer paper, a lower baffle plate and a lower press table. In addition, tooling feet (not shown) extending upwardly from the hold down table and through alignment holes (not shown) in the base 26 may be used to position the composite on the hold down table.

Then, the upper and lower pressing stages are heated and pushed toward each other, thereby heating and pressing the adhesive layer 28 . The baffle can dissipate the heat of the pressing table, so that the heat is evenly applied to the base 26 and the substrate 34 and even the adhesive layer 28 . The buffer paper disperses the pressure of the press table, so that the pressure is evenly applied to the base 26 , the substrate 34 and even the adhesive layer 28 . Initially, the dielectric layer 38 contacts and is pressed against the adhesive layer 28 . As the press continues to operate and heat, the adhesive layer 28 between the base 26 and the substrate 34 is squeezed and begins to melt, thus flowing upward into the notches 44 , 46 and reaching the conductive layer 36 after passing through the dielectric layer 38 . For example, after the uncured epoxy resin is heated and melted, it is squeezed into the gaps 44 , 46 by pressure, but the reinforcing material and filler remain between the base 26 and the base plate 34 . The speed of the adhesive layer 28 rising in the through hole 40 is faster than that of the heat conduction protrusion 22 , and finally fills the gap 44 . The rising speed of the adhesive layer 28 in the through hole 42 is also faster than that of the signal stud 24 , and finally fills up the gap 46 . The adhesive layer 28 also rises to a position slightly higher than the notches 44 and 46, and overflows to the top surface of the heat-conducting boss 22 and the top surface of the conductive layer 36 adjacent to the notch 44, and the top of the signal boss 24 before the pressure table stops. The surface and the top surface of the conductive layer 36 are adjacent to the gap 46 . This can happen if the film thickness is slightly larger than necessary. In this way, the adhesive layer 28 forms a covering thin layer on the top surface of the heat conducting post 22 and the top surface of the signal post 24 . The press platform stops moving after touching the heat conduction boss 22 and the signal boss 24 , but still continues to heat the adhesive layer 28 .

The direction of the upward flow of the adhesive layer 28 in the gaps 44 and 46 is shown by the thick upward arrows in the figure, and the upward movement of the heat conducting post 22 , the signal post 24 and the base 26 relative to the substrate 34 is shown by the thin upward arrows. , and the downward movement of the substrate 34 relative to the heat conduction boss 22 , the signal boss 24 and the base 26 is shown by the downward thin arrow.

The adhesive layer 28 in Fig. 18 has been cured.

For example, after the pressure table stops moving, it still continues to clamp the heat-conducting boss 22, the signal boss 24 and the base 26 and supply heat, thereby converting the melted B-stage epoxy resin into C-stage (C -stage) cured or hardened epoxy resin. Thus, the epoxy is cured in a manner similar to existing multilayer laminations. After the epoxy has cured, the press table separates to allow the structure to be removed from the press.

The cured adhesive layer 28 provides strong mechanical connections between the thermally conductive studs 22 and the substrate 34 , between the signal studs 24 and the substrate 34 , and between the base 26 and the substrate 34 . Adhesive layer 28 can withstand general operating pressure without deformation and damage, and only temporarily distorts when encountering excessive pressure. Furthermore, the adhesive layer 28 can absorb thermal expansion mismatches between the heat conduction studs 22 and the substrate 34 , between the signal studs 24 and the substrate 34 , and between the base 26 and the substrate 34 .

At this stage, the heat-conducting studs 22 , the signal studs 24 and the conductive layer 36 are substantially coplanar, and the adhesive layer 28 and the conductive layer 36 extend to a top surface facing the upward direction. For example, the thickness of the adhesive layer 28 between the base 26 and the dielectric layer 38 is 120 microns, which is 60 microns less than its initial thickness of 180 microns; The through hole 42 is elevated by 60 microns, while the substrate 34 is lowered by 60 microns relative to the heat conduction studs 22 and the signal studs 24 . The height of 300 microns of the heat conduction studs 22 and the signal studs 24 is substantially equal to the combined height of the conductive layer 36 (30 microns), the dielectric layer 38 (150 microns) and the underlying adhesive layer 28 (120 microns). In addition, the heat conduction post 22 is still located at the center of the opening 30 and the through hole 40 and keeps a distance from the substrate 34, and the signal post 24 is still located at the center of the opening 32 and the through hole 42 and keeps a distance from the substrate 34, so as to be adhered. Layer 28 fills the space between base 26 and substrate 34 and fills gaps 44 , 46 . For example, the notch 44 (and the adhesive layer 28 between the heat conduction post 22 and the substrate 34) is 75 microns wide at the top surface of the heat conduction post 22 [(1150-1000)/2], the notch 46 (and the signal post 24 and the substrate The adhesive layer 28 between 34) has a width of 75 microns [(450-300)/2] at the top surface of the signal stud 24 . Adhesive layer 28 extends across dielectric layer 38 within gaps 44 , 46 . In other words, the adhesive layer 28 in the notch 44 extends along the upward direction and a downward direction and spans the thickness of the dielectric layer 38 on the outer wall of the notch 44, while the adhesive layer 28 in the notch 46 extends along the upward direction and this direction. The thickness of the dielectric layer 38 extends downward and spans the outer sidewall of the notch 46 . The adhesive layer 28 also includes a thin top portion above the notches 44, 46, which contacts the top surface of the thermally conductive stud 22, the signal stud 24 and the top surface of the conductive layer 36 and extends 10 above the thermally conductive stud 22, the signal stud 24. Microns.

In the structure shown in FIG. 19 , the tops of the heat conducting studs 22 , the signal studs 24 , the adhesive layer 28 and the conductive layer 36 have been removed.

The tops of the heat conduction studs 22 , the signal studs 24 , the adhesive layer 28 and the conductive layer 36 are removed by grinding, for example, using a diamond grinding wheel and distilled water to treat the top of the structure. Initially, the diamond grinding wheel only removes the adhesive layer 28 . As the grinding continues, the adhesive layer 28 becomes thinner due to the downward movement of the ground surface. The diamond grinding wheel will eventually contact the thermally conductive studs 22 , the signal studs 24 and the conductive layer 36 (not necessarily at the same time), thus starting to grind the thermally conductive studs 22 , the signal studs 24 and the conductive layer 36 . After continuous grinding, the thermally conductive boss 22 , the signal boss 24 , the adhesive layer 28 and the conductive layer 36 all become thinner due to the downward movement of the ground surface. Grinding continues until the desired thickness is removed. Afterwards, the structure was rinsed with distilled water to remove dirt.

The grinding step above grinds off the top of the adhesive layer 28 by 25 microns, the top of the thermally conductive post 22 by 15 microns, the top of the signal post 24 by 15 microns, and the top of the conductive layer 36 by 15 microns. The reduction in thickness has no obvious effect on the heat conduction studs 22 , the signal studs 24 or the adhesive layer 28 , but the thickness of the conductive layer 36 is greatly reduced from 30 microns to 15 microns.

So far, the heat-conducting studs 22 , the signal studs 24 , the adhesive layer 28 and the conductive layer 36 are located on the top surface of the dielectric layer 38 on the smooth splicing side facing the upward direction. Likewise, the heat conduction studs 22 , the signal studs 24 and the adhesive layer 28 are coplanar with each other at the base 26 .

The structure shown in FIG. 20 has a conductive layer 50 deposited on the thermally conductive stud 22 , the signal stud 24 , the adhesive layer 28 and the conductive layer 36 .

The conductive layer 50 is in contact with the thermally conductive studs 22 , the signal studs 24 , the adhesive layer 28 and the conductive layer 36 , and covers them from above. For example, the structure can be immersed in an activator solution, so that the adhesive layer 28 can catalyze the reaction with the electroless copper plating, and then a first copper layer is provided on the thermally conductive studs 22 and the signal studs in an electroless coating manner. 24. On the adhesive layer 28 and the conductive layer 36, a second copper layer is then electroplated on the first copper layer. The first copper layer is about 2 microns thick, and the second copper layer is about 13 microns thick, so the total thickness of the conductive layer 50 is about 15 microns. Thus, the thickness of the conductive layer 36 increases to about 30 microns (15+15). The conductive layer 50 is used as a covering layer for the thermally conductive studs 22 and the signal studs 24 and as a thickened layer for the conductive layer 36 . For ease of illustration, the thermally conductive stud 22, the signal stud 24, the conductive layer 50, and the conductive layers 36 and 50 are all shown as a single layer. Due to the homogeneous coating of copper, the boundaries between the thermally conductive studs 22 and the conductive layer 50, the boundaries between the signal studs 24 and the conductive layer 50, and the boundaries between the conductive layers 36 and 50 (both shown in dotted lines) may be difficult to detect or even Undetectable. However, the boundary between the adhesive layer 28 and the conductive layer 50 is clearly visible.

The upper and lower surfaces of the structure shown in FIG. 21 are respectively provided with a patterned etch stop layer 52 and a patterned etch stop layer 54 . The patterned etch stop layers 52 and 54 shown in the figure are photoresist layers similar to the patterned etch stop layer 16 . The patterned etch stop layer 52 has a pattern for selectively exposing the conductive layer 50 , and the patterned etch stop layer 54 has a pattern for selectively exposing the base 26 .

In the structure shown in FIG. 22, conductive layers 36, 50 have been etched to remove selected portions thereof to form a pattern defined by a patterned etch stop layer 52, and base 26 has also been etched to remove selected portions thereof. to form the pattern defined by the patterned etch stop layer 54 . The etching is a double-sided wet chemical etching similar to that applied to the metal plate 10 . For example, a top nozzle (not shown) and a bottom nozzle (not shown) are used to spray the chemical etching solution on the top surface and the bottom surface of the structure respectively, or the structure is immersed in the chemical etching solution. The chemical etchant can etch through the conductive layers 36 , 50 to expose the adhesive layer 28 and the dielectric layer 38 , thus transforming the originally non-patterned conductive layers 36 , 50 into patterned layers. The chemical etchant also etches through the base 26 to expose the adhesive layer 28 .

In FIG. 23 , the patterned etch stop layers 52 and 54 on the structure have been removed. The patterned etch stop layer 52 , 54 may be removed in the same manner as the patterned etch stop layer 16 and the full coverage etch stop layer 18 .

The etched conductive layers 36 , 50 include pads 56 and routing lines 58 , and the etched conductive layer 50 includes a cover 60 . The welding pad 56 and the routing line 58 are the parts where the conductive layers 36 and 50 are protected by the patterned etching resistance layer 52 and are not etched, and the cover body 60 is the part where the conductive layer 50 is protected by the patterned etching resistance layer 52 and is not etched. part. In this way, the conductive layers 36 and 50 become pattern layers, which include the pads 56 and routing lines 58 but do not include the cover 60 . In addition, the routing line 58 is a copper wire, which contacts the dielectric layer 38 and extends above it, and is adjacent to and electrically connected to the signal stud 24 and the pad 56 .

The etched pedestal 26 includes the pedestal 26 (only its central portion remains) and the terminal 62 . The pedestal 26 is an unetched portion of the original pedestal 26 protected by the patterned etch stop layer 54 , which extends laterally and protrudes 1000 μm beyond the thermally conductive protrusion 22 in the lateral direction. The terminal 62 is the unetched part of the original base 26 protected by the patterned etch stop layer 54, which is adjacent to the signal stud 24, extends below the signal stud 24, and extends laterally from the signal stud 24, Simultaneously contact the adhesive layer 28 and extend below the adhesive layer 28 . The base 26 is still a non-patterned layer, but a patterned layer including the terminals 62 and maintaining a lateral distance from the base 26 is formed outside the periphery of the base 26 . Therefore, the terminals 62 and the base 26 are separated from each other, and the terminals 62 are no longer part of the base 26 . In addition, the signal stud 24 is adjacent to the routing line 58 and the terminal 62 and forms an electrical connection between the routing line 58 and the terminal 62 .

The signal stud 24 , the welding pad 56 , the routing line 58 and the terminal 62 together form a wire 64 . The signal stud 24 and the routing line 58 are a conductive path between the pad 56 and the terminal 62 . Conductor 64 provides vertical (top-to-bottom) routing from pad 56 to terminal 62 . Wire 64 is not limited to this configuration. For example, the above-mentioned conductive paths may include conductive vias penetrating the dielectric layer 38, additional routing lines (which are located above and/or below the dielectric layer 38), and passive devices (such as resistors and capacitors disposed on other pads). ).

The heat sink 66 includes the heat conduction protrusion 22 , the base 26 and the cover 60 . The heat conduction protrusion 22 and the base 26 are integrally formed. The cover 60 is located above the top of the heat conducting post 22 , adjacent to the top of the heat conducting post 22 , covers the top of the heat conducting post 22 from above, and extends laterally from the top of the heat conducting post 22 . After the cover body 60 is installed, the heat conduction protrusion 22 is located in the central area of the circumference of the cover body 60 . The cover 60 also touches and covers a portion of the adhesive layer 28 below it from above. The portion of the adhesive layer 28 is coplanar with the heat-conducting protrusion 22 , adjacent to the heat-conducting protrusion 22 , and laterally surrounds the heat-conducting protrusion 22 .

The heat sink 66 is substantially an inverted T-shaped heat sink, which includes a pillar (the heat conducting boss 22 ), a wing (the portion of the base 26 extending laterally from the pillar), and a heat conducting pad (the cover 60 ).

The structure of FIG. 24 is provided with solder resist green paint 68 on the adhesive layer 28, the dielectric layer 38, the conductive layer 50 and the cover body 60, and is provided with the solder resist green paint on the base 26, the adhesive layer 28 and the terminal 62. 70.

The solder resist green paint 68 is an electrically insulating layer that can be patterned at our option to expose the solder pads 56 and the cover 60, and to cover the routing lines 58, the exposed portions of the adhesive layer 28 and the dielectric layer 38 from above. exposed part. The solder mask green paint 68 has a thickness of 25 microns above the pads 56 and the cover 60 , and the solder mask green paint 68 extends 55 microns (30+25) above the dielectric layer 38 .

The solder resist green paint 70 is an electrically insulating layer that can be patterned to expose the base 26 and the terminals 62 at our option, and cover the exposed portion of the adhesive layer 28 from below. The thickness of the solder resist green paint 70 below the base 26 and the terminals 62 is 25 microns, and the solder resist green paint 70 extends 55 microns (30+25) below the adhesive layer 28 .

The solder resist green paint 68, 70 is initially a photo-imageable liquid resin coated on the structure. Afterwards, patterns are formed on the solder resist green paint 68, 70 by selectively passing light through a photomask (not shown in the figure), so that the part of the solder resist green paint that receives light becomes insoluble, and then a developing solution is used to remove the unresolved solder resist. Part of the solder resist green paint that is exposed to light and can still be dissolved is finally hard-baked. The above steps are existing techniques.

The base 26 , the welding pad 56 , the cover 60 and the terminals 62 of the structure shown in FIG. 25 are provided with covered contacts 72 .

The covered contact 72 is a multi-layer metal plating, which contacts the base 26 and the terminal 62 and covers the exposed portion from below, and contacts the pad 56 and the cover 60 and covers the exposed portion from above. For example, a nickel layer is provided on the base 26, the welding pad 56, the cover 60 and the terminal 62 by electroless coating, and then a gold layer is provided on the nickel layer by electroless coating, wherein The inner nickel layer is about 3 microns thick, and the surface gold layer is about 0.5 microns thick, so the thickness of the coated contact 72 is about 3.5 microns.

The surface treatment of base 26 , solder pad 56 , cover 60 and terminal 62 with covered contact 72 has several advantages. The inner nickel layer provides the primary mechanical and electrical connection and/or thermal connection, while the surface gold layer provides a wettable surface for solder reflow. The covered contact 72 also protects the base 26 , the solder pad 56 , the cover 60 and the terminal 62 from corrosion. Covered contacts 72 may include various metals to meet the requirements of the external connection medium. For example, a silver layer over a nickel layer can be used with solder or wire bonding.

For ease of illustration, the base 26 with the covered contacts 72 , the pads 56 , the cover 60 and the terminals 62 are all shown in a single layer. The boundary (not shown) between the covered contact 72 and the base 26 , the pad 56 , the cover 60 and the terminal 62 is a copper/nickel interface.

So far, the fabrication of the heat conducting plate 74 is completed.

26, 27 and 28 are the sectional view, top view and bottom view of the heat conduction plate 74 respectively, in which the edge of the heat conduction plate 74 has been separated from the supporting frame and/or adjacent heat conduction plates produced in the same batch along the cutting line.

The heat conducting plate 74 includes an adhesive layer 28 , a substrate 34 , a wire 64 , a heat sink 66 and solder resist green paint 68 , 70 . Substrate 34 includes dielectric layer 38 . The wire 64 includes the signal stud 24 , the welding pad 56 , the routing line 58 and the terminal 62 . The heat sink 66 includes the heat conduction protrusion 22 , the base 26 and the cover 60 .

After the heat conducting post 22 extends through the opening 30 and enters the through hole 40 , it is still located at the center of the opening 30 and the through hole 40 . The top of the thermally conductive post 22 is coplanar with an adjacent portion of the adhesive layer 28 above the dielectric layer 38 , and the bottom of the thermally conductive post 22 is coplanar with an adjacent portion of the adhesive layer 28 that contacts the base 26 . The heat conduction protrusion 22 maintains a flat-topped cone shape, and its tapered sidewalls make its diameter gradually decrease upwards from the base 26 toward the flat dome of the heat conduction protrusion 22 adjacent to the cover 60 .

After the signal post 24 extends through the opening 32 and enters the through hole 42 , it is still located at the center of the opening 32 and the through hole 42 . The tops of the signal studs 24 are coplanar with an adjacent portion of the adhesive layer 28 above the dielectric layer 38 , and the bottoms of the signal studs 24 are coplanar with an adjacent portion of the adhesive layer 28 and its contacts 62 . The signal stud 24 maintains a flat-topped cone shape with tapered sidewalls such that its diameter decreases upward from the terminal 62 toward the flat dome of the signal stud 24 adjacent to the routing line 58 .

The base 26 covers the heat conduction protrusion 22 and the cover 60 from below, and keeps a distance from the peripheral edge of the heat conduction plate 74 .

The cover 60 is located above the heat conduction boss 22 , adjacent to it and thermally connected. At the same time, the cover 60 covers the top of the heat conduction protrusion 22 from above, and extends laterally from the top of the heat conduction protrusion 22 . The cover 60 also touches and covers a part of the adhesive layer 28 from above. The part of the adhesive layer 28 is adjacent to the heat conduction protrusion 22 , is coplanar with the heat conduction protrusion 22 , and surrounds the heat conduction protrusion 22 laterally. Cover 60 is also coplanar with solder pad 56 .

The adhesive layer 28 is disposed on the base 26 and extends above it. The adhesive layer 28 is in contact with the gap 44 and interposed between the heat conduction protrusion 22 and the dielectric layer 38 , and fills the space between the heat conduction protrusion 22 and the dielectric layer 38 . The adhesive layer 28 is in contact with and interposed between the signal stud 24 and the dielectric layer 38 in the gap 46 , and fills the space between the signal stud 24 and the dielectric layer 38 . The adhesive layer 28 is in contact with and interposed between the base 26 and the dielectric layer 38 outside the gaps 44 and 46 , and fills the space between the base 26 and the dielectric layer 38 . The adhesive layer 28 extends laterally from the heat-conducting post 22 and crosses the terminal 62, overlaps the terminal 62, and covers a part of the base 26 outside the periphery of the heat-conducting post 22 from above, and covers and surrounds the heat-conducting post 22 along the side direction. And the signal boss 24. The adhesive layer 28 also fills most of the space between the substrate 34 and the heat sink 66 . At this time, the adhesive layer 28 is solidified.

The substrate 34 is disposed on and in contact with the adhesive layer 28 . In addition, the substrate 34 extends above the underlying adhesive layer 28 and extends above the base 26 . Conductive layer 36 (and pads 56 and routing lines 58 ) contact and extend over dielectric layer 38 , and dielectric layer 38 contacts and is interposed between adhesive layer 28 and conductive layer 36 .

The heat conducting stud 22 and the signal stud 24 have the same thickness and are coplanar with each other. Base 26 and terminal 62 have the same thickness and are coplanar with each other. In addition, tops and bottoms of the heat conduction protrusions 22 and the signal protrusions 24 are coplanar with the adhesive layer 28 .

The heat conducting post 22 , the signal post 24 , the base 26 , the cover 60 and the terminal 62 are all kept at a distance from the substrate 34 . Therefore, the substrate 34 and the heat sink 66 are mechanically connected and electrically isolated from each other.

After the heat conducting plate 74 produced in the same batch is cut, the adhesive layer 28 , the dielectric layer 38 and the solder resist green paint 68 , 70 all extend to the vertical edge formed by cutting.

The welding pad 56 is an electrical interface tailor-made for semiconductor devices such as LED packages or semiconductor chips, which will be disposed on the cover 60 in subsequent manufacturing processes. Terminal 62 is an electrical interface tailored to the next level of assembly, such as solderable wires from a printed circuit board. The cover 60 is a thermal interface tailor-made for the semiconductor device. The base 26 is a tailor-made thermal interface for the next layer assembly (such as the aforementioned printed circuit board or a heat sink of an electronic device). In addition, the cover 60 is thermally connected to the base 26 via the heat-conducting studs 22 .

The pads 56 and the terminals 62 are offset from each other in the vertical direction, and are respectively exposed on the top surface and the bottom surface of the heat conducting plate 74 , thereby providing a vertical route between the semiconductor device and the next layer assembly.

The top surfaces of pads 56 and cover 60 are coplanar above dielectric layer 38 , and the bottom surfaces of bases 26 and terminals 62 are coplanar below adhesive layer 28 .

For ease of illustration, the wire 64 is shown as a continuous circuit trace in the cross-sectional view. However, the wire 64 generally provides horizontal signal routing in the X and Y directions at the same time, that is to say, the bonding pad 56 and the terminal 62 form a lateral displacement in the X and Y directions, and the routing line 58 constitutes a path in the X and Y directions.

The heat sink 66 can dissipate the heat energy generated by the semiconductor device subsequently disposed on the cover 60 to the next layer assembly connected to the heat conducting plate 74 . The heat energy generated by the semiconductor device flows into the cover 60 , enters the heat conduction protrusion 22 from the cover 60 , and enters the base 26 through the heat conduction protrusion 22 . Thermal energy is dissipated from the base 26 in the downward direction, for example to an underlying heat sink.

The heat conduction boss 22, the signal boss 24 and the routing line 58 of the heat conduction plate 74 are not exposed, wherein the heat conduction boss 22 is covered by the cover 60, the signal boss 24 and the routing line 58 are covered by the solder resist green paint 68, and The adhesive layer 28 is covered by solder resist green paint 68 , 70 at the same time. For the convenience of illustration, FIG. 27 shows the heat conduction bumps 22 , the signal bumps 24 , the adhesive layer 28 and the routing lines 58 with dotted lines.

The heat conducting plate 74 also includes other wires 64 , and these wires 64 are basically composed of the signal studs 24 , the pads 56 , the routing wires 58 and the terminals 62 . For ease of description, only a single wire 64 is illustrated and illustrated here. In the wire 64 , the signal stud 24 , the pad 56 and the terminal 62 generally have the same shape and size, while the routing line 58 usually adopts a different routing configuration. For example, some of the wires 64 are spaced apart from each other and electrically isolated, while some of the wires 64 cross each other or lead to the same pad 56 , routing line 58 or terminal 62 and are electrically connected to each other. Likewise, some of the pads 56 can be used to receive independent signals, while some of the pads 56 share a signal, power or ground terminal.

The thermally conductive plate 74 is applicable to LED packages having blue, green and red LED chips, where each LED chip includes an anode and a cathode, and each LED package includes corresponding anode and cathode terminals. In this example, the thermally conductive plate 74 may include six solder pads 56 and four terminals 62 so that each anode is directed from a separate solder pad 56 to a separate terminal 62 and each cathode is directed from a separate solder pad 56. A common ground terminal 62 .

Oxides and residues on exposed metal can be removed at various stages of fabrication by a simple cleaning step, such as a brief oxygen plasma cleaning step on the structure in this case. Alternatively, the present structure can be subjected to a short wet chemical cleaning step using a potassium permanganate solution. Similarly, distilled water can also be used to rinse the structure of this case to remove dirt. This cleaning step cleans the desired surface without significantly affecting or damaging the structure.

An advantage of this embodiment is that the conductor 64 does not need to be separated or divided therefrom for a sink or associated circuitry after it is formed. The junctions can be separated during the wet chemical etching step that forms the pads 56 , routing lines 58 , cover 60 and terminals 62 .

The heat conducting plate 74 may include alignment holes (not shown) formed by drilling or cutting through the adhesive layer 28 , the substrate 34 and the solder resist green paint 68 , 70 . In this way, when the heat conduction plate 74 needs to be arranged on a lower carrier in the subsequent process, the pins of the tool can be inserted into the alignment holes, so as to position the heat conduction plate 74 .

The heat conducting plate 74 can omit the cover 60 . To achieve this purpose, the patterned etch stop layer 52 can be adjusted so that the entire conductive layer 50 above the via hole 40 is exposed to the chemical etching solution used to form the bonding pad 56 and the routing line 58 . Another way of omitting the cover 60 is to not provide the conductive layer 50 .

The thermally conductive plate 74 can accommodate multiple semiconductor devices instead of only a single semiconductor device. To achieve this, the patterned etch stop layer 16 can be adjusted to define more thermally conductive bumps 22 and signal bumps 24, the adhesive layer 28 can be adjusted to include more openings 30, 32, and the substrate 34 can be adjusted to include more vias. Holes 40, 42, patterned etch stop layer 52 are adjusted to define more pads 56, routing lines 58 and cover 60, and solder resist green paint 68 is adjusted to include more openings. Devices other than terminals 62 can be shifted laterally to provide a 2x2 array of four semiconductor devices. In addition, the cross-sectional shape and height (ie, side shape) of some but not all devices can also be adjusted. For example, the solder pads 56 , the cover 60 and the terminals 62 can maintain the same side shape, while the routing lines 58 have different routing configurations.

29 , 30 and 31 are respectively a sectional view, a top view and a bottom view of a heat conduction plate 76 in an embodiment of the present invention. The heat conduction plate 76 is provided with a wire 64 on its adhesive layer 28 .

In this embodiment, the dielectric layer 38 is omitted, and the wire 64 is in contact with the adhesive layer 28 . For the sake of brevity, all relevant descriptions of the heat conducting plate 74 that are applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Likewise, components of the heat conducting plate 76 in this embodiment are similar to those of the heat conducting plate 74 , and corresponding reference numerals are used.

The heat conducting plate 76 includes the adhesive layer 28 , the wire 64 , the heat sink 66 and the solder resist green paint 68 , 70 . The wire 64 includes the signal stud 24 , the bonding pad 56 , the routing line 58 and the terminal 62 . The heat sink 66 includes the heat conduction protrusion 22 , the base 26 and the cover 60 .

The conductive layer 36 of this embodiment is thicker than that of the previous embodiment. For example, the thickness of the conductive layer 36 is increased from 30 microns in the previous embodiment to 130 microns, so that the conductive layer 36 will not bend and shake when being moved. The thicknesses of the pads 56 and the routing lines 58 are also increased accordingly, and the pads 56 and the routing lines 58 are in contact with and overlapped on the adhesive layer 28 . The thermally conductive plate 76 does not have a dielectric layer corresponding to the dielectric layer 38 .

The manufacturing method of the heat conducting plate 76 is similar to that of the heat conducting plate 74 , but proper adjustments must be made for the heat conducting studs 22 , the signal studs 24 and the conductive layer 36 . For example, the thickness of the metal plate 10 is changed from 330 microns to 280 microns, so that the heights of the heat conduction protrusions 22 and the signal protrusions 24 are reduced from 300 microns to 250 microns. This can be achieved by shortening the etch time. Then, according to the method described above, the adhesive layer 28 is arranged on the base 26, and then the conductive layer 36 is separately arranged on the adhesive layer 28; the adhesive layer 28 is heated and pressurized to make the adhesive layer 28 flow and solidify; The top surface of the structure is flattened by grinding, and then the conductive layer 50 is deposited on the top surface. Conductive layers 36, 50 are then etched to form pads 56 and routing lines 58, conductive layer 50 is etched to form a cover 60, base 26 is etched to form terminals 62, and solder resist green paint 68 is disposed on the top surface to select The solder pad 56 and the cover 60 are permanently exposed, and the solder resist green paint 70 is placed on the bottom surface of the structure to selectively expose the base 26 and the terminal 62, and finally the base 26, the solder pad 56, and the cover are covered with the contact 72. Body 60 and terminal 62 are surface treated.

32, 33 and 34 are respectively a cross-sectional view, a top view and a bottom view of a semiconductor chip assembly body 100 in an embodiment of the present invention. The semiconductor chip assembly body 100 includes a heat conducting plate 74 and an LED package with back contacts 102.

The semiconductor chip assembly 100 includes a heat conducting plate 74 , an LED package 102 and solders 104 , 106 . The LED package 102 includes an LED chip 108 , a base 110 , a bonding wire 112 , an electrical contact 114 , a thermal contact 116 and a transparent packaging material 118 . An electrode (not shown) of the LED chip 108 is electrically connected to a conductive hole (not shown) in the base 110 via a bonding wire 112 , so as to electrically connect the LED chip 108 to the electrical contact 114 . The LED chip 108 is disposed on the base 110 through a die-bonding material (not shown), so that the LED chip 108 is thermally connected and mechanically adhered to the base 110 , thereby thermally connecting the LED chip 108 to the thermal junction 116 . The base 110 is a ceramic block with low electrical conductivity and high thermal conductivity. The electrical contact 114 and the thermal contact 116 are covered on the back of the base 110 and protrude downward from the back of the base 110 .

The LED package 102 is disposed on the substrate 34 and the heat sink 66 , electrically connected to the substrate 34 , and thermally connected to the heat sink 66 . Specifically, the LED package 102 is disposed on the pad 56 and the cover 60 , overlaps the heat-conducting protrusion 22 , is electrically connected to the substrate 34 via the solder 104 , and is thermally connected to the heat sink 66 via the solder 106 . For example, the solder 104 contacts and is located between the pad 56 and the electrical contact 114 , while electrically connecting and mechanically bonding the pad 56 and the electrical contact 114 , thereby electrically connecting the LED chip 108 to the terminal 62 . Likewise, the solder 106 contacts and is located between the lid 60 and the thermal junction 116 while thermally connecting and mechanically bonding the lid 60 to the thermal junction 116 , thereby thermally connecting the LED chip 108 to the submount 26 . The welding pad 56 is provided with a nickel/gold coated metal pad to facilitate a stable combination with the solder 104, and the shape and size of the welding pad 56 are matched with the electrical contact 114, thereby improving the signal conduction from the substrate 34 to the LED package 102 . Similarly, a nickel/gold coated metal pad is provided on the cover 60 to facilitate a firm combination with the solder 106, and the shape and size of the cover 60 are matched with the thermal junction 116, thereby improving the heat dissipation from the LED package 102 to the heat sink. 66 heat transfer. As for the shape and size of the heat-conducting protrusion 22 , it is not and does not need to be designed to match the thermal junction 116 .

The transparent encapsulation material 118 is a solid, electrically insulating and protective plastic coating, which can provide environmental protection for the LED chip 108 and the bonding wire 112 such as moisture resistance and particle resistance. The LED chips 108 and the bonding wires 112 are embedded in the transparent packaging material 118 .

If it is desired to manufacture the semiconductor chip assembly body 100, a solder is deposited on the pad 56 and the cover 60, and then the contacts 114 and 116 are respectively placed on the solder above the pad 56 and the cover 60, and then the solder is returned to the solder. Solder to form the solder 104, 106 that follows.

For example, the solder paste is selectively printed on the pads 56 and the cover 60 by screen printing, and then the LED package 102 is placed on the LED package 102 in a step-and-repeat manner using a grabbing head and an automatic pattern recognition system. on the heat conducting plate 74. The grabbing head of the reflow machine places the electrical contact 114 and the thermal contact 116 on the solder paste above the solder pad 56 and the cover 60 respectively. Then heat the solder paste to reflow at a relatively low temperature (eg, 190° C.), then remove the heat source, and wait for the solder paste to cool and solidify to form hardened solder 104 , 106 . Alternatively, solder balls can be placed on the solder pads 56 and the cover 60, and then the electrical contacts 114 and thermal contacts 116 are respectively placed on the solder balls above the solder pads 56 and the cover 60, and then the solder balls are heated to make them reflow. Subsequent solders 104, 106 are formed.

Solder can initially be deposited on the thermally conductive plate 74 or the LED package 102 via coating or printing or placement techniques, so that it is positioned between the thermally conductive plate 74 and the LED package 102 , and reflowed. Solder can also be placed on the terminals 62 for use in the next layer of assembly. In addition, a conductive adhesive (such as silver-filled epoxy) or other connection medium can be used instead of solder, and the connection medium on the pad 56 , the cover 60 and the terminal 62 does not have to be the same.

The semiconductor chip assembly body 100 is a second level single crystal module.

35, 36 and 37 are respectively a sectional view, a top view and a bottom view of a semiconductor chip assembly body 200 in an embodiment of the present invention, wherein the semiconductor chip assembly body 200 includes a heat conducting plate 74 and an LED with side pins package body 202 .

In this embodiment, the LED package 202 has side leads and no back contacts. For the sake of brevity, all relevant descriptions of the semiconductor chip assembly body 100 that are applicable to this embodiment are incorporated herein, and the same descriptions will not be repeated. Similarly, the components of the assembly in this embodiment are similar to the components of the assembly 100 , and the corresponding reference numerals are used, but the base number of the codes is changed from 100 to 200. For example, LED chip 208 corresponds to LED chip 108 , submount 210 corresponds to submount 110 , and so on.

The semiconductor chip assembly body 200 includes a heat conducting plate 74 , an LED package body 202 and solders 204 , 206 . The LED package 202 includes an LED chip 208 , a base 210 , bonding wires 212 , pins 214 and a transparent packaging material 218 . The LED chip 208 is electrically connected to the pin 214 via the bonding wire 212 . The rear side of the base 210 includes a thermal contact surface 216 . In addition, the base 210 is narrower than the base 110 and has the same lateral size and shape as the thermal junction 116 . The LED chip 208 is disposed on the base 210 via a die-bonding material (not shown), so that the LED chip 208 is thermally connected and mechanically adhered to the base 210 , thereby thermally connecting the LED chip 208 to the thermal contact surface 216 . Pins 214 extend laterally from base 210 , while thermal contact surface 216 faces downward.

The LED package 202 is disposed on the substrate 34 and the heat sink 66 , electrically connected to the substrate 34 , and thermally connected to the heat sink 66 . Specifically, the LED package 202 is disposed on the pad 56 and the cover 60 , overlaps the heat-conducting protrusion 22 , is electrically connected to the substrate 34 through the solder 204 , and is thermally connected to the heat sink 66 through the solder 206 . For example, the solder 204 contacts and is located between the bonding pad 56 and the lead 214 , while electrically connecting and mechanically bonding the bonding pad 56 and the lead 214 , thereby electrically connecting the LED chip 208 to the terminal 62 . Likewise, the solder 206 contacts and is located between the cover 60 and the thermal contact surface 216 while thermally connecting and mechanically bonding the cover 60 and the thermal contact surface 216 , thereby thermally connecting the LED chip 208 to the submount 26 .

If it is desired to manufacture the semiconductor chip assembly body 200, a solder can be placed on the pad 56 and the cover 60, and then the pin 214 and the thermal contact surface 216 are placed on the solder above the pad 56 and the cover 60 respectively, and then the The solder is reflowed to form subsequent solders 204 , 206 .

The semiconductor chip assembly body 200 is a second level single crystal module.

38 , 39 and 40 are respectively a cross-sectional view, a top view and a bottom view of a semiconductor chip assembly body 300 in an embodiment of the present invention, wherein the semiconductor chip assembly body 300 includes a heat conducting plate 74 and a semiconductor chip 302 .

In this embodiment, the semiconductor device is a chip instead of a package, and the chip 302 is disposed on the heat sink 66 instead of the substrate 34 . In addition, the chip 302 is overlapped on the aforementioned heat-conducting stud 22 instead of the aforementioned substrate 34 , and the chip 302 is electrically connected to the aforementioned solder pad 56 via a bonding wire 304 , and is thermally connected to the aforementioned cover using a die-bonding material 306 Body 60.

The semiconductor chip assembly body 300 includes a heat conducting plate 74 , a chip 302 , a wire bonding 304 , a die-bonding material 306 and a packaging material 308 . The chip 302 includes a top surface 310 , a bottom surface 312 and wire bonding pads 314 . The top surface 310 is the active surface and includes the wire bonding pads 314, while the bottom surface 312 is the thermal contact surface.

The chip 302 is disposed on the heat sink 66 , electrically connected to the substrate 34 , and thermally connected to the heat sink 66 . In detail, the chip 302 is disposed on the cover 60 , located inside the periphery of the cover 60 , overlapping the heat-conducting protrusion 22 but not overlapping the substrate 34 . In addition, the chip 302 is electrically connected to the substrate 34 through the bonding wire 304 , and is thermally connected and mechanically adhered to the heat sink 66 through the die-bonding material 306 . For example, the bonding wire 304 is connected to and electrically connects the bonding pad 56 and the bonding pad 314 , thereby electrically connecting the chip 302 to the terminal 62 . Likewise, the die attach material 306 contacts and is located between the lid 60 and the thermal contact surface 312 while thermally connecting and mechanically bonding the lid 60 to the thermal contact surface 312 , thereby thermally connecting the chip 302 to the submount 26 . A nickel/silver coated metal pad is provided on the pad 56 to facilitate stable bonding with the bonding wire 304 , thereby improving signal transmission from the substrate 34 to the chip 302 . Additionally, the shape and size of the lid 60 is adapted to the thermal contact surface 312 , thereby improving heat transfer from the chip 302 to the heat sink 66 . As for the shape and size of the heat conduction protrusion 22 , it is not and does not need to be designed to match the heat contact surface 312 .

The encapsulation material 308 is a solid electrical insulating and protective plastic coating, which can provide environmental protection for the chip 302 and the bonding wire 304 against moisture and particles. The chip 302 and the bonding wire 304 are embedded in the encapsulation material 308 . In addition, if the chip 302 is an optical chip such as an LED, the packaging material 308 can be transparent. The encapsulation material 308 is transparent in FIG. 39 for convenience of illustration.

To manufacture the semiconductor chip assembly 300 , the chip 302 can be placed on the cover 60 using the die-bonding material 306 , and then the bonding pad 56 and the wire bonding pad 314 are bonded by wire bonding, and then the packaging material 308 is formed.

For example, the die-bonding material 306 is originally a silver-containing epoxy resin paste with high thermal conductivity, and is selectively printed on the cover 60 by screen printing. Chips 302 are then placed on the silver epoxy paste in a step-and-repeat manner using a pick-up head and an automated pattern recognition system. Then, the epoxy resin silver paste is heated to make it harden at a relatively low temperature (eg, 190° C.) to complete the die bonding. The bonding wire 304 is a gold wire, which is then thermally ultrasonically connected to the bonding pad 56 and the bonding pad 314 . Finally, the encapsulation material 308 is transfer molded on the structure.

The chip 302 can be electrically connected to the pad 56 through various connection media, thermally connected and mechanically adhered to the heat sink 66 by various thermal adhesives, and packaged with various packaging materials.

The semiconductor chip assembly 300 is a first level single crystal package.

The above-mentioned semiconductor chip assembly body and heat conduction plate are only illustrative examples, and the present invention can be realized through other various embodiments. In addition, the above-mentioned embodiments can be mixed and matched with each other or used with other embodiments according to design and reliability considerations. For example, the substrate may include multiple arrays of single-layer wires and multiple arrays of multi-layer wires. The heat conduction plate may include a plurality of protrusions arranged in an array for use by a plurality of semiconductor devices. In addition, the heat conduction plate may include more wires in order to cooperate with additional semiconductor devices. Likewise, the semiconductor device can be an LED package with multiple LED chips, and the heat conducting plate can include more wires to match additional LED chips. The semiconductor device and the cover can overlap the substrate and cover the heat conduction post from above.

The semiconductor device can use the heat sink alone or share the heat sink with other semiconductor devices. For example, a single semiconductor device can be disposed on the heat sink, or multiple semiconductor devices can be disposed on the heat sink. For example, four small chips arranged in a 2x2 array can be attached to the thermal bump, and the substrate can include additional wires to match the electrical connection of these chips. This approach is far more economical than disposing a tiny heat-conducting bump on each chip.

The semiconductor chip can be optical or non-optical. For example, the chip can be an LED, a solar cell, a microprocessor, a controller, or a radio frequency (RF) power amplifier. Likewise, the semiconductor package can be an LED package or a radio frequency module. Thus, the semiconductor device can be a packaged or unpackaged optical or non-optical chip. In addition, we can mechanically, electrically and thermally connect the semiconductor device to the thermally conductive plate using a variety of connection media, including soldering and using conductive and/or thermally conductive adhesives.

The heat sink can quickly, effectively and evenly dissipate the heat energy generated by the semiconductor device to the next layer of assembly without passing the heat flow through the adhesive layer, the substrate or other parts of the heat conducting plate. This allows the use of an adhesive layer with lower thermal conductivity, resulting in a significant cost reduction. The heat dissipation seat may include integrally formed heat conduction protrusions and bases, and a cover that is metallurgically and thermally connected with the heat conduction protrusions, thereby improving reliability and reducing costs. The cover can be coplanar with the pad so as to form electrical, thermal and mechanical connections with the semiconductor device. In addition, the cover body can be customized according to the semiconductor device, and the base can be customized according to the next-level assembly, thereby strengthening the thermal connection from the semiconductor device to the next-level assembly. For example, the heat conducting post can be circular on a lateral plane, the cover body can be square or rectangular in a lateral plane, and the side shape of the cover body is the same as the side shape of the thermal junction of the semiconductor device or resemblance.

The heat sink can be electrically connected to or electrically isolated from the semiconductor device and the substrate. For example, the second conductive layer on the polished surface may include a routing line extending through the adhesive layer between the substrate and the cover to electrically connect the semiconductor device to the heat sink. seat. Afterwards, the heat sink can be electrically grounded, so as to electrically ground the semiconductor device.

The heat sink can be made of copper, aluminum, copper/nickel/aluminum alloy or other heat-conducting metal structures.

The heat conducting post can be deposited on the base or integrally formed with the base. The thermally conductive post can be integrally formed with the base, thus becoming a single metal body (such as copper or aluminum). The heat-conducting post can also be integrally formed with the base, so that the interface between the two includes a single metal body (such as copper), and other metals are included elsewhere (such as the upper part of the post is solder, the lower part of the post and the base The seat is copper). The thermally conductive boss can also be integrally formed with the base, so that the interface between the two includes multiple layers of a single metal body (for example, a nickel buffer layer is provided outside an aluminum core, and a copper layer is provided on the nickel buffer layer) .

The signal stud can be deposited on the terminal or integrally formed with the terminal. The signal stud can be integrally formed with the terminal, thus becoming a single metal body (such as copper or aluminum). The signal stud can also be integrally formed with the terminal, so that the interface between the two includes a single metal body (such as copper), and other metals are included elsewhere (for example, the upper part of the stud is solder, and the lower part of the stud and the terminal are is copper). The signal stud can also be integrally formed with the terminal, so that the interface between the two includes a multi-layer single metal body (for example, a nickel buffer layer is provided outside an aluminum core, and a copper layer is provided on the nickel buffer layer).

The heat conduction post can include a flat top surface, and the top surface is coplanar with the adhesive layer. For example, the thermally conductive post can be coplanar with the adhesive layer, or the thermally conductive post can be etched after the adhesive layer is cured, so that the adhesive layer above the thermally conductive post forms a cavity. We can also selectively etch the thermally conductive post to form a cavity extending below the top surface of the thermally conductive post. In any of the above cases, the semiconductor device can be arranged on the heat conducting post and located in the cavity, and the bonding wire can extend from the semiconductor device inside the cavity to the pad outside the cavity . In this case, the semiconductor device can be an LED chip, and the LED light is focused toward the upward direction by the cavity.

The base can provide mechanical support for the substrate. For example, the pedestal prevents the substrate from warping during metal grinding, chip placement, wire bonding, and molding packaging materials. Additionally, the back of the base may include fins protruding in the downward direction. For example, a drill can be used to cut the bottom surface of the base to form lateral grooves, and these lateral grooves are fins. In this example, the thickness of the base can be 500 microns, the depth of the groove can be 300 microns, that is to say, the height of the fins can be 300 microns. The fins can increase the surface area of the base, and if the fins are exposed to the air rather than being mounted on a heat sink, the thermal conductivity of the base via convection can be improved.

The cover can be formed by a variety of deposition techniques after the adhesive layer is cured, before, during or after the formation of the solder pad and/or the terminal, including electroplating, electroless coating, evaporation and sputtering. layer or multilayer structure. The cover body can be made of the same metal material as the heat conduction protrusion, or the same metal material as the top of the heat conduction protrusion adjacent to the cover body. In addition, the cover can span the through hole and extend to the substrate, or be seated within the periphery of the through hole. Thus, the cover can contact the substrate or keep a distance from the substrate. In any of the above cases, the cover extends laterally from the top of the heat conducting post along the side direction.

The adhesive layer can provide a strong mechanical connection between the heat sink and the substrate. For example, the adhesive layer can extend laterally from the heat conducting post and cross the wire to reach the peripheral edge of the assembly, the adhesive layer can fill up the space between the heat sink and the substrate, and the adhesive layer can be a Pore-free structure with evenly distributed bond lines. The adhesive layer can also absorb the mismatch between the heat sink and the substrate due to thermal expansion. In addition, the adhesive layer can be a low cost dielectric and does not need to have high thermal conductivity. Furthermore, the adhesive layer is not easy to delaminate.

We can adjust the thickness of the adhesive layer so that the adhesive layer substantially fills the gap and substantially all of the adhesive is within the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error. Likewise, we can also adjust the thickness of the dielectric layer to achieve this effect.

The substrate can be a low-cost laminate structure and does not need to have high thermal conductivity. Additionally, the substrate may comprise a single conductive layer or multiple conductive layers. Furthermore, the substrate may comprise or consist of the conductive layer.

The conductive layer can be separately disposed on the adhesive layer. For example, the through hole may be formed on the conductive layer first, and then the conductive layer is placed on the adhesive layer, so that the conductive layer contacts the adhesive layer and is exposed toward the upward direction. At the same time, the convex A post then extends into the through hole and emerges in the upward direction through the through hole. In this example, the thickness of the conductive layer can be 100 to 200 microns, such as 125 microns, which is thick enough so that it will not bend and shake during handling, and thin enough so that patterns can be formed without excessive etching .

The conductive layer and the dielectric layer can also be disposed on the adhesive layer together. For example, the conductive layer may be disposed on the dielectric layer first, then the via hole is formed on the conductive layer and the dielectric layer, and then the conductive layer and the dielectric layer are disposed on the adhesive layer, exposing the conductive layer toward the upward direction, and making the dielectric layer contact and interposed between the conductive layer and the adhesive layer, thereby separating the conductive layer from the adhesive layer, and at the same time, the protrusion It then extends into the through hole and is exposed in the upward direction through the through hole. In this example, the thickness of the conductive layer can be 10 to 50 microns, such as 30 microns, which is thick enough to provide reliable signal transmission and thin enough to reduce weight and cost. In addition, the dielectric layer is always a part of the heat conducting plate.

The conductive layer and a carrier can also be disposed on the adhesive layer at the same time. For example, a thin film can be used to adhere the conductive layer to a carrier such as double-oriented polyethylene terephthalate film (Mylar), and then only form the through hole on the conductive layer instead of the carrier, Then the conductive layer and the carrier are arranged on the adhesive layer, the carrier covers the conductive layer, and is exposed toward the upward direction, and the film is contacted and interposed between the carrier and the conductive layer, as for the conductive layer layers are in contact with and between the film and the adhesive layer, while the studs are aligned with the through holes and are covered by the carrier from above. After the adhesive layer is cured, the film can be decomposed by ultraviolet light so as to peel off the carrier from the conductive layer, so that the conductive layer is exposed toward the upward direction, and then the conductive layer can be ground and patterned to form the conductive layer. wire. In this example, the thickness of the conductive layer can be 10 to 50 microns, such as 30 microns, which is thick enough to provide reliable signal transmission on the one hand, and thin enough to reduce weight and cost on the other hand; as for the carrier The thickness can be 300 to 500 microns, which is thick enough so that it will not bend and shake during handling, and thin enough to help reduce weight and cost. The carrier is only a temporary fixture, not a permanent part of the heat conducting plate.

The welding pad and the terminal can adopt various packaging forms according to the needs of the semiconductor device and the next layer assembly.

The top surface of the welding pad and the top surface of the cover can be coplanar, so that the soldering between the semiconductor device and the heat conducting plate can be strengthened by controlling the collapse degree of the solder balls.

The pads and the routing lines on the dielectric layer can be formed by a variety of deposition techniques, including electroplating, electroless coating, evaporation and sputtering, before or after the substrate is placed on the adhesive layer. Techniques form single or multilayer structures. For example, the pattern of the conductive layer can be formed on the substrate when the substrate is not yet disposed on the adhesive layer, or after the substrate is adhered to the protrusions and the base through the adhesive layer.

The process of performing surface treatment with the covered contact can be performed before or after forming the pad and the terminal. For example, the coating layer can be deposited on the base and the second conductive layer, and then a patterned etch stop layer is used to define the pad and the terminal and etched to make the coating layer patterned.

The wires may include additional pads, terminals, conductive vias, signal studs, routing lines, and passive devices, and may have different configurations. The wire can serve as a signal layer, a power layer or a ground layer, depending on the purpose of its corresponding semiconductor device pad. The wire may also comprise various conductive metals such as copper, gold, nickel, silver, palladium, tin, mixtures thereof and alloys thereof. The ideal composition depends not only on the nature of the external connection medium, but also on design and reliability considerations. In addition, those skilled in the art should understand that the copper used in the semiconductor chip assembly can be pure copper, but usually copper-based alloys, such as copper-zirconium (99.9% copper), copper-silver- Phosphorus-magnesium (99.7% copper) and copper-tin-iron-phosphorus (99.7% copper) to improve mechanical properties such as tensile strength and ductility.

In general, it is preferable to provide the cover, dielectric layer, solder resist green paint, covered contacts and second conductive layer on the ground surface, but in some embodiments, they can be omitted. For example, if the openings and through holes are produced by punching instead of drilling, so that the shape and size of the top of the heat-conducting post are suitable for the thermal contact surface of the semiconductor device, the cover and the through-hole can be omitted. The second conductive layer is used to reduce the cost. Likewise, the dielectric layer can be omitted to reduce cost.

The heat conduction plate may include a heat conduction hole. The heat conduction hole is kept at a distance from the protrusion, and extends outside the opening and the through hole through the dielectric layer and the adhesive layer, and is adjacent to and thermally connected to the heat conduction layer. The base and the cover are used to improve the heat dissipation effect from the cover to the base, and promote the diffusion of heat energy in the base.

The assembly in this case can provide horizontal or vertical single-layer or multi-layer signal routing.

US Patent Application No. 12/616,773 filed by Lin Wenqiang et al. on November 11, 2009: "Semiconductor chip assembly with heat sink and substrate with bosses/pedestals" discloses a horizontal single-layer signal Routing Structures Where Pads, Terminals, and Routing Lines Are Over a Dielectric Layer, the contents of this US patent application are hereby incorporated by reference.

US Patent Application No. 12/616,775 filed by Lin Wenqiang et al. on November 11, 2009: "Semiconductor chip assembly with heat sink and wires with protrusions/pedestals" discloses another horizontal single-layer Signal Routing Structures Where Pads, Terminals, and Routing Lines Are Over Adhesive Layers and No Dielectric Layer Is Provided, The contents of this US patent application are hereby incorporated by reference.

No. 12/557,540 U.S. patent application filed by Wang Jiazhong et al. on September 11, 2009: "Semiconductor chip assembly with heat sink with boss/pedestal and horizontal signal routing" discloses a multi-horizontal The structure of layer signal routing, wherein the pads and terminals above the dielectric layer are electrically connected by using the first and second conductive holes passing through the dielectric layer and the routing lines below the dielectric layer. This US patent The content of the application is hereby incorporated by reference.

No. 12/557,541 U.S. patent application filed by Wang Jiazhong et al. on September 11, 2009: "Semiconductor chip assembly with heat sink with boss/pedestal and vertical signal routing" discloses a vertical The structure of multi-layer signal routing, wherein the pads above the dielectric layer and the terminals below the adhesive layer use the first conductive holes passing through the dielectric layer, the routing lines below the dielectric layer and the terminals passing through the adhesive layer The second conductive via makes the electrical connection, the content of this US patent application is hereby incorporated by reference.

The operating format of the heat conduction plate can be single or multiple heat conduction plates, depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a single metal plate, a single adhesive layer, a single substrate, a single top solder mask green paint, and a single bottom solder mask green paint can be used to batch-manufacture multiple thermally conductive plates at the same time, and then separate them. Similarly, for each heat conduction plate in the same batch, we can also use a single metal plate, a single adhesive layer, a single substrate, a single top solder mask green paint and a single bottom solder mask green paint to manufacture multiple groups at the same time. Heat sinks and wires used in semiconductor devices.

For example, a plurality of grooves can be etched on a metal plate to form the base, a plurality of heat conduction bumps and a plurality of signal bumps; then an uncured adhesive layer with openings corresponding to the bumps is placed on the on the base, so that each protrusion extends through a corresponding opening; then a substrate (which has a single conductive layer, a single dielectric layer, and a through hole corresponding to the protrusion) is disposed on the adhesive layer, so that each protrusion extends through a corresponding opening and enters a corresponding through hole; then the base and the substrate are abutted against each other by using a pressure table, forcing the adhesive layer to enter the through hole and intervene between the protrusions and the gap between the substrate; then solidify the adhesive layer, and then grind the protrusion, the adhesive layer and the first conductive layer to form a top surface; then coat the second conductive layer on the protrusion, On the adhesive layer and the first conductive layer; then etch the first and second conductive layers to form a plurality of pads and routing lines respectively corresponding to the signal bumps, and etch the second conductive layer to form a plurality of respectively Corresponding to the cover body of the heat-conducting post, and etching the base to form a plurality of bases corresponding to the heat-conducting post and a plurality of terminals corresponding to the signal post; and then setting the top solder resist green paint on the structure body, and make the top solder resist green paint patterned, so as to expose the solder pads and the cover, and set the bottom solder resist green paint on the structure, so that the bottom solder resist green paint produces patterns, In order to expose the base and the terminal; then surface-treat the base, the pad, the terminal and the cover with covered contacts; finally cut at a proper position on the peripheral edge of the heat conduction plate Or cleave the substrate, the adhesive layer and the solder resist green paint to separate individual heat conducting plates from each other.

The operating format of the semiconductor chip assembly can be a single assembly or multiple assemblies, depending on the manufacturing design. For example, a single assembly can be fabricated separately. Alternatively, multiple assemblies can be produced in batches at the same time, and then the heat conducting plates are separated one by one. Likewise, a plurality of semiconductor devices can also be electrically, thermally and mechanically connected to each heat conducting plate in mass production.

For example, a plurality of solder paste parts may be deposited on a plurality of solder pads and a cover, respectively, and then a plurality of LED packages may be respectively placed on the solder paste parts, and then the solder paste parts may be heated simultaneously to make them return to the solder paste parts. Solder, harden and form multiple welds, and then separate the heat transfer plates one by one.

In another example, a plurality of die-bonding materials are respectively deposited on a plurality of lids, and then a plurality of chips are respectively placed on the die-bonding materials, and then the die-bonding materials are simultaneously heated to harden and A plurality of die-bonding is formed, and then the chips are wire-bonded to corresponding pads, and then a corresponding packaging material is formed on the chips and wire-bonded, and finally the heat conducting plates are separated one by one.

We can separate the thermal plates from each other in a single step or in multiple steps. For example, a plurality of heat conducting plates can be made into a flat plate in batches, and then a plurality of semiconductor devices are arranged on the flat plate, and then a plurality of semiconductor chip assemblies formed by the flat plate are separated one by one. Alternatively, a plurality of heat conduction plates can be made into a flat plate in batches, and then the plurality of heat conduction plates formed by the plate are cut into a plurality of heat conduction strips, and then a plurality of semiconductor devices are respectively arranged on the heat conduction strips , and finally separate the plurality of semiconductor chip assemblies formed by the heat-conducting slats into individuals. Additionally, mechanical cutting, laser cutting, cleaving, or other suitable techniques may be utilized in dividing the thermally conductive plate.

As used herein, the term "adjacent" means that the devices are integrally formed (forming a single body) or are in contact with each other (without spacing or separation from each other). For example, the thermally conductive post is adjacent to the base, regardless of the additive or subtractive method used to form the thermally conductive post.

The term "overlapping" means lying above and extending within the perimeter of an underlying device. "Overlapping" includes extending inside, outside, or within the perimeter. For example, the semiconductor device overlaps the heat-conducting post because an imaginary vertical line can run through the semiconductor device and the heat-conducting post at the same time, regardless of whether there is another imaginary vertical line between the semiconductor device and the heat-conducting post. No matter whether there is another imaginary vertical line that only runs through the semiconductor device but not through the heat-conducting post (that is, it is located outside the periphery of the heat-conducting post). Likewise, the adhesive layer overlaps the base and is overlapped by the welding pad, and the base is overlapped by the heat-conducting bump. Likewise, the heat-conducting protrusion overlaps the base and is located within its periphery. Also, "overlapping" is synonymous with "on top", and "overlapped" is synonymous with "below".

The term "contact" means direct contact. For example, the dielectric layer is in contact with the pad but not in contact with the heat-conducting stud or the base.

The term "covering" means completely covering from above, from below and/or from the sides. For example, the base covers the heat conduction post from below, but the heat conduction post does not cover the base from above.

The word "layer" includes a layer with a pattern or without a pattern. For example, when the substrate is placed on the adhesive layer, the conductive layer can be a blank plate without pattern on the dielectric layer; and when the semiconductor device is placed on the heat sink, the conductive layer can be the dielectric layer. A circuit pattern with spaced wires on the electrical layer. Additionally, a "layer" may contain multiple overlapping layers.

The term "pad" when used in conjunction with the wire means a connection area for connecting and/or engaging an external connection medium (such as solder or bond wire) that electrically connects the wire to the semiconductor device.

The term "terminal" when used in conjunction with the wire means a connection area that contacts and/or engages an external connection medium (such as solder or wire bonding) that electrically connects the wire to the An external device (such as a printed circuit board or a wire connected thereto) associated with the next-level assembly.

The term "cover" when used in conjunction with the heat sink refers to a contact area for connecting and/or engaging an external connection medium (such as solder or thermally conductive adhesive) that can heat the heat sink. connected to the semiconductor device.

The terms "opening" and "through hole" mean a through hole. For example, when the heat-conducting protrusion is inserted into the opening of the adhesive layer, the heat-conducting protrusion is exposed to the adhesive layer in an upward direction. Likewise, when the heat conduction protrusion is inserted into the through hole of the substrate, the heat conduction protrusion is exposed to the substrate along an upward direction.

The term "insertion" refers to relative movement between devices. For example, "insert the heat conduction post into the through hole" includes: the heat conduction post is fixed and moves from the substrate to the base; the substrate is fixed and the heat conduction post moves to the substrate; and The thermally conductive protrusion and the substrate are in close contact with each other. For another example, "insert (or extend) the heat conduction protrusion into the through hole" includes: the heat conduction protrusion penetrates (into and out of) the through hole; and the heat conduction protrusion is inserted but not penetrated (into but not pierced) the through hole.

The phrase "close to each other" also refers to relative movement between devices. For example, "the base and the substrate are in close contact with each other" includes: the base is fixed and moved from the substrate to the base; the substrate is fixed and moved from the base to the substrate; and the base close to the substrate.

The term "alignment" refers to the relative position between devices. For example, when the adhesive layer has been disposed on the base, the substrate has been disposed on the adhesive layer, the heat conduction post has been inserted and aligned with the opening, and the through hole has been aligned with the opening, no matter whether the heat conduction The protrusions are inserted into the through holes or located below the through holes with a distance therefrom, and the heat conduction protrusions are all aligned with the through holes.

The term "disposed on" includes both contact and non-contact with a single or multiple supporting devices. For example, the semiconductor device is disposed on the heat sink, no matter whether the semiconductor device actually touches the heat sink or is separated from the heat sink by a die-bonding material. Likewise, the semiconductor device is disposed on the heat sink, no matter whether the semiconductor device is only disposed on the heat sink or simultaneously disposed on the heat sink and the substrate.

The phrase "adhesive layer...in the notch" means the adhesive layer located in the notch. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer in the gap extends across the dielectric layer. Similarly, "the adhesive layer is in contact with the notch and is between the thermally conductive post and the dielectric layer" means that the adhesive layer in the notch is in contact with and is between the thermally conductive post on the inner wall of the notch and the dielectric layer. Between the dielectric layer on the outer wall of the notch.

The term "above" means extending upward and includes adjoining and non-adjacent devices as well as overlapping and non-overlapping devices. For example, the heat conduction post extends above the base, and at the same time abuts on, overlaps with, and protrudes from the base. Likewise, the heat-conducting stud extends above the dielectric layer, even though the heat-conducting stud is not adjacent to or overlapped with the dielectric layer.

The term "beneath" means extending downward and includes adjoining and non-adjacent devices as well as overlapping and non-overlapping devices. For example, the base extends below the heat conduction protrusion, adjoins the heat conduction protrusion, is overlapped by the heat conduction protrusion, and protrudes from the heat conduction protrusion. Likewise, the heat-conducting protrusion extends below the dielectric layer, even though the heat-conducting protrusion is not adjacent to or overlapped by the dielectric layer.

The so-called "upward" and "downward" vertical directions do not depend on the orientation of the semiconductor chip assembly body (or the heat conducting plate), and those familiar with the art can easily understand the actual directions. For example, the heat conduction protrusion vertically extends above the base along the upward direction, and the adhesive layer vertically extends downward under the pad, which is related to whether the assembly is inverted and/or whether it is placed on a Nothing to do with the heatsink. Likewise, the base extends “laterally” from the heat conducting post along a lateral plane, regardless of whether the assembly is inverted, rotated or tilted. Thus, the upward and downward directions are opposite each other and perpendicular to the side directions, and furthermore, the laterally aligned devices are coplanar with each other in a lateral plane perpendicular to the upward and downward directions.

The semiconductor chip assembly of the present invention has several advantages. This group has high reliability, low price and is very suitable for mass production. This group is especially suitable for high-power semiconductor devices that are prone to high heat and require excellent heat dissipation to operate effectively and reliably, such as LED packages, large semiconductor chips, and multiple small semiconductor devices that are used simultaneously (such as arrays) multiple small semiconductor chips).

The manufacturing process of this case is highly applicable, and combines various mature electrical connection, thermal connection and mechanical connection technologies in a unique and progressive way. In addition, the manufacturing process in this case can be implemented without expensive tools. Therefore, this manufacturing process can greatly improve the yield, yield, performance and cost-effectiveness of existing packaging technologies. Furthermore, the assembly in this case is very suitable for copper chips and lead-free environmental protection requirements.

The embodiments described here are for the purpose of illustration, and the existing devices or steps involved in the art are either simplified or omitted to avoid obscuring the characteristics of the present invention. Likewise, for clarity of the drawings, repeated or unnecessary components and reference numerals may be omitted in the drawings.

Variations and modifications to the embodiments described herein will readily occur to those skilled in the art. For example, the aforementioned materials, dimensions, shapes, sizes, contents of steps and sequence of steps are just examples. Such changes, modifications and equivalents may be made by the above persons without departing from the spirit and scope of the invention, which is defined by the claims.

Claims (50)

1. semiconductor chip group body, it is characterized in that: this semiconductor chip group body comprises at least:

Semiconductor device;

One adhesion layer, it has first opening and second opening at least;

One radiating seat, it comprises a heat conduction projection and a pedestal at least, wherein this heat conduction projection be in abutting connection with this pedestal and along one upward to extending this pedestal top, this pedestal is to extend this heat conduction projection below to opposite downward direction along one upward with this, and along extending laterally from this heat conduction projection perpendicular to this side surface direction that upwards reaches downward direction; And

One lead, it comprises a weld pad, a terminal and a signal projection at least, and wherein this signal projection is to extend this weld pad below and this terminal top, and the conductive path between this weld pad and this terminal comprises this signal projection;

Wherein this semiconductor device is to be positioned at this heat conduction projection top and to be overlapped in this heat conduction projection, this semiconductor device is to be electrically connected to this weld pad, thereby be electrically connected to this terminal, and this semiconductor device is to be thermally coupled to this heat conduction projection, thereby is thermally coupled to this pedestal;

Wherein this adhesion layer is to be arranged on this pedestal, extend this pedestal top, and this heat conduction projection extends laterally to this terminal or crosses this terminal certainly;

Wherein this weld pad is to extend this adhesion layer top, and this terminal then extends this adhesion layer below; And

Wherein this heat conduction projection extends into this first opening, and this signal projection extends into this second opening, and described projection has same thickness and copline each other, and this pedestal and this terminal have same thickness and copline each other.

2. semiconductor chip group body according to claim 1 is characterized in that: this semiconductor device is one to comprise the LED packaging body of led chip.

3. semiconductor chip group body according to claim 2 is characterized in that: this LED packaging body is to utilize one first scolding tin to be electrically connected to this weld pad, and utilizes one second scolding tin to be thermally coupled to this radiating seat.

4. semiconductor chip group body according to claim 1 is characterized in that: this semiconductor device is the semiconductor chip.

5. semiconductor chip group body according to claim 4 is characterized in that: this chip is to utilize a routing to be electrically connected to this weld pad, and utilizes a solid brilliant material to be thermally coupled to this radiating seat.

6. semiconductor chip group body according to claim 1 is characterized in that: this adhesion layer contacts described projection, this pedestal, this weld pad and this terminal.

7. semiconductor chip group body according to claim 1 is characterized in that: this adhesion layer is in described side surface direction covering and around described projection.

8. semiconductor chip group body according to claim 1, it is characterized in that: this adhesion layer similar shape is coated on the sidewall of described projection.

9. semiconductor chip group body according to claim 1 is characterized in that: the top of this adhesion layer and described projection and bottom copline.

10. semiconductor chip group body according to claim 1 is characterized in that: this adhesion layer extends laterally and crosses this terminal from this heat conduction projection.

11. semiconductor chip group body according to claim 1 is characterized in that: this adhesion layer extends to the peripheral edge of this semiconductor chip group body.

12. semiconductor chip group body according to claim 1 is characterized in that: this heat conduction projection is integrally formed with this pedestal, this signal projection is then integrally formed with this terminal.

13. semiconductor chip group body according to claim 1, it is characterized in that: this heat conduction projection is a flat-top awl cylindricality, flat top to this heat conduction projection is to be upwards to successively decrease to its diameter from this pedestal, and this signal projection is a flat-top awl cylindricality, and the flat top to this signal projection is to be upwards to successively decrease to its diameter from this terminal.

14. semiconductor chip group body according to claim 1 is characterized in that: this pedestal covers this heat conduction projection from the below, support this adhesion layer, and keeps at a distance with the peripheral edge of this semiconductor chip group body.

15. semiconductor chip group body according to claim 1 is characterized in that: this lead is to keep at a distance with this radiating seat, and this weld pad, this terminal then contact this adhesion layer with this signal projection.

16. semiconductor chip group body according to claim 1 is characterized in that: this terminal is in abutting connection with this signal projection, extends this signal projection below, and extends laterally from this signal projection along described side surface direction.

17. semiconductor chip group body according to claim 1, it is characterized in that: this radiating seat comprises a lid at least, this lid is positioned at an over top of this heat conduction projection, this top in abutting connection with this heat conduction projection, and cover this top of this heat conduction projection from the top, extend laterally along described side surface direction this top simultaneously from this heat conduction projection.

18. semiconductor chip group body according to claim 17 is characterized in that: this lid and this weld pad are copline in this adhesion layer top.

19. semiconductor chip group body according to claim 17 is characterized in that: this lid is rectangle or square, this top of this heat conduction projection then is circular.

20. semiconductor chip group body according to claim 17, it is characterized in that: the size of this lid and shape are to cooperate the thermo-contact surface of this semiconductor device and design, and the size at this top of this heat conduction projection and shape then are not to cooperate this thermo-contact surface of this semiconductor device and design.

21. a semiconductor chip group body is characterized in that: this semiconductor chip group body comprises at least:

Semiconductor device;

One adhesion layer, it has first opening and second opening at least;

One radiating seat, it comprises a heat conduction projection and a pedestal at least, wherein this heat conduction projection is in abutting connection with this pedestal and integrally formed with this pedestal, and this heat conduction projection is upward to extending this pedestal top along one, this pedestal is to extend this heat conduction projection below to opposite downward direction along one upward with this, and along extending laterally from this heat conduction projection perpendicular to this side surface direction that upwards reaches downward direction; And

One lead, it comprises a weld pad, a terminal, a route line and a signal projection at least, wherein this route line is in abutting connection with this weld pad, this signal projection is then in abutting connection with this route line and this terminal, and extend below this weld pad and this route line, extend this terminal top simultaneously, and the conductive path between this weld pad and this terminal comprises this route line and this signal projection;

Wherein this semiconductor device is to be arranged on this radiating seat, be overlapped in this heat conduction projection but be not overlapped in this signal projection, this semiconductor device is to be electrically connected to this weld pad, thereby be electrically connected to this terminal, and this semiconductor device is to be thermally coupled to this heat conduction projection, thereby is thermally coupled to this pedestal;

Wherein this adhesion layer is to be arranged on this pedestal, extends this pedestal top, and in described side surface direction covering and around described projection, extends to the peripheral edge of this semiconductor chip group body simultaneously;

Wherein this weld pad extends this adhesion layer top; And

Wherein this heat conduction projection extends into this first opening, this signal projection extends into this second opening, described projection has same thickness, copline each other, and extend through this adhesion layer, this pedestal and this terminal have same thickness, each other copline, and extend this adhesion layer below, the top of described projection and bottom are and this adhesion layer copline.

22. semiconductor chip group body according to claim 21, it is characterized in that: this semiconductor device is the semiconductor chip, and be to utilize a solid brilliant material to be arranged on this radiating seat, and utilize a routing to be electrically connected to this weld pad, utilize simultaneously and should be thermally coupled to this radiating seat by solid brilliant material.

23. semiconductor chip group body according to claim 21 is characterized in that: this adhesion layer contacts described projection, this pedestal, this weld pad, this terminal and this route line.

24. semiconductor chip group body according to claim 21, it is characterized in that: this heat conduction projection is a flat-top awl cylindricality, flat top to this heat conduction projection is to be upwards to successively decrease to its diameter from this pedestal, this top of this heat conduction projection is circular, one lid is to be arranged on this top of this heat conduction projection, be positioned at this over top of this heat conduction projection, this top in abutting connection with this heat conduction projection, and cover this top of this heat conduction projection from the top, extend laterally along described side surface direction this top from this heat conduction projection simultaneously, this lid is rectangle or square.

25. semiconductor chip group body according to claim 24 is characterized in that: this lid and this weld pad are copline in this adhesion layer top.

26. a semiconductor chip group body is characterized in that: this semiconductor chip group body comprises at least:

Semiconductor device;

One adhesion layer, it has first opening and second opening at least;

One radiating seat, it comprises a heat conduction projection and a pedestal at least, wherein this heat conduction projection is in abutting connection with this pedestal, and along one upward to extending this pedestal top, this pedestal is to extend this heat conduction projection below to opposite downward direction along one upward with this, and along extending laterally from this heat conduction projection perpendicular to this side surface direction that upwards reaches downward direction;

One substrate, it comprises a weld pad and a dielectric layer at least, and wherein first and second through hole extends through this substrate; And

One lead, it comprises this weld pad, a terminal and a signal projection at least, and wherein this signal projection is to extend this weld pad below and this terminal top, and the conductive path between this weld pad and this terminal comprises this signal projection;

Wherein this semiconductor device is to be positioned at this heat conduction projection top and to be overlapped in this heat conduction projection, this semiconductor device is to be electrically connected to this weld pad, thereby be electrically connected to this terminal, and this semiconductor device is to be thermally coupled to this heat conduction projection, thereby is thermally coupled to this pedestal;

Wherein this adhesion layer is to be arranged on this pedestal, extend this pedestal top, extend into first breach of this first through hole interior between this heat conduction projection and this substrate, extend into second breach of this second through hole interior between this signal projection and this substrate, and in described breach, extend across this dielectric layer, this adhesion layer extends laterally to this terminal or crosses this terminal from this heat conduction projection, and this adhesion layer is between between this heat conduction projection and this dielectric layer, between this signal projection and this dielectric layer and between this pedestal and this dielectric layer;

Wherein this substrate is to be arranged on this adhesion layer, and extends this pedestal top;

Wherein this weld pad is to extend this dielectric layer top, and this terminal then extends this adhesion layer below; And

Wherein this heat conduction projection extends into this first opening and this first through hole, and this signal projection extends into this second opening and this second through hole, and described projection has same thickness and copline each other, and this pedestal and this terminal have same thickness and copline each other.

27. semiconductor chip group body according to claim 26 is characterized in that: this semiconductor device is one to comprise the LED packaging body of led chip.

28. semiconductor chip group body according to claim 27 is characterized in that: this LED packaging body is to utilize one first scolding tin to be electrically connected to this weld pad, and utilizes one second scolding tin to be thermally coupled to this radiating seat.

29. semiconductor chip group body according to claim 26 is characterized in that: this semiconductor device is the semiconductor chip.

30. semiconductor chip group body according to claim 29 is characterized in that: this chip is to utilize a routing to be electrically connected to this weld pad, and utilizes a solid brilliant material to be thermally coupled to this radiating seat.

31. semiconductor chip group body according to claim 26, it is characterized in that: this adhesion layer contacts this heat conduction projection and this dielectric layer in this first breach, and in this second breach, contact this signal projection and this dielectric layer, simultaneously in described this pedestal of breach outer contacting, this terminal and this dielectric layer.

32. semiconductor chip group body according to claim 26 is characterized in that: this adhesion layer is in described side surface direction covering and around described projection.

33. semiconductor chip group body according to claim 26, it is characterized in that: this adhesion layer similar shape is coated on the sidewall of described projection.

34. semiconductor chip group body according to claim 26 is characterized in that: the top of this adhesion layer and described projection and bottom copline.

35. semiconductor chip group body according to claim 26 is characterized in that: this adhesion layer extends laterally and crosses this terminal from this heat conduction projection.

36. semiconductor chip group body according to claim 26 is characterized in that: this adhesion layer extends to the peripheral edge of this semiconductor chip group body.

37. semiconductor chip group body according to claim 26 is characterized in that: this heat conduction projection is integrally formed with this pedestal, this signal projection is then integrally formed with this terminal.

38. semiconductor chip group body according to claim 26, it is characterized in that: this heat conduction projection is a flat-top awl cylindricality, flat top to this heat conduction projection is to be upwards to successively decrease to its diameter from this pedestal, and this signal projection is a flat-top awl cylindricality, and the flat top to this signal projection is to be upwards to successively decrease to its diameter from this terminal.

39. semiconductor chip group body according to claim 26 is characterized in that: this pedestal covers this heat conduction projection from the below, support this substrate, and keeps at a distance with the peripheral edge of this semiconductor chip group body.

40. semiconductor chip group body according to claim 26 is characterized in that: this lead is to keep at a distance with this radiating seat, and this weld pad contacts this dielectric layer, this adhesion layer of this termination contact, and this signal projection then contacts this adhesion layer and this dielectric layer.

41. semiconductor chip group body according to claim 26 is characterized in that: this terminal is in abutting connection with this signal projection, extends this signal projection below, and extends laterally from this signal projection along described side surface direction.

42. semiconductor chip group body according to claim 26, it is characterized in that: this radiating seat comprises a lid at least, this lid is positioned at an over top of this heat conduction projection, this top in abutting connection with this heat conduction projection, and cover this top of this heat conduction projection from the top, extend laterally along described side surface direction this top simultaneously from this heat conduction projection.

43. according to the described semiconductor chip group of claim 42 body, it is characterized in that: this lid and this weld pad are copline in this dielectric layer top.

44. according to the described semiconductor chip group of claim 42 body, it is characterized in that: this lid is rectangle or square, this top of this heat conduction projection then is circular.

45. according to the described semiconductor chip group of claim 42 body, it is characterized in that: the size of this lid and shape are to cooperate the thermo-contact surface of this semiconductor device and design, and the size at this top of this heat conduction projection and shape then are not to cooperate this thermo-contact surface of this semiconductor device and design.

46. a semiconductor chip group body is characterized in that: this semiconductor chip group body comprises at least:

Semiconductor device;

One adhesion layer, it has first opening and second opening at least;

One radiating seat, it comprises a heat conduction projection at least, one pedestal and a lid, wherein this heat conduction projection is in abutting connection with this pedestal and integrally formed with this pedestal, this heat conduction projection is upward to extending this pedestal top along one, and provide hot link for this pedestal and this lid, this pedestal is to extend this heat conduction projection below to opposite downward direction along one upward with this, and along extending laterally from this heat conduction projection perpendicular to this side surface direction that upwards reaches downward direction, this lid is positioned at an over top of this heat conduction projection, this top in abutting connection with this heat conduction projection, and cover this top of this heat conduction projection from the top, extend laterally along described side surface direction this top simultaneously from this heat conduction projection;

One substrate, it comprises a weld pad, a route line and a dielectric layer at least, and wherein first and second through hole extends through this substrate; And

One lead, it comprises this weld pad, this route line, a terminal and a signal projection at least, wherein this route line is in abutting connection with this weld pad, this signal projection is then in abutting connection with this route line and this terminal, and extend below this weld pad and this route line, extend this terminal top simultaneously, and the conductive path between this weld pad and this terminal comprises this route line and this signal projection;

Wherein this semiconductor device is to be arranged on this lid, be overlapped in this heat conduction projection but be not overlapped in this signal projection, this semiconductor device is to be electrically connected to this weld pad, thereby is electrically connected to this terminal, and this semiconductor device is to be thermally coupled to this lid, thereby is thermally coupled to this pedestal;

Wherein this adhesion layer is to be arranged on this pedestal, extend this pedestal top, extend into first breach of this first through hole interior between this heat conduction projection and this substrate, extend into second breach of this second through hole interior between this signal projection and this substrate, and in described breach, extend across this dielectric layer, this adhesion layer is between this heat conduction projection and this dielectric layer, between this signal projection and this dielectric layer and between this pedestal and this dielectric layer, this adhesion layer covers and around described projection in described side surface direction, and extends to the peripheral edge of this semiconductor chip group body;

Wherein this weld pad extends this dielectric layer top; And

Wherein this heat conduction projection extends into this first opening and this first through hole, this signal projection extends into this second opening and this second through hole, described projection has same thickness, copline each other, and extend through this adhesion layer and this dielectric layer, this pedestal and this terminal have same thickness, each other copline, and extend this adhesion layer and this dielectric layer below, the top of described projection and bottom are and this adhesion layer copline.

47. according to the described semiconductor chip group of claim 46 body, it is characterized in that: this semiconductor device is the semiconductor chip, and be to utilize a solid brilliant material to be arranged on this lid, and utilize a routing to be electrically connected to this weld pad, utilize simultaneously and should be thermally coupled to this lid by solid brilliant material.

48. according to the described semiconductor chip group of claim 46 body, it is characterized in that: this adhesion layer contacts described projection and this dielectric layer in described breach, and in described this pedestal of breach outer contacting, this terminal and this dielectric layer, this dielectric layer then contacts this weld pad and this route line, and keeps at a distance with described projection, this pedestal and this terminal.

49. according to the described semiconductor chip group of claim 46 body, it is characterized in that: this heat conduction projection is a flat-top awl cylindricality, its diameter is to be upwards to successively decrease from this pedestal to this lid, this signal projection is a flat-top awl cylindricality, its diameter is to be upwards to successively decrease from this terminal to this route line, this top of this heat conduction projection is circular, and this lid then is rectangle or square.

50. according to the described semiconductor chip group of claim 46 body, it is characterized in that: this lid and this weld pad are copline in this dielectric layer top.

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