CN102117877B - Semiconductor chip assembly - Google Patents

Semiconductor chip assembly Download PDF

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Publication number
CN102117877B
CN102117877B CN2009103127855A CN200910312785A CN102117877B CN 102117877 B CN102117877 B CN 102117877B CN 2009103127855 A CN2009103127855 A CN 2009103127855A CN 200910312785 A CN200910312785 A CN 200910312785A CN 102117877 B CN102117877 B CN 102117877B
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China
Prior art keywords
projection
pedestal
semiconductor chip
substrate
layer
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Expired - Fee Related
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CN2009103127855A
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Chinese (zh)
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CN102117877A (en
Inventor
王家忠
林文强
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Yuqiao Semiconductor Co Ltd
Bridge Semiconductor Corp
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Yuqiao Semiconductor Co Ltd
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Priority to CN2009103127855A priority Critical patent/CN102117877B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor chip assembly. The semiconductor chip assembly at least comprises a semiconductor component, a radiating seat, a substrate and an adhesive layer, wherein the semiconductor component is electrically connected to the substrate and is thermally connected to the radiating seat; the radiating seat at least comprises a convex column and a base; the convex column extends upwards to pass through an opening of the adhesive layer and enter a through hole of the substrate; the base laterally extends and supports the substrate; the adhesive layer extends between the convex column and the substrate and between the base and the substrate; and the substrate at least comprises a first conductive layer, a second conductive layer and a dielectric layer which is positioned between the first conductive layer and the second conductive layer. Thus, the assembly can provide a vertical signal route between a bonding pad above the first conductive layer and a terminal below the adhesive layer.

Description

Semiconductor chip group body
Technical field
The present invention relates to a kind of semiconductor chip group body, refer to a kind of high power semiconductor component that is applicable to especially, refer in particular to the semiconductor chip group body of forming by semiconductor subassembly, substrate, adhesion layer and radiating seat.
Background technology
Semiconductor subassemblies such as semiconductor chip such as through encapsulation and un-encapsulated can provide high voltage, high-frequency and dynamical application; Those are applied as the execution specific function, so the power of required consumption is very high, right power heal height then semiconductor subassembly give birth to heat the more.In addition, behind packaging density raising and dimension reduction, the surface area that can supply dispel the heat also dwindles, and more causes the heat production aggravation.
Semiconductor subassembly be prone to produce problems such as performance decay and shortening in useful life under high-temperature operation, even fault immediately.High heat not only influences chip usefulness, also maybe because of thermal expansion do not match to chip and arround assembly produce the thermal stress effect.Therefore, must make the rapid efficiently radiates heat of chip can guarantee its operating efficiency and reliability.Article one, the high-termal conductivity path is usually with thermal energy conduction and be dissipated into the die pad bigger zone of a surface area than chip or chip place.
Light-emitting diode (Light Emitting Diode, LED) the recent alternative source of light that generally becomes incandescent source, fluorescence light source and halogen light source.LED can be applications such as medical treatment, military affairs, signboard, signal, aviation, navigation, vehicle, portable device, commercialization and household's illumination high-energy source efficient and illumination for a long time cheaply is provided.For example, LED can be equipment such as light fixture, flashlight, headlight, searchlight, traffic signal light and display light source is provided.
High-power die among the LED also produces great amount of heat energy when high brightness output is provided.Yet under high-temperature operation, LED can take place that colour cast, brightness reduce, shorten useful life and problem such as fault immediately.In addition, LED has its restriction aspect heat radiation, and then influences its light output and reliability.Therefore, LED especially highlights the demand of market for the high-power die with great heat radiation effect.
The LED packaging body comprises a led chip, a pedestal, an electric contact and a hot junction usually.Wherein this heat susceptor is linked to this led chip and in order to support this led chip; This electric contact is the anode and the negative electrode of electrically connect to this led chip then; And this hot junction is linked to this led chip via this heat susceptor, and its below carrier can fully dispel the heat to prevent this led chip overheated.
The research and development that industry actively drops into high-power die packaging body and heat-conducting plate with various designs and manufacturing technology are in the hope of satisfying performance requirements in this environment that extremely cost is competed.
Plastics ball bar array (Plastic Ball Grid Array, PBGA) encapsulation be that a chip and a lamination substrate are wrapped in the plastic casing, and then with the tin ball attach to a printed circuit board (PCB) (Printed Circuit Board, PCB) on.Wherein this laminated substrate comprises the dielectric layer that usually is made up of glass fiber, and the heat energy that produces of this chip can reach the tin ball through plastics and dielectric layer thus, and then reaches this printed circuit board (PCB).Yet because the thermal conductivity of plastics and dielectric layer is low, so the radiating effect of PBGA is not good.
(Quad Flat No-lead, QFN) encapsulation is chip to be arranged on one be welded on the copper die pad of printed circuit board (PCB) to quad flat non-pin.The heat energy that this chip produces can reach this printed circuit board (PCB) through die pad thus.Yet,, make the QFN encapsulation can't be applicable to high I/O (I/O) chip or passive component because the routing capabilities of its lead frame intermediary layer is limited.
Heat-conducting plate is that semiconductor subassembly provides functions such as electrical route, heat management and mechanical support.Heat-conducting plate comprise usually one be used for the signal route substrate, a radiating seat or the heat abstractor of heat abstraction function, the weld pad that a power supply property is linked to semiconductor subassembly are provided, and a power supply property is linked to down the terminal of one deck group body.Wherein this substrate can be one have single or multiple lift routing circuit system and an one layer or more dielectric layer laminar structure; This radiating seat can be a metal base, metal derby or buries metal level underground.
Heat-conducting plate engages one deck group body down.For example, following one deck group body can be one have printed circuit board (PCB) and a heat abstractor lamp socket.In this example, a LED packaging body is installed on heat-conducting plate, and this heat-conducting plate is then installed on heat abstractor, and heat-conducting plate/heat abstractor time group body and printed circuit board (PCB) are installed in lamp socket again.Wherein, this heat-conducting plate via the lead electrically connect to this printed circuit board (PCB).By this, this substrate can be with electric signal from this LED packaging body of this printed circuit board (PCB) guiding, and this radiating seat is then dispersed the heat energy of this LED packaging body and is passed to this heat abstractor.Therefore, this heat-conducting plate can be led chip one important hot path is provided.
Authorize the 6th of people such as Juskey; 507; No. 102 United States Patent (USP) discloses a kind of group of body, and wherein the composite base plate that is made up of glass fiber and cured thermosetting comprises a central opening, and have the square or OBL radiating block of similar this central opening attach to this central opening sidewall thereby with this substrate bonded; And in this substrate top and the bottom stick respectively upper and lower conductive layer arranged, and see through the plating guide hole electrically connect each other that runs through this substrate.Moreover other has a chip to be arranged on this radiating block and routing is engaged to conductive layer, and has an encapsulating material mould and establish and form on this chip, and lower conductiving layer then is provided with the tin ball.
When above-mentioned patent case when making, this substrate was one to place second rank (B-stage) the resin film on the lower conductiving layer originally.This radiating block is inserted in this central opening, thereby is positioned on the lower conductiving layer, and is separated by with a gap with this substrate, should go up conductive layer and then be located on this substrate.Treat this upper and lower conductive layer after heating reaches pressing each other, make the resin fusing and flow in the aforementioned gap and solidify that this upper and lower conductive layer promptly forms pattern, thereby on this substrate, forms wiring, and resin flash is revealed on this radiating block.Then remove resin flash, in order to do this radiating block is exposed, at last again with chip placing on this radiating block and carry out routing and engage and encapsulation.
Therefore, the heat energy of said chip generation can reach this printed circuit board (PCB) via this radiating block.Yet, when when producing in enormous quantities, the operation that this radiating block is positioned in this central opening is very taken a lot of work with manual mode, and with high costs.Moreover because the installation tolerance of side direction is little, this radiating block is difficult for accurately being positioned in this central opening, causes being prone between this substrate and this radiating block gap and the uneven situation of routing.Thus, this substrate only part attaches to this radiating block, both can't obtain enough support forces from radiating block, and delamination easily.In addition; Be used to remove the partially conductive layer and also will remove the radiating block that part is not covered by resin flash with the chemical etching liquor that appears resin flash; Cause radiating block uneven and be difficult for combining, the qualification rate that finally causes organizing body is on the low side, reliability is not enough and cost is crossed high shortcoming.
Authorize the 6th, 528, No. 882 of people such as the Ding a kind of high heat radiation ball bar array packaging body that United States Patent (USP) disclosed, its substrate comprises a metal core layer, and chip then is placed in the die pad zone of this metal core layer end face.Wherein, be formed with an insulating barrier, and have blind hole to run through straight-through this metal core layer of this insulating barrier, and be filled with heat radiation tin ball in the hole, and on this substrate, also be provided with in addition and the corresponding tin ball of this heat radiation tin ball in the bottom surface of this metal core layer.The heat energy that chip is produced can flow to this heat radiation tin ball via this metal core layer, flows to printed circuit board (PCB) again; Yet the insulating barrier that is located between this metal core layer and this printed circuit board (PCB) but causes restriction to the hot-fluid that flows to this printed circuit board (PCB).
Authorize the 6th of people such as Lee; 670; No. 219 United States Patent (USP)s are the downward ball bar array of a kind of groove of teaching (Cavity Down Ball Grid Array; CDBGA) packaging body, wherein one have central opening ground plate be arranged on the radiating seat constituting a heat-radiating substrate, and on this radiating seat by in the formed groove of the central opening of this ground plate a chip being installed; And see through one have central opening adhesion layer be provided with one have central opening substrate on this ground plate, then be provided with the tin ball on this substrate.Yet because this tin ball is positioned on this substrate, this radiating seat also can't the contact print circuit board, and the thermolysis that causes this radiating seat is only for thermal convection and non-thermal conductivity, thereby its radiating effect of limit significantly.
The 7th, 038, No. 311 United States Patent (USP)s authorizing people such as Woodall provide a kind of high heat radiation BGA packaging body, and its heat abstractor is inverted T-shaped and comprises a post portion and a wide substrate.Wherein one be provided with window type opening substrate be placed in this wide substrate, an adhesion layer then attaches to this substrate with this post portion and this wide substrate; One chip placing in this post portion and routing be engaged to this substrate, an encapsulating material is mold formed on this chip, then is provided with the tin ball on this substrate.In wherein, this post portion extends through this window type opening, and by this this substrate of wide substrate support, as for this tin ball then between this wide substrate and this substrate periphery.By this, the heat energy that said chip produces can reach this wide substrate via this post portion, reaches printed circuit board (PCB) again; Yet owing to must leave the space that holds this tin ball in this wide substrate, this wide substrate only is being stretched on corresponding to the position between center window and the penetralia tin ball below this substrate.Thus, this substrate is just uneven in manufacture process, and easy shaking and bending, and then causes mold formed all ten minutes difficulty of installation, routing joint and the encapsulating material of this chip.In addition, this wide substrate possibly bend because of the mold formed of encapsulating material, in case and the avalanche of tin ball, just possibly make this packaging body can't be soldered to down one deck group body.Be with, the qualification rate of this packaging body is on the low side, reliability is not enough and cost is too high.
The open case of U.S. Patent application of authorizing people such as Erchak is for No. 2007/0267642 to propose a kind of light-emitting device group body, and wherein the pedestal of an inverted T-shaped comprises the insulating barrier that a substrate, a protuberance and have through hole, on this insulating barrier and be provided with electric contact.Wherein one have through hole and transparent upper cover packaging body be arranged on this electric contact; One led chip is arranged at this protuberance and connects this substrate with routing, and this protuberance in abutting connection with this substrate and extend through this insulating barrier with this packaging body on through hole, in the entering packaging body.And this insulating barrier is arranged on this substrate, and this insulating barrier is provided with electric contact, and this packaging body is arranged on these electric contacts and with this insulating barrier and keeps spacing.By this, the heat energy that this chip produces can reach this substrate via this protuberance, and then arrives a heat abstractor; Yet these electric contacts are difficult for being arranged on this insulating barrier, be difficult to and following one deck group body electrically connect, and the multilayer route can't be provided.
Existing packaging body and heat-conducting plate have significant drawback.For example, the electrical insulating material such as low heat conductivities such as epoxy resin causes restriction to radiating effect; Yet the electrical insulating material that the epoxy resin of filling with pottery or carborundum etc. has high thermal conductivity has the shortcoming that tackness is low and the volume production cost is too high, cause this electrical insulating material maybe be in manufacturing process or the operation initial stage promptly because of the delamination of being heated.If then routing capabilities is limited for this substrate individual layer Circuits System, but if this substrate is the multilayer circuit system, then its blocked up dielectric layer will reduce radiating effect.In addition, preceding case technology still has radiating seat usefulness deficiency, volume is excessive or be difficult for hot link to problems such as following one deck group bodies, and the manufacturing process of preceding case technology also is inappropriate for the low-cost batch operation.
Because all development situations and the relevant limit of existing high power semiconductor component packaging body and heat-conducting plate; So, generally existing person can't meet the user when reality is used, supply required a kind of cost-effective, the usefulness of industry reliably, be suitable for producing in batches, multi-functional, the semiconductor chip group body that can adjust the signal route flexibly and have excellent heat radiation.
Summary of the invention
Main purpose of the present invention is, overcome the problems referred to above that known skill meets with and provide a kind of cost-effective, usefulness reliable, be suitable for producing in batches, multi-functional, the semiconductor chip group body that can adjust the signal route flexibly and have excellent heat radiation.
For reaching above purpose, first kind of technical scheme that the present invention adopted is: a kind of semiconductor chip group body, be used to provide vertical signal route, and it comprises:
One adhesion layer has an opening at least;
One radiating seat; At least comprise a projection and a pedestal; Wherein this projection in abutting connection with this pedestal and along one upwards direction extend this pedestal top; And this pedestal extends this projection below along one with this downward direction in the opposite direction that makes progress, and along extending laterally from this projection perpendicular to this side surface direction that upwards reaches downward direction;
One substrate; Be arranged on this adhesion layer and extend this pedestal top; It comprises a weld pad, a route line, one first conductive hole and a dielectric layer at least, and wherein this weld pad extends this dielectric layer top, and this route line extends this dielectric layer below and is embedded in this adhesion layer; And this first conductive hole extends through this dielectric layer to this route line, and has a through hole to extend through this substrate;
One second conductive hole extends through this adhesion layer to this route line;
One terminal extends this adhesion layer below;
The semiconductor assembly is positioned at this projection top and is overlapped in this projection, perhaps is positioned at this projection below and overlapping by this projection, this semiconductor subassembly electrically connect to this weld pad and this terminal, and hot link to this projection and this pedestal; And
Above-mentioned projection extends through this opening and gets into this through hole to reach this dielectric layer top; This pedestal then extends this adhesion layer and this substrate below; And constitute the conductive path that is positioned between this weld pad and this terminal by this first conductive hole, this route line and this second conductive hole; Wherein this adhesion layer is arranged on this pedestal; And extend in this through hole the breach that is positioned between this projection and this substrate in this pedestal top, in this breach, extend across this dielectric layer, and between between this projection and this dielectric layer and between this pedestal and this substrate.
This semiconductor subassembly is the semiconductor chip, and it extends this projection top, is overlapped in this projection, and electrically connect is to this weld pad, thus electrically connect to this terminal, and this semiconductor chip hot link is to this projection, thus hot link is to this pedestal.
This semiconductor subassembly is the semiconductor chip, utilizes a solid brilliant material to be arranged on this radiating seat, via a routing electrically connect to this weld pad, and via this solid brilliant material hot link to this projection.
This adhesion layer contacts this projection and this dielectric layer in this breach, and outside this breach contact this pedestal, this dielectric layer, this route line, this second conductive hole and this terminal.
This adhesion layer is in this side surface direction covering and around this projection.
This adhesion layer fills up this breach.
This adhesion layer fills up the space between this pedestal and this substrate.
This adhesion layer is overlapped in this terminal.
This adhesion layer extends to the peripheral edge of this group body.
This projection and this pedestal are integrally formed.
This projection and this adhesion layer are in same plane in this dielectric layer top.
This projection is a flat-top awl cylindricality, and its diameter is upwards from the flat top of this pedestal to this projection and successively decreases.
This pedestal and this terminal are in same plane in this adhesion layer below.
This pedestal covers this projection from the below, support this substrate, and keep at a distance with the peripheral edge of this group body.
This substrate and this projection and this pedestal are kept at a distance.
This substrate is a laminar structure.
This radiating seat comprises a lid at least, is positioned at an over top of this projection, covers in abutting connection with the top of this projection and from the top, extends laterally along the top of this side surface direction from this projection simultaneously.
This lid is rectangle or square, and the top of this projection is circular.
This radiating seat comprises a lid at least, and this lid and this weld pad are in same plane in this dielectric layer top.
The material of this radiating seat is a copper.
For reaching above purpose, second kind of technical scheme that the present invention adopted is: a kind of semiconductor chip group body, be used to provide vertical signal route, and it comprises:
One adhesion layer has an opening at least;
One radiating seat; At least comprise a projection, a pedestal and a lid, wherein this projection is in abutting connection with this pedestal and integrally formed with this pedestal, and this projection along one upwards direction extend this pedestal top; And make this pedestal and this lid form hot link; This pedestal extends this projection below along one with this downward direction in the opposite direction that makes progress, and along extending laterally from this projection perpendicular to this side surface direction that upwards reaches downward direction, this lid is positioned at an over top of this projection; Cover in abutting connection with the top of this projection and from the top, extend laterally along the top of this side surface direction simultaneously from this projection;
One substrate; Be arranged on this adhesion layer and extend this pedestal top; It comprises first and second conductive layer, one first conductive hole and a dielectric layer at least, this first conductive layer this dielectric layer of contact and extend this dielectric layer top wherein, this second conductive layer this dielectric layer of contact and extend this dielectric layer below and be embedded in this adhesion layer; And has the selected part that a weld pad is included in this first conductive layer; This weld pad this dielectric layer of contact also extends this dielectric layer top, and has the selected part that a route line is included in this second conductive layer, and this route line this dielectric layer of contact also extends this dielectric layer below; This first conductive hole then contacts and extends through the dielectric layer between this first conductive layer and this route line, and has a through hole to extend through this substrate;
One second conductive hole contacts and extends through this adhesion layer to this route line;
One terminal contacts and extends this adhesion layer below;
The semiconductor chip is arranged on this lid, is overlapped in this projection, and electrically connect is to this weld pad, thus electrically connect to this terminal, and this semiconductor chip hot link is to this lid, thus hot link is to this pedestal; And
Above-mentioned projection extends through this opening and gets into this through hole to reach this dielectric layer top; This pedestal then extends this semiconductor chip, this adhesion layer and this substrate below along this downward direction; And cover this semiconductor chip and this projection from the below and support this substrate, constitute the conductive path that is positioned between this weld pad and this terminal by this first conductive hole, this route line and this second conductive hole, wherein this adhesion layer is arranged on this pedestal; And extend in this through hole the breach that is positioned between this projection and this substrate in this pedestal top; In this breach, extend across this dielectric layer, and in this breach between this projection and this dielectric layer, outside this breach then between this pedestal and this substrate; This adhesion layer more covers and around this projection along this side surface direction, and extends to the peripheral edge of this group body.
This semiconductor chip utilizes a solid brilliant material to be arranged on this lid, via a routing electrically connect to this weld pad, and via this solid brilliant material hot link to this lid.
This substrate and this projection and this pedestal are kept at a distance, and fill up the space between this breach and this pedestal and this substrate by this adhesion layer, and this adhesion layer is restricted in the space between this radiating seat and this substrate.
The top of this projection is circular, and the lid on it is rectangle or square, and this projection is a flat-top awl cylindricality, and its diameter is upwards to this lid from this pedestal and successively decreases.
This projection and this adhesion layer and this lid and this weld pad are all in this same plane of coexistence, dielectric layer top, and this pedestal and this terminal are then in this same plane of coexistence, adhesion layer below, and the material of this radiating seat is a copper.
The present invention also provides a kind of method of making semiconductor chip group body, and it comprises: a projection and a pedestal are provided; One adhesion layer is set on this pedestal, and this projection is inserted an opening of this adhesion layer; One substrate is set on this adhesion layer, and this projection is inserted a through hole of this substrate, thereby in this through hole, form a breach between between this projection and this substrate; Make this adhesion layer upwards flow into this breach; Solidify this adhesion layer; The semiconductor assembly is set on a radiating seat, wherein this radiating seat comprises this projection and this pedestal at least; This semiconductor subassembly of electrically connect to this substrate and is positioned at the terminal of this adhesion layer below; And this semiconductor subassembly of hot link is to this radiating seat.Aforesaid substrate comprises first and second conductive layer and a therebetween dielectric layer at least, makes this group body that vertical signal route can be provided by this.
The present invention also provides the method for another kind of making semiconductor chip group body, comprises the following step:
(A1) projection, a pedestal, an adhesion layer and a substrate are provided, wherein this substrate comprises one first conductive layer, one second conductive layer and a therebetween dielectric layer at least; This projection is in abutting connection with this pedestal, and edge one upwards direction extends this pedestal top, extends an opening that connects this adhesion layer, and extends into a through hole of this substrate; This pedestal extends this projection below along one with this downward direction in the opposite direction that makes progress, and along extending laterally from this projection perpendicular to this side surface direction that upwards reaches downward direction; This adhesion layer is provided with on this pedestal, extends this pedestal top, and between this pedestal and this substrate, and uncured; This substrate is arranged on this adhesion layer, extends this adhesion layer top, and above wherein these first conduction series of strata extended this dielectric layer, this dielectric layer extended this second conductive layer top; And one breach in this through hole and between this projection and this substrate;
(B1) make this adhesion layer upwards flow into this breach;
(C1) solidify this adhesion layer;
(D1) the semiconductor assembly is set and comprises at least on the radiating seat of this projection and this pedestal in one, if not wherein this semiconductor subassembly to be overlapped in this projection promptly overlapping by this projection.This group body comprises a weld pad, a terminal, a route line and first and second conductive hole at least, and wherein this weld pad comprises a selected part of this first conductive layer; This route line comprises a selected part of this second conductive layer; This first conductive hole contacts and extends through the dielectric layer between this first conductive layer and this route line; The contact of second conductive hole also extends through this adhesion layer to this route line; And this termination contact and extend this adhesion layer below;
(E1) this semiconductor subassembly of electrically connect to this weld pad and this terminal one of them; Another person in this semiconductor subassembly of electrically connect to this weld pad and this terminal by this, wherein the conductive path that is positioned between this weld pad and this terminal comprises this first conductive hole, this route line and this second conductive hole; And
(F1) this semiconductor subassembly of hot link to this projection and this pedestal one of them, another person in this semiconductor subassembly of hot link to this projection and this pedestal by this.
The present invention also provides the third to make the method for semiconductor chipset body, comprises the following step:
(A2) projection and a pedestal are provided; Wherein this projection in abutting connection with and be integrally formed in this pedestal; And along one upwards direction extend this pedestal top; And this pedestal extends this projection below along one with this downward direction in the opposite direction that makes progress, and extends laterally along the side surface direction that reaches downward direction that makes progress perpendicular to this from this projection;
(B2) adhesion layer is provided, wherein comprises an opening and extend through this adhesion layer;
(C2) substrate is provided, wherein this substrate comprises first and second conductive layer and a therebetween dielectric layer at least, and contains the selected part that a route line is included in this second conductive layer, and has a through hole to extend through this substrate;
(D2) this adhesion layer is set on this pedestal, and comprises this this opening of projection insertion, wherein this adhesion layer extends this pedestal top, and this projection extends through this opening;
(E2) this substrate is set on this adhesion layer; And comprise this this through hole of projection insertion, wherein this substrate extends this adhesion layer top, and first conductive layer in this substrate extends this dielectric layer top; This dielectric layer also extends second conductive layer top in this substrate; And this projection extends through this opening and gets into this through hole, and this adhesion layer and has a breach in this through hole and between this projection and this substrate between this pedestal and this substrate and uncured;
(F2) this adhesion layer of heat fused;
(G2) with this pedestal and the closing each other of this substrate; This projection is upwards moved in this through hole; And the fusing adhesion layer between this pedestal and this substrate exerted pressure; This pressure forces this fusing adhesion layer upwards to flow into this breach, and this projection and this fusing adhesion layer then extend this dielectric layer top;
(H2) this fusing adhesion layer that is heating and curing is adhered to this substrate with this projection and this pedestal mechanicalness by this;
(I2) one first conductive hole is provided, it extends through this dielectric layer to this route line by this first conductive layer;
(J2) one second conductive hole is provided, it extends through this adhesion layer to this route line;
(K2) provide one to extend the weld pad of this dielectric layer top, and remove the selected part of this first conductive layer;
(L2) provide one to extend the terminal of this adhesion layer below, and remove the selected part of this pedestal;
(M2) lid is provided on this projection, this lid is positioned at an over top of this projection, in abutting connection with and cover the top of this projection from the top, and the top side along this side surface direction from this projection is to extending;
(N2) the semiconductor chip is set on this lid, wherein a radiating seat comprises this projection, this pedestal and this lid at least, and this semiconductor chip is overlapped in this projection;
(O2) this semiconductor chip of electrically connect is to this weld pad, and this semiconductor chip of electrically connect is to this terminal by this, and wherein the conductive path that is positioned between this weld pad and this terminal comprises this first conductive hole, this route line and this second conductive hole in regular turn; And
(P2) this semiconductor chip of hot link is to this lid, and this semiconductor chip of hot link is to this pedestal by this.
Above-mentioned steps (A2) provides this projection and this pedestal to comprise: a metallic plate is provided; On this metallic plate, form patterned etch resistance layer, its selectivity exposes this metallic plate to the open air; This metallic plate of etching makes it form the defined pattern of this patterned etch resistance layer, on this metallic plate, forms a groove by this, and it extends into but does not run through this metallic plate; Then remove this patterned etch resistance layer; Wherein this projection for this metallic plate one do not receive etching part, protrude in this pedestal top, and by this groove side to around; This pedestal does not also receive etching part for one of this metallic plate, and is positioned at this projection and this groove below.
Above-mentioned steps (B2) provides this adhesion layer to comprise: the film of a uncured epoxy resin is provided, and step (G2) makes, and this adhesion layer is mobile can be comprised: melt this uncured epoxy resin; And push the uncured epoxy resin between this pedestal and this substrate, and step (H2) this fusing adhesion layer that is heating and curing can comprise: the uncured epoxy resin that solidifies this fusing.
Above-mentioned steps (C2) provides this substrate to comprise: this route line is provided, and this step comprises the selected part of removing this second conductive layer; Form this through hole afterwards.
Above-mentioned steps (K2) provides this weld pad to comprise: grind this projection, this adhesion layer and this first conductive layer, cause this projection, this adhesion layer and this first conductive layer one towards the uper side surface of this direction that makes progress each other side direction flush; Then remove the selected part of this first conductive layer.In wherein, this grinding can comprise grinds this adhesion layer and does not grind this projection, then grinds this projection, this adhesion layer and this first conductive layer.
Above-mentioned steps (K2) provides this weld pad also can comprise the selected part of removing this first conductive layer.Step (L2) provides this terminal can comprise the selected part of removing this pedestal.Step (I2) provides this first conductive hole to comprise: form one first hole, it extends through this first conductive layer and this dielectric layer to this route line; In this first hole, reach this first conductive layer and the online conductive metal deposition of this route then to form one the 3rd conductive layer.Step (J2) provides this second conductive hole to comprise: form one second hole, it extends through this pedestal and this adhesion layer to this route line; In this second hole, reach this pedestal and the online conductive metal deposition of this route then to form one the 4th conductive layer.
Above-mentioned steps (K2, L2, I2 and J2) provides this weld pad, this terminal and this first and second conductive hole also can comprise: form above-mentioned hole; Conductive metal deposition is to form the 3rd and the 4th conductive layer in these holes; Then utilize first pattern etched resistance layer of this weld pad of definable to remove the selected part of this first and the 3rd conductive layer, and utilize second pattern etched of this terminal of definable to hinder the selected part that layer is removed the 4th conductive layer and this pedestal.
Above-mentioned steps (I2) provides first conductive hole to comprise: in this first hole and this projection, this first conductive layer, this adhesion layer and the online conductive metal deposition of this route to form one the 3rd conductive layer.Step (J2) provides this second conductive hole to comprise: in this second hole and this pedestal, this adhesion layer and the online conductive metal deposition of this route to form one the 4th conductive layer.Step (K2) provides this weld pad to comprise: the selected part of removing this first and the 3rd conductive layer.Step (L2) provides this terminal to comprise: the selected part of removing this pedestal and the 4th conductive layer.
Wherein provide the 3rd and the 4th conductive layer to comprise: the 3rd and the 4th conductive layer simultaneously is covered; The selected part of removing this first, the 3rd and the 4th conductive layer and this pedestal can comprise: etching simultaneously this first, the 3rd and the 4th conductive layer and this pedestal.
Above-mentioned this radiating seat that provides can comprise: after solidifying this adhesion layer with this semiconductor subassembly is set before; One lid is provided on this projection; This lid is positioned at an over top of this projection; In abutting connection with the top of this projection, cover the top of this projection simultaneously from the top, and extend laterally along this side surface direction from this projection top.
Above-mentioned steps (M2) provides this lid to comprise: after grinding and removing the selected part of the 3rd conductive layer, conductive metal deposition is to form one the 3rd conductive layer on this projection.For example, provide this lid to comprise: on the 3rd conductive layer, to form patterned etch resistance layer; Utilize this patterned etch resistance layer etching the 3rd conductive layer to define this lid; Then remove this patterned etch resistance layer.Equally, when forming this weld pad, this this first and the 3rd conductive layer of patterned etch resistance layer etching also capable of using is to define this weld pad.
Above-mentioned steps (G2) flows this adhesion layer can to comprise: fill up this breach with this adhesion layer; Also can comprise this adhesion layer of extruding, make it pass through this breach, arrive this projection and this substrate top, and reach part in this projection end face and this substrate top surface in abutting connection with this breach.
Above-mentioned steps (H2) this fusing adhesion layer that is heating and curing can comprise: this projection and this pedestal mechanicalness are incorporated into this substrate.
Above-mentioned steps (N2) is provided with this semiconductor chip and can comprises: this semiconductor chip is arranged at this projection, this opening and this through hole top, makes this semiconductor chip be overlapped in this projection, this opening and this through hole.Perhaps, this semiconductor chip is set also can comprises: this semiconductor chip is arranged at this projection, this opening and this through hole below, makes this semiconductor chip overlapping by this projection, this opening and this through hole.
Above-mentioned steps (N2, O2 and P2) setting, electrically connect and this semiconductor chip of hot link can comprise: this semiconductor chip is arranged on this projection; This semiconductor chip of electrically connect is to this weld pad, and this semiconductor chip of electrically connect is to this terminal by this; And this semiconductor chip of hot link is to this projection, and this semiconductor chip of hot link is to this pedestal by this.Perhaps, this semiconductor chip of setting, electrically connect and hot link also can comprise: this semiconductor chip is arranged at this pedestal below; This semiconductor chip of electrically connect is to this terminal, and this semiconductor chip of electrically connect is to this weld pad by this; And this semiconductor chip of hot link is to this pedestal, and this semiconductor chip of hot link is to this projection by this.
This semiconductor chip system of above-mentioned steps (N2, O2 and P2) setting, electrically connect and hot link can comprise: utilize a solid brilliant material that the semiconductor chip is arranged on this lid; Between this semiconductor chip and this weld pad, a routing is provided; And between this semiconductor chip and this lid, provide this to consolidate brilliant material.Perhaps, this semiconductor chip of setting, electrically connect and hot link also can comprise: utilize a solid brilliant material that the semiconductor chip is arranged on this pedestal; Between this semiconductor chip and this terminal, a routing is provided; And between this semiconductor chip and this pedestal, provide this to consolidate brilliant material.
Above-mentioned adhesion layer can contact this projection, this pedestal, this lid, this dielectric layer, this route line, this second conductive hole and this terminal; Cover and around this projection in this side surface direction, and extend to this group system make accomplish after with organize body with series-produced other and separate formed peripheral edge.
When this group system make accomplish and with separate with series-produced other group body after, this pedestal can cover this projection from the below, extend laterally from this projection along this side surface direction, supports this substrate simultaneously.
The present invention has multiple advantages.Comprising this radiating seat can provide excellent radiating effect, and makes heat energy this adhesion layer of not flowing through, and therefore, this adhesion layer can be the low-cost dielectric of low heat conductivity and is difficult for delamination; This projection and this pedestal can be integrally formed to improve reliability; This lid can be this semiconductor subassembly custom-made by size to promote connected hot effect; This adhesion layer can be used the mechanicalness that between this radiating seat and this substrate, provides firm and link between between this projection and this substrate and between this pedestal and this substrate; This substrate can provide complicated circuitry system pattern to realize the flexible multilayer signal of tool route; And this pedestal can be this substrate mechanical support is provided, and prevents its flexural deformation.By this, the low temperature process manufacturing capable of using of this group body not only can reduce stress, also can improve reliability, and in addition, the height control operation that this group body circuit board also capable of using, lead frame and coil type substrate manufactory can implement is easily made.
Description of drawings
Figure 1A is structure one cross-sectional schematic of making projection and pedestal in the present invention's one preferred embodiment.
Figure 1B is structure two cross-sectional schematic of making projection and pedestal in the present invention's one preferred embodiment.
Fig. 1 C is structure three cross-sectional schematic of making projection and pedestal in the present invention's one preferred embodiment.
Fig. 1 D is structure four cross-sectional schematic of making projection and pedestal in the present invention's one preferred embodiment.
Fig. 1 E is the schematic top plan view of Fig. 1 D.
Fig. 1 F is the elevational schematic view of Fig. 1 D.
Fig. 2 A is structure one cross-sectional schematic of making adhesion layer in the present invention's one preferred embodiment.
Fig. 2 B is structure two cross-sectional schematic of making adhesion layer in the present invention's one preferred embodiment.
Fig. 2 C is the schematic top plan view of Fig. 2 B.
Fig. 2 D is the elevational schematic view of Fig. 2 B.
Fig. 3 A is structure one cross-sectional schematic of making substrate in the present invention's one preferred embodiment.
Fig. 3 B is structure two cross-sectional schematic of making substrate in the present invention's one preferred embodiment.
Fig. 3 C is structure three cross-sectional schematic of making substrate in the present invention's one preferred embodiment.
Fig. 3 D is structure four cross-sectional schematic of making substrate in the present invention's one preferred embodiment.
Fig. 3 E is structure five cross-sectional schematic of making substrate in the present invention's one preferred embodiment.
Fig. 3 F is the schematic top plan view of Fig. 3 E.
Fig. 3 G is the elevational schematic view of Fig. 3 E.
Fig. 4 A is structure one cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 B is structure two cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 C is structure three cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 D is structure four cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 E is structure five cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 F is structure six cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 G is structure seven cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 H is structure eight cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 I is structure nine cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 J is structure ten cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 K is structure 11 cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 L is structure 12 cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 M is structure 13 cross-sectional schematic of making heat-conducting plate in the present invention's one preferred embodiment.
Fig. 4 N is the schematic top plan view of Fig. 4 M.
Fig. 4 O is the elevational schematic view of Fig. 4 M.
Fig. 5 A is the semiconductor chip group body cross-sectional schematic of the present invention's one preferred embodiment.
Fig. 5 B is the semiconductor chip group body schematic top plan view of the present invention's one preferred embodiment.
Fig. 5 C is the semiconductor chip group body elevational schematic view of the present invention's one preferred embodiment.
Fig. 6 A is the semiconductor chip group body cross-sectional schematic of another preferred embodiment of the present invention.
Fig. 6 B is the semiconductor chip group body schematic top plan view of another preferred embodiment of the present invention.
Fig. 6 C is the semiconductor chip group body elevational schematic view of another preferred embodiment of the present invention.
Label declaration
Metallic plate 10
Surface 12,14
Patterned etch resistance layer 16,40,60,62
The etchant resistive layer 18,38 that comprehensively covers
Groove 20
Projection 22
Pedestal 24
Adhesion layer 26
Opening 28
Substrate 30
First conductive layer 32
Dielectric layer 34
Second conductive layer 36
Route line 42,66
Through hole 44
Breach 46
Hole 48,50
The 3rd conductive layer 52
The 4th conductive layer 54
First conductive hole 56
Second conductive hole 58
Weld pad 64
Lid 68
Terminal 70
Lead 72
Radiating seat 74
The first anti-welding green lacquer 76
The second anti-welding green lacquer 78
Lining contact 80
Heat-conducting plate 82
Semiconductor chip group body 100,200
Semiconductor chip 102,202
Routing 104,204
Gu brilliant material 106,206
Encapsulating material 108,208
End face 110,210
Bottom surface 112,212
Routing connection pad 114,214
Embodiment
Above-mentioned and other characteristic of the present invention and advantage will be in hereinafter further explaining by various embodiment.
See also shown in Figure 1A～Fig. 1 F; Be respectively in the present invention's one preferred embodiment structure four cross-sectional schematic of making projection and pedestal in structure three cross-sectional schematic of making projection and pedestal in structure two cross-sectional schematic of making projection and pedestal in structure one cross-sectional schematic of making projection and pedestal, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, reach the schematic top plan view of Fig. 1 D, the elevational schematic view of Fig. 1 D.As shown in the figure: the present invention is a kind of semiconductor chip group body, and a metallic plate 10 at first is provided, and it comprises opposing main surface (12,14), shown in Figure 1A.This metallic plate 10 can be processed by multiple metal, like copper, aluminium, iron-nickel alloy 42, iron, nickel, silver, gold and alloy thereof.Wherein especially with copper have thermal conductivity height, associativity good with advantage such as low cost, so metallic plate 10 uses one thickness of present embodiment is 300 microns copper coin.
On this metallic plate 10, be formed with the etchant resistive layer 18 that patterned etch resistance layer 16 and covers comprehensively, shown in Figure 1B.This patterned etch resistance layer 16 is the photoresist layer that is deposited on this metallic plate 10 with the etchant resistive layer 18 that should cover comprehensively; Its production method is to utilize compression molding techniques simultaneously photoresist layer to be pressed on this surface (12,14) respectively with hot roller, in wherein moist spin-coating method and pouring curtain rubbing method also form technology for the photoresist layer that is suitable for.Continue it, in photoresist layer,, make the light selectivity one light shield (not shown) closing, remove soluble photoresist layer part so that photoresist layer forms pattern with developer solution again, promptly constitute this patterned etch resistance layer 16 through this light shield then according to known technology.Therefore, thereby the photoresist layer on this surface 12 exposes pattern formation patterned etch resistance layer 16 to the open air for having an alternative, thereby the photoresist layer on this surface 14 then is pattern-free and keeps the etchant resistive layer 18 that covering formation covers comprehensively.
On this metallic plate 10, be formed with one and be dug into but do not penetrate the groove 20 of this metallic plate 10, shown in Fig. 1 C.This groove 20 forms with the mode of this metallic plate 10 of etching, so that this metallic plate 10 forms by patterned etch resistance layer 16 defined pattern.In present embodiment, this etching mode is a wet chemical etch, and a top jet nozzle (not shown) capable of using is sprayed on this metallic plate 10 with chemical etching liquor; Also or, utilize the etchant resistive layer 18 that comprehensively covers that back-protective is provided, structure is immersed in the chemical etching liquor to form this groove 20.Wherein, this chemical etching liquor can have the height specific aim to copper, can be carved into this metallic plate 10 and reach 270 microns.Therefore, this groove 20 extends into from this surface 12 but does not penetrate this metallic plate 10, can with 30 microns of this surface 14 distances, the degree of depth then is 270 microns; In addition, this chemical etching liquor also causes side direction to be etched into to the metallic plate 10 of patterned etch resistance layer 16 below.In view of the above, the chemical etching liquor that can be suitable for can be the solution that contains alkali ammonia or the diluted mixture thing of nitric acid and hydrochloric acid, and in other words, above-mentioned chemical etching liquor can be acidity or alkalescence.In wherein, be enough to form the desirable etching period that this groove 20 do not cause this metallic plate 10 excessively to be exposed to chemical etching liquor and then can determine by trial and error pricing.
Metallic plate 10 behind the etchant resistive layer 18 of removing patterned etch resistance layer 16 and covering comprehensively is shown in Fig. 1 D, Fig. 1 E and Fig. 1 F.Wherein these photoresist layers solvent processing remove, it is NaOH/potassium hydroxide solution of 14 that solvent for use can be pH.In this way, therefore the metallic plate after etching 10 comprises the structure of a projection 22 and a pedestal 24.
Above-mentioned projection 22 is for one receiving the not etched part of patterned etch resistance layer 16 protection on this metallic plate 10.This projection 22 is integrally formed with this pedestal 24 in abutting connection with this pedestal 24, and is stretched on this pedestal 24 tops, in side direction then by 20 encirclements of this groove.Wherein this projection 22 is high in the degree of depth of this groove 20, is 270 microns, and the diameter of its end face equals the diameter of the circular portion on this surface 12, is 1000 microns, and the diameter of bottom then equals in abutting connection with the diameter of the circular portion of this pedestal 24, is 1100 microns.Therefore, these projection 22 similar frustums are flat-top awl cylindricality, and its sidewall convergent, diameter then upwards successively decrease towards its flat circular end face from these pedestal 24 places.In wherein, this sidewalls forms because of the chemical etching liquor side direction is etched into these patterned etch resistance layer 16 belows, so the circumference of this end face and this bottom is concentric, shown in Fig. 1 E.
This pedestal 24 one does not receive etching part for this metallic plate 10 below this projection 22, this projection 22 is along a lateral plane certainly, extends laterally like side surface direction such as left and right, and thickness is 30 microns.
This projection 22 can treated conjugation with reinforcement and epoxy resin and scolder with this pedestal 24.For example, this projection 22 and this pedestal 24 can be through chemical oxidation or microetch to produce more coarse surface.
This projection 22 is single metal (copper) body through the formation of reduction method in the present embodiment with this pedestal 24.In wherein, also capable of using one has this metallic plate 10 of contact punching press of groove or hole, and this groove or hole are in order to define the position of this projection 22, in order to do making this projection 22 become stamping forming single metallic object with this pedestal 24; Also or; Utilization increases method and forms this projection 22, for example see through electroplate, chemical vapour deposition (CVD) (Chemical Vapor Deposition, CVD), physical vapour deposition (PVD) (Physical Vapor Deposition; PVD) etc. technology is deposited on this projection 22 on this pedestal 24; Also or, utilize partly to increase method and form this projection 22 top of top, bottom this projection 22 of deposition that for example can form in these projection 22 its etchings; Or this projection 22 also can be sintered in this pedestal 24.In addition, this projection 22 is with this pedestal 24 and can be the multi-piece type metallic object, for example on copper pedestal 24, electroplates scolder projection 22; In the case, this projection 22 is to join with metallurgical interface with this pedestal 24, is adjacent to each other but is not integrally formed.
See also shown in Fig. 2 A～Fig. 2 D; Be respectively in the present invention's one preferred embodiment structure two cross-sectional schematic of making adhesion layer in structure one cross-sectional schematic of making adhesion layer, the present invention's one preferred embodiment, and the schematic top plan view of Fig. 2 B, the elevational schematic view of Fig. 2 B.As shown in the figure: the film that the uncured epoxy resin in second rank (B-stage) is provided is as an adhesion layer 26, and its thick 150 microns, shown in Fig. 2 A.
Above-mentioned adhesion layer 26 can be multiple organic or inorganic various dielectric films or the film that system becomes that be electrically insulated.For example, originally this adhesion layer 26 can be a film, after the thermosetting epoxy resin of resin kenel immerses a reinforcement material, promptly is partially cured to mid-term.Wherein, this epoxy resin can be FR-4, also can use such as other epoxy resin such as multifunctional and BMI-triazine (BT) resins.In application-specific, cyanate, polyimides and polytetrafluoroethylene (PTFE) also are available epoxy resin.In addition, this reinforcement material can be electron level glass, also can be other reinforcement material, like high strength glass, low dielectric constant glass, quartz, Ke Weila fiber (Kevlar Aramid) and paper etc.; Moreover this reinforcement material also can be fabric, adhesive-bonded fabric or non-directional microfibre.By this, can be with adding such as silicon fillers such as (levigation vitreous silicas) in the film to promote thermal conductivity, thermal shock resistance and thermal expansion matching property.In wherein, commercially available prepreg capable of using is an example like the SPEEDBOARD C film of Wisconsin, USA Ao Kelai W.L.Gore Associates.
This adhesion layer 26 has an opening 28 at least, shown in Fig. 2 B, Fig. 2 C and Fig. 2 D.This opening 28 is that mechanically brill passes through this film and forms for penetrating the center window of this adhesion layer 26, and its diameter is 1150 microns.In wherein, this opening 28 also can utilize other fabrication techniques, like punching out and punching press etc.
See also shown in Fig. 3 A～Fig. 3 G, be respectively in the present invention's one preferred embodiment structure five cross-sectional schematic of making substrate in structure four cross-sectional schematic of making substrate in structure three cross-sectional schematic of making substrate in structure two cross-sectional schematic of making substrate in structure one cross-sectional schematic of making substrate, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, and the schematic top plan view of Fig. 3 E, the elevational schematic view of Fig. 3 E.As shown in the figure: a substrate 30 is provided, and it comprises one first conductive layer 32, a dielectric layer 34 and one second conductive layer 36, shown in Fig. 3 A.These first conductive layer, 32 these dielectric layers 34 of contact also extend its top, and these second conductive layer, 36 these dielectric layers 34 of contact also extend its below, and this dielectric layer 34 contacts these first and second conductive layers (32,36) and fits and is folded in therebetween.Wherein this first and second conductive layer (32,36) is electrical conductor, and this dielectric layer 34 then is the body that is electrically insulated.For example, this first and second conductive layer (32,36) is 40 micron thick and patternless copper coin, and after accomplishing steps such as removing photoresist layer and cleaning successively, its thickness will reduce to 30 microns, and this dielectric layer 34 then is the epoxy resin of 120 micron thick.
Be formed with a comprehensive etchant resistive layer 38 that covers and patterned etch resistance layer 40 on first and second conductive layer of aforesaid substrate 30 (32,36) respectively, shown in Fig. 3 B.Should be photoresist layer with this patterned etch resistance layer 40 by comprehensive etchant resistive layer that covers 38, and difference similar aforesaid etchant resistive layer 18 and 16.This etchant resistive layer 38 no any patterns and cover this first conductive layer 32 wherein, this etchant resistive layer 40 then is provided with the pattern that alternative exposes this second conductive layer 36 to the open air.
In Fig. 3 C, second conductive layer 36 of this substrate 30 is removed selected part by etching, thereby forms one by these patterned etch resistance layer 40 defined patterning conductor layers.Wherein, this is etched to back side wet chemical etch, and it is similar with the engraving method that is used for this metallic plate.This moment, this first conductive layer 32 still was a patternless copper coin, and 36 of this second conductive layers cause this dielectric layer 34 to expose after etching, make this second conductive layer 36 convert a patterned layer into from a pattern-free layer.In present embodiment, for ease of each figure relatively, this second conductive layer 36 one roughly is positioned at this dielectric layer 34 belows in graphic, but in this step, can structure be inverted so that utilize gravity to strengthen etch effect.
In the substrate 30 of Fig. 3 D, the etchant resistive layer 38 that comprehensively covers all removes with patterned etch resistance layer 40.The mode that divests this etchant resistive layer 38 and 40 can be identical with the mode that divests etchant resistive layer 16 and 18.Second conductive layer 36 after the above-mentioned etching comprises route line 42.Therefore, this route line 42 receives the not etched part of patterned etch resistance layer 40 protection for this second conductive layer 36.In addition, this route line 42 is this dielectric layer 34 of contact and the copper cash that extends its below.
This substrate 30 has a through hole 44, shown in Fig. 3 E, Fig. 3 F and Fig. 3 G.This through hole 44 is for penetrating the center window of this substrate 30; With this first conductive layer 32 and this dielectric layer 34 mechanically bores pass through formation (precisely because in do not comprise this second conductive layer 36; Remove in the zone since then because of this layer has seen through wet chemical etch), the diameter of this through hole 44 is 1150 microns.In wherein, this through hole 44 can also other technology form for example punching out and punching press.The preferably, this opening 28 (shown in Fig. 2 B) has same diameter with this through hole 44, and on same rig floor, sees through same way as formation with identical drill bit.
It is a laminar structure that aforesaid substrate 30 illustrates at this, and only this substrate 30 also can be other multilayer body that is electrical connected, like ceramic wafer or printed circuit board (PCB).Likewise, this substrate 30 can comprise the layer body of several embedded circuit in addition.
See also shown in Fig. 4 A～Fig. 4 O, be respectively in the present invention's one preferred embodiment structure 13 cross-sectional schematic of making heat-conducting plate in structure 12 cross-sectional schematic of making heat-conducting plate in structure 11 cross-sectional schematic of making heat-conducting plate in structure ten cross-sectional schematic of making heat-conducting plate in structure nine cross-sectional schematic of making heat-conducting plate in structure eight cross-sectional schematic of making heat-conducting plate in structure seven cross-sectional schematic of making heat-conducting plate in structure six cross-sectional schematic of making heat-conducting plate in structure five cross-sectional schematic of making heat-conducting plate in structure four cross-sectional schematic of making heat-conducting plate in structure three cross-sectional schematic of making heat-conducting plate in structure two cross-sectional schematic of making heat-conducting plate in structure one cross-sectional schematic of making heat-conducting plate, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, the present invention's one preferred embodiment, and the schematic top plan view of Fig. 4 M, and the elevational schematic view of Fig. 4 M.As shown in the figure: heat-conducting plate of the present invention comprises this projection 22, this pedestal 24, this adhesion layer 26 and this substrate 30.Wherein this adhesion layer 26 is arranged on this pedestal 24, and shown in Fig. 4 A, this adhesion layer 26 drops on this pedestal 24, this projection 22 is upwards inserted and runs through this opening 28, and this adhesion layer 26 then contacts and be positioned this pedestal 24.The preferably, this projection 22 is positioned at the middle position of this opening 28 in insertion and after running through this opening 28 and does not contact this adhesion layer 26.
Aforesaid substrate 30 is arranged on this adhesion layer 26, shown in Fig. 4 B.This substrate 30 drops on this adhesion layer 26, this projection 22 is upwards inserted and runs through this through hole 44, and this substrate 30 then contacts and be positioned this adhesion layer 26.The preferably, this projection 22 is positioned at the middle position of this through hole 44 in insertion and after running through this through hole 44 and does not contact this substrate 30.Be with, produce a breach 46 in this through hole 44 and between this projection 22 and this substrate 30.These breach 46 lateral rings are around this projection 22, simultaneously by these substrate 30 flanked.In addition, this opening 28 aligns each other with this through hole 44 and has same diameter.
At this moment, this substrate 30 is placed on this adhesion layer 26 and contact with it, and extends this adhesion layer 26 tops.This projection 22 extends through this opening 28 and gets into this through hole 44, and arrives this dielectric layer 34.This projection 22 is than low 60 microns of the end face of this first conductive layer 32, and via this through hole 44 in one upwards direction expose.This pedestal 24 of this adhesion layer 26 contacts but is kept at a distance with this dielectric layer 34 with this substrate 30 and between this between the two.In this stage, this adhesion layer 26 still is the film of the uncured epoxy resin in second rank, then is air in this breach 46.
This adhesion layer 26 flows in this breach 46, shown in Fig. 4 C after heating and pressurizing.The method that forces this adhesion layer 26 to flow into this breach 46 is that this first conductive layer 32 is imposed downward pressure and/or this pedestal 24 is imposed upward pressure, also is about to this pedestal 24 and these substrate 30 relative pressings, uses this adhesion layer 26 is exerted pressure; At the same time also to these adhesion layer 26 heating.Adhesion layer 26 after being heated can be shaped arbitrarily under pressure.Therefore, after the adhesion layer 26 that is positioned at 30 of this pedestal 24 and this substrates is squeezed, changes its original-shape and upwards flow into this breach 46.In wherein, this pedestal 24 still continues towards pressing each other, till this adhesion layer 26 fills up this breach 46 with this substrate 30.In addition, after the gap of 30 of this pedestal 24 and substrates dwindled, this adhesion layer 26 still filled up in this gap of dwindling.For example; Can this pedestal 24 and this first conductive layer 32 be arranged at the upper and lower of a pressing machine presents a theatrical performance as the last item on a programme between the (not shown); And; Can and go up buffering paper (not shown) with an overhead gage and be folded between this first conductive layer 32 and the upper holder, and with a lower baffle plate and down buffering paper (not shown) be folded between this pedestal 24 and the bottom platen.With this superimposed body that constitutes be followed successively by from top to bottom upper holder, overhead gage, on cushion paper, substrate 30, adhesion layer 26, pedestal 24, cushion paper, lower baffle plate and bottom platen down.In addition, the instrument pin (not shown) that extends upward and pass these pedestal 24 registration holes (not shown) from bottom platen capable of using is positioned this superimposed body on the bottom platen.
Continue it, with the upper and lower heating and each other advancing of presenting a theatrical performance as the last item on a programme, by this to these adhesion layer 26 heating and exert pressure.The heat that wherein will present a theatrical performance as the last item on a programme with baffle plate is disperseed, and even makes heat be uniformly applied to this pedestal 24 and these substrate 30 these adhesion layers 26.This buffering paper then disperses the pressure of presenting a theatrical performance as the last item on a programme, and even makes pressure be uniformly applied to this pedestal 24 and these substrate 30 these adhesion layers 26.Originally, this second conductive layer 36 stretches into this adhesion layer 26 and embeds wherein, causes these dielectric layer 34 contacts and is pressed on this adhesion layer 26.Along with perseveration and the lasting heating of presenting a theatrical performance as the last item on a programme, the adhesion layer 26 that this pedestal 24 and this substrate are 30 is squeezed and begins fusing, thereby upwards flows into this breach 46, through this dielectric layer 34, arrives this first conductive layer 32 at last.For example, uncured epoxy resin clamp-oned in this breach 46 by pressure, but reinforcement material and filler is still stayed between this pedestal 24 and this substrate 30 after meeting heat fusing.The speed that this adhesion layer 26 rises in this through hole 44 is greater than this projection 22, eventually to filling up this breach 46.This adhesion layer 26 also rises to the position of a little higher than this breach 46, and present a theatrical performance as the last item on a programme stop the action before, the end face of overflow to these projection 22 end faces and this first conductive layer 32 is in abutting connection with these breach 46 places.If film thickness is slightly larger than actual required this situation that just possibly take place.Thus, this adhesion layer 26 just forms one at these projection 22 end faces and covers thin layer.Presenting a theatrical performance as the last item on a programme stops action after touching this projection 22, but still continues 26 heating of this adhesion layer.
This adhesion layer 26 flow direction (in figure, making progress shown in the thick arrow) upwards in this breach 46; This projection 22 moves up as making progress shown in the thin arrow with respect to this substrate 30 with this pedestal 24, and this substrate 30 moves down then shown in thin arrow downwards with respect to this projection 22 and this pedestal 24.
Adhesion layer 26 in Fig. 4 D has cured.For example, presenting a theatrical performance as the last item on a programme still continues this projection 22 of clamping and this pedestal 24 and heat supplies after stopping to move, and the second rank epoxy resin that will melt by this converts that solidify on third rank (C-stage) or the epoxy resin of sclerosis into.Therefore, epoxy resin solidifies with the mode of similar known multilayer pressing.After treating epoxy resin cure, the separation of presenting a theatrical performance as the last item on a programme is so that take out structure from the machine of presenting a theatrical performance as the last item on a programme.Providing firm mechanicalness to link between this projection 22 and this substrate 30 and between this pedestal 24 and this substrate 30 through the adhesion layer after the above-mentioned curing 26.This adhesion layer 26 can bear general operation pressure and unlikely distortion damage, then only distortion temporarily when meeting excessive pressure; Moreover this adhesion layer 26 also can absorb between this projection 22 and this substrate 30 and the thermal expansion between this pedestal 24 and this substrate 30 does not match.
In this stage, this projection 22 and this first conductive layer 32 be copline roughly, this adhesion layer 26 and this first conductive layer 32 then extend to one face this direction that makes progress end face.For example, adhesion layer that this pedestal 24 and this second conductive layer are 36 26 thick 90 microns reduces 60 microns for 150 microns than its original depth; This projection 22 raises 60 microns in this through hole 44, and this substrate 30 then descends 60 microns with respect to this projection 22.270 microns of this projection 22 height are equal to this first conductive layer 32 (30 microns), this dielectric layer 34 (150 microns), this second conductive layer 36 (30 microns) basically and combine highly with this adhesion layer 26 of below (90 microns).In addition, this projection 22 still is positioned at this opening 28 keeps at a distance with the middle position of this through hole 44 and with this substrate 30, and 26 of this adhesion layers fill up the space of 30 of this pedestal 24 and this substrates and fill up this breach 46.For example, this breach 46 (and this projection 22 and this substrate 30 adhesion layer 26) is at these projection 22 end face places wide 75 microns ((1150-1000)/2).This adhesion layer 26 extends across this dielectric layer 34 in this breach 46.In other words, the adhesion layer in this breach 46 26 extends and crosses over dielectric layer 34 thickness of these breach 46 lateral walls along should make progress a direction and a downward direction.This adhesion layer 26 also comprises the thin top portion of these breach 46 tops, and it contacts this projection 22 and extends 10 microns with the end face of this first conductive layer 32 and above this projection 22.
The top of this projection 22, this adhesion layer 26 and this first conductive layer 32 is removed, shown in Fig. 4 E.Remove with lapping mode at the top of this projection 22, this adhesion layer 26 and this first conductive layer 32, for example to rotate the top of diamond wheel and distilled water Processing Structure body.Originally, diamond wheel only grinds off this adhesion layer 26; Continue to grind, then this adhesion layer 26 is moved down attenuation because of grinding the surface.Diamond wheel contacts this projection 22 and this first conductive layer 32 (simultaneously uninevitable) at last, thereby begins to grind this projection 22 and this first conductive layer 32; After continuing to grind, this projection 22, this adhesion layer 26 and this first conductive layer 32 are all moved down attenuation because of grinding the surface.To be ground continuing to removed till the desired thickness, removes dirt with the distilled water flushing structure.
Above-mentioned grinding steps grinds off 25 microns with the top of this adhesion layer 26, the top of this projection 22 is ground off 15 microns, and the top of this first conductive layer 32 is ground off 15 microns.Wherein, thickness reduces the influence of this projection 22 or this adhesion layer 26 and not obvious, but makes the thickness of this first conductive layer 32 significantly be reduced to 15 microns from 30 microns.So far, this projection 22, this adhesion layer 26 and this first conductive layer 32 are positioned on the level and smooth splicing side end face that one of these dielectric layer 34 tops face this direction that makes progress jointly.
Structure shown in Fig. 4 F has hole 48 and 50.This hole 48 is a blind hole, and it extends through this first conductive layer 32 and this dielectric layer 34 to this route line 42, only keeps at a distance with this adhesion layer 26.And this hole 50 is all a blind hole, and it extends through this pedestal 24 and this adhesion layer 26 to this route line 42, only keeps at a distance with this dielectric layer 34.Wherein this hole (48,50) forms with radium-shine bore mode, but other technology such as machine drilling and electric paste etching of also can arranging in pairs or groups.In wherein, this hole (48,50) can have the sidewall of convergent and the diameter that successively decreases with the degree of depth, but for ease of illustrating, and the hole (48,50) in graphic all has vertical sidewall and changeless diameter.
Structure has one the 3rd conductive layer 52, one the 4th conductive layer 54, one first conductive hole 56 and one second conductive hole 58 shown in Fig. 4 G.The 3rd conductive layer 52 is deposited on the aforementioned side end face of this projection 22, this adhesion layer 26 and this first conductive layer 32 and contact with it.Cover this projection 22, this adhesion layer 26 and this first conductive layer 32 simultaneously from the top.Wherein, the 3rd conductive layer 52 is a pattern-free and thick 15 microns copper layer, and integrally formed with this first conductive hole 56.
Above-mentioned the 4th conductive layer 54 is deposited on the bottom surface of this pedestal 24 and contact with it, covers this pedestal 24 simultaneously from the below.Wherein, the 4th conductive layer 54 is a pattern-free and thick 15 microns copper layer, and integrally formed with this second conductive hole 58.
Above-mentioned first conductive hole 56 extends into this hole 48 from this first conductive layer 32.This first conductive hole 56 is to be deposited on this dielectric layer 34 and this route line 42 and contact with it in this hole 48.Wherein, this first conductive hole 56 is coated through holes, and it can be with this first and third conductive layer (32,52) electrically connect to this route line 42.
Above-mentioned second conductive hole 58 extends into this hole 50 from this pedestal 24.This second conductive hole 58 is deposited on this adhesion layer 26 and this route line 42 in this hole 50 and contact with it.Wherein, this second conductive hole 58 is coated through holes, and it can be with this pedestal 24 and the 4th conductive layer 54 electrically connects to this route line 42.
For example; Can structure be immersed in the activator solution; Thereby make the dielectric layer 34 of its sidewall of this hole (48,50) and this adhesion layer 26 produce the catalyst reaction respectively with electroless copper; Then one first bronze medal layer is located on the sidewall of this projection 22, this pedestal 24, this adhesion layer 26, this first conductive layer 32, this route line 42 (being positioned at the structure reverse side) and this hole (48,50) with electroless plating lining mode, then one second bronze medal layer is located on this first bronze medal layer with plating mode.About 2 microns of this first bronze medal bed thickness, about 13 microns of this second bronze medal bed thickness is so the gross thickness of lining copper layer is about 15 microns.Thus, the thickness of this first conductive layer 32 just increases to about 40 microns (25+15), and in wherein, after accomplishing steps such as removing photoresist layer and cleaning successively, the thickness of this first conductive layer 32 will reduce to about 30 microns; Likewise, the thickness of this pedestal 24 increases to about 55 microns (30+25), and only after accomplishing steps such as removing photoresist layer and cleaning successively, its thickness also will reduce to about 45 microns.
The 3rd conductive layer 52 is as a cover layer of this projection 22 and a thickening layer of this first conductive layer 32, and the 4th conductive layer 54 then is a thickening layer of this pedestal 24.In addition, this first and second conductive hole (56,58) is to be formed at respectively in this hole (48,50).For ease of explanation, this pedestal 24, this first～four conductive layer (32,36,52,54) and this first and second conductive hole (56,58) all show with individual layer.Because copper is homogeneity lining, the boundary line (all illustrating with dotted line) that the boundary line that the boundary line that this projection 22 and the 3rd conductive layer are 52, this pedestal 24 and the 4th conductive layer are 54 and this first conductive layer 32 and the 3rd conductive layer are 52 possibly be difficult for discovering even can't discovering.Yet this adhesion layer 26 is clearly visible in the boundary line at contiguous these projection 22 places with the 3rd conductive layer 52.Likewise, this dielectric layer 34 is also clearly visible with the boundary line of this second conductive hole 58 in this hole 50 with boundary line and this adhesion layer 26 of this first conductive hole 56 in this hole 48.In addition, for ease of illustrating, this first and second conductive hole (56,58) all is shown as the column that fills up this hole (48,50) but not hollow tube body in graphic.
Be respectively equipped with patterned etch resistance layer 60 and 62 on the upper and lower surface of structure shown in Fig. 4 H.Patterned etch resistance layer 60 and 62 similar this etchant resistive layer 16 as shown in the figure and 40 photoresist layer.Wherein this etchant resistive layer 60 is provided with the pattern that alternative exposes the 3rd conductive layer 52 to the open air, and this etchant resistive layer 62 then is provided with the pattern that alternative exposes the 4th conductive layer 54 to the open air.
In the structure shown in Fig. 4 I, this first and third conductive layer (32,52) is removed its selected part to form patterned etch resistance layer 60 defined pattern by etching; This pedestal 24 is also removed its selected part to form patterned etch resistance layer 62 defined pattern via etching with the 4th conductive layer 54.Said etching is similar with the front and the back side wet chemical etch that are applied to this metallic plate.For example, a top nozzle capable of using and a below nozzle (all not showing among the figure) are sprayed on the end face and the bottom surface of structure with chemical etching liquor, perhaps structure are immersed in the chemical etching liquor.Penetrate this first and third conductive layer (32,52) exposing this adhesion layer 26 and this dielectric layer 34 to the open air through above-mentioned chemical etching liquor etching, thereby patternless first and third conductive layer (32,52) converts patterned layer into originally.In wherein, this chemical etching liquor also etching penetrates this pedestal 24 and the 4th conductive layer 54 to expose this adhesion layer 26 to the open air.
In Fig. 4 J, the patterned etch resistance layer 60 and 62 on the structure is all removed, and removing method can be identical with the mode of removing etchant resistive layer 16 and 18.
First and third conductive layer after the etching (32,52) comprises a weld pad 64 and a route line 66, and the 3rd conductive layer 52 after the etching comprises a lid 68.Wherein this weld pad 64 is that this first and third conductive layer (32,52) receives 60 protection of patterned etch resistance layer and not etched part with this route line 66, and 68 of this lids receive the not etched part of patterned etch resistance layer 60 protection for the 3rd conductive layer 52.Therefore, this first and third conductive layer (32,52) just becomes patterned layer, comprises this weld pad 64 on it with this route line 66 but do not comprise this lid 68.In addition, this route line 66 is a copper conductor, and its this dielectric layer 34 of contact also extends its top, simultaneously this first conductive hole 56 and this weld pad 64 of adjacency and electrically connect.
Pedestal 24 after the etching and the 4th conductive layer 54 comprise the middle body and a terminal 70 of this pedestal 24, and wherein the middle body of this pedestal 24 is to cover (following general designation pedestal 24/54) from the below by the 4th conductive layer 54.This pedestal 24/54 is that this pedestal 24 receives 62 protection of patterned etch resistance layer and not etched part with the 4th conductive layer 54, and it is along extending laterally beyond outside this projection 22 1000 microns.This terminal 70 is that this pedestal 24 receives 62 protection of patterned etch resistance layer and not etched part with the 4th conductive layer 54, and its this adhesion layer 26 of contact also extends its below.This pedestal 24/54 itself still is a pattern-free layer, comprises this terminal 70 and keeps the patterned layer of lateral spacings with this pedestal 24 but outside these pedestal 24 peripheries, then form one.Therefore, this terminal 70 is separate with this pedestal 24, and the part of non-this pedestal 24 of this terminal 70.In addition, this second conductive hole 58 forms electrically connect in abutting connection with this terminal 70 and between this route line 42 and this terminal 70.
This route line 42 and 66, this first and second conductive hole 56 and 58, this weld pad 64 and this terminal 70 common leads 72 that form.Likewise, the conductive path 70 of this weld pad 64 and this terminals is to pass through this route line 66, this first conductive hole 56, this route line 42 and this second conductive hole 58 (vice versa) in regular turn.This lead 72 provides vertical (from top to bottom) route from this weld pad 64 to this terminal 70, and this lead 72 is not limited to this configuration, and for example this weld pad 64 also is formed directly in this first conductive hole, 56 tops, saves this route line 66 by this; This second conductive hole 58 then sees through these adhesion layer 26 belows and hinders layer 62 a defined route line electrically connect to this terminal 70 by patterned etch.Moreover above-mentioned conductive path can comprise other conductive hole and route line (its be arranged in first, second and/or other conductive layer) and passive component, for example is arranged at resistance and electric capacity on other weld pad.
Constitute radiating seat 74 by above-mentioned projection 22, pedestal 24/54 and lid 68.Wherein this projection 22 is integrally formed with this pedestal 24/54, and this lid 68 is positioned at the over top of this projection 22, in abutting connection with the top of this projection 22, covers the top of this projection 22 simultaneously from the top, and by the top of this projection 22 toward extending laterally.After waiting to be provided with this lid 68, this projection 22 is seated the middle section in these lid 68 circumference, and the also contact and cover the part of its below adhesion layer 26 from the top of this lid 68, and this part of this adhesion layer 26 and this projection 22 coplines are in abutting connection with this projection 2
2, while this projection 22 of flanked.
Above-mentioned radiating seat 74 is essentially the radiating block of an inverted T-shaped, and it comprises post portion (being projection 22), alar part (being the part that pedestal 24/54 extends laterally from post portion) and a heat conductive pad (being lid 68).
In the structure shown in Fig. 4 K, be provided with one first anti-welding green lacquer 76 in this dielectric layer 34, the 3rd conductive layer 52 and this lid 68, and on this pedestal 24/54, this adhesion layer 26 and this terminal 70, also be provided with one second anti-welding green lacquer 78.Wherein, this first anti-welding green lacquer 76 is an electrical insulation layer, and it can form pattern according to our selection exposing this weld pad 64 and this lid 68 to the open air, and covers exposed parts and this route line 66 of this dielectric layer 34 from the top.In the thickness of this first anti-welding green lacquer 76 above this weld pad 64 wherein is 25 microns, and this first anti-welding green lacquer 76 extends 55 microns (30+25) in these dielectric layer 34 tops; And this second anti-welding green lacquer 78 is all an electrical insulation layer, can form pattern according to our selection exposing this pedestal 24/54 and this terminal 70 to the open air, and cover the exposed parts of this adhesion layer 26 from the below.In the thickness of this second anti-welding green lacquer 78 below this terminal 70 wherein is 25 microns, and this second anti-welding green lacquer 78 extends 70 microns (45+25) in these adhesion layer 26 belows.
Above-mentioned first and second anti-welding green lacquer (76,78) is originally for coating the smooth video picture type liquid resin on the structure; Go up in this first and second anti-welding green lacquer (76,78) more afterwards and form pattern; It makes decree light selective permeation light shield (not shown); Utilize a developing solution to remove the solubilized part of this first and second anti-welding green lacquer (76,78) then, carry out roastingly firmly at last again, above step is known skill.
In the structure shown in Fig. 4 L, be provided with lining contact 80 with this terminal 70 in this pedestal 24/54, this weld pad 64, this lid 68.This lining contact 80 is a multiple layer metal coating, and this weld pad 64 of contact covers its exposed parts simultaneously with this lid 68 from the top for it, and this pedestal 24/54 of contact covers its exposed parts simultaneously with this terminal 70 from the below.For example; One nickel dam is located on this pedestal 24/54, this weld pad 64, this lid 68 and this terminal 70 with electroless plating lining mode; Then again a gold medal layer is located on this nickel dam with electroless plating lining mode; Wherein the interior nickel bed thickness is about 3 microns, and about 0.5 micron of surperficial golden bed thickness is so the thickness of this lining contact 80 is about 3.5 microns.
Above-mentioned have several advantages with this lining contact 80 as the surface treatment of this pedestal 24/54, this weld pad 64, this lid 68 and this terminal 70; Comprise: inner nickel dam provides main mechanicalness and electrically connect and/or hot link, and surface gold layer then provides a wettable surface in order to the scolder reflow; This lining contact 80 also protects this pedestal 24/54, this weld pad 64, this lid 68 not to be corroded with this terminal 70; And this lining contact 80 can comprise various metals to meet the outside needs that link media.For example, one overlayed on silver layer on the nickel dam can arrange in pairs or groups scolding tin or routing.Wherein, For ease of explanation; The pedestal 24/54, weld pad 64, lid 68 and the terminal 70 that are provided with this lining contact 80 all show with simple layer body mode, and the boundary line (not shown) of 70 of this lining contact 80 and this pedestal 24/54, this weld pad 64, this lid 68 and this terminals is copper/nickel interface.So far, accomplish the making of a heat-conducting plate 82.
The edge of this heat-conducting plate 82 separates with bracing frame and/or with series-produced adjacent heat-conducting plate along line of cut, shown in Fig. 4 M, Fig. 4 N and Fig. 4 O.This heat-conducting plate 82 comprises this pedestal 24/54, this adhesion layer 26, this substrate 30, this terminal 70, this radiating seat 74 and this first and second anti-welding green lacquer (76,78).Wherein, this substrate 30 comprises this dielectric layer 34, this route line (42,66), this first conductive hole 56 and this weld pad 64; This radiating seat 74 comprises this projection 22, this pedestal 24/54 and this lid 68.In wherein, this lead 72 is by this route line (42,66), this first and second conductive hole (56,58), this weld pad 64 and 70 formations of this terminal.
After this projection 22 extends through this opening 28 and gets into this through hole 44, still be positioned at the middle position of this opening 28 and this through hole 44, and be positioned at an adjacent part copline of these dielectric layer 34 tops with this adhesion layer 26.This projection 22 keeps flat-top awl cylindricality, and its sidewalls makes its diameter upwards successively decrease towards the smooth dome in abutting connection with this lid 68 from this pedestal 24/54.This pedestal 24/54 covers this projection 22 from the below, and keeps at a distance with the peripheral edge of this heat-conducting plate 82.This lid 68 is positioned at this projection 22 tops, and in abutting connection with also being hot link, this lid 68 covers the top of this projection 22 simultaneously from the top with it, and this edge, projection 22 tops extends laterally certainly.This lid 68 is also from top contact and cover the part of this adhesion layer 26, and this part of this adhesion layer 26 is in abutting connection with this projection 22, with these projection 22 coplines, and this projection 22 of flanked.This lid 68 also with these weld pad 64 coplines.
This adhesion layer 26 is arranged on this pedestal 24/54 and side's extension on it.This adhesion layer 26 contacts and between this projection 22 and this dielectric layer 34, in order to fill up the space of 34 of this projection 22 and this dielectric layers.In addition, this adhesion layer 26 also contact and between this pedestal 24/54 and this substrate 30 to fill up space therebetween.This adhesion layer 26 is simultaneously along the side surface direction covering and around this projection 22, and this adhesion layer 26 has solidified.
This substrate 30 is arranged on this adhesion layer 26 and contact with it, also extends the top of below adhesion layer 26 and this pedestal 24/54 simultaneously.Wherein, this first conductive layer 32 (and this weld pad 64 and this route line 66) contacts this dielectric layer 34 and extends its top; These dielectric layer 34 contact these second conductive layers 36 (comprising this route line 42) also extend its top, and this dielectric layer 34 is between this first and second conductive layer 32, between 36; This second conductive layer 36 (comprising this route line 42) then contacts this adhesion layer 26 and is embedded wherein.
Above-mentioned projection 22, pedestal 24/54 and lid 68 are all kept at a distance with this substrate 30.Therefore, this substrate 30 is connected with these radiating seat 74 mechanicalnesses and electrical isolation each other.
After cutting, its adhesion layer 26, dielectric layer 34 and first and second anti-welding green lacquer (76,78) all extend to and cut the vertical edge that forms with batch heat-conducting plate of making 82.
This weld pad 64 is one to aim at the electrical interface of semiconductor subassembly custom-made by size such as semiconductor chip, and this semiconductor subassembly will be arranged in successive process on this lid 68.This terminal 70 is one to aim at down the tailor-made electrical interface of one deck group scale of construction body, for example descends one deck group body to can be a printed circuit board (PCB), and this heat-conducting plate 82 then is arranged in successive process on this printed circuit board (PCB).This lid 68 is one to aim at the hot interface of this semiconductor subassembly custom-made by size.This pedestal 24/54 is one to aim at the hot interface of this printed circuit board (PCB) custom-made by size.In addition, this lid 68 be via this projection 22 hot link to this pedestal 24/54.
This weld pad 64 and this terminal 70 be dislocation and expose to the end face and the bottom surface of this heat-conducting plate 82 respectively each other in vertical direction, and the vertical route between this semiconductor subassembly and following one deck group body is provided by this.And the end face that this weld pad 64 and this lid 68 are positioned at these dielectric layer 34 tops is copline each other, and also copline each other of the bottom surface that this pedestal 24/54 and this terminal 70 are positioned at these adhesion layer 26 belows.In wherein, for ease of explain that it is a continuous circuits trace that this lead 72 illustrates in cutaway view; Yet this lead 72 provides horizontal signal routes of X and Y direction usually simultaneously, that is this weld pad 64 misplaces with Y direction formation side direction at X with this terminal 70 each other, and this route line 42 and 66 constitutes the path of X and Y direction separately or jointly.
This radiating seat 74 can diffuse to following one deck group body that this pedestal 24/54 is connected with the heat energy that semiconductor subassembly produced that is arranged at subsequently on this lid 68.The heat energy that this semiconductor subassembly produces flows into this lid 68, and this lid 68 gets into this projection 22 certainly, and gets into this pedestal 24/54 via this projection 22.Heat energy sheds along this downward direction from this pedestal 24/54, for example diffuses to a below heat abstractor.Likewise, this radiating seat 74 also can diffuse to following one deck group body that this lid 68 is connected with the heat energy that semiconductor subassembly produced that is arranged at subsequently on this pedestal 24/54.
The projection 22 of this heat-conducting plate 82, first and second conductive hole 56 and 58 or route line 42 and 66 all do not expose.This projection 22 is covered by this lid 68, and this first and second conductive hole (56,58) and this route line 42 and 66 are to be covered by this first anti-welding green lacquer 76, as for the end face of this adhesion layer 26 then simultaneously by this lid 68 and this first anti-welding green lacquer 76 coverings.For ease of explanation, will illustrate this projection 22, this adhesion layer 26, this first and second conductive hole (56,58) and this route line 42 and 66 with dotted line among Fig. 4 N.
This heat-conducting plate 82 also comprises other lead 72; Those leads 72 are by this first and second conductive hole (56,58), this route line 42 and 66, this weld pad 64 and 70 formations of this terminal basically, and have a multilayer conductive path at this weld pad 64 and 70 of this terminals.For ease of explanation, only explain and illustrate plain conductor 72 at this.In this lead 72, this first and second conductive hole (56,58), this weld pad 64 and this terminal 70 are of similar shape and size usually, and this route line 42 then adopts different route configurations usually with 66.For example, part lead 72 is provided with spacing, and is separated from one another, and is electrical isolation, part lead 72 then interlaced with each other or lead same weld pad 64, route line (42,66) or terminal 70 and electrically connect each other.Likewise, part of solder pads 64 can be in order to receive independent signal, and part of solder pads 64 is then shared a signal, power supply or earth terminal.In addition; Part lead 72 can comprise this route line 42 and this first and second conductive hole (56,58) so that the multilayer route to be provided; Part lead 72 does not then contain this route line 42 and this first and second conductive hole (56,58), and only in this first conductive layer 32 the individual layer route is provided.
The structure of this heat-conducting plate 82 can be adjusted to some extent with a plurality of chips of arranging in pairs or groups and use, in order to do making each I/O signal from indivedual weld pads 64 guiding other terminals 70, and each weld pad 64 same earth terminal 70 that when ground connection, then leads.
Remove oxide and residue on the exposed metal at simple and easy cleaning of each fabrication stage all capable of using one, for example can implement an of short duration oxygen electricity and starch cleaning structure of the present invention.Perhaps, a potassinm permanganate solution capable of using carries out an of short duration wet chemistry cleaning to structure of the present invention.Likewise, distilled water drip washing also capable of using structure of the present invention is to remove dirt.This cleaning can clean required surface and structure do not caused tangible influence or destruction.
The invention has the advantages that after this lead 72 forms and do not need therefrom to separate or be partitioned into confluence or associated circuitry.The confluence can be separated in the wet chemical etch step that forms this weld pad 64, this route line 66, this lid 68 and this terminal 70.
This heat-conducting plate 82 can comprise brill and pass through or cut the registration holes (not shown) that logical this adhesion layer 26, this substrate 30 and this first and second anti-welding green lacquer (76,78) form.Thus, when this heat-conducting plate 80 needs in successive process, be arranged at a below carrier, just can the instrument pin be inserted in this registration holes, use that this heat-conducting plate 82 is placed the location.
This heat-conducting plate 82 can omit this lid 68.Desire to reach this purpose, can adjust patterned etch resistance layer 60, the 3rd conductive layer 52 of whole through hole 44 tops all is exposed in order in the chemical etching liquor that forms this weld pad 64 and this route line 66.
This heat-conducting plate 82 can hold a plurality of semiconductor subassemblies but not only hold single semiconductor subassembly.Desire to reach this purpose; Can adjust patterned etch resistance layer 16 with the more projections 22 of definition; Adjust this adhesion layer 26 to comprise more openings 28, adjust this substrate 30 to comprise more multi-through hole 44, adjustment patterned etch resistance layer 40 is to define more multirouting line 42; Adjustment patterned etch resistance layer 60 and 62 is with the more weld pad of definition 64, route line 66, lid 68 and terminal 70, and adjusts this first and second anti-welding green lacquer (76,78) to comprise more openings.Likewise, this substrate 30 also can comprise more multirouting line 42 and conductive hole 56 and 58.This assembly beyond terminal 70 can change lateral position so that be that four semiconductor subassemblies provide a 2x2 array.In addition, part but the section shape of non-all component and height (being side view) also can be adjusted to some extent.For example, this weld pad 64, this lid 68 can keep identical side view with this terminal 70, and this route line 42 and 66 then has different route configurations.
See also shown in Fig. 5 A～Fig. 5 C, be respectively semiconductor chip group body schematic top plan view, and the semiconductor chip group body elevational schematic view of the present invention's one preferred embodiment of semiconductor chip group body cross-sectional schematic, the present invention's one preferred embodiment of the present invention's one preferred embodiment.As shown in the figure: the semiconductor subassembly among this embodiment is one to be arranged at the chip on the lid.This chip is overlapped in aforementioned projection, and electrically connect to aforementioned weld pad, and then forms electrically connect with aforementioned terminal, and the hot link simultaneously of this chip is aforementioned lid extremely, thereby forms hot link with aforementioned pedestal.
The semiconductor chip group body 100 of present embodiment comprises a heat-conducting plate 82, semiconductor chip 102, a routing 104, one solid brilliant material 106 and 108 formations of an encapsulating material; And this semiconductor chip 102 comprises an end face 110, a bottom surface 112 and a routing connection pad 114; Wherein this end face 110 is active surface and comprises this routing connection pad 114, and this bottom surface 112 then is the thermo-contact surface.
Above-mentioned semiconductor chip 102 is arranged on this radiating seat 74, and electrically connect is to this substrate 30, and hot link is to this radiating seat 74.Detailed it, this semiconductor chip 102 is arranged on this lid 68, is positioned at the periphery of this lid 68, is overlapped in this projection 22 but underlapped in this substrate 30.In addition, this semiconductor chip 102 to this substrate 30, attaches to this radiating seat 74 via these solid brilliant material 106 hot links and mechanicalness via these routing 104 electrically connects simultaneously.For example, this routing 104 connect and electrically connect to this weld pad 64 and this routing connection pad 114, by this with these semiconductor chip 102 electrically connects to this terminal 70.Likewise, this solid brilliant material 106 contacts and between this lid 68 and this thermo-contact surface 112, it is surperficial 112 that hot link simultaneously and mechanicalness attach to this lid 68 and this thermo-contact, by this with these semiconductor chip 102 hot links in this pedestal 24.This weld pad 64 is provided with the coated metal connection pad of nickel/silver in order to firmly combining with this routing 104, improves the transmission of the signal to this semiconductor chip 102 from this substrate 30 by this.In addition, the shape of this lid 68 and size and this thermo-contact surface 112 are joined right, and the heat of improving by this from this semiconductor chip 102 to this radiating seat 74 transmits.
This encapsulating material 108 is a solid-state compressible protectiveness plastic overmold body, can be this semiconductor chip 102 and this routing 104 environmental protection such as anti-moist and anti-particulate are provided.Wherein, this semiconductor chip 102 is embedded in this encapsulating material 108 with this routing 104.And if this semiconductor chip 102 is the optical chips such as LED, then this encapsulating material 108 can be transparence, and in wherein, this encapsulating material 108 promptly is transparence in order to illustrating in Fig. 5 B.
If desire makes above-mentioned semiconductor chip group body 100, capable of using should this semiconductor chip 102 being arranged on this lid 68 solid brilliant material 106 engages this weld pad 64 and this routing connection pad 114 then with routing, form this encapsulating material 108 afterwards again.
For example, this solid brilliant material 106 was one to have the argentiferous epoxy paste of high-termal conductivity originally, and was printed on this lid 68 with screen painting mode selectivity.Utilize one to grasp a head and an automation pattern identification system then, this semiconductor chip 102 is positioned on this epoxy resin silver paste with the stepping repetitive mode; Then heat this epoxy resin silver paste, it is hardened to accomplish solid crystalline substance down in relative low temperature (as 190 ℃).This routing 104 is a gold thread, and it is connected to this weld pad 64 and this routing connection pad 114 with hot ultrasonic waves subsequently; And, at last again with these encapsulating material 108 transfer mouldings on this structure.
This semiconductor chip 102 can see through multiple binding media electrically connect to this weld pad 64, utilizes multiple hot adhesive agent hot link or mechanicalness to attach to this radiating seat 74, and with multiple encapsulating material encapsulation.
So far, this semiconductor chip group body 100 is a first order monocrystalline packaging body.
See also shown in Fig. 6 A～Fig. 6 C, be respectively semiconductor chip group body schematic top plan view, and the semiconductor chip group body elevational schematic view of another preferred embodiment of the present invention of semiconductor chip group body cross-sectional schematic, another preferred embodiment of the present invention of another preferred embodiment of the present invention.As shown in the figure: the semiconductor chip among this embodiment is arranged at aforementioned pedestal but not is arranged on the aforementioned lid.This chip is overlapping by aforementioned projection, and electrically connect to aforementioned terminal is so that form electrically connect with aforementioned weld pad, and hot link simultaneously to aforementioned pedestal is so that form hot link with the aforementioned cover body.
For asking simple and clear, allly be applicable to that with organizing the relevant explanation of body 100 (please join shown in Fig. 5 A～Fig. 5 C) this embodiment all incorporates into here, repetition is refused in identical explanation.Likewise, the assembly of present embodiment group body and the similar person of assembly who organizes body 100 all adopt the corresponding reference label, but the radix of its coding change 200 into by 100.For example, semiconductor chip 202 is corresponding to semiconductor chip 102, and routing 204 is then corresponding to routing 104, by that analogy.
The semiconductor chip group body 200 of present embodiment comprises a heat-conducting plate 82, semiconductor chip 202, a routing 204, one solid brilliant material 206 and 208 formations of an encapsulating material; And this semiconductor chip 202 is in this inversion and comprise (when not being inverted) end face 210, a bottom surface 212 and a routing connection pad 214; Wherein this end face 210 is active surface and comprises this routing connection pad 214, and this bottom surface 212 then is the thermo-contact surface.
Above-mentioned semiconductor chip 202 is arranged on this radiating seat 74, and electrically connect is to this substrate 30, and hot link is to this radiating seat 74.Know clearly it, this semiconductor chip 202 is arranged on this pedestal 24, is positioned at the periphery of this pedestal 24, and is overlapping but not overlapping by this substrate 30 by this projection 22.In addition, this semiconductor chip 202 to this terminal 70, attaches to this radiating seat 74 via these solid brilliant material 206 hot links and mechanicalness via these routing 204 electrically connects simultaneously.For example, this routing 204 connect and electrically connect to this routing connection pad 214 and this terminal 70, by this with these semiconductor chip 202 electrically connects to this weld pad 64.Likewise, this solid brilliant material 206 is between this pedestal 24 and this thermo-contact surface 212, and it is surperficial 212 that hot link simultaneously and mechanicalness attach to this pedestal 24 and this thermo-contact, by this with these semiconductor chip 202 hot links in this lid 68.In wherein, this encapsulating material 208 is transparence so that illustrate in Fig. 6 C.
If desire makes above-mentioned semiconductor chip group body 200, capable of using should this semiconductor chip 202 being arranged on this pedestal 24 solid brilliant material 206 engages this routing connection pad 214 and this terminal 70 then with routing, form this encapsulating material 208 afterwards again.
So far, this semiconductor chip group body 200 is a first order monocrystalline packaging body.
Above-mentioned semiconductor chip group body and heat-conducting plate are merely illustrative example, and the present invention still can see through other various embodiments and realize.In addition, the foregoing description can be according to the consideration of design and reliability, and the collocation that is mixed with each other is used or used with other embodiment mix and match.For example; One has a plurality of projections to cooperate the heat-conducting plate of a plurality of semiconductor chips; Its part lead 72 can comprise this route line 42 and 66, this first and second conductive hole 56 and 58 and this terminal 70; In addition part lead 72 does not then contain this route line 42 and 66 and this first and second conductive hole 56 and 58, and does not extend through this adhesion layer 26 or this dielectric layer 34.Likewise, this semiconductor subassembly and this lid can be overlapped in the adhesion layer of this substrate and below, and this semiconductor subassembly also can be overlapping by this substrate.
This semiconductor subassembly can use this radiating seat alone or share this radiating seat with other semiconductor subassembly.For example, can single semiconductor subassembly be arranged on this radiating seat, or a plurality of semiconductor subassemblies are arranged on this radiating seat.For example, can four pieces of small chips that are arranged in the 2x2 array be attached to this projection, this substrate then can comprise extra lead to cooperate the electric connection of those chips.This practice has more economic benefit far beyond a small projection is set for each chip.
This semiconductor chip can be optical or non-optical property.For example, this chip can be a LED, a solar cell, a power chip or a controller chip.In addition, multiple binding media capable of using to this heat-conducting plate, comprises this semiconductor subassembly mechanicalness binding, electrically connect and hot link to utilize welding and use modes such as conduction and/or heat conduction adhesive agent to reach.
This radiating seat can rapidly, effectively and evenly be distributed to down one deck group body with the heat energy that this semiconductor subassembly produced and need not make type of thermal communication cross the elsewhere of this adhesion layer, this substrate or this heat-conducting plate.Just can use the lower adhesion layer of thermal conductivity thus, thereby significantly reduce cost.This radiating seat can be copper, and comprises integrally formed projection and pedestal, and with this projection be metallurgical the binding and a connected hot lid, improve reliability by this and reduce cost.This lid can with this weld pad copline so as to form electrically with this semiconductor subassembly, heat energy and mechanicalness link.In addition, if desire places this radiating seat top with this semiconductor subassembly, this lid can be complied with this semiconductor subassembly custom-made by size, and this pedestal then can be strengthened from this semiconductor subassembly to the hot link of one deck group body down according to one deck group scale of construction body is tailor-made down by this.For example, this projection can be rounded on a lateral plane, and this lid can be square or rectangle on a lateral plane, and the side view of the side view of this lid and this semiconductor subassembly hot junction is same or similar.Likewise, if desire places this radiating seat below with this semiconductor subassembly, this pedestal also can be complied with this semiconductor subassembly custom-made by size, and this lid then can be according to one deck group scale of construction body is tailor-made down.
This radiating seat can be electrically connect or electrical isolation with this semiconductor subassembly and this substrate.For example, a route line of the 3rd conductive layer can extend through this adhesion layer between this substrate and this lid, use this semiconductor subassembly electrically connect to this radiating seat.Then, this radiating seat is ground connection electrically, uses the electrical ground connection of this semiconductor subassembly.
This projection can be deposited on this pedestal or be integrally formed with this pedestal.For example, this projection can be integrally formed and become single metallic object with this pedestal, and perhaps this projection and this pedestal can comprise single metallic object and comprise other metal in other part in its interface.This projection can comprise a smooth end face or a top.For example, this projection can with this adhesion layer copline, perhaps this projection can be accepted etching after this adhesion layer solidifies, thereby the adhesion layer above this projection forms a depression.Also alternative this projection of etching is used the depression that formation one extends under its end face in this projection.Under above-mentioned arbitrary situation, this semiconductor subassembly all can be arranged on this projection and be arranged in this depression, and this routing then may extend to this semiconductor subassembly that is positioned at this depression, leaves this depression then and extends to this weld pad.In this example, this semiconductor subassembly can be a led chip, and this depression then can be with LED light towards the direction focusing that should make progress.
This pedestal can be this substrate mechanical support is provided.For example, this pedestal can prevent the flexural deformation in the process of metal grinding, chip setting, routing joint and mold encapsulant of this substrate.In addition, the back of this pedestal can comprise along the fin of this downward direction projection.For example, the bottom surface of this pedestal of routing machine cutting capable of using is with the formation lateral grooves, and these lateral grooves are fin.In this example, the thickness of this pedestal is 500 microns, and the degree of depth of these grooves is 300 microns, that is the height of these fins is 300 microns.These fins can increase the surface area of this pedestal, are arranged on the heat abstractor if these fins are exposed in the air, then can promote the thermal conductivity of this pedestal via thermal convection.
This lid can be after this adhesion layer solidifies, that this weld pad and/or terminal form is preceding, in or after, process with multiple deposition technique, comprise with technology formation single or multiple lift structures such as platings, electroless plating lining, evaporation and splashes.This lid can adopt the metal material identical with this projection.In addition, this through hole of the extensible leap of this lid also arrives this substrate, perhaps maintains in the circumference range of this through hole.Therefore, this lid can contact this substrate or keep at a distance with this substrate.Under above arbitrary situation, this lid all extends laterally along side surface direction from the top of this projection.
This adhesion layer can provide firm mechanicalness to link between this radiating seat and this substrate.For example, this adhesion layer can fill up the space between this radiating seat and this substrate, and this adhesion layer can be positioned at this space, and this adhesion layer can be one and has the no hole structure of equally distributed joint line.This adhesion layer also can absorb between this radiating seat and this substrate because of the phenomenon that do not match that thermal expansion produced.In addition, this adhesion layer can be a low-cost dielectric, and need not possess high-termal conductivity.Moreover this adhesion layer is difficult for delamination.
Can adjust the thickness of this adhesion layer, make this adhesion layer essence fill up this breach, and make all adhesive agents after solidifying and/or grinding, essence is positioned within the structure.For example, desirable film thickness can be determined by trial and error pricing.
This substrate can provide flexible multilayer signal route at X and Y direction, so that complicated route pattern to be provided.Visual this semiconductor subassembly of this weld pad and this terminal adopts multiple packing forms with the needs of following one deck group body.In addition, this substrate can be a low-cost laminar structure, and need not have high-termal conductivity.
The end face of this weld pad and this lid can be copline, just can strengthen the welding between this semiconductor subassembly and this heat-conducting plate by the avalanche degree of control tin ball thus.
This weld pad and this route line of this dielectric layer top can be processed with multiple deposition technique before or after this substrate places this adhesion layer, comprised with technology such as plating, electroless plating lining, evaporation and splashes forming the single or multiple lift structure.For example, can, this substrate promptly on this substrate, form this first and second conductive layer when not placing this adhesion layer as yet.
Carrying out the surface-treated operation with said lining contact can be before or after this weld pad and the formation of this terminal for it.For example, this coating can be deposited on the 3rd and the 4th conductive layer, then utilizes patterned etch resistance layer definition this weld pad and this terminal and carries out etching, so that this coating has pattern.
This lead can comprise extra weld pad, terminal, route line and conductive hole and passive component, and can be not isomorphism type.This lead can be used as a signal layer, a power layer or a ground plane, looks the purpose of its corresponding semiconductor assembly weld pad and decides.This lead also can comprise various conducting metals, for example copper, gold, nickel, silver, palladium, tin and alloy thereof.Desirable composition had both depended on the outside character that links media, also depended on the consideration of design and reliability aspect.In addition; The personage who is skillful in this skill should understand; Used copper can be fine copper in this semiconductor chip group body; But be main alloy with copper usually,, use and improve like mechanical performances such as tensile strength and ductility like copper-zirconium (99.9% bronze medal), copper-Yin-phosphorus-magnesium (99.7% bronze medal) and copper-Xi-iron-phosphorus (99.7% bronze medal).
Preferably be provided with this lid, this anti-welding green lacquer, this lining contact and the 3rd and the 4th conductive layer in the ordinary course of things, but in some embodiment, then can omit it.
The operation form of this heat-conducting plate can be single or a plurality of heat-conducting plates, looks designing for manufacturing and decides.For example, can make single heat-conducting plate separately.Perhaps, the anti-welding green lacquer in single metal plate capable of using, single adhesion layer, single substrate, the anti-welding green lacquer of single end face and single bottom surface is batch a plurality of heat-conducting plates of manufacturing simultaneously, and then row separates again.Likewise; To each heat-conducting plate in same batch, the anti-welding green lacquer in single metal plate also capable of using, single adhesion layer, single substrate, the anti-welding green lacquer of single end face and single bottom surface batch is made radiating seat and the lead that a multicomponent does not supply single semiconductor subassembly to use simultaneously.
For example, can on a metallic plate, etch many grooves to form this pedestal and a plurality of projection; Then with one have the opening of corresponding these projections uncured adhesion layer be arranged on this pedestal, in order to do making each projection all extend through a corresponding opening; Then a said substrate (it has the through hole of single first conductive layer, single dielectric layer, a plurality of respectively corresponding these projections and the below route line of many respectively corresponding these through holes) is arranged on this adhesion layer, in order to do making each projection all extend through a corresponding opening and getting into a pair of through hole of answering; Then utilize and present a theatrical performance as the last item on a programme, get into the breach between between these projections and this substrate in these through holes to force this adhesion layer with this pedestal and the closing each other of this substrate; This adhesion layer is solidified, grind these projections, this adhesion layer and this first conductive layer then to form an end face; Form a plurality of first holes and a plurality of second hole afterwards, wherein these first holes run through this first conductive layer and this dielectric layer to these route lines, and these second holes then run through this pedestal and this adhesion layer to these route lines; Then the lining of the 3rd conductive layer is arranged on these projections, this adhesion layer and this first conductive layer; The lining of the 4th conductive layer is arranged on this pedestal; A plurality of first conductive holes are covered respectively to be arranged in these first holes, and a plurality of second conductive holes are covered respectively are arranged in these second holes; Then this first and the 3rd conductive layer of etching is to form the weld pad of a plurality of respectively corresponding these projections; Etching the 3rd conductive layer to be forming a plurality of respectively lids of corresponding these projections, and this pedestal of etching and the 4th conductive layer are to form a plurality of terminals of distinguishing corresponding these projections; Then this first anti-welding green lacquer is placed on the structure; And make this first anti-welding green lacquer produce pattern, and use and expose these weld pads and these lids to the open air, in addition this second anti-welding green lacquer is placed on the structure; Make this second anti-welding green lacquer produce pattern, use and expose these pedestals and these terminals to the open air; Then this pedestal, these weld pads, these terminals and these lids are carried out surface treatment with the lining contact; In the cutting of the appropriate location of these heat-conducting plate peripheral edges or this substrate of splitting, this adhesion layer and these anti-welding green lacquers, indivedual heat-conducting plates are separated from one another in order to do making at last.
The operation form of this semiconductor chip group body can be single group of body or a plurality of groups of bodies, depends on designing for manufacturing.For example, can make single group of body separately.Perhaps, batch a plurality of groups of bodies of manufacturing separate each heat-conducting plate afterwards more one by one simultaneously; Likewise, also can a plurality of semiconductor subassembly electrically connects, hot link and mechanicalness be linked to each heat-conducting plate in batch volume production.
For example; Can a plurality of solid brilliant materials be deposited on respectively on a plurality of lids; Then a plurality of chips are positioned over respectively on these solid brilliant materials, heat these solid brilliant materials afterwards more simultaneously so that its sclerosis and form a plurality of solid brilliantly then is engaged to corresponding pad with these chip routings; Then form corresponding encapsulating material, again each heat-conducting plate is separated one by one at last at these chips and routing.
Can make each heat-conducting plate separated from one another through one step or multiple tracks step.For example, can a plurality of heat-conducting plates batch be processed a flat board, then a plurality of semiconductor subassemblies are arranged on this flat board, a plurality of semiconductor chip group bodies that afterwards again should flat board constituted separate one by one.Perhaps; Can a plurality of heat-conducting plates batch be processed a flat board; A plurality of heat-conducting plate branches that then should flat board constituted are cut to a plurality of heat conduction laths; Then a plurality of semiconductor subassemblies are arranged at respectively on these heat conduction laths, a plurality of semiconductor chip group bodies that again each heat conduction lath constituted at last are separated into individuality by strip.In addition, machine cuts capable of using, radium-shine cutting, compartition or other applicable technology when cutting apart heat-conducting plate.
By this, manufacturing process of the present invention has the height applicability, and combines to use electrical ties, hot link and the mechanicalness connecting technology of various maturations with unique, progressive mode.In addition, manufacturing process of the present invention does not need expensive tool to implement.Therefore, this manufacturing process can significantly promote output, yield, usefulness and the cost benefit of conventional package technology.Moreover the group body utmost point of this case is suitable for copper chip and unleaded environmental requirement.
In this article, " adjacency " meaning of one's words finger assembly is integrally formed, promptly forms single individuality; Or be in contact with one another, promptly each other continuously at a distance from or do not separate.For example, this projection is in abutting connection with this pedestal, and this adopts when forming this projection the method that increases or reduction method irrelevant.
" overlapping " meaning of one's words refers to be positioned at the top and extends the periphery of a below assembly." overlapping " comprises and extends the inside and outside of this periphery or be seated in this periphery.For example; This semiconductor subassembly is overlapped in this projection; Be to run through this semiconductor subassembly and this projection simultaneously because of an imaginary vertical line; Be all the assembly (like this lid) that this imagination vertical line runs through no matter whether have another between this semiconductor subassembly and this projection, no matter and also whether have another imaginary vertical line only to run through this semiconductor subassembly and do not run through this projection (that is the periphery that is positioned at this projection is outer).Likewise, this adhesion layer is overlapped in this pedestal and this terminal and overlapping by this weld pad, and this pedestal is then overlapping by this projection.Likewise, this projection system is overlapped in this pedestal and is positioned at its periphery.In addition, " overlapping " and " be positioned at top " synonym, " by overlapping " then with " being positioned at the below " synonym.
" contact " meaning of one's words refers to direct contact.For example, this dielectric layer contacts this first and second conductive layer but does not contact this projection or this pedestal.
" covering " language refers to from the top, covers fully from the below and/or from the side.For example, this pedestal covers this projection from the below, but this projection does not cover this pedestal from the top.
" layer " word comprises the layer body that is provided with pattern or does not establish pattern.For example, when this substrate was arranged on this adhesion layer, this first conductive layer can be a blank patternless flat board and this second conductive layer can be one and has the at interval circuit pattern of lead; When this semiconductor subassembly is arranged on this radiating seat, this first conductive layer can be one have a pattern circuit.In addition, " layer " can comprise a plurality of layers that coincide.
" weld pad " language refers to that one is used to be connected and/or engage the connecting area of outside connection media (like scolder or routing) when using with this substrate collocation; When this semiconductor subassembly was positioned at this radiating seat top, this outside connects media can make this weld pad and this semiconductor subassembly reach electrically connect.
" terminal " language is meant a connecting area when using with this group body collocation, and it can contact and/or engage the outside media (like scolder or routing) that links; When this semiconductor subassembly was positioned at this radiating seat top, this outside links media can be with this terminal electrically connect to an external equipment (like a printed circuit board (PCB) or a connected lead).
" lid " language is meant that one is used to be connected and/or engage the contact area of outside connection media (like scolder or heat conduction adhesive agent) when using with this radiating seat collocation; When this semiconductor subassembly was positioned at this radiating seat top, this outside connects media can make this lid and this semiconductor subassembly reach hot link.
" opening " refers to perforated holes together with languages such as " through holes ".For example, when this projection inserted this opening of this adhesion layer, it was exposed to this adhesion layer along the direction that makes progress.Likewise, when this projection inserted this through hole of this substrate, this projection was exposed to this substrate along the direction that makes progress.
Relatively moving between " insertion " meaning of one's words finger assembly.For example, " this projection is inserted in this through hole " and comprise: this projection is fixed and moved to this pedestal by this substrate; This substrate is fixed and moved to this substrate by this projection; And this projection and the closing each other of this substrate.Again for example, " it is interior that this projection is inserted (or extending to) this through hole " comprises: this projection runs through (penetrate and pass) this through hole; And this projection inserts but does not run through (penetrate but do not pass) this through hole.
" closing each other " one also the relatively moving between finger assembly of speaking.For example, " this pedestal and the closing each other of this substrate " comprise: this pedestal is fixed and by this this pedestal of substrate migration; This substrate is fixed and moved to this substrate by this pedestal; And this pedestal and this substrate each other near.
" be arranged at " one the language comprise with single or a plurality of supporting components between contact and noncontact.For example, this semiconductor subassembly is arranged on this radiating seat, no matter this this radiating seat of semiconductor subassembly actual contact or be separated by with a solid brilliant material with this radiating seat.Likewise, this semiconductor subassembly is arranged on this radiating seat, and though this semiconductor subassembly only be arranged on this radiating seat or be arranged at this radiating seat simultaneously and this substrate on.
" adhesion layer ... among this breach " meaning of one's words refers to be arranged in this adhesion layer of this breach.For example, " adhesion layer extends across this dielectric layer in this breach " means this adhesion layer extension in this breach and crosses over this dielectric layer.Likewise, " adhesion layer is in contact among this breach and between between this projection and this dielectric layer " mean that this adhesion layer in this breach contacts and between this dielectric layer of this projection of this breach madial wall and this breach lateral wall.
" top " meaning of one's words is pointed to go up and is extended, and comprises adjacency and non-adjacent assembly and overlapping and non-overlapped assembly.For example, this projection extends this pedestal top, simultaneously in abutting connection with, be overlapped in this pedestal and go out from this pedestal projection.Likewise, this projection extends to this dielectric layer top, even if this projection not in abutting connection with or be overlapped in this dielectric layer.
" below " meaning of one's words is pointed to and is extended below, and comprises adjacency and non-adjacent assembly and overlapping and non-overlapped assembly.For example, this base extension is in this projection below, and is overlapping by this projection in abutting connection with this projection, and goes out from this projection projection.Likewise, this projection extends this dielectric layer below, even if this projection is not in abutting connection with this dielectric layer or overlapping by this dielectric layer.
The vertical direction that so-called " making progress " reaches " downwards " is not the orientation that depends on this semiconductor chip group body (or this heat-conducting plate), and all personages who is familiar with this skill can understand the direction of its actual indication easily.For example, this projection along direction vertical extent upwards in this pedestal top, this adhesion layer then along the downward direction vertical extent in this weld pad below, whether whether this and this group body be inverted and/or be arranged on the heat abstractor has nothing to do.Likewise, this pedestal extends from this projection " side direction " along a lateral plane, and whether this and this group body is inverted, rotates or is tilted and have nothing to do.Therefore, should be upwards and downward direction against each other and perpendicular to side surface direction, in addition, the assembly of side direction alignment one perpendicular to this upwards with the lateral plane of downward direction on copline each other.
Semiconductor chip group body of the present invention has multiple advantages.The reliability of this group body is high, price is plain and extremely be fit to volume production.This group body is particularly useful for producing high heat and needing excellent radiating effect can effectively reach the high power semiconductor component of reliable operation such as large-scale semiconductor chip etc. is easy.
Said embodiment is the usefulness of illustration, and wherein related this skill known tip assemblies or step or warp are simplified or omitted to some extent in order to avoid fuzzy characteristics of the present invention.Likewise, graphic clear for making, graphic middle the repetition or non-essential assembly and reference number or omission to some extent.
The personage who is skillful in this skill is directed against embodiment described herein when thinking easily and various variation and modification.For example, aforementioned base materials, size, shape, size, step content and sequence of steps all are merely example.Above-mentioned personage can be engaged in these changes, adjustment and impartial skill in not breaking away under the present invention's spirit and the range of condition, and wherein the scope of the invention is defined by claims.
In sum; The present invention is a kind of semiconductor chip group body, can effectively improve the various shortcoming of usefulness, and the reliability of this group body is high, price is plain and extremely be fit to volume production; Be particularly useful for producing high heat and needing excellent radiating effect can effectively reach the high power semiconductor component of reliable operation such as large-scale semiconductor chip etc. is easy; Can significantly promote output, yield, usefulness and cost benefit, and compliance with environmental protection requirements, and then make generation of the present invention can more progressive, more practical, more meet user institute palpus; Really met the application for a patent for invention important document, the whence proposes patent application in accordance with the law.

Claims (25)

1. a semiconductor chip group body is used to provide vertical signal route, it is characterized in that comprising:
One adhesion layer has an opening at least;
One radiating seat; At least comprise a projection and a pedestal; Wherein this projection in abutting connection with this pedestal and along one upwards direction extend this pedestal top; And this pedestal extends this projection below along one with this downward direction in the opposite direction that makes progress, and along extending laterally from this projection perpendicular to this side surface direction that upwards reaches downward direction;
One substrate; Be arranged on this adhesion layer and extend this pedestal top; It comprises a weld pad, a route line, one first conductive hole and a dielectric layer at least, and wherein this weld pad extends this dielectric layer top, and this route line extends this dielectric layer below and is embedded in this adhesion layer; And this first conductive hole extends through this dielectric layer to this route line, and has a through hole to extend through this substrate;
One second conductive hole extends through this adhesion layer to this route line;
One terminal extends this adhesion layer below;
The semiconductor assembly is positioned at this projection top and is overlapped in this projection, perhaps is positioned at this projection below and overlapping with this projection, this semiconductor subassembly electrically connect to this weld pad and this terminal, and hot link to this projection and this pedestal; And
Above-mentioned projection extends through this opening and gets into this through hole to reach this dielectric layer top; This pedestal then extends this adhesion layer and this substrate below; And constitute the conductive path that is positioned between this weld pad and this terminal by this first conductive hole, this route line and this second conductive hole; Wherein this adhesion layer is arranged on this pedestal; And extend in this through hole the breach that is positioned between this projection and this substrate in this pedestal top, in this breach, extend across this dielectric layer, and between between this projection and this dielectric layer and between this pedestal and this substrate.
2. semiconductor chip group body according to claim 1 is characterized in that this semiconductor subassembly is the semiconductor chip; It extends this projection top; Be overlapped in this projection, and electrically connect is to this weld pad, thereby electrically connect is to this terminal; And this semiconductor chip hot link is to this projection, thereby hot link is to this pedestal.
3. semiconductor chip group body according to claim 1; It is characterized in that this semiconductor subassembly is the semiconductor chip, utilize a solid brilliant material to be arranged on this radiating seat; Via a routing electrically connect to this weld pad, and via this solid brilliant material hot link to this projection.
4. semiconductor chip group body according to claim 1 is characterized in that, this adhesion layer contacts this projection and this dielectric layer in this breach, and outside this breach contact this pedestal, this dielectric layer, this route line, this second conductive hole and this terminal.
5. semiconductor chip group body according to claim 1 is characterized in that, this adhesion layer is in this side surface direction covering and around this projection.
6. semiconductor chip group body according to claim 1 is characterized in that this adhesion layer fills up this breach.
7. semiconductor chip group body according to claim 1 is characterized in that this adhesion layer fills up the space between this pedestal and this substrate.
8. semiconductor chip group body according to claim 1 is characterized in that this adhesion layer is overlapped in this terminal.
9. semiconductor chip group body according to claim 1 is characterized in that this adhesion layer extends to the peripheral edge of this group body.
10. semiconductor chip group body according to claim 1 is characterized in that this projection and this pedestal are integrally formed.
11. semiconductor chip group body according to claim 1 is characterized in that, this projection and this adhesion layer are in same plane in this dielectric layer top.
12. semiconductor chip group body according to claim 1 is characterized in that, this projection is a flat-top awl cylindricality, and its diameter is upwards from the flat top of this pedestal to this projection and successively decreases.
13. semiconductor chip group body according to claim 1 is characterized in that, this pedestal and this terminal are in same plane in this adhesion layer below.
14. semiconductor chip group body according to claim 1 is characterized in that, this pedestal covers this projection from the below, support this substrate, and keep at a distance with the peripheral edge of this group body.
15. semiconductor chip group body according to claim 1 is characterized in that this substrate and this projection and this pedestal are kept at a distance.
16. semiconductor chip group body according to claim 1 is characterized in that this substrate is a laminar structure.
17. semiconductor chip group body according to claim 1; It is characterized in that this radiating seat comprises a lid at least, be positioned at an over top of this projection; Cover in abutting connection with the top of this projection and from the top, extend laterally along the top of this side surface direction simultaneously from this projection.
18. semiconductor chip group body according to claim 17 is characterized in that this lid is rectangle or square, and the top of this projection is circular.
19. semiconductor chip group body according to claim 1 is characterized in that this radiating seat comprises a lid at least, and this lid and this weld pad are in same plane in this dielectric layer top.
20. semiconductor chip group body according to claim 1 is characterized in that the material of this radiating seat is a copper.
21. a semiconductor chip group body is used to provide vertical signal route, it is characterized in that comprising:
One adhesion layer has an opening at least;
One radiating seat; At least comprise a projection, a pedestal and a lid, wherein this projection is in abutting connection with this pedestal and integrally formed with this pedestal, and this projection along one upwards direction extend this pedestal top; And make this pedestal and this lid form hot link; This pedestal extends this projection below along one with this downward direction in the opposite direction that makes progress, and along extending laterally from this projection perpendicular to this side surface direction that upwards reaches downward direction, this lid is positioned at an over top of this projection; Cover in abutting connection with the top of this projection and from the top, extend laterally along the top of this side surface direction simultaneously from this projection;
One substrate; Be arranged on this adhesion layer and extend this pedestal top; It comprises first and second conductive layer, one first conductive hole and a dielectric layer at least, this first conductive layer this dielectric layer of contact and extend this dielectric layer top wherein, this second conductive layer this dielectric layer of contact and extend this dielectric layer below and be embedded in this adhesion layer; And has the selected part that a weld pad is included in this first conductive layer; This weld pad this dielectric layer of contact also extends this dielectric layer top, and has the selected part that a route line is included in this second conductive layer, and this route line this dielectric layer of contact also extends this dielectric layer below; This first conductive hole then contacts and extends through the dielectric layer between this first conductive layer and this route line, and has a through hole to extend through this substrate;
One second conductive hole contacts and extends through this adhesion layer to this route line;
One terminal contacts and extends this adhesion layer below;
The semiconductor chip is arranged on this lid, is overlapped in this projection, and electrically connect is to this weld pad, thus electrically connect to this terminal, and this semiconductor chip hot link is to this lid, thus hot link is to this pedestal; And
Above-mentioned projection extends through this opening and gets into this through hole to reach this dielectric layer top; This pedestal then extends this semiconductor chip, this adhesion layer and this substrate below along this downward direction; And cover this semiconductor chip and this projection from the below and support this substrate, constitute the conductive path that is positioned between this weld pad and this terminal by this first conductive hole, this route line and this second conductive hole, wherein this adhesion layer is arranged on this pedestal; And extend in this through hole the breach that is positioned between this projection and this substrate in this pedestal top; In this breach, extend across this dielectric layer, and in this breach between this projection and this dielectric layer, outside this breach then between this pedestal and this substrate; This adhesion layer more covers and around this projection along this side surface direction, and extends to the peripheral edge of this group body.
22. semiconductor chip group body according to claim 21 is characterized in that, this semiconductor chip utilizes a solid brilliant material to be arranged on this lid, via a routing electrically connect to this weld pad, and via this solid brilliant material hot link to this lid.
23. semiconductor chip group body according to claim 21; It is characterized in that; This substrate and this projection and this pedestal are kept at a distance, and fill up the space between this breach and this pedestal and this substrate by this adhesion layer, and this adhesion layer is restricted in the space between this radiating seat and this substrate.
24. semiconductor chip group body according to claim 21 is characterized in that, the top of this projection is circular, and the lid on it is rectangle or square, and this projection is a flat-top awl cylindricality, and its diameter is upwards to this lid from this pedestal and successively decreases.
25. semiconductor chip group body according to claim 21; It is characterized in that; This projection and this adhesion layer and this lid and this weld pad are all in this same plane of coexistence, dielectric layer top, and this pedestal and this terminal are then in this same plane of coexistence, adhesion layer below, and the material of this radiating seat is a copper.
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CN102916107A (en) * 2011-08-05 2013-02-06 柏腾科技股份有限公司 Composite heating panel structure and method for applying the composite heating panel structure to package light emitting diode
CN104269359A (en) * 2014-09-05 2015-01-07 江苏长电科技股份有限公司 Novel quad fat no-lead package process method

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