CN218867084U - Derived type heat radiation structure, fan-out type packaging structure and integrated circuit - Google Patents
Derived type heat radiation structure, fan-out type packaging structure and integrated circuit Download PDFInfo
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- CN218867084U CN218867084U CN202222160842.6U CN202222160842U CN218867084U CN 218867084 U CN218867084 U CN 218867084U CN 202222160842 U CN202222160842 U CN 202222160842U CN 218867084 U CN218867084 U CN 218867084U
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Abstract
The utility model relates to a derivation type heat radiation structure, fan-out type packaging structure and integrated circuit, derivation type heat radiation structure includes the base plate, establish the chip package hole on the base plate first surface, establish the first heat conduction metal layer on chip package hole bottom surface, establish the second heat conduction metal layer on the base plate second surface and establish the heat transfer pole in the base plate, the both ends of heat transfer pole are connected with first heat conduction metal layer and second heat conduction metal layer respectively. The fan-out type packaging structure comprises the lead-out type heat dissipation structure. The integrated circuit comprises the fan-out packaging structure. The application discloses derivation type heat radiation structure, fan-out type packaging structure and integrated circuit for solve the difficult problem of present fan-out type packaging structure heat dissipation, widen the application of fan-out type encapsulation.
Description
Technical Field
The present application relates to the field of electronic technologies, and in particular, to a lead-out heat dissipation structure, a fan-out package structure, and an integrated circuit.
Background
With the continuous development of the packaging technology and the continuous increase of the demand of function integration, the function of a single chip becomes a short board, and the multi-chip packaging can not only realize the integration of multiple functions, but also realize the integration of different wafer process nodes, and becomes a great trend of the development of the packaging technology at present. The multi-Chip integration has various implementation forms such as Flip Chip (Flip Chip), system in Package (System in Package), fan Out Wafer Level Package (FOWLP), and the like. The fanout wafer level package has the advantages of no need of a substrate, flexible packaging mode, unlimited chip size, capability of multi-chip combined packaging, capability of sharing a production line with the traditional wafer level package (wafer level package), and the like, and is more and more concerned by the packaging industry, and the growth trend is very rapid in recent years. Meanwhile, due to the adoption of fan-out type packaging, the size of a chip can be reduced, the required number of wafers is reduced, and the fan-out type packaging has great advantages under the background that the wafer capacity and the substrate capacity are short. However, because the fan-out package is protected by plastic package materials, the back heat dissipation channel of the chip is greatly affected, which brings great challenges to the heat dissipation performance of the chip and also limits the possibility that the high-power chip adopts multi-chip fan-out wafer level package. For the heat dissipation problem, many schemes have been proposed in the industry to improve the heat dissipation capability of the package, such as attaching a heat sink to the back of the chip, but due to the combination problem and the interface problem, the heat dissipation improvement has not achieved an ideal effect.
SUMMERY OF THE UTILITY MODEL
In order to solve the problem of difficulty in heat dissipation of the fan-out type packaging process, the application provides a lead-out type heat dissipation structure, a fan-out type packaging structure and an integrated circuit, and the lead-out type heat dissipation structure, the fan-out type packaging structure and the integrated circuit are used for solving the problem of difficulty in heat dissipation of the existing fan-out type packaging structure and widening the application field of fan-out type packaging.
The above object of the present application is achieved by the following technical solutions:
in a first aspect, the present application provides a lead-out heat dissipation structure, including:
a substrate;
a chip packaging hole arranged on the first surface of the substrate;
the first heat conduction metal layer is arranged on the bottom surface of the chip packaging hole;
the second heat-conducting metal layer is arranged on the second surface of the substrate;
and the heat transfer rod is arranged in the substrate, and two ends of the heat transfer rod are respectively connected with the first heat-conducting metal layer and the second heat-conducting metal layer.
In one possible implementation of the first aspect, the number of the heat transfer rods is plural.
In one possible implementation manner of the first aspect, the projections of the plurality of heat transfer bars on the bottom surface of the chip packaging hole are uniformly arranged.
In one possible implementation of the first aspect, the number of heat transfer rods is one;
the projection area of the heat transfer rod on the bottom surface of the chip packaging hole is smaller than or equal to the projection area of the first heat conduction metal layer on the bottom surface of the chip packaging hole.
In one possible implementation manner of the first aspect, the number of the second heat-conductive metal layers is one.
In one possible implementation manner of the first aspect, the number of the second heat-conducting metal layers is multiple;
a second layer of thermally conductive metal is in contact with at least one of the first layers of thermally conductive metal via the heat transfer rods.
In a second aspect, the present application provides a fan-out package structure, including the lead-out heat dissipation structure as described in the first aspect and any implementation manner of the first aspect.
In a third aspect, the present application provides an integrated circuit comprising a fan-out package structure as described in the second aspect.
Overall speaking, the derivation type heat radiation structure, fan-out type packaging structure and integrated circuit that this application provided have used active heat conduction mode to carry out the transfer with the heat that produces in the chip work, compare in the heat diffusion mode of passive form, and the radiating effect of this kind of derivation type heat radiation mode is better. Because the metal has good thermal conductivity, the second heat-conducting metal layer can be rapidly cooled by means of air cooling, water cooling and the like, so that the temperature of the first heat-conducting metal layer and the temperature of the heat transfer rod can be maintained in a lower interval, and the temperature of the chip in the chip packaging hole can be maintained in a lower interval.
Drawings
Fig. 1 is a schematic view of a lead-out heat dissipation structure provided in the present application.
Fig. 2 is a schematic structural diagram of a chip package hole on a substrate provided by the present application.
Fig. 3 is a schematic diagram of back side metallization of a first chip and a second chip provided in the present application.
Fig. 4 is a schematic diagram of plastic packaging of a die according to the present application.
Fig. 5 is a schematic diagram of one embodiment of a perforation provided herein.
Fig. 6 and 7 are schematic diagrams of backside metallization of a reconstituted wafer with through-holes according to the present disclosure.
In the drawing, 1, a first chip, 2, a second chip, 11, a substrate, 12, a chip package hole, 13, a first heat conductive metal layer, 14, a second heat conductive metal layer, 15, a heat transfer rod, 121, a first passivation layer, 131, a first pad, 221, a second passivation layer, 231, a second pad, 611, a first insulating layer, 612, a redistribution layer, 613, a second insulating layer, 614, a UBM layer, 711, and a solder ball.
Detailed Description
The technical solution of the present application will be described in further detail below with reference to the accompanying drawings.
For a clearer understanding of the technical solutions in the present application, first, a simple description is made of a fan-out package structure.
The fan-out package generally means that under wafer level/panel level packaging, the packaging area is different from die, and packaging of a substrate is not needed, the core element of the fan-out package is an RDL rewiring layer on a chip, and the RDL replaces the function of transmitting signals on a lower substrate of the traditional packaging, so that the fan-out package can be free of the substrate and the height of a finished chip is lower.
Fan-out packages can increase I/O density because the package structure can be expanded in area to bring wires to the outside by RDL, which can put down enough solder balls to increase I/O density. Taking the integrated circuit InFO packaging process as an example, the process does not use a substrate nor a heat sink cap on top.
The main structure of the fan-out package is supported and radiated by a circle of epoxy resin and a top epoxy resin film, which brings a problem because EMC/LMC is far less firm than a substrate, warpage is easy to occur in the packaging process, and the yield is further influenced, and many difficulties in the whole fan-out packaging process are generated around the problem.
Referring to fig. 1 and 2, for the led-out heat dissipation structure disclosed in the present application, the heat dissipation structure is composed of a substrate 11, chip packaging holes 12, a first heat conducting metal layer 13, a second heat conducting metal layer 14, heat transfer rods 15, and the like, where for convenience of description, an upper surface and a lower surface of the substrate 11 when the substrate 11 is horizontally placed are referred to as a first surface of the substrate 11 and a second surface of the substrate 11, respectively.
The first surface of the substrate 11 is provided with chip packaging holes 12, and the chip packaging holes 12 are used for placing chips. The first heat conducting metal layer 13 is disposed on the bottom surface of the chip packaging hole 12 and contacts with the chip, and functions to conduct out heat generated during the operation of the chip.
The second heat-conductive metal layer 14 is disposed on the second surface of the substrate 11 and connected to the first heat-conductive metal layer 13 through the heat-transfer rod 15, and functions to transfer heat absorbed by the first heat-conductive metal layer 13 to the second heat-conductive metal layer 14 and then to radiate the heat from the second heat-conductive metal layer 14.
The heat transfer rod 15 is disposed in the substrate 11, and both ends thereof are connected to the first and second heat- conductive metal layers 13 and 14, respectively.
The number of the heat transfer rods 15 may be one or multiple, and the specific number needs to be determined according to the heat generation amount, for example, the power consumption of the product is large, the generated heat amount is relatively large, a larger heat dissipation area is needed, and in this case, the number or the diameter of the heat transfer rods 15 may be increased.
When the number of the heat transfer rods 15 is one, the projection area of the heat transfer rods 15 on the bottom surface of the chip packaging hole 12 is smaller than or equal to the projection area of the first heat-conducting metal layer 13 on the bottom surface of the chip packaging hole 12.
When the number of the heat transfer rods 15 is plural, projections of the plural heat transfer rods 15 on the bottom surface of the chip packaging hole 12 are uniformly arranged.
The number of the second heat conductive metal layers 14 may be one or more.
When the number of the second heat-conducting metal layers 14 is one, the second heat-conducting metal layers are simultaneously connected to the first heat-conducting metal layers 13 in the plurality of chip-packaging holes 12 on the substrate 11 through the heat-transfer rods 15.
When the number of the second heat-conducting metal layers 14 is plural, one second heat-conducting metal layer 14 is connected to the first heat-conducting metal layer 13 in at least one chip-packaging hole 12 on the substrate 11 through the heat-transfer rod 15.
Overall speaking, the fan-out type packaging structure that this application provided has used active heat conduction mode to carry out the heat that produces in with chip work and has shifted, compares in the heat diffusion mode of passive form, and the radiating effect of this kind of derivation type radiating mode is better.
Because the metal has good thermal conductivity, the second heat-conducting metal layer 14 can be rapidly cooled by means of air cooling, water cooling and the like, so that the temperatures of the first heat-conducting metal layer 13 and the heat transfer rod 15 can be maintained in a lower interval, and the temperature of the chip in the chip packaging hole 12 can be maintained in a lower interval.
The lead-out heat dissipation structure of the present application is further described below in connection with the production of fan-out packages.
Referring to fig. 1, two or more wafers are provided, each wafer including a plurality of identical chip substrates, each chip substrate having a dicing channel between adjacent chip substrates, each chip substrate including a first surface and a second surface opposite to each other, the first surface having a bonding pad and a passivation layer covering the first surface, the passivation layer having a first window exposing the bonding pad.
Referring to fig. 3, the first chip 1 is located on one wafer, the second chip 2 is located on another wafer, and the first chip 1 has a first passivation layer 121 covering the first surface and a first pad 131 not covered by the passivation layer.
In some possible implementations, the materials of the first passivation layer 121 are silicon nitride and silicon dioxide.
In some possible implementations, the material of the first pad 131 may be an aluminum copper alloy, copper, or other conductive material.
The second chip 2 has a second passivation layer 221 covering the first surface and a second pad 231 not covered by the passivation layer.
In some possible implementations, the material of the second passivation layer 221 is silicon nitride and silicon dioxide.
In some possible implementations, the material of the second pad 231 may be an aluminum copper alloy, copper, or other conductive material.
The second surface of the wafer where the first chip 1 and the second chip 2 are located is thinned, generally, the original wafer thickness is 725um, before back metallization is performed, the wafer needs to be thinned to a required thickness, generally, the thickness is 70-120um, the thinning method is to use mechanical grinding, and form the first heat-conducting metal layer 13 through back metallization, and the first heat-conducting metal layer 13 covers the whole thinned second surface of the wafer.
In some possible implementations, the material of the first heat-conducting metal layer 13 may be a heat-conducting material such as copper, silver, or gold.
The method for back metallization comprises the following steps: the first surface of the thinned wafer is inverted and adhered to the glass carrier plate through glue to expose the thinned second surface, the thinned second surface of the wafer is deposited through a physical vapor deposition method (such as physical sputtering) to form a first seed layer, the seed layer is made of titanium, titanium tungsten and the like, the seed layer has the function of forming a plurality of 'nuclear centers' on the substrate, and the phenomenon that electroplated metal is unevenly distributed to form island-shaped distribution under the condition that no seed layer exists is avoided.
And then, electroplating the first heat-conducting metal layer 13 on the surface of the first seed layer by using methods of gluing, exposing, developing and chemical plating, wherein the first heat-conducting metal layer 13 can increase the heat dissipation area and improve the heat dissipation efficiency.
Then, wafer dicing is performed along dicing streets between adjacent chip substrates on the same wafer, as shown in fig. 3, a plurality of single-grain chip structures, i.e., grains, are formed, and the second surfaces of the grains are completely covered by the first heat-conducting metal layer 13.
Referring to fig. 4, next, a plurality of cut crystal grains are placed on a glass carrier for wafer reconfiguration, first surfaces of the crystal grains are downward attached to the glass carrier by glue, and after the attachment, plastic packaging is performed, wherein the plastic packaging process includes:
firstly, filling a plastic package material on the surface of a mounted wafer, then melting and converting the plastic package material into a flowing state through high temperature and high pressure, covering and protecting the surfaces of the wafer except the first surface adhered to the glass carrier plate by the flowing plastic package material, cooling and performing post-curing to form a plastic package layer, namely the substrate 11 mentioned above.
The periphery of the crystal grain is subjected to stress protection through plastic packaging, the glass carrier plate is removed after the plastic packaging is finished, and the first surface of the crystal grain is upward to form a new reconstituted wafer, as shown in fig. 4.
And continuously carrying out mechanical grinding and thinning on the second surface of the reconstructed wafer to a specified thickness, and forming a plurality of through holes on the thinned flat surface. In some possible implementations, the method of forming the perforations is:
the through holes are formed by a physical laser through hole method, the number and the diameter of the through holes are defined according to actual requirements, for example, the power consumption of a product is large, the generated heat is relatively large, a larger heat dissipation area is needed, and the number or the diameter of the through holes can be increased; the position of the perforation reaches the first heat conductive metal layer 13 of the original die as shown in fig. 5.
Referring to fig. 6, back metallization is performed again on the back of the thinned and punched reconstituted wafer to form a second heat-conducting metal layer 14, and the manufacturing method of the second heat-conducting metal layer 14 is the same as that of the first heat-conducting metal layer 13, and details thereof are not repeated here.
And growing a wiring layer on the first surface of the reconstituted wafer, wherein the wiring layer can be formed by a method of chemical plating, physical deposition or physical evaporation. The first surface is electrically connected to the first surface, and the first surface sequentially includes a first insulating layer 611, a redistribution layer 612, a second insulating layer 613, and an UBM (under ball metal) layer 614, as shown in fig. 1.
In some possible implementations, the material of the first insulating layer 611 may be polyphenylene oxide, polyimide, epoxy resin, etc., and is formed on the surface of the reconstituted wafer by means of gluing, exposing, developing and curing.
In some possible implementations, the material of the redistribution layer 612 may be a conductive material such as copper, silver, or gold, and is formed by gluing, exposing, developing, electroplating/physical sputtering, or evaporation.
In some possible implementations, the material and formation method of the second insulating layer 613 are the same as those of the first insulating layer.
In some possible implementations, the material and formation method of UBM layer 614 are identical to that of re-routing layer 612.
The application also discloses a fan-out type packaging structure, which comprises any one of the lead-out type heat dissipation structures recorded in the contents.
The application also discloses an integrated circuit, which comprises the fan-out type packaging structure recorded in the content.
The embodiments of the present invention are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereby, so: all equivalent changes made according to the structure, shape and principle of the present application shall be covered by the protection scope of the present application.
Claims (8)
1. A lead-out heat dissipation structure, comprising:
a substrate (11);
a chip packaging hole (12) provided on the first surface of the substrate (11);
a first heat-conducting metal layer (13) arranged on the bottom surface of the chip packaging hole (12);
a second heat-conducting metal layer (14) provided on the second surface of the substrate (11);
and the heat transfer rod (15) is arranged in the substrate (11), and two ends of the heat transfer rod (15) are respectively connected with the first heat-conducting metal layer (13) and the second heat-conducting metal layer (14).
2. A lead-out heat dissipation structure according to claim 1, wherein the number of heat transfer rods (15) is plural.
3. The lead-out heat dissipation structure according to claim 2, wherein projections of the plurality of heat transfer bars (15) on the bottom surface of the chip packaging hole (12) are uniformly arranged.
4. A lead-out heat dissipation structure according to claim 1, wherein the number of heat transfer rods (15) is one;
the projection area of the heat transfer rod (15) on the bottom surface of the chip packaging hole (12) is smaller than or equal to the projection area of the first heat-conducting metal layer (13) on the bottom surface of the chip packaging hole (12).
5. The lead-out heat dissipation structure according to any one of claims 1 to 4, wherein the number of the second thermally conductive metal layers (14) is one.
6. The lead-out heat dissipation structure according to any one of claims 1 to 4, wherein the number of the second heat-conductive metal layers (14) is plural;
a second layer (14) of heat-conducting metal is connected to the at least one first layer (13) of heat-conducting metal by means of heat-transfer rods (15).
7. A fan-out package structure comprising the lead-out heat dissipation structure of any one of claims 1 to 6.
8. An integrated circuit comprising the fan-out package structure of claim 7.
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| CN2022102176440 | 2022-03-08 | ||
| CN202210217644.0A CN114334672A (en) | 2022-03-08 | 2022-03-08 | Fan-out type packaging structure and packaging method |
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| CN205984951U (en) * | 2016-08-30 | 2017-02-22 | 华天科技（昆山）电子有限公司 | Fan -out packaging structure of two -sided subsides dress |
| CN106531700B (en) * | 2016-12-06 | 2019-05-28 | 江阴长电先进封装有限公司 | A kind of chip-packaging structure and its packaging method |
| CN107123601B (en) * | 2017-05-27 | 2020-03-17 | 华进半导体封装先导技术研发中心有限公司 | High-heat-dissipation device packaging structure and board-level manufacturing method |
| CN107134440A (en) * | 2017-06-21 | 2017-09-05 | 中芯长电半导体（江阴）有限公司 | Fan-out-type wafer level packaging structure and preparation method thereof |
| CN112509991A (en) * | 2020-09-10 | 2021-03-16 | 成都芯源系统有限公司 | Integrated circuit package structure, integrated circuit package unit and related manufacturing method |
| CN112185827A (en) * | 2020-10-20 | 2021-01-05 | 上海艾为电子技术股份有限公司 | Chip wafer, chip packaging structure and packaging method |
| CN112151472A (en) * | 2020-11-24 | 2020-12-29 | 江阴长电先进封装有限公司 | Chip packaging structure and packaging method thereof |
| CN113314480A (en) * | 2021-06-29 | 2021-08-27 | 成都氮矽科技有限公司 | Panel-level fan-out type packaging structure and method for silicon-based GaN HEMT device |
| CN114005812A (en) * | 2021-10-28 | 2022-02-01 | 华进半导体封装先导技术研发中心有限公司 | Fan-out type packaging structure and construction method thereof |
| CN114141637A (en) * | 2021-12-01 | 2022-03-04 | 甬矽电子(宁波)股份有限公司 | Fan-out type chip packaging method and fan-out type chip packaging structure |
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