CN112053962B - System-level stack package and preparation method thereof - Google Patents
System-level stack package and preparation method thereof Download PDFInfo
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- CN112053962B CN112053962B CN202010958922.9A CN202010958922A CN112053962B CN 112053962 B CN112053962 B CN 112053962B CN 202010958922 A CN202010958922 A CN 202010958922A CN 112053962 B CN112053962 B CN 112053962B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Abstract
The invention discloses a system-level stack package and a preparation method thereof, wherein the method comprises the following steps: forming a first semiconductor packaging block, then forming a second semiconductor packaging block, providing a flexible circuit substrate, then attaching one first semiconductor packaging block to a middle joint area of the flexible circuit substrate, then attaching two second semiconductor packaging blocks to two end joint areas of the flexible circuit substrate respectively, then bending upwards the bending area, enabling each second semiconductor packaging block to be attached to the side surface of the first semiconductor packaging block, so as to obtain a first semiconductor stacked packaging block, providing a heat dissipation plate, arranging one first semiconductor stacked packaging block on each heat dissipation bulge of the heat dissipation plate, then arranging a circuit substrate on the upper surface and the lower surface of the heat dissipation plate respectively, and enabling each circuit substrate to be electrically connected with a plurality of first semiconductor stacked packaging blocks.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a system-level stack package and a preparation method thereof.
Background
On the premise that the requirements for the functions and the performance of the semiconductor package of portable intelligent systems such as a smart phone, a smart watch, a smart bracelet and a portable computer are continuously improved, the size and the weight of the semiconductor package are required to be continuously reduced, and the functions of the whole semiconductor package, namely system-in-package, are generally required to be realized in a smaller space. Given the complexity of system-in-package and the diversity of semiconductor dies, different types of chips, devices and sub-assemblies may be included in a system-in-package, and thus low cost, high heat dissipation, high reliability, high density and fast operating speed are targets of system-in-package. In which, attention has been paid to how to improve the structure of the conventional system-on-package to ensure the integration and improve the heat dissipation performance.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies of the prior art and providing a system-in-package and a method for fabricating the same.
In order to achieve the above object, the present invention provides a method for manufacturing a system-in-package stack package, comprising the following steps:
(1) providing a first carrier, forming a first rewiring layer on the first carrier, forming a second rewiring layer on the first rewiring layer, then arranging a first semiconductor chip on the second rewiring layer, then forming one or more first conductive blocks on the second rewiring layer on two sides of the first semiconductor chip, wherein the height of each first conductive block is smaller than that of the first semiconductor chip, and then forming a first molding resin layer on the second rewiring layer, wherein the first molding resin layer completely wraps the first conductive blocks and the first semiconductor chip; and then, thinning the first molding resin layer to expose the back surface of the first semiconductor chip, then forming one or more first grooves on two opposite side surfaces of the first molding resin layer, wherein the first grooves expose the upper surfaces of the corresponding first conductive blocks, then removing the first carrier plate, and then forming second conductive blocks on the first redistribution layer to obtain a first semiconductor packaging block.
(2) Providing a second carrier, forming a third redistribution layer on the second carrier, arranging a second semiconductor chip on the third redistribution layer, and then forming a second molding resin layer on the third redistribution layer, wherein the second molding resin layer completely wraps the second semiconductor chip; and then, thinning the second molding resin layer to expose the back surface of the second semiconductor chip, then forming one or more second grooves on one side of the second molding resin layer, forming a first metal pillar in each second groove to electrically connect the first metal pillar with the third redistribution layer, wherein the height of the first metal pillar is greater than that of the second semiconductor chip, then removing the second carrier plate, and then forming a third conductive block on the third redistribution layer to obtain a second semiconductor package block.
(3) Providing a flexible circuit substrate, wherein the flexible circuit substrate comprises a middle joint area, two end joint areas and a bending area which is positioned in the middle joint area and the end joint areas, and the bending area is not provided with a conductive circuit layer.
(4) And then, attaching one first semiconductor packaging block to the middle joint area of the flexible circuit substrate, then attaching two second semiconductor packaging blocks to the two end joint areas of the flexible circuit substrate respectively, and then bending the bending area upwards to enable each second semiconductor packaging block to be attached to the side surface of the first semiconductor packaging block, enable each first metal column to be embedded into the corresponding first groove, enable each first metal column to be electrically connected with the corresponding first conductive block, and enable the first semiconductor packaging block and the two second semiconductor packaging blocks to define a cavity so as to obtain a first semiconductor stacked packaging block.
(5) And then providing a heat dissipation plate, wherein a plurality of heat dissipation bulges arranged in a matrix manner are arranged on the upper surface and the lower surface of the heat dissipation plate, and then a first semiconductor stacked packaging block is arranged on each heat dissipation bulge, so that each heat dissipation bulge is embedded into the corresponding concave cavity.
(6) And then, respectively arranging a circuit substrate on the upper surface and the lower surface of the heat dissipation plate, so that each circuit substrate is electrically connected with a plurality of first semiconductor stacked packaging blocks.
Preferably, in the step (1), the first redistribution layer and the second redistribution layer each include a multilayer dielectric layer and a multilayer metal layer, the dielectric layer is made of one or a combination of two or more of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, the metal layer is made of one or a combination of two or more of copper, aluminum, palladium, nickel, gold, silver and titanium, and the first groove is formed by a laser ablation process.
Preferably, in the step (1), the first conductive block is formed by sputtering, evaporation, chemical vapor deposition, electroplating or chemical plating, the material of the first conductive block is one or a combination of two or more of copper, aluminum, titanium and nickel, and the second conductive block includes a metal pillar and a solder ball.
Preferably, in the step (2), the third redistribution layers each include a plurality of dielectric layers and a plurality of metal layers, the dielectric layers are made of one or a combination of two or more of epoxy resin, silica gel, phosphosilicate glass, polyvinyl alcohol and organic glass, the metal layers are made of one or a combination of two or more of copper, aluminum, palladium, nickel, gold, silver and titanium, the first metal posts are made of one or a combination of two or more of copper, aluminum, nickel and titanium, and the third conductive blocks include metal posts and solder balls.
Preferably, in the step (4), before the bending region is bent, underfill resin layers are formed in a gap between the first semiconductor package block and the middle bonding region of the flexible circuit substrate and a gap between the second semiconductor package block and the end bonding region of the flexible circuit substrate.
Preferably, in the step (4), the first metal pillar and the corresponding first conductive block are electrically connected by a conductive adhesive layer.
Preferably, in the step (4), a first heat-conductive interface layer, a second heat-conductive interface layer, and a third heat-conductive interface layer are formed in the cavity in this order.
Preferably, the upper surface and the lower surface of the second heat conduction interface layer are both uneven surfaces, and the heat conductivity coefficient of the second heat conduction interface layer is greater than the heat conductivity coefficient of the first heat conduction interface layer and greater than the heat conductivity coefficient of the third heat conduction interface layer.
The invention also provides a system-level stack package prepared by the method.
Compared with the prior art, the invention has the following advantages:
in the manufacturing process of the system-on-package of the present invention, by forming the first conductive bumps in the first semiconductor package blocks, and one or more first grooves are formed on both opposite side surfaces of the first molding resin layer, the first grooves exposing upper surfaces of the respective first conductive bumps, and one or more second grooves are formed at one side of the second molding resin layer of the second semiconductor package block, and forming a first metal pillar in each of the second grooves, and embedding the first metal pillar into the first groove to realize a first semiconductor package block and a second semiconductor package block, and then can not set up the conducting wire layer on the bending region of flexible circuit base plate, and then can avoid because flexible circuit base plate buckles and lead to the problem that the conducting wire layer became invalid, and then guaranteed the validity and the stability of system level stack encapsulation. The method comprises the steps of attaching one first semiconductor packaging block to the middle joint area of the flexible circuit substrate, attaching two second semiconductor packaging blocks to the two end joint areas of the flexible circuit substrate respectively, bending the bending area upwards to enable each second semiconductor packaging block to be attached to the side surface of the first semiconductor packaging block, limiting a cavity by the first semiconductor packaging block and the two second semiconductor packaging blocks to obtain a first semiconductor stacked packaging block, further providing a heat dissipation plate, arranging a plurality of heat dissipation bulges in a matrix arrangement on the upper surface and the lower surface of the heat dissipation plate, arranging one first semiconductor stacked packaging block on each heat dissipation bulge to enable each heat dissipation bulge to be embedded into the corresponding cavity, and arranging a plurality of heat conduction interface layers in the cavity, the arrangement of the structure can enable the stacked package to dissipate heat quickly on one hand, and can improve the integration level of the stacked package on the other hand.
Drawings
Fig. 1-5 are schematic structural diagrams of various manufacturing processes of a system-on-package in an embodiment of the invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first feature on or over a second feature, including embodiments in which the first feature and the second feature are formed so as to be in direct contact, and also including embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, various examples of the disclosure may use repeated reference characters and/or words. The repeated symbols or words are for purposes of simplicity and clarity, and
and are not intended to limit the relationship between the various embodiments and/or the appearance structures.
Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, may be used herein for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 5, the present embodiment provides a system-in-package and a method for fabricating the same.
In a specific embodiment, as shown in fig. 1, first, step (1) is performed, a first carrier is provided, a first redistribution layer 101 is formed on the first carrier, a second redistribution layer 102 is formed on the first redistribution layer 101, a first semiconductor chip 103 is disposed on the second redistribution layer 102, one or more first conductive bumps 104 are formed on the second redistribution layer 102 on both sides of the first semiconductor chip 103, the height of the first conductive bump 104 is smaller than that of the first semiconductor chip 103, a first molding resin layer 105 is formed on the second redistribution layer 100, and the first molding resin layer 105 completely wraps the first conductive bump 104 and the first semiconductor chip 103; then, a thinning process is performed on the first molding resin layer 105 to expose the back surface of the first semiconductor chip 103, then one or more first grooves 106 are formed on both opposite side surfaces of the first molding resin layer 105, the first grooves 106 expose the upper surfaces of the corresponding first conductive bumps 104, then the first carrier board is removed, and then second conductive bumps 107 are formed on the first redistribution layer 101 to obtain a first semiconductor package block.
In the step (1), the first redistribution layer 101 and the second redistribution layer 102 each include a plurality of dielectric layers and a plurality of metal layers, the dielectric layers are made of one or a combination of two or more of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, the metal layers are made of one or a combination of two or more of copper, aluminum, palladium, nickel, gold, silver and titanium, and the first grooves are formed by a laser ablation process.
In the step (1), the first conductive block 104 is formed by sputtering, evaporation, chemical vapor deposition, electroplating or chemical plating process, the material of the first conductive block 104 is one or a combination of two or more of copper, aluminum, titanium and nickel, and the second conductive block includes a metal column and a solder ball.
In a specific embodiment, a first carrier board is provided, which may be a metal carrier board, a first redistribution layer 101 is formed on the first carrier board, a second redistribution layer 102 is formed on the first redistribution layer 101, each of the first redistribution layer 101 and the second redistribution layer 102 includes multiple layers of dielectric and multiple layers of metal, the dielectric is specifically silicon oxide, the metal layer is a copper layer, an aluminum layer or a copper aluminum alloy layer, a first semiconductor chip 103 is then disposed on the second redistribution layer 102, the first semiconductor chip 103 is electrically connected to the second redistribution layer 102, one or more first conductive blocks 104 are then formed on the second redistribution layer 102 on both sides of the first semiconductor chip 103, the first conductive blocks 104 are copper pillars formed by an electroplating process, the height of the copper pillars is smaller than the height of the first semiconductor chip 103, next, a first molding resin layer 105, which may be specifically an epoxy resin layer, is formed through a molding process.
Then, a thinning process is performed on the first molding resin layer 105, specifically, a CMP process may be performed to expose the back surface of the first semiconductor chip 103, then one or more first grooves 106 are formed on both opposite side surfaces of the first molding resin layer 105, the first grooves 106 expose the upper surfaces of the corresponding first conductive bumps 104, specifically, the first grooves 106 are formed by a laser ablation process, then the first carrier board is removed, and then second conductive bumps 107 are formed on the first redistribution layer 101, where the second conductive bumps 107 include metal pillars and solder balls, so as to obtain a first semiconductor package.
In a specific embodiment, as shown in fig. 2, step (2) is followed by providing a second carrier board, forming a third redistribution layer 201 on the second carrier board, disposing a second semiconductor chip 202 on the third redistribution layer 201, and then forming a second molding resin layer 203 on the third redistribution layer 201, wherein the second molding resin layer 203 completely wraps the second semiconductor chip 202; then, a thinning process is performed on the second molding resin layer 203 to expose the back surface of the second semiconductor chip 202, then one or more second grooves 204 are formed on one side of the second molding resin layer 203, a first metal pillar 205 is formed in each of the second grooves 204 to electrically connect the first metal pillar 205 with the third redistribution layer 201, the height of the first metal pillar 205 is greater than that of the second semiconductor chip 202, then the second carrier is removed, and then a third conductive bump 206 is formed on the third redistribution layer 201 to obtain a second semiconductor package.
In the step (2), the third redistribution layer 201 includes multiple layers of dielectric layers and multiple layers of metal layers, the dielectric layers are made of one or a combination of two or more of epoxy resin, silica gel, phosphosilicate glass, polyvinyl alcohol, and organic glass, the metal layers are made of one or a combination of two or more of copper, aluminum, palladium, nickel, gold, silver, and titanium, the first metal pillar 205 is made of one or a combination of two or more of copper, aluminum, nickel, and titanium, and the third conductive block 206 includes a metal pillar and a solder ball.
In a specific embodiment, a second carrier board is provided, which may be a metal carrier board, a third redistribution layer 201 is formed on the second carrier board, the third redistribution layer 201 includes multiple layers of dielectric, specifically epoxy resin, and multiple layers of metal, specifically copper, then a second semiconductor chip 202 is disposed on the third redistribution layer 201, the second semiconductor chip 202 is electrically connected to the third redistribution layer 201, and then a second molding resin layer 203, which may be specifically epoxy resin, is formed through a molding process.
Then, a thinning process is performed on the second molding resin layer 203 to expose the back surface of the second semiconductor chip 202, one or more second grooves 204 are then formed in one side of the second molding resin layer 203, and in particular, the second grooves 204 are formed by a laser ablation process, then, a first metal pillar 205 is formed in each of the second grooves 204, so that the first metal pillar 205 is electrically connected to the third redistribution layer 201, the height of the first metal pillar 205 is greater than the height of the second semiconductor chip 202, and in particular, the material of the first metal pillar 205 may include copper, and the first metal pillar 205 is formed through an electroplating process, then, the second carrier is removed, and then a third conductive block 206 is formed on the third redistribution layer 201, the third conductive bumps 206 include metal pillars and solder balls to obtain second semiconductor package bumps.
In a specific embodiment, as shown in fig. 3, step (3) is performed to provide a flexible circuit board 300, where the flexible circuit board 300 includes a middle bonding area, two end bonding areas, and a bending area located at the middle bonding area and the end bonding areas, and no conductive trace layer is disposed on the bending area.
In a specific embodiment, the flexible circuit substrate 300 includes an organic body and a conductive circuit layer on the organic body, more specifically, the organic body may include organic materials such as polyimide resin, epoxy resin, phenol resin, BCB resin, etc., and the conductive circuit layer includes a metal aluminum wiring pattern or a metal copper wiring pattern.
In a specific embodiment, as shown in fig. 3, step (4) is performed, and then one first semiconductor package block is mounted on the middle bonding area of the flexible circuit substrate 300, and then two second semiconductor package blocks are mounted on the two end bonding areas of the flexible circuit substrate 300, respectively, and then the bending area is bent upward, so that each second semiconductor package block is mounted on the side surface of the first semiconductor package block, so that each first metal pillar 205 is embedded in the corresponding first groove 106, so that each first metal pillar 205 is electrically connected to the corresponding first conductive bump 104, and the first semiconductor package block and the two second semiconductor package blocks define a cavity 400, so as to obtain a first semiconductor stacked package block.
In the step (4), before the bending region is bent, underfill resin layers are formed in gaps between the first semiconductor package blocks and the middle bonding region of the flexible circuit substrate and gaps between the second semiconductor package blocks and the end bonding regions of the flexible circuit substrate, where the underfill resin layers may be one or more of silicone rubber, cyclic olefin polymer, liquid crystal polymer, and rubber.
In the step (4), the first metal pillar 205 and the corresponding first conductive block 104 are connected by a conductive adhesive layer, for example, the conductive adhesive layer may be a conductive silver paste.
In step (4), a first heat-conducting interface layer, a second heat-conducting interface layer, and a third heat-conducting interface layer (not shown) are formed in the cavity 400, which are stacked in this order. More specifically, the upper surface and the lower surface of the second heat conduction interface layer are both uneven surfaces, and the heat conductivity coefficient of the second heat conduction interface layer is greater than the heat conductivity coefficient of the first heat conduction interface layer and greater than the heat conductivity coefficient of the third heat conduction interface layer.
In a specific embodiment, the materials of the first, second, and third thermal interface layers may include silicon, aluminum oxide, aluminum nitride, boron nitride, or other suitable materials, and the second thermal interface layer further includes fillers with higher thermal conductivity such as metal particles, graphite, graphene, carbon nanotubes, and the like, so that the thermal conductivity of the second thermal interface layer is greater than the thermal conductivity of the first thermal interface layer and greater than the thermal conductivity of the third thermal interface layer.
In a specific embodiment, as shown in fig. 4, step (5) is performed, and then a heat dissipation plate 500 is provided, wherein a plurality of heat dissipation bumps 501 are disposed on the upper surface and the lower surface of the heat dissipation plate 500 in a matrix arrangement, and then a first semiconductor stacked package block is disposed on each heat dissipation bump 501, such that each heat dissipation bump 501 is embedded into a corresponding cavity 400.
In the step (5), the heat dissipation plate 500 has an inlet and an outlet, and a fluid passage is formed inside the heat dissipation plate to facilitate a heat dissipation medium to pass through the heat dissipation plate.
In a specific embodiment, as shown in fig. 5, step (6) is performed next, and then a circuit substrate 600 is disposed on the upper surface and the lower surface of the heat dissipation plate 500, respectively, so that each of the circuit substrates 600 electrically connects a plurality of the first semiconductor stacked packages.
In a specific embodiment, the circuit substrate 600 is electrically connected to the first semiconductor stack package through a conductive solder.
As shown in fig. 5, the present invention also provides a system-in-package stack package prepared by the above method.
In another embodiment, the present invention provides a method for manufacturing a system-on-package, including the steps of:
(1) providing a first carrier, forming a first rewiring layer on the first carrier, forming a second rewiring layer on the first rewiring layer, then arranging a first semiconductor chip on the second rewiring layer, then forming one or more first conductive blocks on the second rewiring layer on two sides of the first semiconductor chip, wherein the height of each first conductive block is smaller than that of the first semiconductor chip, and then forming a first molding resin layer on the second rewiring layer, wherein the first molding resin layer completely wraps the first conductive blocks and the first semiconductor chip; and then, performing thinning treatment on the first molding resin layer to expose the back surface of the first semiconductor chip, then forming one or more first grooves on two opposite side surfaces of the first molding resin layer, wherein the first grooves expose the upper surfaces of the corresponding first conductive blocks, then removing the first carrier plate, and then forming second conductive blocks on the first redistribution layer to obtain a first semiconductor packaging block.
(2) Providing a second carrier, forming a third wiring layer on the second carrier, arranging a second semiconductor chip on the third wiring layer, and then forming a second molding resin layer on the third wiring layer, wherein the second molding resin layer completely wraps the second semiconductor chip; and then, thinning the second molding resin layer to expose the back surface of the second semiconductor chip, then forming one or more second grooves on one side of the second molding resin layer, forming a first metal pillar in each second groove to electrically connect the first metal pillar with the third redistribution layer, wherein the height of the first metal pillar is greater than that of the second semiconductor chip, then removing the second carrier plate, and then forming a third conductive block on the third redistribution layer to obtain a second semiconductor package block.
(3) Providing a flexible circuit substrate, wherein the flexible circuit substrate comprises a middle joint area, two end joint areas and a bending area which is positioned in the middle joint area and the end joint areas, and the bending area is not provided with a conductive circuit layer.
(4) And then, attaching one first semiconductor packaging block to the middle joint area of the flexible circuit substrate, then attaching two second semiconductor packaging blocks to the two end joint areas of the flexible circuit substrate respectively, and then bending the bending area upwards to enable each second semiconductor packaging block to be attached to the side surface of the first semiconductor packaging block, enable each first metal column to be embedded into the corresponding first groove, enable each first metal column to be electrically connected with the corresponding first conductive block, and enable the first semiconductor packaging block and the two second semiconductor packaging blocks to define a cavity so as to obtain a first semiconductor stacked packaging block.
(5) And then providing a heat dissipation plate, wherein a plurality of heat dissipation bulges arranged in a matrix form are arranged on the upper surface and the lower surface of the heat dissipation plate, and then a first semiconductor stacked packaging block is arranged on each heat dissipation bulge, so that each heat dissipation bulge is embedded into the corresponding cavity.
(6) And then, respectively arranging a circuit substrate on the upper surface and the lower surface of the heat dissipation plate, so that each circuit substrate is electrically connected with a plurality of first semiconductor stacked packaging blocks.
In some other embodiments, in step (1), the first redistribution layer and the second redistribution layer each include a multilayer dielectric layer and a multilayer metal layer, the dielectric layer is made of one or a combination of two or more of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, the metal layer is made of one or a combination of two or more of copper, aluminum, palladium, nickel, gold, silver and titanium, and the first groove is formed by a laser ablation process.
In some other embodiments, in the step (1), the first conductive block is formed by sputtering, evaporation, chemical vapor deposition, electroplating or chemical plating, the material of the first conductive block is one or a combination of two or more of copper, aluminum, titanium and nickel, and the second conductive block includes a metal column and a solder ball.
In some other embodiments, in step (2), the third redistribution layers each include a plurality of dielectric layers and a plurality of metal layers, the dielectric layers are made of one or a combination of two or more of epoxy resin, silicone, phosphosilicate glass, polyvinyl alcohol, and organic glass, the metal layers are made of one or a combination of two or more of copper, aluminum, palladium, nickel, gold, silver, and titanium, the first metal pillars are made of one or a combination of two or more of copper, aluminum, nickel, and titanium, and the third conductive bumps include metal pillars and solder balls.
In some other embodiments, in the step (4), before bending the bending region, an underfill resin layer is formed in a gap between the first semiconductor package block and the middle bonding region of the flexible circuit substrate and a gap between the second semiconductor package block and the end bonding region of the flexible circuit substrate.
In some other embodiments, in the step (4), the first metal pillar and the corresponding first conductive block are electrically connected by a conductive adhesive layer.
In some other embodiments, in the step (4), a first thermal interface layer, a second thermal interface layer, and a third thermal interface layer are formed in the cavity in a sequential stack.
In some other embodiments, the upper surface and the lower surface of the second thermal interface layer are both uneven surfaces, and the thermal conductivity of the second thermal interface layer is greater than the thermal conductivity of the first thermal interface layer and greater than the thermal conductivity of the third thermal interface layer.
In some other embodiments, the present invention also provides a system-on-package prepared by the above method.
As described above, the system-in-package-on-package and the method for manufacturing the same according to the present invention have the following advantages: in the manufacturing process of the system-on-package of the present invention, by forming the first conductive bumps in the first semiconductor package blocks, and one or more first grooves are formed on both opposite side surfaces of the first molding resin layer, the first grooves exposing upper surfaces of the respective first conductive bumps, and one or more second grooves are formed at one side of the second molding resin layer of the second semiconductor package block, and forming a first metal pillar in each of the second grooves, and embedding the first metal pillar into the first groove to realize a first semiconductor package block and a second semiconductor package block, and then can not set up the conducting wire layer on the bending region of flexible circuit base plate, and then can avoid because flexible circuit base plate buckles and lead to the problem that the conducting wire layer became invalid, and then guaranteed the validity and the stability of system level stack encapsulation. The first semiconductor packaging block is attached to the middle joint area of the flexible circuit substrate, the two second semiconductor packaging blocks are respectively attached to the two end joint areas of the flexible circuit substrate, then the bending area is bent upwards, so that each second semiconductor packaging block is attached to the side surface of the first semiconductor packaging block, a cavity is defined by the first semiconductor packaging block and the two second semiconductor packaging blocks to obtain a first semiconductor stacked packaging block, a heat dissipation plate is further provided, a plurality of heat dissipation bulges arranged in a matrix form are arranged on the upper surface and the lower surface of the heat dissipation plate, then the first semiconductor stacked packaging block is arranged on each heat dissipation bulge, so that each heat dissipation bulge is embedded into the corresponding cavity, and a plurality of heat conduction interface layers are arranged in the cavity, the arrangement of the structure can enable the stacked package to dissipate heat quickly on one hand, and can improve the integration level of the stacked package on the other hand.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method of making a system-in-package, comprising: the method comprises the following steps:
(1) providing a first carrier, forming a first rewiring layer on the first carrier, forming a second rewiring layer on the first rewiring layer, then arranging a first semiconductor chip on the second rewiring layer, then forming one or more first conductive blocks on the second rewiring layer on two sides of the first semiconductor chip, wherein the height of each first conductive block is smaller than that of the first semiconductor chip, and then forming a first molding resin layer on the second rewiring layer, wherein the first molding resin layer completely wraps the first conductive blocks and the first semiconductor chip; then, thinning the first molding resin layer to expose the back surface of the first semiconductor chip, then forming one or more first grooves on two opposite side surfaces of the first molding resin layer, wherein the first grooves expose the upper surfaces of the corresponding first conductive blocks, then removing the first carrier plate, and then forming second conductive blocks on the first redistribution layer to obtain a first semiconductor packaging block;
(2) providing a second carrier, forming a third redistribution layer on the second carrier, arranging a second semiconductor chip on the third redistribution layer, and then forming a second molding resin layer on the third redistribution layer, wherein the second molding resin layer completely wraps the second semiconductor chip; then, performing thinning treatment on the second molding resin layer to expose the back surface of the second semiconductor chip, then forming one or more second grooves on one side of the second molding resin layer, forming a first metal column in each second groove so as to enable the first metal column to be electrically connected with the third triple wiring layer, wherein the height of the first metal column is larger than that of the second semiconductor chip, then removing the second carrier plate, and then forming a third conductive block on the third triple wiring layer to obtain a second semiconductor packaging block;
(3) providing a flexible circuit substrate, wherein the flexible circuit substrate comprises a middle joint area, two end joint areas and a bending area which is positioned in the middle joint area and the end joint areas, and a conductive circuit layer is not arranged on the bending area;
(4) then, attaching one first semiconductor package block to the middle bonding area of the flexible circuit substrate, then attaching two second semiconductor package blocks to the two end bonding areas of the flexible circuit substrate respectively, and then bending the bending area upwards, so that each second semiconductor package block is attached to the side surface of the first semiconductor package block, each first metal column is embedded into the corresponding first groove, each first metal column is further electrically connected with the corresponding first conductive block, and the first semiconductor package block and the two second semiconductor package blocks define a cavity to obtain a first semiconductor stacked package block;
(5) then, providing a heat dissipation plate, wherein a plurality of heat dissipation bulges arranged in a matrix form are arranged on the upper surface and the lower surface of the heat dissipation plate, and then, a first semiconductor stacked packaging block is arranged on each heat dissipation bulge, so that each heat dissipation bulge is embedded into the corresponding cavity;
(6) and then, respectively arranging a circuit substrate on the upper surface and the lower surface of the heat dissipation plate, so that each circuit substrate is electrically connected with a plurality of first semiconductor stacked packaging blocks.
2. The method of manufacturing a system-on-package according to claim 1, wherein: in the step (1), the first redistribution layer and the second redistribution layer respectively comprise a plurality of layers of dielectrics and a plurality of layers of metal layers, the materials of the dielectrics are one or a combination of more than two of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, the materials of the metal layers comprise one or a combination of more than two of copper, aluminum, palladium, nickel, gold, silver and titanium, and the first groove is formed through a laser ablation process.
3. The method of manufacturing a system-on-package according to claim 2, wherein: in the step (1), the first conductive block is formed by sputtering, evaporation, chemical vapor deposition, electroplating or chemical plating process, the material of the first conductive block is one or a combination of two or more of copper, aluminum, titanium and nickel, and the second conductive block comprises a metal column and a solder ball.
4. The method of manufacturing a system-on-package according to claim 1, wherein: in the step (2), the third triple wiring layers respectively comprise a plurality of layers of media and a plurality of layers of metal, the media layers are made of one or a combination of more than two of epoxy resin, silica gel, phosphorosilicate glass, polyvinyl alcohol and organic glass, the metal layers are made of one or a combination of more than two of copper, aluminum, palladium, nickel, gold, silver and titanium, the first metal columns are made of one or a combination of more than two of copper, aluminum, nickel and titanium, and the third conductive blocks comprise metal columns and solder balls.
5. The method of manufacturing a system-on-package according to claim 1, wherein: in the step (4), before bending the bending region, an underfill resin layer is formed in a gap between the first semiconductor package block and the middle bonding region of the flexible circuit substrate and a gap between the second semiconductor package block and the end bonding region of the flexible circuit substrate.
6. The method of manufacturing a system-on-package according to claim 1, wherein: in the step (4), the first metal posts and the corresponding first conductive blocks are connected through a conductive adhesive layer.
7. The method of manufacturing a system-on-package according to claim 1, wherein: in the step (4), a first heat conduction interface layer, a second heat conduction interface layer, and a third heat conduction interface layer are formed in the cavity in a stacked manner in this order.
8. The method of manufacturing a system-on-package according to claim 7, wherein:
the upper surface and the lower surface of the second heat conduction interface layer are both uneven surfaces, and the heat conductivity coefficient of the second heat conduction interface layer is larger than that of the first heat conduction interface layer and larger than that of the third heat conduction interface layer.
9. A system-in-package-on-package prepared by the method of any one of claims 1-8.
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| CN114267598B (en) * | 2021-12-07 | 2022-10-11 | 宜确半导体（苏州）有限公司 | Packaging structure and packaging method of radio frequency front-end integrated circuit |
| CN114093773B (en) * | 2022-01-21 | 2022-04-12 | 威海艾迪科电子科技股份有限公司 | Integrated circuit, foldable packaging structure and forming method thereof |
| CN114420574B (en) * | 2022-03-31 | 2022-06-21 | 威海嘉瑞光电科技股份有限公司 | Flexible packaging component and forming method thereof |
| CN115241140B (en) * | 2022-08-08 | 2023-01-31 | 温州欧乐彩科技有限公司 | Withstand voltage type semiconductor device with high-efficient heat radiation structure |
| CN115565890B (en) * | 2022-12-07 | 2023-04-18 | 西北工业大学 | Folding type multi-chip flexible integrated packaging method and flexible integrated packaging chip |
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