CN110010593A - A kind of three-dimensional stacked system in package technique - Google Patents
A kind of three-dimensional stacked system in package technique Download PDFInfo
- Publication number
- CN110010593A CN110010593A CN201811176969.9A CN201811176969A CN110010593A CN 110010593 A CN110010593 A CN 110010593A CN 201811176969 A CN201811176969 A CN 201811176969A CN 110010593 A CN110010593 A CN 110010593A
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- layer
- pad
- copper
- chip
- circuit board
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Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000005538 encapsulation Methods 0.000 claims abstract description 8
- 238000012545 processing Methods 0.000 claims abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 52
- 239000010949 copper Substances 0.000 claims description 42
- 229910052802 copper Inorganic materials 0.000 claims description 42
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 238000005516 engineering process Methods 0.000 claims description 21
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 20
- 229910052737 gold Inorganic materials 0.000 claims description 20
- 239000010931 gold Substances 0.000 claims description 20
- 238000001259 photo etching Methods 0.000 claims description 19
- 239000004411 aluminium Substances 0.000 claims description 18
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052759 nickel Inorganic materials 0.000 claims description 18
- 229910052709 silver Inorganic materials 0.000 claims description 18
- 239000004332 silver Substances 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 17
- 229910000679 solder Inorganic materials 0.000 claims description 17
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 16
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 239000011135 tin Substances 0.000 claims description 15
- 229910052718 tin Inorganic materials 0.000 claims description 15
- 238000005520 cutting process Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 238000009713 electroplating Methods 0.000 claims description 9
- 238000005553 drilling Methods 0.000 claims description 8
- 239000000843 powder Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000004814 polyurethane Substances 0.000 claims description 5
- 238000004140 cleaning Methods 0.000 claims description 4
- 230000005496 eutectics Effects 0.000 claims description 4
- 239000011521 glass Substances 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 238000000280 densification Methods 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000003698 laser cutting Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 229920003023 plastic Polymers 0.000 claims description 3
- 229920002635 polyurethane Polymers 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052716 thallium Inorganic materials 0.000 claims description 3
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 239000010408 film Substances 0.000 description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- -1 poly- ammonia Ester Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a kind of three-dimensional stacked system in package technique, include the following steps: 101) to make flexible circuit board step, 102) functional chip processing step, 103) encapsulation step；Present invention offer manufacturing system class encapsulation structure is at low cost, and integrated level is high, a kind of good three-dimensional stacked system in package technique of thermal diffusivity.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, it is related to a kind of three-dimensional stacked system in package technique.
Background technique
The fast development of electronic product is the main drive that current encapsulation technology is evolved.Miniaturization, high density, high frequency are high
Speed, high-performance, high reliability and low cost are the mainstream development directions of Advanced Packaging, and it is also most to have that system in package, which is most important,
Potentiality meet integrated one of the technology of this high-density systems.
In various system in package, the core that middle layer is silicon based three-dimensional integrated RF micro-system is done using silicon pinboard
Technology provides shortest connection distance, the smallest pad size and center spacing to substrate for chip to chip and chip.With
The advantages of other interconnection techniques such as Wire Bonding Technology is compared, silicon switching plate technique includes: better electric property, higher band
Wide, higher density, smaller size, lighter weight.
But silicon pinboard process requirement uses TSV technology, the technique that centre is related to includes photoetching, dry etching,
The complex steps such as PVD, CVD and plating, cost and technical difficulty are relatively high, are not suitable for a large amount of general of civil field product
And.
Summary of the invention
The present invention overcomes the deficiencies in the prior art, provide that manufacturing system class encapsulation structure is at low cost, and integrated level is high, heat dissipation
A kind of good three-dimensional stacked system in package technique of property.
Technical scheme is as follows:
A kind of three-dimensional stacked system in package technique, specific processing include the following steps:
101) it makes flexible circuit board step: covering first layer copper film in the organic film surface of first layer, pass through photoetching, wet etching
Technique makes first layer connection, then covers copper wire with second layer organic film, and expose first layer communication by bore process
The pad of line；Second layer copper film is covered again again in the organic film surface of the second layer, the second connection is made, with third layer organic film
Second layer connection is covered, and drills and exposes the pad of second layer connection, forms flexible circuit board；
First layer organic film, second layer organic film and third layer organic film all use polytetrafluoroethylplastic plastic, epoxy resin or poly-
Urethane, thickness is between 100nm to 1000um；First layer connection, second layer connection material use copper, nickel, aluminium, gold
Or silver, thickness is between 100nm to 1000um, and width is between 100nm to 1000um；
Engraved structure, the diameter of engraved structure are made in flexible circuit board upper surface by machine drilling or laser drilling process
Range is 1um to 10000um, and metal block is placed in engraved structure by mosaic technology；Metal block uses copper, nickel, aluminium, Jin Huo
Silver；And drill in the another side of flexible circuit board, it is coated with scaling powder, places solder sphere, solder sphere diameter range is arrived in 50um
1000um, solder sphere use tin ball, ping-pong ball or gold goal, then the simultaneously cleaning scaling powder that flows back, to obtain the flexible circuit board of Place；
102) functional chip processing step: producing pit by the method for photoetching and dry etching in functional chip upper surface,
Pit uses cube, inverted trapezoidal, cylinder or hemispherical, and dimple size range is between 10um to 10000um, the size
Including cube, the length, width and height of inverted trapezoidal or cylinder, hemispheric diameter, height；The thickness range of functional chip is
200um to 2000um；
Insulating layer, thickness of insulating layer model are formed in functional chip upper surface cvd silicon oxide or silicon nitride or directly thermal oxidation
It is trapped among between 10nm to 100um, seed layer is just made by physical sputtering, magnetron sputtering or evaporation process on the insulating layer,
For seed layer thickness range in 1nm to 100um, this body structure of seed layer is one or more layers, the material of seed layer using titanium, copper,
Aluminium, silver, palladium, gold, thallium, tin or nickel；By electro-coppering, make copper metal full of pit, and densification copper at a temperature of 200 to 500 degree,
Functional chip surface is set only to be left to fill out copper in pit with CMP process；
RDL is made on functional chip surface by photoetching, electroplating technology comprising first makes insulating layer, thickness of insulating layer range
In 10nm to 1000um, material uses silica or silicon nitride, and is opened a window by photoetching, dry etch process, can make RDL
Copper is filled out with functional chip PAD and pit to connect；RDL, RDL packet are made on functional chip surface by photoetching, electroplating technology again
Include the pad of cabling and key function；
Wherein pad is made by photoetching, electroplating technology, and pad height range is adopted in 10nm to 1000um, the metal of pad
With copper, aluminium, nickel, silver, gold or tin, this body structure of pad is one or more layers；
103) encapsulation step: cutting function chip die is located at the centre that pit fills out copper position, cuts at one single chip, cutting position
Mode is cut using laser cutting or cutter cutting；One single chip is welded in flexible circuit board, the bottom of one single chip is with soft
Property wiring board metal block contact, the pad of one single chip is with the pad interconnection on the RDL of flexible circuit board；
Miscellaneous function chip is welded on the functional chip back side, and other miscellaneous function chips are welded in flexible circuit board,
Metal block contact of the bottom of other miscellaneous function chips with flexible circuit board；The pad of other miscellaneous function chips is with flexible wires
Pad interconnection on the RDL of road plate；Wherein other miscellaneous function chip surfaces have solder ball, and solder ball diameter range is in 50um
Bumping bump technology is used to 1000um or other miscellaneous function chip surfaces, bump diameter range is arrived in 50um
500um, altitude range is in 10um to 100um, and bump material is using one of copper, aluminium, nickel, silver, gold or tin or a variety of, convex block
This body structure is one or more layers；
Folded flexible wiring board interconnects flexible circuit board with miscellaneous function chip；Cutting flexible circuit board obtains single mould group.
Further, functional chip material uses wafer, glass, quartz, silicon carbide, aluminium oxide, epoxy resin or poly- ammonia
Ester.
Further, the surface insulation layer of functional chip can be removed with dry etching or wet corrosion technique.
Further, insulating layer is covered on the surface RDL, open a window exposed pad on the insulating layer；The metal of RDL uses herein
One or more of copper, aluminium, nickel, silver, gold, tin, this body structure of RDL use one or more layers, and the thickness range of RDL is
10nm to 1000um；Pad opens a window diameter as 10um to 10000um.
Further, pad interconnection is welded using gluing or eutectic.
Advantage is the present invention compared with prior art: the present invention does interconnection layer using flexible circuit board, different chips
It is stacked and makes its PAD connection, while pad is set in the side wall of chip, core is arranged by FC technique in chip side wall
Piece increases the integrated level of system-in-package module, at low cost with this technique manufacturing system class encapsulation structure, and integrated level is high, dissipates
It is hot good.
Detailed description of the invention
Fig. 1 is flexible circuit board structure figure of the invention；
Fig. 2 is the structure chart that soldered ball is arranged on Fig. 1 of the invention；
Fig. 3 is the structure chart of functional chip of the invention；
Fig. 4 is the structure chart that RDL and pad are arranged on functional chip of the invention；
Fig. 5 is the structure chart of one single chip of the invention；
Fig. 6 is the structure chart that chip of the invention is welded on flexible circuit board；
Fig. 7 is the structure chart that miscellaneous function chip is arranged in Fig. 6 of the invention；
Fig. 8 is the structure chart that other miscellaneous function chips are arranged in Fig. 7 of the invention；
Fig. 9 is the structure chart that Fig. 8 of the invention folds one side；
Figure 10 is structure chart of the invention.
It is identified in figure: flexible circuit board 101, engraved structure 102, copper wire 103, soldered ball 104, functional chip 201, pit
202, pad 203, RDL204, miscellaneous function chip 301, other miscellaneous function chips 401.
Specific embodiment
Embodiments of the present invention are described below in detail, in which the same or similar labels are throughly indicated identical or classes
As element or the element of similar functions.It is exemplary below with reference to the embodiment of attached drawing description, is only used for explaining
The present invention and cannot function as limitation of the present invention.
Those skilled in the art can understand that unless otherwise defined, all terms used herein (including skill
Art term and scientific and technical terminology) there is meaning identical with the general understanding of those of ordinary skill in fields of the present invention.Also
It should be understood that those terms such as defined in the general dictionary should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless definition as here, will not be explained in an idealized or overly formal meaning.
The label about step mentioned in each embodiment, it is only for the convenience of description, without substantial
The connection of sequencing.Different step in each specific embodiment can carry out the combination of different sequencings, realize this hair
Bright goal of the invention.
The present invention is further described with reference to the accompanying drawings and detailed description.
As shown in Figures 1 to 10, a kind of three-dimensional stacked system in package technique, specific processing include the following steps:
101) it makes flexible circuit board step: covering first layer copper film in the organic film surface of first layer, pass through photoetching, wet etching
Technique makes first layer connection, then covers copper wire 103 with second layer organic film, and expose first layer by bore process and lead to
Interrogate the pad of line.Second layer copper film is covered again again in the organic film surface of the second layer, makes the second connection, it is organic with third layer
Film covers second layer connection, and drills and expose the pad of second layer connection, forms flexible circuit board.I.e. specific production one
Kind flexible circuit board 101, manufacturing process include covering first layer copper film on 101 surface of first layer organic film first, passing through light
It carves and wet-etching technology makes copper wire 103, then cover copper wire 103 with another layer, that is, second layer organic film, pass through drillman
Skill exposes pad on copper wire 103, covers second layer copper film again in the organic film surface of the second layer, and make another layer of metal wire i.e.
Copper wire 103, finally completes the protection to copper wire 103 with the covering of third layer organic film, and the weldering of copper wire 103 on the second layer is exposed in drilling
Disk.
First layer organic film, second layer organic film and third layer organic film all use polytetrafluoroethylplastic plastic, epoxy resin
Or the organic thin films such as polyurethane, effect are to play the role of carrying copper wire 103, thickness is between 100nm to 1000um.
First layer connection, second layer connection material use copper, nickel, aluminium, gold or silver, thickness between 100nm to 1000um,
Width is between 100nm to 1000um.
Engraved structure 102, hollow out knot are made in flexible circuit board upper surface by machine drilling or laser drilling process
The diameter range of structure 102 is 1um to 10000um, places metal block in engraved structure 102 by mosaic technology.Metal block is adopted
With copper, nickel, aluminium, gold or silver.And drill in the another side of flexible circuit board, it is coated with scaling powder, places solder sphere, welds bulb diameter
Range uses tin ball, ping-pong ball or gold goal in 50um to 1000um, solder sphere, then the simultaneously cleaning scaling powder that flows back, to obtain Place
Flexible circuit board 101.It drills in 101 another side of flexible circuit board, is coated with scaling powder, place solder ball 104, solder ball is straight
Diameter range is in 50um to 1000um, and ball can also be ping-pong ball, gold goal etc. herein.Flow back simultaneously cleaning scaling powder, obtains the soft of Place
Property circuit board 101.
102) 201 processing step of functional chip: pass through the method system of photoetching and dry etching in 201 upper surface of functional chip
Pit 202 is made, pit 202 is arrived using cube, inverted trapezoidal, cylinder or hemispherical, 202 size range of pit in 10um
Between 10000um, which includes cube, the length, width and height of inverted trapezoidal or cylinder, hemispheric diameter, height.Function
The thickness range of chip 201 is 200um to 2000um.Functional chip 201 is also possible to other materials, such as glass using silicon wafer wafer
Glass, quartz, silicon carbide, the inorganic material such as aluminium oxide are also possible to epoxy resin, the organic materials such as polyurethane, major function
It is to provide the chip of electrical functions.
Insulating layer, insulation are formed in 201 upper surface cvd silicon oxide of functional chip or silicon nitride or directly thermal oxidation
Layer thickness range is just made between 10nm to 100um by physical sputtering, magnetron sputtering or evaporation process on the insulating layer
Seed layer, seed layer thickness range is in 1nm to 100um, this body structure of seed layer is one or more layers, and the material of seed layer uses
Titanium, copper, aluminium, silver, palladium, gold, thallium, tin or nickel etc..By electro-coppering, make copper metal full of pit 202, and in 200 to 500 degree temperature
Lower densification copper is spent, keeps copper finer and close.201 surface of functional chip is set only to be left to fill out copper in pit 202 with CMP process.Function core
201 surface insulation layer of piece can be removed with dry etching or wet corrosion technique.201 surface insulation layer of functional chip can also be with
Retain.
RDL204 is made on 201 surface of functional chip by photoetching, electroplating technology comprising is first made insulating layer, is insulated
For layer thickness range in 10nm to 1000um, material uses silica or silicon nitride, and is opened by photoetching, dry etch process
Window can be such that RDL204 and the copper of filling out of functional chip 201PAD and pit 202 connects.Again by photoetching, electroplating technology in function
201 surface of chip makes RDL204, and RDL204 includes the pad 203 of cabling and key function.It can also be covered on the surface RDL204
Lid insulating layer, open a window exposed pad 203 on the insulating layer.RDL204 metal can be copper, aluminium, nickel, silver, gold, the materials such as tin herein
Material can be one layer and be also possible to multilayer, and thickness range is 10nm to 1000um.The windowing of pad 203 10um to 10000um is straight
Diameter.
Wherein pad 203 is made by photoetching, electroplating technology, and 203 altitude range of pad is in 10nm to 1000um, weldering
The metal of disk 203 uses copper, aluminium, nickel, silver, gold or tin, and 203 body structures of pad are one or more layers.
103) encapsulation step: at one single chip, cutting position is located at pit 202 and fills out copper position 201 wafer of cutting function chip
The centre set, cutting mode is using laser cutting or cutter cutting, the purpose is to which the copper in pit 202 is cut into two parts,
The side of the part of exposing is as solder pad 203.One single chip is welded in flexible circuit board, the bottom of one single chip with
The metal block contact of flexible circuit board can preferably conduct heat.RDL204 of the pad 203 of one single chip with flexible circuit board
On pad 203 interconnect.Welding can be gluing herein, be also possible to eutectic welding.
Miscellaneous function chip 301 is welded on 201 back side of functional chip, and other miscellaneous function chips 401 are welded on
In flexible circuit board, that is, it is welded on flexible circuit board 101 and inlays on the position of copper metal block.The bottom of other miscellaneous function chips 401
Heat can preferably be conducted with the metal block contact of flexible circuit board in portion.The pad 203 of other miscellaneous function chips 401 is with soft
Property wiring board RDL204 on pad 203 interconnect.Welding herein equally can be gluing, be also possible to eutectic weldering.Wherein its
He has solder ball in 401 surface of miscellaneous function chip, and solder ball diameter range is in 50um to 1000um or other miscellaneous functions
401 surface of chip uses Bumping bump technology, and bump diameter range is arrived in 50um to 500um, altitude range in 10um
100um, bump material use one of copper, aluminium, nickel, silver, gold or tin or a variety of, this body structure of convex block is one or more layers.
By folded flexible wiring board, interconnect flexible circuit board with miscellaneous function chip 301.Cutting flexible circuit board obtains
To single mould group.I.e. specifically as shown in figure 9, folded flexible wiring board one end, makes the RDL204 drilling pad of flexible circuit board
203 interconnect with 301 surface pads 203 of miscellaneous function chip.As shown in Figure 10, the folded flexible wiring board other end, makes flexible wires
The 301 surface soldered ball 104 of other miscellaneous function chip or Bumping of road plate are on functional chip 201 and miscellaneous function chip 301
The pit side wall in face interconnects.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, without departing from the inventive concept of the premise, can also make several improvements and modifications, these improvements and modifications also should be regarded as
In the scope of the present invention.
Claims (5)
1. a kind of three-dimensional stacked system in package technique, which is characterized in that specific processing includes the following steps:
101) it makes flexible circuit board step: covering first layer copper film in the organic film surface of first layer, pass through photoetching, wet etching
Technique makes first layer connection, then covers first layer connection with second layer organic film, and pass through bore process exposing the
The pad of one layer of connection；Second layer copper film is covered again again in the organic film surface of the second layer, is made the second connection, is used third
Layer organic film covers second layer connection, and drills and expose the pad of second layer connection, forms flexible circuit board；
First layer organic film, second layer organic film and third layer organic film all use polytetrafluoroethylplastic plastic, epoxy resin or poly-
Urethane, thickness is between 100nm to 1000um；First layer connection, second layer connection material use copper, nickel, aluminium, gold
Or silver, thickness is between 100nm to 1000um, and width is between 100nm to 1000um；
Engraved structure, the diameter of engraved structure are made in flexible circuit board upper surface by machine drilling or laser drilling process
Range is 1um to 10000um, and metal block is placed in engraved structure by mosaic technology；Metal block uses copper, nickel, aluminium, Jin Huo
Silver；And drill in the another side of flexible circuit board, it is coated with scaling powder, places solder sphere, solder sphere diameter range is arrived in 50um
1000um, solder sphere use tin ball, ping-pong ball or gold goal, then the simultaneously cleaning scaling powder that flows back, to obtain the flexible circuit board of Place；
102) functional chip processing step: producing pit by the method for photoetching and dry etching in functional chip upper surface,
Pit uses cube, inverted trapezoidal, cylinder or hemispherical, and dimple size range is between 10um to 10000um, the size
Including cube, the length, width and height of inverted trapezoidal or cylinder, hemispheric diameter, height；The thickness range of functional chip is
200um to 2000um；
Insulating layer, thickness of insulating layer model are formed in functional chip upper surface cvd silicon oxide or silicon nitride or directly thermal oxidation
It is trapped among between 10nm to 100um, seed layer is just made by physical sputtering, magnetron sputtering or evaporation process on the insulating layer,
For seed layer thickness range in 1nm to 100um, this body structure of seed layer is one or more layers, the material of seed layer using titanium, copper,
Aluminium, silver, palladium, gold, thallium, tin or nickel；By electro-coppering, make copper metal full of pit, and densification copper at a temperature of 200 to 500 degree,
Functional chip surface is set only to be left to fill out copper in pit with CMP process；
RDL is made on functional chip surface by photoetching, electroplating technology comprising first makes insulating layer, thickness of insulating layer range
In 10nm to 1000um, material uses silica or silicon nitride, and is opened a window by photoetching, dry etch process, can make RDL
Copper is filled out with functional chip PAD and pit to connect；RDL, RDL packet are made on functional chip surface by photoetching, electroplating technology again
Include the pad of cabling and key function；
Wherein pad is made by photoetching, electroplating technology, and pad height range is adopted in 10nm to 1000um, the metal of pad
With copper, aluminium, nickel, silver, gold or tin, this body structure of pad is one or more layers；
103) encapsulation step: cutting function chip die is located at the centre that pit fills out copper position, cuts at one single chip, cutting position
Mode is cut using laser cutting or cutter cutting；One single chip is welded in flexible circuit board, the bottom of one single chip is with soft
Property wiring board metal block contact, the pad of one single chip is with the pad interconnection on the RDL of flexible circuit board；
Miscellaneous function chip is welded on the functional chip back side, and other miscellaneous function chips are welded in flexible circuit board,
Metal block contact of the bottom of other miscellaneous function chips with flexible circuit board；The pad of other miscellaneous function chips is with flexible wires
Pad interconnection on the RDL of road plate；Wherein other miscellaneous function chip surfaces have solder ball, and solder ball diameter range is in 50um
Bumping bump technology is used to 1000um or other miscellaneous function chip surfaces, bump diameter range is arrived in 50um
500um, altitude range is in 10um to 100um, and bump material is using one of copper, aluminium, nickel, silver, gold or tin or a variety of, convex block
This body structure is one or more layers；
Folded flexible wiring board interconnects flexible circuit board with miscellaneous function chip；Cutting flexible circuit board obtains single mould group.
2. a kind of three-dimensional stacked system in package technique according to claim 1, it is characterised in that: functional chip material is adopted
With wafer, glass, quartz, silicon carbide, aluminium oxide, epoxy resin or polyurethane.
3. a kind of three-dimensional stacked system in package technique according to claim 1, it is characterised in that: the surface of functional chip
Insulating layer can be removed with dry etching or wet corrosion technique.
4. a kind of three-dimensional stacked system in package technique according to claim 1, it is characterised in that: covered on the surface RDL
Insulating layer, open a window exposed pad on the insulating layer；Herein the metal of RDL using one of copper, aluminium, nickel, silver, gold, tin or
A variety of, this body structure of RDL uses one or more layers, and the thickness range of RDL is 10nm to 1000um；Pad opens a window diameter as 10um
To 10000um.
5. a kind of three-dimensional stacked system in package technique according to claim 1, it is characterised in that: pad interconnection uses glue
The welding of viscous or eutectic.
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