CN115023031A

CN115023031A - High-density integrated substrate structure and manufacturing method

Info

Publication number: CN115023031A
Application number: CN202210941386.0A
Authority: CN
Inventors: 陈彦亨; 林正忠
Original assignee: Shenghejing Micro Semiconductor Jiangyin Co Ltd
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2022-08-08
Filing date: 2022-08-08
Publication date: 2022-09-06

Abstract

The invention provides a high-density integrated substrate structure and a manufacturing method, wherein the substrate structure comprises: the packaging structure comprises a rewiring layer, a high-density interconnection substrate, a filling packaging layer and a solder array; the first interconnection face of the high-density interconnection substrate is electrically connected to the second wiring face. The invention improves the line density which can be realized by the substrate structure and reduces the size required by the substrate structure through the fan-out of the rewiring layer to the high-density interconnection substrate line; meanwhile, the characteristic that the rewiring layer can be directly packaged is utilized, so that the former process and the latter process do not need to be carried out separately, and the preparation time is shortened; in addition, the substrate structure can be compatible with chips and components of different types through the arrangement of the rewiring layer; and finally, the support effect of the high-density interconnection substrate is matched, the non-planarity or curling caused by insufficient packaging strength of the heavy wiring layer is reduced, and the performance reliability of the substrate structure is improved.

Description

High-density integrated substrate structure and manufacturing method

Technical Field

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a high-density integrated substrate structure and a manufacturing method thereof.

Background

With the rapid development of the semiconductor industry, the minimum feature size of the chip is continuously breaking through the limit and entering the nanometer level. The development of miniaturization and densification of semiconductor products has made higher demands on circuit density and precision of integrated substrates, and thus high density integrated substrates (HDI PCBs) using a micro via process have appeared.

The line width of the HDI PCB in the prior art can only reach 10 mu m, so that the line density of an integrated substrate device is greatly limited, thereby limiting the minimum size which can be reached by the integrated substrate and simultaneously limiting the diversity of chips or components which can be compatible with the integrated substrate device.

And most of the HDI PCB packages used at present are separated into a front process and a rear process, wherein the time for carrying, converting and re-matching is longer, so that the production efficiency of the integrated substrate device is greatly reduced.

Existing fan-out packages may achieve higher density packaging by directly connecting the solder bumps to the chip through a redistribution layer (RDL). However, in this technology, the RDL is filled with epoxy resin, so that the package support strength is low, and the inside of the whole package is easy to warp or not be planar, which affects the structural stability in the package.

In another prior art, 2.5D packaging technology connects a substrate and a chip together through an interposer to achieve higher density packaging. The interposer may be a monolithic glass, silicon, or silicon bridge (TSV). However, the cost of the whole piece of glass or silicon is too high, the problem of filling gaps of the TSVs can affect the stability of the device, and the preparation time of the TSVs in the interposer is also long.

It should be noted that the above description of the technical background is only for the sake of clarity and complete description of the technical solutions of the present application and for the understanding of the skilled person, and the technical solutions are not considered to be known to the skilled person merely because they are described in the background section of the present application.

Disclosure of Invention

In view of the above shortcomings of the prior art, the present invention is directed to a high-density integrated substrate structure and a manufacturing method thereof, which are used to solve the problem of how to achieve high-density and high-reliability of the integrated substrate in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme:

in a first aspect, the present invention provides a high-density integrated substrate structure, comprising: the packaging structure comprises a rewiring layer, a high-density interconnection substrate, a filling packaging layer and a solder array;

two opposite surfaces of the redistribution layer, which are electrically connected, are a first wiring surface and a second wiring surface; the high-density interconnection substrate comprises a first interconnection surface and a second interconnection surface which are opposite, and the first interconnection surface is effectively electrically connected with the second wiring surface; the filling packaging layer is filled between the first wiring surface and the second interconnection surface and covers the re-wiring layer and the high-density interconnection substrate;

the solder array includes an interconnect solder array disposed between the first interconnect face and the second interconnect face of the high-density interconnect substrate and a substrate solder array disposed on the second interconnect face of the high-density interconnect substrate.

Optionally, the underfill encapsulation layer extends below the second interconnect level, covering a portion of the second interconnect level of the substrate solder array.

Optionally, the high-density integrated substrate structure further includes a semiconductor chipset, the semiconductor chipset is located on the first wiring surface, and the semiconductor chipset includes an opposite bonding surface and an external connection surface; the bonding surface of the semiconductor chip set is electrically connected to the first wiring surface.

Optionally, the semiconductor chip set includes one or more chips or components selected from a capacitor, an inductor, a resistor, a transistor switch, a millimeter wave antenna, a graphic processor, a power management unit, a dynamic random access memory, a flash memory, and a filter.

Optionally, the redistribution layer includes a plurality of line layers and a plurality of dielectric layers stacked in sequence, and a conductive via located between two adjacent line layers.

Optionally, the line width and the line distance of each line layer are gradually reduced from the first wiring surface to the second wiring surface.

Optionally, the conductive line width on the first wiring surface is 1.5 micrometers to 5 micrometers, and the conductive line pitch is 1.5 micrometers to 5 micrometers.

In a second aspect, the present invention provides a method for manufacturing a high-density integrated substrate structure, the method comprising:

providing a temporary substrate; forming a separation layer on the temporary substrate; forming a rewiring layer on the separation layer, wherein two opposite surfaces of the rewiring layer, which are electrically connected, are a first wiring surface and a second wiring surface, and the separation layer is in contact with the first wiring surface;

forming an interconnection solder array on the second wiring surface; disposing a high-density interconnect substrate on the second wiring plane, the high-density interconnect substrate including opposing first and second interconnect planes; the first interconnection surface of the high-density interconnection substrate is effectively electrically connected with the second wiring surface through the interconnection solder array; disposing a substrate solder array on a second interconnect face of the high-density interconnect substrate, the substrate solder array in operative electrical connection with the second interconnect face of the high-density interconnect substrate;

filling a filling packaging layer in a region from the first wiring surface to the second interconnection surface so as to cover the rewiring layer and the high-density interconnection substrate; or the underfill encapsulant layer extends from the first wiring level to below the second interconnect level to cover the redistribution layer, the high-density interconnect substrate, and a portion of the substrate solder array near the second interconnect level;

and removing the temporary substrate through the separation layer to expose the first wiring surface.

Optionally, the method for manufacturing a high-density integrated substrate structure further includes: arranging a semiconductor chip set on the first wiring surface, wherein the semiconductor chip set comprises a welding surface and an external surface which are opposite; the bonding surface of the semiconductor chip group is effectively electrically connected with the first wiring surface.

Optionally, the redistribution layer is formed by sequentially laminating a plurality of line layers and a plurality of dielectric layers, wherein an effective electrical connection is formed between two adjacent line layers through a conductive via.

As described above, the high-density integrated substrate structure and the manufacturing method of the present invention have the following beneficial effects:

the invention improves the line density which can be realized by the substrate structure and reduces the size required by the substrate structure by the fan-out of the high-density interconnection substrate line by the rewiring layer;

the invention utilizes the characteristic that the rewiring layer can be directly packaged, so that the former and latter processes do not need to be carried out separately, and the preparation time is shortened;

the substrate structure can be compatible with different types of chips and components by arranging the rewiring layer;

the invention is matched with the supporting function of the high-density interconnection substrate, reduces non-planarity or curling caused by insufficient packaging strength of the heavy wiring layer, and improves the performance reliability of the substrate structure.

Drawings

Fig. 1 is a schematic structural diagram illustrating a separation layer and a redistribution layer formed on a temporary substrate in step 1 according to a second embodiment of the present invention.

Fig. 2 is a schematic structural diagram showing the arrangement of the interconnection solder array, the high-density interconnection substrate, and the substrate solder array in step 2 in the second embodiment of the present invention.

Fig. 3 is a schematic structural diagram showing the step 3 of setting the filling encapsulation layer according to the second embodiment of the present invention.

Fig. 4 is a schematic structural diagram showing the removal of the temporary substrate in step 4 according to the second embodiment of the present invention.

Fig. 5 is a schematic diagram illustrating an alternative high-density integrated substrate structure according to an embodiment of the invention.

Fig. 6 is a schematic diagram illustrating an alternative high-density integrated substrate structure according to an embodiment of the invention.

Description of the element reference

100. A rewiring layer; 111. a first wiring surface; 112. a second wiring surface; 121. a circuit layer; 122. a dielectric layer;

200. a high-density interconnect substrate; 211. a first interconnect face; 212. a second interconnect face;

300. filling the packaging layer;

400. a semiconductor chip set; 411. welding a surface; 412. an outer junction surface; 420. a component;

510. an interconnected solder array; 520. a substrate solder array;

610. a temporary substrate; 620. and (5) separating the layers.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As used herein, the drawings are not intended to be limiting, but are to be construed in an illustrative and exemplary manner. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

The first embodiment is as follows:

as shown in fig. 6, the present invention provides a high-density integrated substrate structure, which includes: a rewiring layer 100, a high-density interconnect substrate 200, a fill-in-package layer 300, and a solder array;

two opposite surfaces of the redistribution layer 100 to be electrically connected are a first wiring surface 111 and a second wiring surface 112; the high-density interconnection substrate 200 includes a first interconnection face 211 and a second interconnection face 212 which are opposite to each other, and the first interconnection face 211 is in effective electrical connection with the second wiring face 112; the filling encapsulation layer 300 is filled between the first wiring surface 111 and the second interconnection surface 212, and covers the rewiring layer 100 and the high-density interconnection substrate 200;

the solder array includes an interconnection solder array 510 and a substrate solder array 520, the interconnection solder array 510 is disposed between the first interconnection face 211 and the second wiring face 112 of the high-density interconnection substrate 200, and the substrate solder array 520 is disposed on the second interconnection face 212 of the high-density interconnection substrate 200.

At present, the most advanced process line width of the existing Printed Circuit Board (PCB) can only be about 10 μm, and the line width of the redistribution layer 100 (RDL) can reach 1.5 μm. The invention improves the line density which can be realized by the high-density integrated substrate structure through the fan-out of the heavy wiring layer 100 to the high-density interconnection substrate 200 (HDI PCB) line, thereby reducing the required size of the high-density integrated substrate structure; the narrower line width is beneficial to reducing the parasitic resistance of the PCB, improving the power supply efficiency and the power supply control response speed; the sharing of the RDL on the line density makes the high-density interconnection substrate 200 not need to make many layers to realize circuits with the same density, and the reduction of the number of layers of the high-density interconnection substrate 200 greatly reduces the cost of the high-density integrated substrate structure.

Meanwhile, the RDL can be directly packaged after the circuit of the RDL is printed, so that the front process and the rear process of the whole high-density integrated substrate structure do not need to be carried out in different factories, and the preparation time is shortened compared with that of the traditional high-density integrated substrate (HDI PCB); meanwhile, since the high-density interconnection substrate 200 can be prepared before or during the RDL preparation, the preparation time is also shortened compared with the conventional 2.5D package in which the through-hole (TSV) preparation is required after the RDL preparation is completed.

In addition, because only epoxy resin is used as a packaging body of the RDL in the traditional fan-out packaging, the RDL is easy to generate non-planarity, curling and other phenomena in the subsequent chip mounting and other steps due to poor supporting strength, and the device reliability is influenced.

Illustratively, the fill package layer 300 extends below the second interconnect level 212, covering portions of the substrate solder array 520 proximate the second interconnect level 212. By extending and filling the filling package layer 300, the substrate solder array 520 is further fixed in the filling package layer 300 at a position close to the second interconnection surface 212, which is beneficial to improving the connection strength of the substrate solder array 520 and preventing the solder bumps from falling off due to external interference.

Optionally, the material of the filling encapsulation layer 300 is one of epoxy resin, polyimide or silicone, and the epoxy resin may be thermosetting epoxy resin or thermoplastic epoxy resin. Specifically, the material of the filling encapsulation layer 300 may also be selected from other suitable materials, which are not limited herein.

Optionally, the material of the solder array is one of copper, nickel, gold, tin or carbon nanotubes. Specifically, the material of the solder array may also be selected from other suitable materials, which are not limited herein.

As an example, the high-density integrated substrate structure further includes a semiconductor chip group 400, the semiconductor chip group 400 is located on the first wiring plane 111, the semiconductor chip group 400 includes an opposite soldering plane 411 and an external connection plane 412; the bonding surface 411 of the semiconductor chip assembly 400 is electrically connected to the first wiring surface 111.

As shown in fig. 5-6, the semiconductor chip set 400 includes one or more chips or components 420 of a capacitor, an inductor, a resistor, a transistor switch, a millimeter wave antenna, a graphic processor, a power management unit, a dynamic random access memory, a flash memory, and a filter. The invention enables the high-density integrated substrate structure to be compatible with various components 420 or/and chips by fan-out of the high-density interconnected substrate 200 lines through the rewiring layer 100, thereby improving the system-level packaging capability of the high-density integrated substrate structure.

As an example, the rewiring layer 100 includes a plurality of line layers 121 and a plurality of dielectric layers 122, which are sequentially stacked, and a conductive via between two adjacent line layers 121. Optionally, the material of the circuit layer 121 is one of copper, aluminum, titanium, gold, silver, and nickel; the material of the dielectric layer 122 may be one of epoxy resin, silicone, polyimide, active resin, silicon oxide, phosphosilicate glass, and fluorine-containing glass. Specifically, the material of the line layer 121 and the material of the dielectric layer 122 may also be selected from other suitable materials, which are not limited herein.

As an example, the line width and the line pitch of each line layer 121 gradually decrease from the first wiring surface 111 to the second wiring surface 112.

As an example, the conductive line width on the first wiring surface 111 is 1.5 micrometers to 5 micrometers, and the conductive line pitch is 1.5 micrometers to 5 micrometers. The minimum dimension of the line width and the line distance of the circuit layer 121, which can be achieved by the invention, is further improved by the design that the line width and the line distance of the circuit layer 121 are gradually reduced from the first wiring surface 111 to the second wiring surface 112.

As an example, the high-density integrated substrate structure forms a package on package (PoP). Alternatively, the high-density integrated substrate structure may be designed as a 2.5D package, a fan-out package (FO), a flip chip package (FCCSP), a System In Package (SIP), or other advanced package types according to the requirement.

Example two:

the invention provides a manufacturing method of a high-density integrated substrate structure, which comprises the following steps:

step 1: providing a temporary substrate 610; forming a separation layer 620 over the temporary substrate 610; forming a redistribution layer 100 on the separation layer 620, wherein two opposite surfaces of the redistribution layer 100, which are electrically connected, are a first wiring surface 111 and a second wiring surface 112, and the separation layer 620 is in contact with the first wiring surface 111;

step 2: forming an interconnection solder array 510 on the second wiring surface 112; disposing a high-density interconnect substrate 200 on the second wiring plane 112, the high-density interconnect substrate 200 including opposing first and second interconnect planes 211 and 212; the first interconnect surface 211 of the high-density interconnect substrate 200 is in operative electrical connection with the second wiring surface 112 through the interconnect solder array 510; disposing a substrate solder array 520 on the second interconnect face 212 of the high-density interconnect substrate 200, the substrate solder array 520 making an operative electrical connection with the second interconnect face 212 of the high-density interconnect substrate 200;

and step 3: filling the filling encapsulation layer 300 in the region from the first wiring face 111 to the second interconnect face 212 to cover the redistribution layer 100 and the high-density interconnect substrate 200;

and 4, step 4: the temporary substrate 610 is removed through the separation layer 620 to expose the first wiring surface 111.

The method for manufacturing the high-density integrated substrate structure according to the present invention will be described in detail with reference to the accompanying drawings, wherein the above sequence does not strictly represent the sequence of the method for manufacturing the high-density integrated substrate structure protected by the present invention, and can be changed by those skilled in the art according to the actual manufacturing steps.

First, as shown in fig. 1, step 1 is performed to provide a temporary substrate 610; forming a separation layer 620 over the temporary substrate 610; the redistribution layer 100 is formed on the separation layer 620, two opposing surfaces of the redistribution layer 100, which are electrically connected, are the first wiring surface 111 and the second wiring surface 112, and the separation layer 620 is in contact with the first wiring surface 111.

Optionally, the material of the temporary substrate 610 is one of glass, metal, semiconductor, polymer, and ceramic. Preferably, glass is used as the temporary substrate 610 material to reduce cost while reducing the difficulty of forming and peeling the separation layer 620.

Optionally, the dimensions of the temporary substrate 610 are 12 inches, 8 inches, or square tile dimensions.

Optionally, the material of the separation layer 620 is a thermoplastic material, a laser curable material, an ultraviolet curable material, a composite adhesive film, a composite metal, or the like. Specifically, the thermoplastic material may be wax, a soluble bonding agent, or the like, and the laser curable material may be a light-to-heat conversion material (LTHC).

Alternatively, the line layer 121 in the redistribution layer 100 is formed by one of physical vapor deposition, chemical vapor deposition, sputtering, electroplating, and chemical plating.

Specifically, the rewiring layer 100 is formed by sequentially laminating a plurality of wiring layers 121 and a plurality of dielectric layers 122, wherein effective electrical connection is made between two adjacent wiring layers 121 through conductive vias.

Specifically, after the redistribution layer 100 is formed, the redistribution layer 100 is subjected to laser etching to expose the circuit layer 121 on the second wiring surface 112. Alternatively, the circuit layer 121 on the second wiring surface 112 may be exposed by mechanical grinding or other methods.

Then, as shown in fig. 2, step 2 is performed to form an interconnection solder array 510 on the second wiring surface 112; disposing a high-density interconnect substrate 200 on the second wiring plane 112, the high-density interconnect substrate 200 including opposing first and second interconnect planes 211 and 212; the first interconnect surface 211 of the high-density interconnect substrate 200 is in operative electrical connection with the second wiring surface 112 through the interconnect solder array 510; the substrate solder array 520 is disposed on the second interconnect side 212 of the high-density interconnect substrate 200, the substrate solder array 520 making an effective electrical connection with the second interconnect side 212 of the high-density interconnect substrate 200.

As an example, the preparation step of the high-density interconnect substrate 200 includes: drilling micropores, electroplating blind holes, filling and transferring patterns on the core plate; browning a core plate, sticking a prepreg and sticking a protective film; drilling the positions of the semi-solidified sheets corresponding to the micropores of the core plate; filling the holes of the prepreg with the conductive paste, heating and curing the conductive paste, and removing the protective film to obtain an interconnection layer; and the plurality of interconnection layers are superposed and pressed, and the plurality of interconnection layers are effectively electrically connected through the conductive paste. Specifically, the practitioner can design according to the actual application scenario.

Alternatively, the solder array is prepared by electrochemical deposition, electroplating, sputtering or evaporation.

Alternatively, the solder arrays may be distributed only on the periphery of the object to be soldered by ordinary flip chip bonding (FCOB), or the solder balls may be formed to cover the entirety of the second interconnection surface 212 by controlled collapse chip bonding (C4), or the solder caps may be formed on the solder columns by ultra fine pitch dedicated chip bonding (C2). C2 can obtain smaller solder cell pitch, i.e., greater solder cell density, i.e., density of IO ports (input/output ports), on the premise of being less prone to short circuit; however, the solder bump is in the form of a solder cap, and the surface tension is not enough to achieve self-alignment with the solder column, so the solder bump self-alignment capability of C2 is lower than that of C4. Practitioners need to balance and select the soldering method of the solder array according to the requirements on IO port density and solder position precision.

Then, as shown in fig. 3, step 3 is performed to fill the filling encapsulation layer 300 in the region from the first wiring plane 111 to the second interconnect plane 212 to cover the rewiring layer 100 and the high-density interconnect substrate 200.

Optionally, the underfill encapsulant layer 300 is filled to extend from the first wiring level 111 to below the second interconnect level 212 to cover the redistribution layer 100, the high-density interconnect substrate 200, and the portion of the substrate solder array 520 near the second interconnect level 212.

Alternatively, the filling encapsulation layer 300 is formed by one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, and spin coating.

Next, as shown in fig. 4, in step 4, the temporary substrate 610 is removed through the separation layer 620 to expose the first wiring surface 111.

In the prior art, a substrate structure is also reserved in fan-out packaging of a chip-last (chip-last) package, but the substrate structure itself is used as a support structure in the whole preparation process, so that a circuit structure in the substrate itself is subjected to certain pressure, and instability of a circuit in the substrate is caused. According to the invention, other structures are prepared on the temporary substrate 610, the temporary substrate 610 is removed in a bonding mode after the preparation is finished, and the high-density interconnection substrate 200 and the redistribution layer 100 are respectively prepared and then are connected in an overlapping mode, so that the reliability of circuits of the structures cannot be influenced by the action of external pressure in the preparation process, and the yield of the substrate structure is favorably improved.

Specifically, when the temporary substrate 610 is removed, the separation layer 620 of thermoplastic material is thermally treated to achieve debonding of the temporary substrate 610, the laser-cured material is laser ablated at an appropriate frequency to form micro-holes, and other types of materials may be reacted by corresponding chemicals to achieve debonding of the temporary substrate 610.

Specifically, after the temporary substrate 610 is removed, the first wiring surface 111 is cleaned, the material of the separation layer 620 and other impurities remaining on the surface thereof are removed, and the quality of the first wiring surface 111 is detected.

Optionally, the method for manufacturing a high-density integrated substrate structure further includes: disposing a semiconductor chip group 400 on the first wiring surface 111, the semiconductor chip group 400 including opposing bonding surfaces 411 and an external connection surface 412; the bonding surface 411 of the semiconductor chip assembly 400 is effectively electrically connected to the first wiring surface 111.

In conclusion, the high-density integrated substrate structure and the manufacturing method thereof improve the line density which can be realized by the substrate structure and reduce the size required by the substrate structure through the fan-out of the rewiring layer to the high-density interconnection substrate line; meanwhile, the characteristic that the rewiring layer can be directly packaged is utilized, so that the former process and the latter process do not need to be carried out separately, and the preparation time is shortened; in addition, the substrate structure can be compatible with chips and components of different types through the arrangement of the rewiring layer; and finally, the support effect of the high-density interconnection substrate is matched, the non-planarity or curling caused by insufficient packaging strength of the heavy wiring layer is reduced, and the performance reliability of the substrate structure is improved.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A high-density integrated substrate structure, the substrate structure comprising: the packaging structure comprises a rewiring layer, a high-density interconnection substrate, a filling packaging layer and a solder array;

two opposite surfaces of the redistribution layer, which are electrically connected, are a first wiring surface and a second wiring surface;

the high-density interconnection substrate comprises a first interconnection surface and a second interconnection surface which are opposite, and the first interconnection surface is effectively and electrically connected with the second wiring surface;

the filling packaging layer is filled between the first wiring surface and the second interconnection surface and covers the re-wiring layer and the high-density interconnection substrate;

2. The high-density integrated substrate structure of claim 1, wherein the fill encapsulation layer extends below the second interconnect level covering a portion of the substrate solder array proximate the second interconnect level.

3. The structure of claim 1, further comprising a semiconductor chip set disposed on the first wiring surface, the semiconductor chip set comprising opposing bonding surfaces and a circumscribing surface; the bonding surface of the semiconductor chip set is electrically connected to the first wiring surface.

4. The structure of claim 3, wherein the semiconductor chip set comprises one or more chips or components selected from the group consisting of capacitors, inductors, resistors, transistor switches, millimeter wave antennas, graphics processors, power management units, dynamic random access memories, flash memories, and filters.

5. The structure of claim 1, wherein the redistribution layer comprises a plurality of circuit layers and a plurality of dielectric layers stacked in sequence, and a conductive via between two adjacent circuit layers.

6. The structure of claim 5, wherein the line width and the line distance of each circuit layer are gradually reduced from the first wiring surface to the second wiring surface.

7. The structure of claim 5, wherein the conductive line on the first wiring surface has a width of 1.5-5 μm and a pitch of 1.5-5 μm.

8. A method of fabricating a high-density integrated substrate, the method comprising:

providing a temporary substrate;

forming a separation layer on the temporary substrate;

forming a rewiring layer on the separation layer, wherein two opposite surfaces of the rewiring layer, which are electrically connected, are a first wiring surface and a second wiring surface, and the separation layer is in contact with the first wiring surface;

forming an interconnection solder array on the second wiring surface;

disposing a high-density interconnect substrate on the second wiring plane, the high-density interconnect substrate including opposing first and second interconnect planes; the first interconnection surface of the high-density interconnection substrate is effectively electrically connected with the second wiring surface through the interconnection solder array;

disposing a substrate solder array on a second interconnect face of the high-density interconnect substrate, the substrate solder array in operative electrical connection with the second interconnect face of the high-density interconnect substrate;

9. The method of manufacturing a high-density integrated substrate according to claim 8, further comprising: arranging a semiconductor chip set on the first wiring surface, wherein the semiconductor chip set comprises a welding surface and an external surface which are opposite; the bonding surface of the semiconductor chip group is effectively electrically connected with the first wiring surface.

10. The method of manufacturing a high-density integrated substrate as claimed in claim 8, wherein said rewiring layer is formed by sequentially laminating a plurality of wiring layers and a plurality of dielectric layers, wherein effective electrical connection is formed between two adjacent wiring layers through a conductive via.