CN112151537B - High-energy-density nano-capacitor three-dimensional integrated structure and preparation method thereof - Google Patents
High-energy-density nano-capacitor three-dimensional integrated structure and preparation method thereof Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
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Abstract
The invention discloses a high-energy-density nano-capacitor three-dimensional integrated structure and a preparation method thereof. The silicon nano structure is etched on the surface of the silicon chip, the first nano capacitor is prepared, the nano line structure is formed on the surface of the first nano capacitor, the second nano capacitor is prepared, and the two nano capacitors are connected in parallel, so that the capacitance density and the energy density can be obviously increased, the electrical reliability of the nano capacitors is enhanced, and the size reduction of nano capacitor devices is facilitated.
Description
Technical Field
The invention belongs to the field of integrated circuit manufacturing, and particularly relates to a high-energy-density nano-capacitor three-dimensional integrated structure and a preparation method thereof.
Background
Currently, batteries remain the primary energy supply component for portable electronic devices. While battery technology is constantly evolving, there is still a compromise between the capacity and volume and weight of the battery. Accordingly, some alternative power supply components, such as micro fuel cells, plastic solar cells, and energy collection systems, which are large in capacity, light in weight, and small in volume, have been researched and developed. In all of the above mentioned cases, an energy buffer system is usually required to maintain a continuous and stable energy output. For example, it is generally believed that fuel cell systems have slower start-up times and lower kinetic energy. Therefore, a hybrid system in which the fuel cell provides the base power and the buffer system provides the start-up power is the best solution. Furthermore, energy harvesting systems rely on energy sources that are not continuously available in the environment; therefore, an energy buffer system is needed to maintain uninterrupted operation of the device. Further, energy buffer systems can provide peak loads, while energy generating systems cannot. Generally, the energy buffer system is either a battery or a capacitor. One important drawback of batteries is their limited discharge efficiency. In contrast, a capacitor may provide a larger discharge current. Other advantages of using a capacitor as an energy buffer include longer cycle life and higher power density. In addition to the advantages mentioned above, capacitors are easier to scale down than batteries using appropriate materials and structural designs. Capacitance density and storage capacity can be greatly increased by introducing high aspect ratio structures, such as carbon nanotubes, silicon nanowires, silicon nanopores, and silicon deep trench structures, and depositing high dielectric constant materials in these high aspect ratio structures. Such a capacitor fabricated using nanostructures may be referred to as a nanocapacitor. However, the high aspect ratio structure adopted by the existing nano capacitor is single, and the storage capacity cannot be increased to a greater extent, so that the nano capacitor is limited to be used as an effective energy buffer component.
Disclosure of Invention
In order to solve the above problems, the present invention discloses a high energy density nano-capacitor three-dimensional integrated structure, comprising: the first nano capacitor structure and the second nano capacitor structure are arranged on the substrate, wherein the second nano capacitor structure is positioned above the first nano capacitor structure; a first nano-capacitor structure comprising an array of silicon nanopores formed in a silicon substrate; the first isolation medium covers the surface of the silicon nanopore array; the first bottom metal electrode layer covers the surface of the first isolation medium; the first insulating medium covers the surface of the first bottom metal electrode layer; and the first top metal electrode layer covers the surface of the first insulating medium and completely fills the silicon nano holes. An intermediate isolation dielectric formed between the first and second nanocapacitive structures; a second nano-capacitor structure comprising a nano-wire structure located on the surface of the intermediate isolation medium; the second bottom metal electrode layer covers the surface of the nanowire structure; a second insulating medium covers the surface of the second bottom metal electrode layer; a second top metal electrode layer covers the surface of the second insulating medium;
a metal contact which comprises a first groove structure, a second groove structure, a third groove structure and a fourth groove structure which are respectively formed on the surfaces of the first top metal electrode layer, the second bottom metal electrode layer and the first bottom metal electrode layer by a third insulating medium; the first groove structure is adjacent to the second groove structure, and the third groove structure is adjacent to the fourth groove structure; the copper diffusion barrier layer covers the surfaces of the four grooves and gaps between adjacent nanowire structures; a copper seed crystal layer covers the surface of the copper diffusion impervious layer; the copper metal layer covers the surface of the copper seed crystal layer and completely fills the four grooves and gaps between adjacent nanowire structures; the first top metal electrode layer and the second top metal electrode layer are electrically communicated through the first groove structure and the second groove structure; the second bottom metal electrode layer is electrically communicated with the first bottom metal electrode layer through the third groove structure and the fourth groove structure.
In the three-dimensional integrated structure of the high-energy-density nano capacitor, preferably, the nano wire structure is a carbon nano tube, a silicon nano wire, a Ge nano wire or a ZnO nano wire.
In the high-energy-density nano-capacitor three-dimensional integrated structure, the diameter range of the monocrystalline silicon nano-pores is preferably 0.5-1 μm, and the depth range is preferably 10-20 μm.
The invention also discloses a preparation method of the high-energy-density nano-capacitor three-dimensional integrated structure, which comprises the following steps: photoetching and etching the silicon substrate to form a silicon nanopore array; sequentially forming a first isolation medium, a first bottom metal electrode layer, a first insulating medium and a first top metal electrode layer on the surface of the silicon nano-hole array, wherein the first top metal electrode layer completely fills the silicon nano-holes to obtain a first nano-capacitor structure; forming an intermediate isolation medium on the surface of the first top metal electrode layer; forming a nanowire structure on the surface of the intermediate isolation medium; sequentially forming a second bottom metal electrode layer, a second insulating medium and a second top metal electrode layer on the surface of the nanowire structure to obtain a second nano capacitor structure; metal wiring is performed such that the first nanocapacitive structure and the second nanocapacitive structure are connected in parallel.
In the preparation method of the high-energy-density nano-capacitor three-dimensional integrated structure, preferably, the nano-wire structure is a carbon nano-tube, a silicon nano-wire, a Ge nano-wire or a ZnO nano-wire.
In the method for preparing the three-dimensional integrated structure of the high-energy-density nano capacitor, the carbon nano tube is preferably formed by the following method: depositing a layer of Ni metal film on the surface of the intermediate isolation medium to be used as a metal catalyst; photoetching and etching to form mutually separated Ni metal catalyst arrays; the carbon nanotubes are formed by chemical vapor deposition under the catalytic action of the Ni metal, and the Ni metal is finally positioned on the tops of the carbon nanotubes.
In the method for preparing the high-energy-density nano-capacitor three-dimensional integrated structure, the carbon nano-tube is preferably formed by adopting a gas-liquid-solid process.
In the method for preparing the high-energy-density nano-capacitor three-dimensional integrated structure, preferably, the step of performing metal wiring to connect the first nano-capacitor structure and the second nano-capacitor structure in parallel comprises the following steps: removing part of the second top metal electrode layer, the second insulating medium, the second bottom metal electrode layer and the middle spacing medium on one side by adopting photoetching and etching processes, thereby exposing the first top metal electrode layer;
removing parts of the second top metal electrode layer, the second insulating medium, the second bottom metal electrode layer, the middle isolating medium, the first top metal electrode layer and the first insulating medium on the other side by adopting photoetching and etching processes, so as to expose the first bottom metal electrode layer; further removing part of the second top metal electrode layer and the second insulating medium on the side by adopting photoetching and etching processes, thereby exposing the second bottom metal electrode layer; forming a third insulating medium on the surface of the structure;
etching the third insulating medium by adopting photoetching and etching processes, and respectively forming a first groove structure, a second groove structure, a third groove structure and a fourth groove structure on the surfaces of the exposed first top metal electrode layer, second bottom metal electrode layer and first bottom metal electrode layer from left to right; the first groove structure is adjacent to the second groove structure, and the third groove structure is adjacent to the fourth groove structure; sequentially forming a copper diffusion barrier layer and a copper seed crystal layer on the surface of the structure, and electroplating a copper metal layer to completely fill the gap between the trench structure and the adjacent carbon nano-wire structure;
removing the copper metal layer, the copper seed crystal layer and the copper diffusion barrier layer above the nanowire structure by adopting a chemical polishing process, so that the copper diffusion barrier layer is split into a left region and a right region which are not connected with each other; the first top metal electrode layer and the second top metal electrode layer are electrically communicated through the first groove structure and the second groove structure; the second bottom metal electrode layer is electrically communicated with the first bottom metal electrode layer through the third groove structure and the fourth groove structure.
According to the invention, the silicon nano structure is etched on the surface of the silicon chip and the first nano capacitor is prepared, then the carbon nano tube or other nano wire structures are formed on the surface of the first nano capacitor and the second nano capacitor is prepared, and the two nano capacitors are connected in parallel, so that the capacitance density and the energy density can be obviously increased. In addition, the depth-to-width ratio of the silicon nano structure can be properly reduced, so that the step filling rate of metal and medium in the silicon nano structure is high, the integrity is good, and the electrical reliability of the nano capacitor can be enhanced. The silicon nano structure and the carbon nano tube or other nano wire structures are stacked in the vertical direction, so that the plane area is not additionally occupied, and the size reduction of the nano capacitor device is facilitated. And the copper diffusion barrier layer and the copper metal layer between the adjacent carbon nano tubes or other nano wire structures are reserved, so that the advantage of fast heat dissipation of metal can be utilized, and the carbon nano tube can serve as a heat dissipation plate.
Drawings
FIG. 1 is a flow chart of a method for fabricating a three-dimensional integrated structure of high energy density nanocapacitors.
Fig. 2 to 11 are schematic structural diagrams of steps of a method for manufacturing a high-energy-density nanocapacitor three-dimensional integrated structure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly and completely understood, the technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention, and it should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention. The described embodiments are only some embodiments of the invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Furthermore, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details. Unless otherwise specified below, each part in the device may be formed of a material known to those skilled in the art, or a material having a similar function developed in the future may be used.
The technical solution of the present invention is further described below with reference to fig. 1 to 11 and the embodiments. Fig. 1 is a flow chart of a method for manufacturing a high-energy-density nanocapacitor three-dimensional integrated structure, and fig. 2-11 are schematic structural diagrams of steps of the method for manufacturing the high-energy-density nanocapacitor three-dimensional integrated structure. As shown in fig. 1, the preparation method comprises the following specific steps:
step S1: forming a silicon nanopore array. Specifically, firstly, spin-coating a photoresist and defining a pattern of a silicon nanopore through exposure and development processes; subsequently, the silicon substrate 200 is etched using a Deep Reactive Ion Etching (DRIE) process to form a silicon nanopore array, and the resulting structure is shown in fig. 2. Wherein, the diameter range of the monocrystalline silicon nanometer holes is 0.5 to1 μm and a depth range of 10-20 μm; CF may be selected for the plasma used to etch silicon substrate 2004、SF6At least one of (1).
Step S2: a first nanocapacitor structure is fabricated. Firstly, a layer of SiO is deposited on the surface of the silicon nano-pore by adopting a chemical vapor deposition process2A thin film as a first isolation medium 201; then, using physical vapor deposition process to form SiO2A TiN film and an Al film are sequentially deposited on the surface of the film 2012O3A thin film and a TiN thin film as the first bottom metal electrode layer 202, the first insulating medium 203 and the first top metal electrode layer 204, respectively, and the first top metal electrode layer completely fills the silicon nano-holes. Finally, a layer of SiO is deposited on the surface of the first top metal electrode layer 204 by using a chemical vapor deposition process2The thin film acts as an intermediate isolation medium 205 and the resulting structure is shown in fig. 3. The thickness ranges of the first isolation medium 201 and the middle isolation medium 205 are both 100-200 nm, the thickness range of the first bottom metal electrode layer 202 is 50-150 nm, the thickness range of the first insulation medium 203 is 10-50 nm, and the thickness range of the first top metal electrode layer 204 is 100-300 nm. In the present embodiment, a deep reactive ion etching process is employed to obtain the through-silicon via structure, but the present invention is not limited thereto, and at least one process of dry etching such as ion mill etching, plasma etching, reactive ion etching, deep reactive ion etching, laser ablation, or wet etching by using an etchant solution may be selected. In addition, SiO is used in the present embodiment2As a first isolation medium and a middle isolation medium, TiN is used as a first bottom and a first top metal electrode layer, and Al2O3The thin film is used as the first insulating dielectric layer, but the invention is not limited thereto, and SiO can be selected2、Si3N4At least one of SiON, SiCOH and SiCOFH is used as a first isolation medium and an intermediate isolation medium; at least one of TaN, TiN, WN, MoN, Ni, and Ru may be selected as the first bottom and first top metal electrode layers; selection of Al2O3、ZrO2、TiO2、HfO2、La2O3、HfZAt least one of rO, HfAlO and HfTiO is used as a first insulating medium layer. The first isolation medium, the intermediate isolation medium, the first insulation medium, the first bottom metal electrode layer and the first top metal electrode layer can be grown in a mode of selecting at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and pulsed laser deposition.
Step S3: and forming a carbon nano tube array on the surface of the first nano capacitor structure. Firstly, a layer of Ni metal film is deposited on the surface of an intermediate isolation medium 205 by adopting a physical vapor deposition process to serve as a metal catalyst 206; then spin-coating photoresist and defining a Ni metal catalyst array pattern through exposure and development processes; the Ni metal thin film is then etched using an RIE process to form an array of Ni metal catalysts separated from each other, and the resulting structure is shown in fig. 4. Then, the structure is put into a cavity of Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment, and C is introduced2H2And NH3(ii) a Forming the carbon nano tube 207 as a nano wire structure under the catalysis of Ni metal within the temperature range of 600-700 ℃, wherein the Ni metal is finally positioned at the top of the carbon nano tube, and the obtained structure is shown in figure 5. In this embodiment, the carbon nanotubes are prepared by a PECVD process, but the present invention is not limited thereto, and may be prepared by a vapor-liquid-solid process (VLS). In addition, in the present embodiment, the carbon nanotube is used as the high aspect ratio structure, but the present invention is not limited thereto, and other nanowire structures such as a silicon nanowire, a Ge nanowire, or a ZnO nanowire may be used.
Step S4: and preparing a second nano capacitor structure on the surface of the carbon nano tube array. Firstly, a TiN film and an Al film are sequentially deposited on the surface of the carbon nano tube 207 by adopting a physical vapor deposition process2O3A thin film and a TiN thin film as the second bottom metal electrode layer 208, the second insulating dielectric 209 and the second top metal electrode layer 210, respectively, the resulting structure is shown in fig. 6. The thickness range of the second bottom metal electrode layer is 50-150 nm, the thickness range of the second insulating medium is 10-50 nm, and the thickness range of the second top metal electrode layer is 100-300 nm. In this embodiment mode, TiN is used as the second bottom metalElectrode layer and second top metal electrode layer of Al2O3The film is used as a second insulating medium layer, but the invention is not limited to the film, and at least one of TaN, TiN, WN, MoN, Ni and Ru can be selected as a second bottom metal electrode layer and a second top metal electrode layer; selection of Al2O3、ZrO2、TiO2、HfO2、La2O3At least one of HfZrO, HfAlO and HfTiO is used as the second insulating medium layer. The second insulating medium, the second bottom metal electrode layer and the second top metal electrode layer can be grown in a manner of at least one selected from physical vapor deposition, chemical vapor deposition, atomic layer deposition and pulsed laser deposition.
Step S5: metal wiring is performed such that the first nanocapacitive structure and the second nanocapacitive structure are connected in parallel. Firstly, removing a part of the second top metal electrode layer 210, the second insulating medium 209, the second bottom metal electrode layer 208 and the middle spacing medium 205 on the left side by adopting photoetching and etching processes, thereby exposing the first top metal electrode layer 204; then, a photoetching and etching process is adopted to remove a part of the second top metal electrode layer 210, the second insulating medium 209, the second bottom metal electrode layer 208, the middle isolation medium 205, the first top metal electrode layer 204 and the first insulating medium 203 on the right side, so that the first bottom metal electrode layer 202 is exposed; subsequently, photolithography and etching processes are used to remove portions of the second top metal electrode layer 210 and the second insulating dielectric 209 on the right side, thereby exposing the second bottom metal electrode layer 208, and the resulting structure is shown in fig. 7. Further adopting chemical vapor deposition process to deposit a layer of SiO on the surface of the structure2The film acts as a third insulating medium 211 and the resulting structure is shown in fig. 8. Next, etching the third insulating medium 211 by using photolithography and etching processes, and forming a first trench structure, a second trench structure, a third trench structure and a fourth trench structure on the surfaces of the exposed first top metal electrode layer 204, second top metal electrode layer 210, second bottom metal electrode layer 208 and first bottom metal electrode layer 202 from left to right; and the first trench structure is adjacent to the second trench structure, the third trench structure is adjacent to the fourth trench structure,the resulting trench structure is shown in fig. 9. And further depositing a TaN film and a Co film on the surfaces of the four groove structures in sequence by adopting a chemical vapor deposition process to respectively serve as the copper diffusion barrier layer 212 and the copper seed layer 213. Subsequently, a layer of Cu material is electroplated on the surface of the copper seed layer 213 as a copper metal layer 214 by an electroplating process, and the resulting structure is shown in fig. 10. Wherein the copper metal layer 214 completely fills the gap between adjacent carbon nanotubes 207. Finally, a chemical polishing process is used to remove the copper metal layer 214, the copper seed layer 213 and the copper diffusion barrier layer 212 above the carbon nanotube 207, so that the copper diffusion barrier layer 212 is split into two left and right unconnected regions, and the resulting structure is shown in fig. 11. SiO is used in the present embodiment2As the third insulating medium, TaN is used as a copper diffusion barrier layer and a Co thin film is used as a copper seed layer, but the invention is not limited thereto, and SiO can be selected2、Si3N4At least one of SiON, SiCOH, SiCOFH as a third insulating medium; TaN, TiN, ZrN and MnSiO can be selected3As a copper diffusion barrier; at least one of Cu, Ru, Co, RuCo, CuRu and CuCo is selected as the copper seed layer. The third insulating medium, the copper diffusion impervious layer and the copper seed layer can be grown in a mode of at least one of physical vapor deposition, chemical vapor deposition and atomic layer deposition. The first top metal electrode layer 204 is in electrical communication with the second top metal electrode layer 210 through the first trench structure and the second trench structure; the second bottom metal electrode layer 208 is in electrical communication with the first bottom metal electrode layer 202 through the third trench structure and the fourth trench structure; that is to say, the first nano capacitor structure and the second nano capacitor structure are communicated with each other through the top electrode and the bottom electrode, so that the parallel connection is realized.
As shown in fig. 11, the high energy density nanocapacitor three-dimensional integrated structure includes:
the first nano capacitor structure and the second nano capacitor structure, wherein the second nano capacitor structure is located above the first nano capacitor structure.
The basic skeleton of the first nano-capacitor structure is a silicon nano-hole formed by etching the silicon substrate 200; the first isolation medium 201 covers the surface of the silicon nanopore; the first bottom metal electrode layer 202 covers the surface of the first isolation medium 201; the first insulating medium 203 covers the surface of the first bottom metal electrode layer 202; the first top metal electrode layer 204 covers the surface of the first insulating medium 203 and completely fills the silicon nano-holes. Furthermore, an intermediate isolation medium 205 covers the surface of the first top metal electrode layer 204. However, in order to extract the first top metal electrode layer 204, the left part of the first top metal electrode layer 204 is not covered by the intermediate isolation medium 205; in order to lead out the first bottom metal electrode layer 202, a portion of the first bottom metal electrode layer 202 on the right side is not covered with the first insulating medium 203.
The basic skeleton of the second nano-capacitor structure is a carbon nanotube 207 positioned on the surface of the middle isolation medium 205, and the metal catalyst 206 is positioned on the top of the carbon nanotube 207; the second bottom metal electrode layer 208 covers the surface of the carbon nanotube 207; a second insulating medium 209 covers the surface of the second bottom metal electrode layer 208; a second top metal electrode layer 210 covers the surface of the second insulating medium 209. In addition, in order to lead out the second bottom metal electrode layer 208, a part of the second bottom metal electrode layer 208 on the right side is not covered with the second insulating medium 209.
A first trench structure, a second trench structure, a third trench structure and a fourth trench structure are respectively formed on the surfaces of the first top metal electrode layer 204, the second top metal electrode layer 210, the second bottom metal electrode layer 208 and the first bottom metal electrode layer 202, which are exposed from left to right, of the third insulating medium 211; and the first trench structure is adjacent to the second trench structure and the third trench structure is adjacent to the fourth trench structure. The copper diffusion barrier layer 212 covers the surfaces of the four trenches and is broken in the middle region without connection; the copper seed layer 213 covers the surface of the copper diffusion barrier layer 212; the copper metal layer 214 covers the surface of the copper seed layer 213 and completely fills the trench. The gap between adjacent carbon nanotubes is formed with a copper diffusion barrier layer 212, a copper seed layer 213 and a copper metal layer 214, wherein the copper metal layer 214 completely fills the gap.
The first top metal electrode layer 204 is in electrical communication with the second top metal electrode layer 210 through the first and second trench structures; second bottom metal electrode layer 208 is in electrical communication with first bottom metal electrode layer 202 through the third and fourth trench structures; that is to say, the first nano capacitor structure and the second nano capacitor structure are communicated with each other through the top electrode and the bottom electrode, so that the parallel connection is realized.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Claims (7)
1. A high-energy density nano-capacitor three-dimensional integrated structure is characterized in that,
the method comprises the following steps:
the first nano capacitor structure and the second nano capacitor structure are arranged on the substrate, wherein the second nano capacitor structure is positioned above the first nano capacitor structure;
a first nanocapacitive structure comprising an array of silicon nanopores formed in a silicon substrate (200); a first isolation medium (201) covers the surface of the silicon nanopore array; a first bottom metal electrode layer (202) covers the surface of the first isolation medium (201); a first insulating medium (203) covers the surface of the first bottom metal electrode layer (202); a first top metal electrode layer (204) covers the surface of the first insulating medium (203) and completely fills the silicon nano holes;
an intermediate isolation dielectric (205) formed between the first and second nanocapacitive structures;
a second nanocapacitive structure comprising a nanowire structure (207) located at a surface of said intermediate isolation medium (205); a second bottom metal electrode layer (208) covering the nanowire structure surface; a second insulating medium (209) covers the surface of the second bottom metal electrode layer (208); a second top metal electrode layer (210) covers the surface of the second insulating medium (209);
a metal contact, which comprises a first groove structure, a second groove structure, a third groove structure and a fourth groove structure respectively formed on the surfaces of the first top metal electrode layer (204), the second top metal electrode layer (210), the second bottom metal electrode layer (208) and the first bottom metal electrode layer (202) by a third insulating medium (211); the first groove structure is adjacent to the second groove structure, and the third groove structure is adjacent to the fourth groove structure; a copper diffusion barrier layer (212) covering the surfaces of the four trenches and the gaps between adjacent nanowire structures; a copper seed layer (213) covering the surface of the copper diffusion barrier layer (212); a copper metal layer (214) covers the surface of the copper seed layer (213) and completely fills the four grooves and the gaps between the adjacent nanowire structures;
the first top metal electrode layer (204) is in electrical communication with the second top metal electrode layer (210) through the first trench structure and the second trench structure; the second bottom metal electrode layer (208) is in electrical communication with the first bottom metal electrode layer (202) through the third trench structure and the fourth trench structure.
2. The high energy density nanocapacitive three-dimensional integrated structure of claim 1,
the nanowire structure is a carbon nanotube, a silicon nanowire, a Ge nanowire or a ZnO nanowire.
3. The high energy density nanocapacitive three-dimensional integrated structure of claim 1,
the diameter range of the silicon nano-pores is 0.5-1 μm, and the depth range is 10-20 μm.
4. A method for preparing a three-dimensional integrated structure of a high-energy-density nano capacitor is characterized in that,
the method comprises the following steps:
photoetching and etching the silicon substrate (200) to form a silicon nano-pore array;
sequentially forming a first isolation medium (201), a first bottom metal electrode layer (202), a first insulating medium (203) and a first top metal electrode layer (204) on the surface of the silicon nano-hole array, wherein the first top metal electrode layer (204) completely fills the silicon nano-holes to obtain a first nano-capacitor structure;
forming an intermediate isolation medium (205) on the surface of the first top metal electrode layer (204);
forming nanowire structures on the surface of the intermediate isolation medium (205);
sequentially forming a second bottom metal electrode layer (208), a second insulating medium (209) and a second top metal electrode layer (210) on the surface of the nanowire structure to obtain a second nano capacitor structure;
carrying out metal wiring to enable the first nano capacitor structure and the second nano capacitor structure to be connected in parallel, and the method specifically comprises the following steps:
removing a part of the second top metal electrode layer (210), the second insulating medium (209), the second bottom metal electrode layer (208) and the middle spacing medium (205) on one side by adopting photoetching and etching processes, thereby exposing the first top metal electrode layer (204);
removing parts of the second top metal electrode layer (210), the second insulating medium (209), the second bottom metal electrode layer (208), the middle isolating medium (205), the first top metal electrode layer (204) and the first insulating medium (203) on the other side by adopting photoetching and etching processes, so that the first bottom metal electrode layer (202) is exposed; further adopting photoetching and etching processes to remove a part of the second top metal electrode layer (210) and the second insulating medium (209) on the side, thereby exposing the second bottom metal electrode layer (208);
forming a third insulating medium (211) on the surface of the structure;
etching the third insulating medium (211) by adopting photoetching and etching processes, and respectively forming a first groove structure, a second groove structure, a third groove structure and a fourth groove structure on the surfaces of the exposed first top metal electrode layer (204), second top metal electrode layer (210), second bottom metal electrode layer (208) and first bottom metal electrode layer (202) from left to right; the first groove structure is adjacent to the second groove structure, and the third groove structure is adjacent to the fourth groove structure;
sequentially forming a copper diffusion barrier layer (212) and a copper seed layer (213) on the surface of the structure, and electroplating a copper metal layer (214) to completely fill the gap between the trench structure and the adjacent carbon nanowire structure;
removing the copper metal layer (214), the copper seed layer (213) and the copper diffusion barrier layer (212) above the nanowire structure by adopting a chemical polishing process, so that the copper diffusion barrier layer (212) is split into a left region and a right region which are not connected with each other;
wherein the first top metal electrode layer (204) is in electrical communication with the second top metal electrode layer (210) through the first trench structure and the second trench structure; the first bottom metal electrode layer (202) is in electrical communication with the second bottom metal electrode layer (208) through the third trench structure and the fourth trench structure.
5. The method for preparing the high energy density nano-capacitor three-dimensional integrated structure according to claim 4,
the nanowire structure is a carbon nanotube, a silicon nanowire, a Ge nanowire or a ZnO nanowire.
6. The method for preparing the high energy density nano-capacitor three-dimensional integrated structure according to claim 5,
carbon nanotubes were formed using the following method:
depositing a layer of Ni metal film on the surface of the intermediate isolation medium (205) to be used as a metal catalyst;
photoetching and etching to form mutually separated Ni metal catalyst arrays;
the carbon nanotubes are formed by chemical vapor deposition under the catalytic action of the Ni metal, and the Ni metal is finally positioned on the tops of the carbon nanotubes.
7. The method for preparing the high energy density nano-capacitor three-dimensional integrated structure according to claim 5,
and forming the carbon nano tube by adopting a gas-liquid-solid process.
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