CN112908991B - Three-dimensional integrated structure and manufacturing method thereof - Google Patents
Three-dimensional integrated structure and manufacturing method thereof Download PDFInfo
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- CN112908991B CN112908991B CN202110106352.5A CN202110106352A CN112908991B CN 112908991 B CN112908991 B CN 112908991B CN 202110106352 A CN202110106352 A CN 202110106352A CN 112908991 B CN112908991 B CN 112908991B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
Abstract
The invention provides a three-dimensional integrated structure. The capacitor comprises a first nano capacitor, a second nano capacitor and a conductive piece; through preparing first nanometer electric capacity on the silicon substrate, the intensity of integrated configuration has been guaranteed, and first isolation medium separates first bottom metal electrode layer and silicon substrate, it has avoided first nanometer electric capacity probably to have the short circuit condition, the reliability of first nanometer electric capacity has been guaranteed, second nanometer electric capacity adopts insulating substrate to make, because self insulating property, second bottom metal electrode layer can directly set up at insulating substrate, processing technology has been reduced, and second bottom metal electrode layer passes through first connecting hole and first bottom metal electrode layer lug connection, make processing technology simpler, the time of preparing integrated configuration has been shortened. In addition, the invention also provides a manufacturing method of the three-dimensional integrated structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional integrated structure and a manufacturing method thereof.
Background
At present, batteries remain the main energy supply component for portable electronic devices, and although battery technology is continuously developed, a compromise still needs to be made between the capacity and volume and weight of the batteries. Accordingly, some alternative power supply components, such as micro fuel cells, plastic solar cells, and energy collection systems, which are large in capacity, light in weight, and small in volume, have been researched and developed.
In all of the above mentioned cases, an energy buffer system is generally required to maintain a continuous and stable energy output. For example, it is generally believed that fuel cell systems have slower start-up times and lower kinetic energy. A hybrid system in which the fuel cell provides the base power and the energy buffer system provides the start-up power is the best solution. Furthermore, energy harvesting systems rely on energy sources that are not continuously available in the environment, and therefore, energy buffering systems are needed to maintain uninterrupted operation of the device.
Generally, the energy buffer system is a battery or a capacitor. An important disadvantage of a battery is its limited discharge efficiency, in contrast to a capacitor which can provide a larger discharge current. Other advantages of using capacitors as energy buffer systems include longer cycle life and higher power density, and capacitors are easier to scale down compared to batteries using appropriate materials and structural designs, in addition to the advantages mentioned above.
Capacitance density and storage capacity can be greatly increased by introducing high aspect ratio structures, such as carbon nanotubes, silicon nanowires, silicon nanopores and silicon deep trench structures, and depositing high dielectric constant materials in the high aspect ratio structures, and the capacitor prepared by adopting the nanostructure can be called as a nanocapacitor. However, when the aspect ratio exceeds a certain value, the step coverage and integrity of the material on the surface of the high aspect ratio structure are greatly weakened, and even the deposited material may have holes in the field, thereby affecting the performance of the capacitor and greatly reducing the strength of the capacitor structure. In addition, to etch structures with very high aspect ratios, the precision requirements for the etching equipment can be very high. Further, when the lateral dimensions of these high aspect ratio structures, such as silicon nanopores, are very small, metal, insulating material and metal can only be directly deposited on the surface of the high aspect ratio structures to form the nanocapacitor structure, and the resistivity of the silicon material is high, which results in a large series resistance of the nanocapacitors, and thus reduces the power density.
Patent publication No. CN111916559A discloses a semiconductor structure and a method for forming the same, comprising: providing a substrate; forming a groove in the substrate; and forming a plurality of layers of overlapped composite layers in the groove and on the substrate, wherein the composite layers comprise electrode layers and first dielectric layers positioned on the electrode layers, and the composite layers positioned on the upper layer expose part of the top surfaces of the composite layers positioned on the lower layer. Forming a groove in the substrate, and forming a plurality of overlapped composite layers in the groove and on the substrate, wherein the composite layers comprise an electrode layer and a first dielectric layer positioned on the electrode layer. The surface area of the substrate is increased through the grooves, the electrode layers and the first dielectric layers are formed in the grooves in a crossed and stacked mode, the surface area of the substrate occupied by the capacitor devices formed by the electrode layers and the first dielectric layers is effectively reduced, and the integration level of the finally formed semiconductor structure is improved. The capacitor is not compact in structure, the integrity of the capacitor is guaranteed, and the resistivity of the nano capacitor is still high.
Therefore, there is a need to provide a method for manufacturing a three-dimensional integrated structure, which solves the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a three-dimensional integrated structure and a manufacturing method thereof, so that the processing technology is simpler, the processing time is shortened, the capacitor density is increased, the integrity of the capacitor is ensured, and the overall performance of the capacitor is improved.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a three-dimensional integrated structure, comprising:
a first nanocapacitor comprising a silicon substrate, a first isolation medium, a first bottom metal electrode layer and a first top metal electrode layer; the upper surface of the silicon substrate is provided with a plurality of first accommodating grooves, the first isolation medium, the first bottom metal electrode layer and the first top metal electrode layer are arranged in the first accommodating grooves and on the surface of the silicon substrate, and the first isolation medium separates the first bottom metal electrode layer from the silicon substrate;
a second nanocapacitor comprising an insulating substrate, a second bottom metal electrode layer and a second top metal electrode layer; the insulating substrate is arranged on a first top metal electrode layer, the insulating substrate is provided with a plurality of second accommodating grooves, a first connecting hole and a second connecting hole, the first connecting hole is communicated to the first bottom metal electrode layer, the second connecting hole is communicated to the first top metal electrode layer, and the second bottom metal electrode layer is arranged in the second accommodating grooves and is electrically connected with the first bottom metal electrode layer through the first connecting hole;
and the first conductive piece is electrically connected with the first top metal electrode layer and the second top metal electrode layer through the second connecting hole respectively.
The three-dimensional integrated structure provided by the invention has the beneficial effects that: the first nanometer capacitor is prepared on the silicon substrate, the strength of an integrated structure is guaranteed, the first bottom metal electrode layer and the silicon substrate are separated through the first isolation medium, the first nanometer capacitor is prevented from being possibly short-circuited, the reliability of the first nanometer capacitor is guaranteed, it is worth explaining that the second nanometer capacitor is made of the insulating substrate, due to the insulating property of the second nanometer capacitor, the second bottom metal electrode layer can be directly arranged on the insulating substrate, the processing technology is reduced, the second bottom metal electrode layer is directly connected with the first bottom metal electrode layer through the first connecting hole, the processing technology is simpler, the time for preparing the integrated structure is shortened, the second bottom metal electrode layer is arranged in the first connecting hole, and the integrity of the structure of the second nanometer capacitor is guaranteed. More preferably, first electrically conductive piece is through the second connecting hole with first top metal electrode layer and second top metal electrode layer electricity connection, owing to adopt first connecting hole and second connecting hole to realize that first nanometer electric capacity and second nanometer electric capacity are parallelly connected, greatly increased the power density of electric capacity, furthest shortens electricity connection path, thereby can reduce signal delay time, strengthen signal transmission speed and reduce the consumption, and in first electrically conductive piece located the second connecting hole, the integrality of second nanometer electric capacity structure has further been ensured, the wholeness ability of electric capacity has been improved.
Preferably, the silicon substrate is made of a silicon material, and the insulating substrate is made of alternately laminated SiO 2 Layer and Si 3 N 4 The layers are made. The beneficial effects are that: the silicon substrate made of silicon material ensures the strength of the structure, and SiO is adopted 2 Layer and Si 3 N 4 The insulating substrate formed by the layers alternately has an insulating effect, so that the second bottom metal electrode layer can be directly arranged on the insulating substrate, and the processing technology is reduced.
Preferably, the first nanocapacitor further comprises a first insulating medium and a second insulating medium; wherein, the first and the second end of the pipe are connected with each other,
the first insulating medium is arranged between the first bottom metal electrode layer and the first top metal electrode layer;
the first nano capacitor is provided with a first groove, the first groove is positioned at one end of the first connecting hole, the side surface of the first groove is a combined layer of the first insulating medium and the first top metal electrode layer, and the bottom surface of the first groove is the first bottom metal electrode layer;
the second isolation medium is arranged in the first groove, and the first connecting hole penetrates through the second isolation medium. The beneficial effects are that: through setting up first insulating medium, and locate first insulating medium between first bottom metal electrode layer and the first top metal electrode layer, realized first bottom metal electrode layer and first top metal electrode layer separation when having ensured the compactedness of first nanometer electric capacity structure, avoid the electric connection that first bottom metal electrode layer and first top metal electrode layer probably exist, ensured the parallelly connected reliability of first nanometer electric capacity and second nanometer electric capacity. More preferably, the first groove is formed in the first nano capacitor, the second isolation medium is arranged in the first groove, the second bottom metal electrode layer is prevented from being electrically connected with the first top metal motor layer when passing through the first connecting hole, the reliability of the first nano capacitor and the second nano capacitor when being connected in parallel is further guaranteed, the integrity of the structure of the first nano capacitor is realized, and the structural strength of the first nano capacitor is guaranteed.
Preferably, the second nanocapacitor further comprises a second insulating medium, the second insulating medium is disposed between the second bottom metal electrode layer and the second top metal electrode layer, and the second bottom metal electrode layer, the second insulating medium, and the second top metal electrode layer cover the second receiving groove and the upper surface of the insulating substrate. The beneficial effects are that: the second bottom metal electrode layer and the second top metal electrode layer are separated through the second insulating medium, and the second bottom metal electrode layer, the second insulating medium and the second top metal electrode layer cover the second accommodating groove and the upper surface of the insulating substrate, so that the second nano capacitor is compact in structure, and the integrity of the second nano capacitor is guaranteed at the same time.
Preferably, the second nanocapacitor further comprises a third isolation medium and the fourth isolation medium;
the second nano capacitor is provided with a second groove and a third groove, the second groove is positioned at the other end of the first connecting hole, and the side surface of the second groove is a combined layer of the second top metal electrode layer and the second insulating medium, the bottom surface of the second groove is the second bottom metal electrode layer, the third groove is positioned at one end of the second connecting hole, and the side surface of the third groove is the second bottom metal electrode layer, the second insulating medium and the second top metal electrode layer, the bottom surface of the third groove is the upper surface of the insulating substrate, the third isolation medium is arranged in the second groove, and the extension hole of the first connection hole penetrates through the third isolation medium, the fourth isolation medium is arranged in the third groove, and the second connection hole penetrates through the fourth isolation medium. The beneficial effects are that: through set up second recess and third recess on second nanometer electric capacity, set up third isolation medium and fourth isolation medium in second recess and third recess, because the effect of fourth isolation medium, first electrically conductive piece has avoided being connected with second bottom metal electrode layer electricity when passing through the second connecting hole, has further ensured the reliability when first nanometer electric capacity and second nanometer electric capacity are parallelly connected.
Preferably, the bottom metal electrode layer further comprises a second conductive member, the second conductive member is "T" shaped, one end of the second conductive member is disposed in the extension hole of the first connection hole and electrically connected to the second bottom metal electrode layer, and the other end of the second conductive member is connected to the third isolation medium. The beneficial effects are that: through setting up the electrically conductive piece of second in the extension hole of first connecting hole, realized integrated structure and external components's electricity and be connected, and the extension hole side of first connecting hole is the third and keeps apart the medium, has avoided the electrically connected of electrically conductive piece of second and second top metal electrode layer, has further ensured the parallelly connected reliability of first nanometer electric capacity and second nanometer electric capacity.
Preferably, the first conductive member is "T" shaped, one end of the first conductive member is disposed in the second connection hole and abuts against the first top metal electrode layer, and the other end of the first conductive member is connected to the second top metal electrode layer. The beneficial effects are that: and a fourth isolation medium and a T-shaped first conductive piece are combined, so that one end of the first conductive piece is arranged in the second connecting hole and is abutted against the first top metal electrode layer, and the other end of the first conductive piece is connected with the second top metal electrode layer, and the reliability of electric connection of the first top metal electrode layer and the second top metal electrode layer is realized.
Preferably, the first holding tank and the second holding tank are both "soil" type recesses. The beneficial effects are that: through setting up first holding tank and second holding tank as "soil" type recess that a plurality of intervals were arranged, increased integrated structure's integrated level, the first bottom metal electrode layer of effectual reduction, second bottom metal electrode layer, first top metal electrode layer and second top metal electrode layer occupy silicon substrate and insulating thorough surface area.
A method of fabricating a three-dimensional integrated structure, comprising the steps of:
s01: opening the first accommodating groove on the silicon substrate;
s02: arranging the first isolation medium, the first bottom metal electrode layer and the first top metal electrode layer on the surface of the silicon substrate and in the first accommodating groove, wherein the first isolation medium separates the first bottom metal electrode layer from the silicon substrate to prepare the first nano capacitor;
s03: providing an insulating substrate on the first top metal electrode layer;
s04: forming the second accommodating groove and the first connection hole on the insulating substrate, wherein the first connection hole is conducted to the first bottom metal electrode layer;
s05: arranging a second bottom metal electrode layer and a second top metal electrode layer on the surface of the insulating substrate and in the second accommodating groove, wherein the second bottom metal electrode layer is electrically connected with the first bottom metal electrode layer through the first connecting hole, so that the second nano capacitor is prepared;
s06: arranging the second connecting hole in the second nano capacitor, wherein the second connecting hole is communicated with the first top metal electrode layer;
s07: and arranging the first conductive piece, wherein the first conductive piece is respectively and electrically connected with the first top metal electrode layer and the second top metal electrode layer through the second connecting hole.
The manufacturing method of the three-dimensional integrated structure provided by the invention has the beneficial effects that: the first holding tank is arranged on the silicon substrate, the first insulating medium, the first bottom metal electrode layer and the first top metal electrode layer are arranged in the first holding tank to prepare the first nano capacitor, the strength of the integrated structure is ensured by adopting the silicon substrate, the first insulating medium separates the first bottom metal electrode layer from the silicon substrate, the first nano capacitor is prevented from having a short circuit condition possibly, and the reliability of the first nano capacitor is ensured, it is worth explaining that the second nano capacitor is made of the insulating substrate, and the second bottom metal electrode layer can be directly arranged on the insulating substrate due to the self insulating property, so that the processing technology is reduced, and the second bottom metal electrode layer is directly connected with the first bottom metal electrode layer through the first connecting hole, so that the processing technology is simpler, the time for preparing the integrated structure is shortened, and the second bottom metal electrode layer is arranged in the first connecting hole, the integrity of the second nanocapacitive structure is guaranteed. More preferably, first electrically conductive piece is connected first top metal electrode layer and second top metal electrode layer electricity through the second connecting hole, has realized parallelly connected of first nanometer electric capacity and second nanometer electric capacity, greatly increased the power density of electric capacity to first electrically conductive piece is located in the second connecting hole, has further ensured the integrality of second nanometer electric capacity structure, has improved the wholeness ability of electric capacity.
Preferably, the step S02 is further provided with the first insulating medium and the second insulating medium, wherein the first bottom metal electrode layer, the first insulating medium and the first top metal electrode layer are sequentially provided, then the first groove is formed in the first nanocapacitor, and the second insulating medium is provided in the first groove. The beneficial effects are that: through setting up first insulating medium, and locate first insulating medium between first bottom metal electrode layer and the first top metal electrode layer, realized first bottom metal electrode layer and first top metal electrode layer separation when having ensured the compactedness of first nanometer electric capacity structure, avoid the electric connection that first bottom metal electrode layer and first top metal electrode layer probably exist, ensured the parallelly connected reliability of first nanometer electric capacity and second nanometer electric capacity. More preferably, the first groove is formed in the first nano capacitor, the second isolation medium is arranged in the first groove, the second bottom metal electrode layer is prevented from being electrically connected with the first top metal motor layer when passing through the first connecting hole, the reliability of the first nano capacitor and the second nano capacitor when being connected in parallel is further guaranteed, the integrity of the structure of the first nano capacitor is realized, and the structural strength of the first nano capacitor is guaranteed.
Preferably, the second insulating medium is further disposed in step S05, and the second bottom metal electrode layer, the second insulating medium and the second top metal electrode layer are sequentially disposed in the second accommodating groove and on the upper surface of the insulating substrate until the second bottom metal electrode layer, the second insulating medium and the second top metal electrode cover the second accommodating groove and the upper surface of the insulating substrate. The beneficial effects are that: the second bottom metal electrode layer and the second top metal electrode layer are separated by the second insulating medium, and the second bottom metal electrode layer, the second insulating medium and the second top metal electrode layer cover the second accommodating groove and the upper surface of the insulating substrate, so that the second nano capacitor is compact in structure, and the integrity of the second nano capacitor is guaranteed at the same time.
Preferably, in step S06, the second groove and the third groove are formed in the second nanocapacitor in advance, the second groove is located at the other end of the first connection hole, the third isolation medium is disposed in the second groove, the fourth isolation medium is disposed in the third groove, the extension hole of the first connection hole is configured to conduct the third isolation medium, and the second connection hole is conducted to the first top metal electrode layer through the fourth isolation medium and the insulating substrate. The beneficial effects are that: through set up second recess and third recess on second nanometer electric capacity, set up third isolation medium and fourth isolation medium in second recess and third recess, because the effect of fourth isolation medium, first electrically conductive piece has avoided being connected with second bottom metal electrode layer electricity when passing through the second connecting hole, has further ensured the reliability when first nanometer electric capacity and second nanometer electric capacity are parallelly connected.
Preferably, the step S07 further includes providing the second conductive member, wherein one end of the second conductive member is disposed in the extended hole of the first connection hole and electrically connected to the second bottom metal electrode layer, and the other end of the second conductive member is connected to the third isolation medium. The beneficial effects are that: through setting up the electrically conductive piece of second in the extension hole of first connecting hole, realized integrated structure and external components's electricity and be connected, and the extension hole side of first connecting hole is the third and keeps apart the medium, has avoided the electrically connected of electrically conductive piece of second and second top metal electrode layer, has further ensured the parallelly connected reliability of first nanometer electric capacity and second nanometer electric capacity.
Drawings
FIG. 1 is a schematic diagram of one embodiment of a three-dimensional integrated structure of the present invention;
FIG. 2 is a flow chart illustrating a method for fabricating a three-dimensional integrated structure according to the present invention;
fig. 3-16 are schematic structural diagrams illustrating steps of a method for fabricating a three-dimensional integrated structure according to an embodiment of the present invention.
The reference numbers illustrate:
the package structure includes a silicon blind hole 2001, a first receiving groove 2002, a first groove 2003, a second receiving groove 2004, a first connecting hole 2005, a second groove 2006, a third groove 2007 and a second connecting hole 2008.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a three-dimensional integrated structure, specifically referring to fig. 1, including: a first nanocapacitor, the first nanocapacitor includes a silicon substrate 200, a first isolation medium 201, a first bottom metal electrode layer 202, and a first top metal electrode layer 204, it should be noted that a first receiving groove 2002 is formed on an upper surface of the silicon substrate 200, the first isolation medium 201, the first bottom metal electrode layer 202, and the first top metal electrode layer 204 are disposed in the first receiving groove 2002 and on a surface of the silicon substrate 200, and the first isolation medium 201 separates the first bottom metal electrode layer 202 from the silicon substrate 200. Thereby avoiding possible contact between the silicon substrate 200 and the first bottom metal electrode layer 202, which could result in short-circuiting of the first nanocapacitor.
The second nanocapacitor comprises an insulating substrate 208, a second bottom metal electrode layer 209 and a second top metal electrode layer 211, and it should be noted that the insulating substrate 208 is directly disposed on the first top metal electrode layer 204, and an isolation medium does not need to be added due to the insulating property of the insulating substrate 208. In addition, a second receiving groove 2004 and a first connection hole 2005 and a second connection hole 2008 located at two side edges of the second receiving groove 2004 are opened on the upper surface of the insulating substrate 208, wherein the first connection hole 2005 is conducted to the first bottom metal electrode layer 202, the second connection hole 2008 is conducted to the first top metal electrode layer 204, and when the second bottom metal electrode layer 209 is disposed, the second bottom metal electrode layer 209 is disposed in the second receiving groove 2004 and the first connection hole 2005 at the same time, so that the second bottom metal electrode layer 209 is electrically connected to the first bottom metal electrode layer 202 through the first connection hole 2005. And the time for preparing the integrated structure is shortened, and the processing technology is simplified.
The first conductive member 215 is disposed at the second connection hole 2008, and the first conductive member 215 is electrically connected to the first top metal electrode layer 204 and the second top metal electrode layer 211 through the second connection hole 2008, respectively.
It is worth to be noted that, the first nanocapacitor manufactured by using the silicon substrate 200 ensures the structural strength, and more preferably, the first conductive member 215 electrically connects the first top metal electrode layer 204 and the second top metal electrode layer 211 through the second connection hole 2008, so that the first nanocapacitor and the second nanocapacitor are vertically connected in parallel, the power density of the capacitor is greatly increased, and the first conductive member 215 is arranged in the second connection hole 2008, so that the structural integrity of the second nanocapacitor is further ensured, and the overall performance of the capacitor is improved.
Preferably, the first nanocapacitor further comprises a first insulating medium 203 and a second isolating medium 205, in this embodiment, the first nano-capacitor is prepared by sequentially stacking the first isolation medium 201, the first bottom metal electrode layer 202, the first insulating medium 203 and the first top metal electrode layer 204 in the first accommodating groove 2002 and on the upper surface of the silicon substrate 200, the first nano capacitor is provided with a first groove 2003, it should be noted that the first groove 2003 is located at one end of the first connection hole 2005, and the side surface of the opened first groove 2003 is a combined layer of the first insulating medium 203 and the first top metal electrode layer 204, the bottom surface of the first groove 2003 is the first bottom metal electrode layer 202, the second isolation medium 205 is disposed in the first groove 2003, and the first connection hole 2005 passes through the second isolation medium 205.
By arranging the first insulating medium 203 and arranging the first insulating medium 203 between the first bottom metal electrode layer 202 and the first top metal electrode layer 204, the first bottom metal electrode layer 202 and the first top metal electrode layer 204 are separated while the compactness of the first nano capacitor structure is ensured, the possible electric connection between the first bottom metal electrode layer 202 and the first top metal electrode layer 204 is avoided, and the reliability of the first nano capacitor and the second nano capacitor in parallel connection is ensured. Preferably, the first groove 2003 is formed in the first nano capacitor, and the second isolation medium 205 is arranged in the first groove 2003, so that the second bottom metal electrode layer 209 is prevented from being electrically connected with the first top metal motor layer when passing through the first connecting hole 2005, the reliability of the first nano capacitor and the second nano capacitor when being connected in parallel is further guaranteed, meanwhile, the structural integrity of the first nano capacitor is realized, and the structural strength of the first nano capacitor is guaranteed.
Preferably, the second nanocapacitor further includes a second insulating medium 210, the second bottom metal electrode layer 209, the second insulating medium 210, and the second top metal electrode layer 211 are sequentially stacked in the second receiving groove 2004 and on the upper surface of the insulating substrate 208, the second insulating medium 210 is disposed between the second bottom metal electrode layer 209 and the second top metal electrode layer 211 to separate the second bottom metal electrode layer 209 and the second top metal electrode layer 211, and the second bottom metal electrode layer 209, the second insulating medium 210, and the second top metal electrode layer 211 cover the second receiving groove 2004 and the upper surface of the insulating substrate 208, so that the second nanocapacitor is compact and the integrity of the second nanocapacitor is guaranteed.
Preferably, the second nanocapacitor further includes a third isolation medium 212 and the fourth isolation medium 213, and a second groove 2006 and a third groove 2007 are formed on an upper surface of the second nanocapacitor, the second groove 2006 is located at the other end of the first connection hole 2005, a side surface of the second groove 2006 is a combined layer of the second top metal electrode layer 211 and the second insulation medium 210, and a bottom surface of the second groove 2006 is the second bottom metal electrode layer 209.
The third groove 2007 is located at one end of the second connection hole 2008, the side surfaces of the third groove 2007 are the second bottom metal electrode layer 209, the second insulating medium 210 and the second top metal electrode layer 211, the bottom surface of the third groove 2007 is the upper surface of the insulating substrate 208, the third isolation medium 212 is located in the second groove 2006, the extension hole of the first connection hole 2005 penetrates through the third isolation medium 212, the fourth isolation medium 213 is located in the third groove 2007, and the second connection hole 2008 penetrates through the fourth isolation medium 213.
By forming the second groove 2006 and the third groove 2007 on the second nanocapacitor, the third isolation medium 212 is arranged in the second groove 2006, the fourth isolation medium 213 is arranged in the third groove 2007, and due to the action of the fourth isolation medium 213, the first conductive member 215 is prevented from being electrically connected with the second bottom metal electrode layer 209 when passing through the second connection hole 2008, so that the reliability of the first nanocapacitor and the second nanocapacitor in parallel is further guaranteed.
In another embodiment of the present disclosure, the second conductive member 216 is further included, it is worth to be noted that the second conductive member 216 is "T" shaped, one end of the second conductive member 216 is disposed in the extended hole of the first connection hole 2005 and electrically connected to the second bottom metal electrode layer 209, the other end of the second conductive member 216 is connected to the third isolation medium 212, similarly to the case that one end of the second conductive member 216 is inserted into the first connection hole 2005, and the other end of the second conductive member 216 is connected to the third isolation medium 212.
The second conductive member 216 is disposed in the extension hole of the first connection hole 2005, so that the integrated structure is electrically connected to an external device, and the third isolation medium 212 is disposed on the side surface of the extension hole of the first connection hole 2005, so that the second conductive member 216 is prevented from being electrically connected to the second top metal electrode layer 211, and the reliability of the first nanocapacitor and the second nanocapacitor connected in parallel is further guaranteed.
Preferably, the first conductive member 215 has a "T" shape, one end of the first conductive member 215 is disposed in the second connection hole 2008 and abuts against the first top metal electrode layer 204, and the other end of the first conductive member 215 is connected to the second top metal electrode layer 211. Due to the arrangement of the fourth isolation medium 213 and the T-shaped first conductive member 215, one end of the first conductive member 215 is disposed in the second connection hole 2008 and abuts against the first top metal electrode layer 204, and the other end of the first conductive member 215 is connected to the second top metal electrode layer 211, so that the first conductive member 215 is prevented from contacting the second bottom metal electrode layer 209, and the reliability of electrical connection between the first top metal electrode layer 204 and the second top metal electrode layer 211 is realized.
Further preferably, the first receiving groove 2002 and the second receiving groove 2004 are both a plurality of "soil" type grooves arranged at intervals, in this embodiment, the first receiving groove 2002 and the second receiving groove 2004 are both arranged by two "soil" type grooves arranged at intervals, so that the integration level of the integrated structure is increased, and the surface area of the silicon substrate 200 and the thoroughly insulated surface area occupied by the first bottom metal electrode layer 202, the second bottom metal electrode layer 209, the first top metal electrode layer 204 and the second top metal electrode layer 211 is effectively reduced. Of course, in practical production applications, the number of "soil" type grooves may be spaced at intervals on the upper surfaces of the silicon substrate 200 and the insulating substrate 208 according to practical requirements.
Preferably, the silicon substrate 200 is made of a silicon material, and the insulating substrate208 made of alternately laminated SiO 2 Layer 206 and Si 3 N 4 Layer 207, in this embodiment the insulating substrate 208 is made of SiO 2 Layer 206 and Si 3 N 4 The layers 207 are alternately stacked, but are not limited thereto in practical applications. The strength of the structure is ensured by the silicon substrate 200 made of silicon material, which is made of SiO 2 Layer 206 and Si 3 N 4 The insulating substrate 208 formed by the alternating layers 207 has an insulating effect, so that the second bottom metal electrode layer 209 can be directly arranged on the insulating substrate 208, and the processing process is reduced.
A method for manufacturing a three-dimensional integrated structure, as shown in fig. 2, includes the following steps:
s01: the first accommodating groove 2002 is formed in the silicon substrate 200;
s02: arranging the first isolation medium 201, the first bottom metal electrode layer 202 and the first top metal electrode layer 204 on the surface of the silicon substrate 200 and in the first accommodating groove 2002, wherein the first isolation medium 201 separates the first bottom metal electrode layer 202 from the silicon substrate 200 to prepare the first nanocapacitor;
s03: providing an insulating substrate 208 on said first top metal electrode layer 204;
s04: opening the second receiving groove 2004 and the first connection hole 2005 in the insulating substrate 208, and the first connection hole 2005 is conducted to the first bottom metal electrode layer 202;
s05: a second bottom metal electrode layer 209 and the second top metal electrode layer 211 are arranged on the surface of the insulating substrate 208 and in the second accommodating groove 2004, and the second bottom metal electrode layer 209 is electrically connected with the first bottom metal electrode layer 202 through the first connecting hole 2005, so that the second nanocapacitor is prepared;
s06: the second connection hole 2008 is formed in the second nano capacitor, and the second connection hole 2008 is conducted to the first top metal electrode layer 204;
s07: the first conductive member 215 is disposed, and the first conductive member 215 is electrically connected to the first top metal electrode layer 204 and the second top metal electrode layer 211 through the second connection hole 2008, respectively.
Referring to fig. 3, the first accommodating groove 2002 is formed in the silicon substrate 200 in advance, specifically, a photoresist is spin-coated on the upper surface of the silicon substrate 200, the shape of the blind silicon hole 2001 is identified by an exposure and development process, and the blind silicon hole 2001 is formed by Etching the silicon substrate 200 by using a Deep Reactive Ion Etching (DRIE) process.
Referring to fig. 4, then, oxygen ions are implanted into the silicon substrate 200 by ion implantation, the oxygen ions will diffuse downward to a certain depth, and then the energy of the implanted oxygen ions is reduced to implant oxygen ions into the silicon substrate 200 again, at this time, the diffusion depth of the oxygen ions will be reduced; the energy of the implanted oxygen ions is continuously reduced and the implantation process is repeated, so that a plurality of layers of oxygen ions at different depths are formed on the side wall of the silicon blind hole 2001. The silicon substrate 200 is then placed in a tube furnace for annealing, and the implanted oxygen ions react with the silicon to form silicon oxide.
Referring to fig. 5, the position of the silicon oxide on the sidewall of the silicon blind via 2001 and the interval between two adjacent layers of silicon oxide can be adjusted by adjusting the energy difference between the oxygen ion implantation and the two preceding and succeeding implantations. And finally, etching off the silicon oxide by using hydrofluoric acid as an etchant to form a silicon trench structure on the side wall of the silicon blind hole 2001, thereby obtaining the first accommodating groove 2002.
In this embodiment, oxygen ions are implanted by an ion implantation process. However, the present invention is not limited thereto, and the first receiving groove 2002 may be obtained by implanting nitrogen ions by an ion implantation process to form a silicon nitride material, and then etching the silicon nitride by hot phosphoric acid to form a silicon trench structure.
Further, referring to fig. 6, in the step S02, a layer of the first isolation medium 201 is first deposited inside the first accommodation groove 2002 and on the upper surface of the silicon substrate 200 by using a chemical vapor deposition method, then the first bottom metal electrode layer 202, the first insulation medium 203, and the first top metal electrode layer 204 are sequentially deposited on the surface of the first isolation medium 201 by using an atomic layer deposition process, and finally the first accommodation groove 2002 is completely filled with the first top metal electrode layer 204, so that the first nanocapacitor is prepared.
Referring to fig. 7, photolithography and etching processes are then used to remove the first top metal electrode layer 204 and the first insulating medium 203 on the left portion of the first nanocapacitor, so as to expose the first bottom metal electrode layer 202, and form the first groove 2003. And finally, growing the second isolation medium 205 in the first groove 2003 by adopting a chemical vapor deposition process, wherein the second isolation medium 205 completely fills the first groove 2003 structure, and the integrity of the first nano-capacitor structure is ensured.
In step S03, referring to fig. 8, a layer of SiO is sequentially deposited on the surface of the first nanocapacitive structure by a chemical vapor deposition process 2 And a layer of Si 3 N 4 Then repeating the above process to alternately grow SiO 2 Layer 206 and Si 3 N 4 Layer 207 until the number and thickness of the insulating substrate 208 are obtained, it being noted that SiO is added 2 Layer 206 acts as a sacrificial layer.
In step S04, referring to fig. 9, a photoresist is then spun on the upper surface of the insulating substrate 208 and a pattern of blind vias is defined by an exposure and development process, and then the insulating substrate 208 is etched by a DRIE process until a layer of SiO in contact with the first top metal electrode layer 204 2 Layer 206.
Referring to FIG. 10, a hot phosphoric acid solution is further used to selectively etch and remove part of Si on the side wall of the blind hole 3 N 4 A layer 207 prepared as the second receiving groove 2004.
Referring to fig. 11, finally, a photolithography and an etching process are used to remove the left portion of the insulating substrate 208 and the second isolation medium 205, so as to form the first connection hole 2005, and the bottom end of the first connection hole 2005 is exposed out of the first bottom metal electrode layer 202.
In the step S05, referring to fig. 12, an atomic layer deposition process is first used to deposit a layer of the second bottom metal electrode layer 209 in the first connection hole 2005, in the second receiving cavity 2004 and on the upper surface of the insulating substrate 208, and the second bottom metal electrode layer 209 completely fills the first connection hole 2005. Then, the second insulating medium 210 and the second top metal electrode layer 211 are sequentially deposited on the surface of the second bottom metal electrode layer 209 by using an atomic layer deposition process, and it is worth mentioning that the second top metal electrode layer 211 completely fills the second receiving groove 2004 and covers the upper surface of the insulating substrate 208, so as to form the second nanocapacitor.
In the step S06, referring to fig. 13, firstly, photolithography and etching processes are used to remove the second top metal electrode layer 211 and the second insulating medium 210 on the left side portion of the insulating substrate 208 and expose the second bottom metal electrode layer 209, so as to form the second groove 2006. Then, the second top metal electrode layer 211, the second insulating medium 210 and the second bottom metal electrode layer 209 on the right side portion are removed until the insulating substrate 208 is exposed, and the third groove 2007 is formed. Then, a chemical vapor deposition process is used to deposit isolation dielectrics in the second groove 2006, on the second top metal electrode layer 211 and in the third groove 2007, and photolithography and etching processes are used to remove the isolation dielectrics on the upper surface of the second top metal electrode layer 211, so as to form the third isolation dielectric 212 and the fourth isolation dielectric 213.
Referring to fig. 14, a photolithography and etching process is then used to remove a portion of the third isolation medium 212, so as to form an extended hole as the first connection hole 2005, and expose the second bottom metal electrode layer 209. Further, photolithography and etching processes are used to remove the fourth isolation medium 213 and the insulating substrate 208 thereunder until the first top metal electrode layer 204 is exposed, i.e. the second connection hole 2008 is formed.
In the step S07, referring to fig. 15, an atomic layer deposition process is further used to deposit the metal layer 214 in the extended hole of the first connection hole 2005, the upper surface of the second top metal electrode layer 211, the upper surface of the third isolation medium 212, the upper surface of the fourth isolation medium 213 and the second connection hole 2008.
Referring to fig. 16, a photolithography and etching process is finally used to remove a portion of the metal layer 214, thereby forming the first conductive member 215 and the second conductive member 216.
It should be noted that the plasma selected for etching may be selected to be CF 4 、SF 6 、CHF 3 、CF 4 /O 2 (CF 4 And O 2 Mixture of) SF 6 /O 2 (SF 6 And O 2 Mixture of) CHF 3 /O 2 (CHF 3 And O 2 Mixtures of (b) can be used. And the insulating substrate 208 can be selected from amorphous C and Si 3 N 4 Lamination, SiO 2 With Si 3 N 4 Lamination, SiO 2 Laminated with amorphous C, SiO 2 And GeO 2 Lamination of Si 3 N 4 With GeO 2 Any of the laminates.
In addition, SiO may be selected 2 、Si 3 N 4 The first isolation dielectric 201, the second isolation dielectric 205, the third isolation dielectric 212 and the fourth isolation dielectric 213 are made of one of SiON, SiCOH or SiCOFH, the first bottom metal electrode layer 202, the first top metal electrode layer 204, the second bottom metal electrode layer 209 and the second top metal electrode layer 211 can be made of any one of TaN, TiN, WN, MoN, Ni or Ru, and the Al can be made of Al 2 O 3 、ZrO 2 、TiO 2 、HfO 2 、La 2 O 3 The first insulating medium 203 and the second insulating medium 210 are made of any one material among HfZrO, HfAlO, and HfTiO, thereby greatly improving the selectivity of product materials.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to the embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (12)
1. A three-dimensional integrated structure, comprising:
a first nanocapacitor comprising a silicon substrate, a first isolation medium, a first bottom metal electrode layer and a first top metal electrode layer; the upper surface of the silicon substrate is provided with a plurality of first accommodating grooves, the first isolation medium, the first bottom metal electrode layer and the first top metal electrode layer are arranged in the first accommodating grooves and on the surface of the silicon substrate, and the first isolation medium separates the first bottom metal electrode layer from the silicon substrate;
a second nanocapacitor comprising an insulating substrate, a second bottom metal electrode layer and a second top metal electrode layer; the insulating substrate is arranged on a first top metal electrode layer, the insulating substrate is provided with a plurality of second accommodating grooves, a first connecting hole and a second connecting hole, the first connecting hole is communicated to the first bottom metal electrode layer, the second connecting hole is communicated to the first top metal electrode layer, and the second bottom metal electrode layer is arranged in the second accommodating grooves and is electrically connected with the first bottom metal electrode layer through the first connecting hole;
the first conductive piece is electrically connected with the first top metal electrode layer and the second top metal electrode layer through the second connecting hole respectively;
the silicon substrate is made of silicon material, and the insulating substrate is made of SiO alternately laminated 2 Layer and Si 3 N 4 And (4) preparing layers.
2. The three-dimensional integrated structure of claim 1, wherein:
the first nano-capacitor further comprises a first insulating medium and a second insulating medium; wherein the content of the first and second substances,
the first insulating medium is arranged between the first bottom metal electrode layer and the first top metal electrode layer;
the first nano capacitor is provided with a first groove, the first groove is positioned at one end of the first connecting hole, the side surface of the first groove is a combined layer of the first insulating medium and the first top metal electrode layer, and the bottom surface of the first groove is the first bottom metal electrode layer;
the second isolation medium is arranged in the first groove, and the first connecting hole penetrates through the second isolation medium.
3. The three-dimensional integrated structure of claim 2, wherein:
the second nano capacitor further comprises a second insulating medium, the second insulating medium is arranged between the second bottom metal electrode layer and the second top metal electrode layer, and the second bottom metal electrode layer, the second insulating medium and the second top metal electrode layer cover the second accommodating groove and the upper surface of the insulating substrate.
4. The three-dimensional integrated structure of claim 3, wherein:
the second nano-capacitor further comprises a third isolation medium and a fourth isolation medium;
the second nano capacitor is provided with a second groove and a third groove, the second groove is positioned at the other end of the first connecting hole, and the side surface of the second groove is a combined layer of the second top metal electrode layer and the second insulating medium, the bottom surface of the second groove is the second bottom metal electrode layer, the third groove is positioned at one end of the second connecting hole, and the side surface of the third groove is the second bottom metal electrode layer, the second insulating medium and the second top metal electrode layer, the bottom surface of the third groove is the upper surface of the insulating substrate, the third isolation medium is arranged in the second groove, and the extension hole of the first connection hole penetrates through the third isolation medium, the fourth isolation medium is arranged in the third groove, and the second connection hole penetrates through the fourth isolation medium.
5. The three-dimensional integrated structure of claim 4, wherein:
the first conductive piece is T-shaped, one end of the first conductive piece is arranged in the extending hole of the first connecting hole and is electrically connected with the first bottom metal electrode layer, and the other end of the first conductive piece is connected with the third isolation medium.
6. The three-dimensional integrated structure of claim 5, wherein:
the first conductive piece is T-shaped, one end of the first conductive piece is arranged on the second connecting hole and abutted to the first top metal electrode layer, and the other end of the first conductive piece is connected with the second top metal electrode layer.
7. The three-dimensional integrated structure of claim 1, wherein:
the first holding tank with the second holding tank is "soil" type recess.
8. A manufacturing method for manufacturing a three-dimensional integrated structure according to any one of claims 1 to 7, characterized in that:
s01: forming the first accommodating groove on the silicon substrate;
s02: arranging the first isolation medium, the first bottom metal electrode layer and the first top metal electrode layer on the surface of the silicon substrate and in the first accommodating groove, wherein the first isolation medium separates the first bottom metal electrode layer from the silicon substrate to prepare the first nano capacitor;
s03: providing an insulating substrate on the first top metal electrode layer;
s04: forming the second accommodating groove and the first connecting hole on the insulating substrate, wherein the first connecting hole is conducted to the first bottom metal electrode layer;
s05: arranging a second bottom metal electrode layer and a second top metal electrode layer on the surface of the insulating substrate and in the second accommodating groove, wherein the second bottom metal electrode layer is electrically connected with the first bottom metal electrode layer through the first connecting hole, so that the second nano capacitor is prepared;
s06: arranging the second connecting hole in the second nano capacitor, wherein the second connecting hole is communicated with the first top metal electrode layer;
s07: and arranging the first conductive piece, wherein the first conductive piece is respectively and electrically connected with the first top metal electrode layer and the second top metal electrode layer through the second connecting hole.
9. The method of manufacturing a three-dimensional integrated structure according to claim 8, wherein:
the step S02 is further provided with a first insulating medium and a second insulating medium, wherein the first bottom metal electrode layer, the first insulating medium, and the first top metal electrode layer are sequentially disposed, then a first groove is formed in the first nanocapacitor, and the second insulating medium is disposed in the first groove.
10. The method of manufacturing a three-dimensional integrated structure according to claim 8, wherein:
a second insulating medium is further disposed in step S05, and the second bottom metal electrode layer, the second insulating medium, and the second top metal electrode layer are sequentially disposed in the second accommodating groove and on the upper surface of the insulating substrate until the second bottom metal electrode layer, the second insulating medium, and the second top metal electrode layer cover the second accommodating groove and the upper surface of the insulating substrate.
11. The method of claim 10, wherein:
in step S06, a second groove and a third groove are formed in the second nanocapacitor in advance, the second groove is located at the other end of the first connection hole, a third isolation medium is disposed in the second groove, a fourth isolation medium is disposed in the third groove, an extension hole of the first connection hole is formed to conduct the third isolation medium, and the second connection hole is conducted to the first top metal electrode layer through the fourth isolation medium and the insulating substrate.
12. The method of manufacturing a three-dimensional integrated structure according to claim 11, wherein:
in step S07, a second conductive member is further disposed, one end of the second conductive member is disposed in the extension hole of the first connection hole and electrically connected to the second bottom metal electrode layer, and the other end of the second conductive member is connected to the third isolation medium.
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