CN113929053A

CN113929053A - MEMS device wafer level packaging method and packaging structure

Info

Publication number: CN113929053A
Application number: CN202010675993.8A
Authority: CN
Inventors: 黄河; 刘孟彬; 向阳辉
Original assignee: Smic Ningbo Co ltd Shanghai Branch
Current assignee: Smic Ningbo Co ltd Shanghai Branch
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2022-01-14
Also published as: WO2022012476A1

Abstract

The embodiment of the invention provides a wafer-level packaging method and a packaging structure of an MEMS device, wherein the method comprises the following steps: providing a device wafer, wherein a first chip and a first electric connection part electrically connected with the first chip are formed in the device wafer; providing a cover having an interconnect structure formed therein, the interconnect structure including a second electrical connection; forming a fence on the first surface of the device wafer or the first surface of the sealing cover, wherein the area surrounded by the fence is a cavity; after the enclosing wall is formed, the bonding sealing cover corresponds to the device wafer, the first chip corresponds to the cavity, the first electric connection part and the second electric connection part are opposite and are at least partially positioned outside the enclosing wall to form an electric connection cavity, and the electric connection cavity is provided with an opening; a first conductive block is formed to electrically connect the first electrical connection portion and the second electrical connection portion. The MEMS device wafer level packaging method and the packaging structure provided by the embodiment of the invention can improve the compatibility and the yield of the obtained product.

Description

MEMS device wafer level packaging method and packaging structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a wafer-level packaging method and a packaging structure of an MEMS (micro-electromechanical system) device.

Background

With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. The existing packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional Package (3D), System In Package (SiP), and the like, and System integration packages adopting three-dimensional stacking modes of different forms have been increasingly applied.

At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts wafer level package in package (WLPSIP) in a three-dimensional stacking mode.

In the wafer level system packaging process, two bare chips need to be bonded together to realize physical connection, and interconnection leads thereof need to be connected to realize electrical connection.

Disclosure of Invention

The embodiment of the invention provides a wafer-level packaging method and a packaging structure of an MEMS device, which are used for improving the compatibility and the yield of an obtained product while realizing wafer-level packaging.

To solve the above problems, an embodiment of the present invention provides a wafer level packaging method for an MEMS device, including:

providing a device wafer, wherein a first chip and a first electric connection part electrically connected with the first chip are formed in the device wafer;

providing a cover having an interconnect structure formed therein, the interconnect structure including a second electrical connection;

forming a wall on the first surface of the device wafer or the first surface of the sealing cover, wherein the area surrounded by the wall is a cavity;

bonding the sealing cover and the device wafer after the enclosing wall is formed, wherein the first chip corresponds to the cavity, the first electric connection part and the second electric connection part are opposite and are at least partially positioned outside the enclosing wall to form an electric connection cavity, and the electric connection cavity is provided with an opening;

forming a first conductive block to electrically connect the first electrical connection portion and the second electrical connection portion.

Accordingly, to solve the above problem, an embodiment of the present invention further provides a MEMS device package structure, including:

a device substrate in which a first chip and a first electrical connection portion electrically connected to the first chip are formed;

a cover having an interconnect structure formed therein, the interconnect structure including a second electrical connection; (ii) a

The enclosure is positioned between the device substrate and the sealing cover, the first chip corresponds to a cavity defined by the enclosure, and the first electric connection part is opposite to the second electric connection part and is at least partially positioned outside the enclosure;

and a first conductive block electrically connecting the first electrical connection portion and the second electrical connection portion.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the wafer-level packaging method for the MEMS device, provided by the embodiment of the invention, the sealing cover with the interconnection structure is bonded with the MEMS device wafer, the interconnection between the MEMS device and an external signal can be realized, and the device wafer and the sealing cover are connected through the enclosing wall, so that a generation space is provided for the first conductive block electrically connecting the first electric connection part and the second electric connection part of the sealing cover, a cavity working environment is provided for a working area of the MEMS device, and the performance of the device is improved.

In the alternative, the first electric connection part of the device wafer is electrically connected with the second electric connection part of the sealing cover by using an electroplating process, and the MEMS is electrically led out to the top of the sealing cover, so that a Through Silicon Via (TSV) process is avoided, the manufacturing cost is saved, the difficulty in packaging a wafer-level system in a three-dimensional stacking mode is reduced, and the yield of products is improved.

In an alternative, in the wafer-level packaging method for the MEMS device provided by the embodiment of the present invention, the provided cap includes a release layer located between the substrate and the dielectric layer, on one hand, the substrate may provide support for processing the interconnect structure, or simultaneously provide support for bonding the cap and the device wafer; on the other hand, the existence of the release layer can remove the substrate through the release of the release layer after finishing the processing of the interconnection structure or finishing the bonding of the sealing cover and the device wafer, thereby improving the convenience of removing the substrate, realizing the accurate control of removing the substrate, avoiding the damage to the device caused by the lower accuracy of thickness control when the substrate is removed in a grinding mode, and improving the yield of products.

Drawings

Fig. 1 to 8 are schematic structural diagrams corresponding to steps of a wafer level packaging method according to an embodiment of the invention;

fig. 9 to 10 are schematic structural diagrams corresponding to a part of steps in another embodiment of the wafer level packaging method of the present invention.

Detailed Description

Wafer level system packaging mainly includes two important processes of physical connection and electrical connection. Among them, the most typical packaging method may be: 1) the upper bare chip and the lower bare chip are stacked on the substrate in a three-dimensional mode through the curing glue, and lead bonding pads of the two bare chips are led to the substrate through a lead interconnection (wire bond) process; 2) the upper bare chip and the lower bare chip are stacked on the substrate in a three-dimensional manner through the curing adhesive, the lead bonding pad of the upper bare chip is led to the lead bonding pad of the lower bare chip by adopting a wire bond process, and then the lead bonding pad of the lower bare chip is led to the substrate; 3) realizing flip-chip bonding by means of bump welding (bump) prefabricated on the surface of the upper bare chip or bump welding prefabricated on the surface of the lower bare chip, and leading a lead pad of the lower bare chip onto the substrate by means of a wire bond; 4) the flip-chip bonding is realized by the projection spot welding prefabricated on the surface of the upper bare chip or the projection spot welding prefabricated on the surface of the lower bare chip, and the lead bonding pad of the lower bare chip is connected to the back surface of the lower bare chip by a through silicon via interconnection (TSV) structure prefabricated in the lower bare chip.

Among them, the bump flip-chip bonding process is increasingly used, especially for high-density system integration packaging based on the through silicon via interconnection process and micro-bump flip-chip bonding. However, the TSV structure prefabricated in the lower die connects the lead pad of the lower die to the back surface of the lower die, and with the development trend of integrated circuits, the complexity of integrated circuit design is continuously increased, and the layout of the metal interconnection structure is correspondingly more and more complicated, so that the difficulty of TSV process is increased, and even the TSV structure cannot be formed due to the blocking effect of the functional structure (e.g., the metal interconnection structure) in the lower die.

In order to solve the technical problem, an embodiment of the present invention provides a wafer-level packaging method for an MEMS device, in which a cap having an interconnection structure is bonded to an MEMS device wafer, so that interconnection between the MEMS device and an external signal can be achieved, and the device wafer and the cap are connected by a surrounding wall, so as to provide a generation space for a first conductive block electrically connecting a first electrical connection portion and a second electrical connection portion of the cap, and simultaneously provide a cavity working environment for a working area of the MEMS device, thereby improving performance of the device.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 to 8 are schematic structural diagrams corresponding to steps of an embodiment of a wafer level packaging method according to the present invention.

Referring to fig. 1, a device wafer 100 is provided, in which a first chip 110 and a first electrical connection portion 120 electrically connected to the first chip 110 are formed in the device wafer 100.

The wafer level packaging method is used for realizing wafer level system packaging, and the device wafer 100 is used for bonding with a chip to be integrated in a subsequent process. Of course, device wafer 100 is a MEMS device wafer. The device wafer 100 is fabricated using integrated circuit fabrication techniques. In this embodiment, device wafer 100 includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

A first chip 110 and a first electrical connection portion 120 are formed in the device wafer 100, and certainly, in order to realize electrical connection with an electrical connection portion of a chip to be integrated in a subsequent process, the first electrical connection portion 120 is located on a first surface of the device wafer 100, that is, a surface of the first electrical connection portion 120 is exposed; in addition, the first electrical connection portion 120 does not cover the first chip 110 and exposes the first chip 110, which provides a foundation for forming a cavity working environment of the first chip 110 in a subsequent process.

The surface of the first electrical connection portion 120 protrudes from the surface of the first chip 110, and is electrically connected to the internal structure of the first chip 110. In other embodiments, the surface of the first electrical connection portion 120 may be the same surface as the surface of the first chip 110, or the surface of the first electrical connection portion 120 is lower than the surface of the first chip 110.

In this embodiment, the device wafer 100 includes a front wafer surface and a back wafer surface opposite to the front wafer surface, and the first electrical connection portion 120 is located on the front wafer surface, i.e., the first electrical connection portion 120 is exposed on the front wafer surface. Wherein wafer backside refers to the bottom surface of the substrate in device wafer 100.

It should be noted that the exposed position of the first electrical connection portion 120 can be protected by a dielectric layer (not labeled) to prevent short circuit, and in the wafer level packaging method of the MEMS device, the dielectric layer is etched to expose the first electrical connection portion 120.

For convenience of illustration, the present embodiment is described by taking the device wafer 100 as an example in which three first chips 110 are formed. The number of the first chips 110 is not limited to three. In addition, for convenience of illustration, the number of the first electrical connection portions 120 electrically connected to the same first chip 110 is two to realize input and output of signals of the first chip 110, and of course, the number of the first electrical connection portions 120 electrically connected to the same first chip 110 may be plural.

It can be understood that each first chip 110 of the same device wafer 100 may be the same type of chip having the same function, and may also be a chip having a different function, and each first chip 110 of the same device wafer 100 may specifically include: at least one of a bulk acoustic wave filter, a surface acoustic wave filter, a solid-state mounted resonator, a microphone, and a fingerprint recognition device.

Referring to fig. 2, a cover 300 is provided, an interconnection structure 331 is formed in the cover 300, and the interconnection structure 331 includes a second electrical connection portion 331 a.

The cover 300 is part of a structure to be integrated of a wafer level package in which an interconnect structure 331 is formed, changing the position of the first electrical connection 120 at the wafer plane while enabling packaging of the device wafer 100.

The cover 300 is manufactured by using an integrated circuit manufacturing technology, and the second electrical connection portion 331a is located on a first surface of the cover 300, that is, the second electrical connection portion 331a is exposed.

It should be noted that the exposed position of the second electrical connection portion 331a can be protected by a dielectric layer (not labeled) to prevent short circuit, and in the wafer level packaging method of the MEMS device, the dielectric layer is etched to expose the second electrical connection portion 331a, and a groove is formed on the surface of the second electrical connection portion 331a lower than the surface of the dielectric layer.

The cap 300 may include a substrate 310, in this embodiment, the substrate 310 is a silicon substrate, in other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or glass, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. In other embodiments, the cap may not include a substrate, but only a dielectric layer with an interconnect structure formed thereon.

In this embodiment, the closure 300 is obtained by:

providing a substrate 310;

forming a release layer 320 on the substrate 310, the release layer 320 covering the substrate 310;

a dielectric layer 330 is formed on the release layer 320, and an interconnect structure 331 is formed in the dielectric layer 330.

In other embodiments, the step of forming the cap 300 may further include, after forming the interconnect structure 331 in the dielectric layer 330, releasing the release layer 320 and removing the substrate 310. I.e., cap 300 is a dielectric layer that includes only interconnect structure 331 formed therein.

The substrate 310 provides support for the fabrication of the interconnect structure 331 of the cap 300. The substrate of the cover 300 can be described by referring to the related description above, and will not be described herein. The release layer 320 provides convenience for removing the substrate 310, in this embodiment, the release layer 320 is a germanium release layer; in other embodiments, the release layer material is at least one of carbon and a pyrolytic film; when the substrate is a light-transmitting glass, the material of the release layer can also be a photolytic film.

The dielectric layer 330 provides a forming space for the interconnect structure 331, and as shown in fig. 2, a dielectric material layer is first deposited on the release layer 320, and then etching and filling are performed at corresponding positions of the dielectric material layer to form the interconnect structure 331.

In this embodiment, the dielectric layer 330 is made of high-resistivity silicon, the interconnection structure 331 is made of copper, the resistivity of copper is low, and the copper material is selected to facilitate improvement of the conductivity of the interconnection structure 331; moreover, the interconnection structure 331 is formed in the interconnection structure hole, and the copper filling property is better, so that the formation quality of the interconnection structure 331 in the interconnection structure hole is improved. In other embodiments, the material of the dielectric layer may also be other materials with higher resistance, and the material of the interconnect structure may also be other applicable conductive materials, such as: nickel, zinc, tin, gold, tungsten, magnesium.

It is easily understood that, in order to realize interconnection, the interconnection structure further includes a third electrical connection portion electrically connected to the second electrical connection portion, and the third electrical connection portion and the second electrical connection portion are respectively located on two opposite surfaces of the cover. In this embodiment, as shown in fig. 2, the cover 300 includes a substrate 310 and a release layer 320, where the third electrical connection portion and the second electrical connection portion are respectively located on two opposite surfaces of the cover, that is, the interconnect structure 331 may include a second electrical connection portion 331a located on a first surface of the dielectric layer 330 and a third electrical connection portion 331c located on a second surface of the dielectric layer 330, and of course, the interconnect structure may further include a plug 331b electrically connecting the second electrical connection portion 331a and the third electrical connection portion 331c, and include a redistribution layer (RDL) structure (not shown in the figure), where the first surface of the dielectric layer 330 is opposite to the second surface of the dielectric layer 330. In other embodiments, the cover only includes a dielectric layer formed with the interconnect structure, and the third electrical connection and the second electrical connection are located on two opposite surfaces of the dielectric layer, i.e., on two opposite surfaces of the cover.

In order to reduce the thickness of the package structure after wafer-level packaging of the MEMS device, thinning may be performed after the processing of the interconnect structure 311 or wafer-level packaging of the MEMS device is completed. While the release layer 320 is formed on the substrate 310 first, and then the dielectric layer 330 is formed on the release layer 320, on one hand, the substrate 310 may provide support for processing the interconnect structure 331 or simultaneously provide support for bonding the cap 300 and the device wafer 100; on the other hand, the existence of the release layer 320 can remove the substrate 310 through the release of the release layer 320 after the processing of the interconnection structure 331 is completed or the bonding of the cap 300 and the device wafer 100 is completed, so that the convenience of removing the substrate 310 is improved, the accurate control of removing the substrate 310 can be realized, the damage to the device caused by the lower thickness control accuracy when the substrate 310 is removed by grinding is avoided, and the yield of the product is improved.

In other embodiments, a dielectric layer may be formed directly on the substrate to form the interconnect structure.

The cap 300 may be a wafer level cap, i.e., the cap 300 has a wafer size, the number of interconnect structures 331 of the cap 300 is the same as the number of first electrical connections 110 of the device wafer 100.

In this embodiment, taking the example that the number of the first chips 110 of the device wafer 100 is three, and the number of the first electrical connection portions 120 electrically connected to each first chip 110 is two, the number of the interconnection structures 331 of the cap 300 is six accordingly. The number of interconnect structures 331 is not limited to six.

When the cap 300 is a wafer-level cap, wafer-level packaging can be realized by one-time bonding, so that the processing process can be simplified, and the packaging speed can be increased.

In other embodiments, the cover 300 may be a chip-scale cover, and providing a cover as described herein includes providing a plurality of chip-scale covers, which may be the same as the number of the first chips 110 of the device wafer 100 or different from the number of the first chips 110 of the device wafer 100, and of course, the number of the second electrical connection portions 331a of each chip-scale cover is the same as the number of the first electrical connection portions 120 of each first chip 110.

When the structures of the first chips 110 of the device wafer 100 are the same, the structures of the chip-scale covers may be the same, or may be different on the basis of ensuring the subsequent bonding and packaging requirements; when the structures of the respective first chips 110 of the device wafer 100 are the same, chip-level caps having different structures may be selected to achieve the via interconnection of different first chips 110.

A plurality of discrete chip-scale lids may be obtained by dicing the wafer-scale lid.

Referring to fig. 3, a fence 200 is formed on the first surface of the device wafer 100, and an area surrounded by the fence 200 is a cavity 210.

By forming the fence 200 on the first surface of the device wafer 100, a support is formed between the device wafer 100 and the cap 300, providing space for the electrical connection of the first electrical connection 120 and the second electrical connection 331 a.

The area surrounded by the enclosing wall 200 is a cavity 210, which corresponds to the position of the first chip 110 of the device wafer 100, and provides a moving space for the first chip, thereby improving the performance of the first chip.

In this embodiment, the fence 200 may be formed on a portion of the surface of the first electrical connection structure 120 and an edge of the first chip 110. Of course, the fence 200 may be formed on only a portion of the surface of the first electrical connection structure 120, or a portion of the surface of the first electrical connection structure 120, in the same step, so as to improve the packaging efficiency, and avoid occupying the corresponding area of the first chip 110 to form the unsealed cavity 210.

In this embodiment, the material of the fence 200 may be a Dry Film (Dry Film). The dry film is a viscous photoresist film used in semiconductor chip packaging or printed circuit board manufacturing, and a pattern can be formed in the dry film by exposure and development.

In another embodiment, the material of the enclosing wall 200 may be a metal, a metal layer is deposited on the first surface of the device wafer 100, then the metal layer is etched, and the remaining metal layer is used as the enclosing wall, or a dielectric layer is deposited on the first surface of the device wafer 100, the dielectric layer on the portion of the surface of the first electrical connection structure 120 close to the first chip 100 and the edge of the first chip 110 is etched, a filling hole is formed, the metal is filled in the filling hole, and the remaining dielectric layer is removed, so as to obtain the enclosing wall; in other embodiments, the material of the fence may also be a photosensitive material, so that patterning can be achieved through a photolithography process, and damage to the electrode or the external interconnection line can be reduced.

Note that the thickness of the fence 200 is not too small nor too large. If the thickness is too small, the height of the enclosing wall 200 is insufficient, so that sufficient filling space for the electrical connection material of the first electrical connection portion 120 and the second electrical connection portion 331a cannot be provided, the difficulty of filling the subsequent conductive material therein is increased, and the most sufficient space for the cavity 210 cannot be provided, and the requirement of the first chip 110 for the movable space cannot be satisfied; if the thickness is too large, the thickness of the package structure formed subsequently is too large, which is not favorable for the development of miniaturization of the device. For this reason, in the present embodiment, the thickness of the fence 200 ranges from 5 micrometers to 50 micrometers.

Referring to fig. 4, after the enclosure wall 200 is formed, the cap 300 and the device wafer 100 are bonded, the first chip 110 corresponds to the cavity 210, and the first electrical connection portion 120 and the second electrical connection portion 331a are opposite to each other and are at least partially located outside the enclosure wall 200 to form an electrical connection cavity 400.

After the formation of the perimeter walls 200, system integration of the cap 300 with the device wafer 100 is achieved by bonding the cap 300 to the perimeter walls 200. Moreover, the first surface of the cover 300 is bonded to the surrounding wall 200, so that the second electrical connection portion 331a faces the first electrical connection portion 120, and the first electrical connection portion 120 and the second electrical connection portion 331a are electrically connected.

In this embodiment, after the cover 300 is bonded to the enclosing wall 200, an electrical connection cavity 400 is formed between the first electrical connection portion 120 and the second electrical connection portion 331a, the electrical connection cavity 400 is used for filling an electrical connection material, and the first electrical connection portion 120 is electrically connected to the second electrical connection portion 331 a.

In the present embodiment, the material of the fence 200 is a dry film, and the cap 300 is adhered to the fence 200 to bond the cap 300 and the device wafer 100. In other embodiments, the material of the fence 200 is metal, and the bonding between the cap 300 and the device wafer 100 is achieved by metal-to-metal bonding.

In the embodiment, the cap 300 is a wafer-level cap, and after the cap 300 is bonded to the device wafer 100, the cap 300 may be cut to facilitate subsequent filling of the electrical connection material, in addition to the electrical connection cavity 400 at the edge.

Specifically, referring to fig. 5, the cap 300 is cut along the cutting lines to form openings 600 for filling the electrical connection material.

The opening 600 communicates with the electrical connection cavity 400 so that the filling electrical connection material enters the electrical connection cavity 400 through the opening 600 to electrically connect the first electrical connection portion 120 and the second electrical connection portion 331 a.

In this embodiment, a laser cutting process may be employed to cut the cover 300 along the cutting path to form the opening 600; in other embodiments, the opening 600 may be formed by cutting the cap 300 along a cutting path using a knife cutting process.

In other embodiments, the cap is a chip-scale cap, and when the cap is bonded to the device wafer, each chip-scale cap is bonded to each first chip, and after the chip-scale cap is bonded to the first chip, the electrical connection cavity between the first electrical connection portion and the second electrical connection portion is an unsealed cavity, and an opening is directly formed, so that an electrical connection material can be filled into the electrical connection cavity.

Referring to fig. 6 and 7, a first conductive block 410 is formed to electrically connect the first electrical connection portion 120 and the second electrical connection portion 331 a.

The first electrical connection portion 120 and the second electrical connection portion 331a are electrically connected through the first conductive bump 410, so that the package cap 300 and the device wafer 100 are interconnected and the electrical property of the device wafer 100 is led out, thereby preparing for a subsequent packaging process. For example, electrical connection of the first chip 110 to other substrates (e.g., circuit boards) can be subsequently achieved through the second conductive bumps 420 (shown in fig. 7).

Specifically, an electrical connection material may be filled into the electrical connection cavity 400 from the boundary of the opening 600 by using a plating process to form the first conductive block 410, and the first conductive block 410 in the electrical connection cavity 400 is in contact with both the first electrical connection portion 120 and the second electrical connection portion 331a, so that the first electrical connection portion 120 and the second electrical connection portion 331a may be electrically connected. Through the electroplating process, a good filling effect can be achieved in the electrical connection cavity 400, thereby improving the reliability of the electrical connection.

In this embodiment, the electroplating process is electroless plating (i.e., electroless plating). Specifically, the bonded cap 300 and the device wafer 100 are placed in a solution containing metal ions (e.g., a solution such as electroless silver plating, nickel plating, or copper plating), without being energized, and according to the principle of redox reaction, the metal ions are reduced to metal by a strong reducing agent and deposited on the surfaces of the first electrical connection portion 120 and the second electrical connection portion 331a to form a dense metal plating layer, and after a certain reaction time, the metal plating layer fills the electrical connection cavity 400, thereby forming the first conductive bump 410. Accordingly, the material of the first conductive block 410 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.

In other embodiments, a bump (bumping) process may also be used to form a solder bump on the first electrical connection portion or the second electrical connection portion as the first electrical connection block.

As shown in fig. 6, in the present embodiment, after bonding the cap 300 and the device wafer 100 and cutting to form the opening 600, the release layer 320 is released, and the substrate 310 is removed.

Releasing the release layer 320 after the bonding of the cap 300 and the device wafer 100 is completed can reduce the thickness requirement for the dielectric layer 330 of the cap 300 and reduce the bonding difficulty.

The opening 600 is formed first and then the release layer 320 is released, so that the etching area or the heating area of the release layer 320 can be enlarged, the removal speed of the release layer 320 is increased, and the processing efficiency is improved.

As mentioned above, in this embodiment, the substrate 310 is a silicon substrate, and the release layer 320 is a germanium release layer; the removal of release layer 320 and substrate 310 may be accomplished by etching release layer 320 through a wet etch process. In other embodiments, when the material of the release layer is a pyrolytic film, the removal of the release layer and the substrate can be achieved by heating, and when the material of the release layer is a photolytic film and the substrate is a transparent glass, the removal of the release layer and the substrate can be achieved by illumination.

Of course, in another embodiment, the release layer and the substrate may be removed first and then cut to form the opening 600.

As shown in fig. 7, since the interconnect structure 331 may include a second electrical connection portion 331a located on the first surface of the dielectric layer 330 (i.e., the first surface of the cap 300), a third electrical connection portion 331c located on the second surface of the dielectric layer 330, and a plug 331b electrically connecting the second electrical connection portion 331a and the third electrical connection portion 331c, after the release layer 320 and the substrate 310 are removed, the third electrical connection portion 331c is exposed on the second surface of the dielectric layer 330, so that the first conductive bump 410 is formed by electroplating, and at the same time, a second conductive bump 420 is also formed on the surface of the third electrical connection portion 331c, so as to achieve subsequent electrical connection with another substrate (e.g., a circuit board).

Thus, the first conductive block 410 and the second conductive block 420 can be formed by one-time electroplating, so that the process flow can be simplified, and the process efficiency can be improved.

In other embodiments, the second conductive bump may also be formed by ball-planting on the third electrical connection portion, and the second conductive bump and the first conductive bump may be separately generated.

Therefore, in the wafer-level packaging method for the MEMS device provided by the embodiment of the present invention, the cap 300 having the interconnect structure 330 is bonded to the wafer device 100, and the first electrical connection portion 120 of the device wafer 100 is electrically connected to the second electrical connection portion 331a of the cap 300 by using the electroplating process, so that the connection point of the first electrical connection portion 120 of each first chip 110 of the device wafer 100 can be rewired in the plane direction of the device wafer 100, thereby improving the flexibility and compatibility of connection between the first chip 110 of the device wafer 100 and other chips; the device wafer 100 and the cap 300 are connected through the enclosing wall 200, a generating space of the first conductive block 410 is provided for the first electrical connection portion 120 to be electrically connected with the second electrical connection portion 331a of the cap 300, the electrical connection between the three-dimensionally stacked components is realized through the electroplating process, the use of the through silicon via interconnection technology is omitted, the difficulty of packaging the wafer-level system in the three-dimensional stacking mode is reduced, the yield of products can be improved, the device wafer 100 and the cap 300 are connected through the enclosing wall 200, the cavity 210 can be formed at the position corresponding to the first chip 110, a movable space is provided for the first chip 110, and the performance of the device is improved.

In another embodiment, referring to fig. 8, after the step of forming the first conductive block 410 by electroplating, the method further includes: the opening 600 is filled with an injection molding agent to form the encapsulation layer 500.

The encapsulation layer 500 serves to protect and insulate the first conductive bumps 410. Therefore, the material of the encapsulation layer 500 is an insulating material. In this embodiment, the material of the encapsulation layer 500 is epoxy resin, and in other embodiments, the material of the encapsulation layer includes one or two of a dielectric material and a molding compound, where the dielectric material may be silicon oxide, silicon nitride, or other dielectric materials.

The encapsulation layer 500 may also provide protection and insulation for the second conductive bumps 420 when the second conductive bumps 420 are formed, and in order to simultaneously satisfy protection of the second conductive bumps 420 and facilitate connection of the second conductive bumps 420 with other circuits, as shown in fig. 8, the encapsulation layer 500 may cover a portion of the second conductive bumps 420.

In other embodiments, the encapsulation layer 500 may also completely cover the top surface of the second conductive block 420, or be flush with the top surface of the second conductive block 420, for which purpose the encapsulation layer may be planarized until the second conductive block 420 is exposed. In other embodiments, after the encapsulation layer is formed, the encapsulation layer over the second conductive blocks may be etched to expose the second conductive blocks.

Further, the filling after forming the opening 600 of the first conductive block 410 further includes:

the device wafer 100 bonded with the interconnect structures 331 is diced, and the first chips 110 of the device wafer 100 are separated.

The device wafer 100 bonded with the interconnect structures 331 is diced to obtain the first chips 110 having the interconnect structures 331.

The dicing process for dicing the device wafer 100 may be a knife dicing process or a laser dicing process.

Fig. 9 to 10 are schematic structural diagrams corresponding to steps of another embodiment of the wafer level packaging method of the present invention.

The same points of the embodiments of the present invention as those of the previous embodiments are not described herein again, and the embodiments of the present invention are different from the previous embodiments in that: a wall 200 is formed on the first surface of the cover 300, and the area enclosed by the wall 200 is a cavity 210.

Referring to fig. 9, a wall 200 is formed on the first surface of the cover 300, and the area surrounded by the wall 200 is a cavity 210.

For the detailed description of the fence 200, reference is made to the foregoing contents, which are not repeated herein. It should be noted that the cavity 210 enclosed by the enclosing wall 200 needs to correspond to the first chip 110 when the device wafer 100 is bonded later, and the second electrical connection portion 331a is not completely covered by the enclosing wall 200, so as to ensure the subsequent electrical connection with the first electrical connection portion 120.

Of course, when the cap 300 is a cap chip, the dam 200 is formed on each cap chip, and each cap chip formed with the dam 200 is bonded to the device wafer 100.

Referring to fig. 10, after the enclosure wall 200 is formed, the cap 300 and the device wafer 100 are bonded, the first chip 110 corresponds to the cavity 210, and the first electrical connection portion 120 and the second electrical connection portion 331a are opposite to each other and are at least partially located outside the enclosure wall 200.

Bonding the cap 300 with the enclosure wall 200 and the device wafer 100, so that the first chip 110 corresponds to the cavity 210, and the first electrical connection portion 120 and the second electrical connection portion 331a are opposite and both located at least partially outside the enclosure wall 200.

For details of this step, please refer to the description of fig. 4, which is not repeated herein.

The subsequent processes are the same as those in the previous embodiments, and are not described herein again. For a specific description of the packaging method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Correspondingly, the invention also provides a MEMS device packaging structure, which comprises:

a cover having an interconnect structure formed therein, the interconnect structure including a second electrical connection;

FIG. 8 is a schematic structural diagram of an embodiment of a MEMS device package structure of the present invention.

The MEMS device packaging structure provided by the embodiment of the invention takes the device wafer 100 as a device substrate and the dielectric layer 330 for forming the interconnection structure 331 as a sealing cover, and comprises the following components:

a device wafer 100, wherein a first chip 110 and a first electrical connection portion 120 electrically connected to the first chip 110 are formed in the device wafer 100;

a cover having an interconnect structure 331 formed therein, the interconnect structure 331 including a second electrical connection portion 331 a;

a wall 200 between the device wafer 100 and the cover, the first chip 110 corresponding to the cavity defined by the wall 200, the first electrical connection portion 120 and the second electrical connection portion 331a being opposite to each other and at least partially located outside the wall 200,

and a first conductive block 410 electrically connecting the first electrical connection portion 120 and the second electrical connection portion 331 a.

Specifically, device wafer 100 is a MEMS device wafer. The device wafer 100 is fabricated using integrated circuit fabrication techniques.

In this embodiment, device wafer 100 includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

The exposed position of the first electrical connection portion 120 can be protected by a dielectric layer (not labeled) to prevent short circuit, and in the wafer level packaging method of the MEMS device, the dielectric layer is etched to expose the first electrical connection portion 120.

Each first chip 110 of the same device wafer 100 may be the same type of chip having the same function, or may also be a chip having different functions, and each first chip 110 of the same device wafer 100 may specifically include: at least one of a bulk acoustic wave filter, a surface acoustic wave filter, a solid-state mounted resonator, a microphone, and a fingerprint recognition device.

The cap may be a wafer level cap, i.e., the cap has a wafer size, the number of interconnect structures 331 of the cap is the same as the number of first electrical connections 110 of the device wafer 100.

In this embodiment, taking the number of the first chips 110 of the device wafer 100 as three, and the number of the first electrical connection portions 120 electrically connected to each of the first chips 110 as two as an example, the number of the interconnection structures 331 of the cap is six. The number of interconnect structures 331 is not limited to six.

When the sealing cover is a wafer-level sealing cover, the wafer-level packaging can be realized through one-time bonding in the packaging process, so that the processing technology can be simplified, and the packaging speed can be increased.

In other embodiments, when the device substrate is a device wafer, the cap can also be a chip-scale cap, so that chip-scale caps with different structures can be selected to achieve different interconnection requirements.

In another specific embodiment, the device substrate may also be an MEMS device chip, the MEMS device package structure is an MEMS device chip-scale package structure, and correspondingly, the cap is also a chip-scale cap, and other structures are similar to the device wafer, and are not described herein again.

The cover serves as a part of the package structure in which the interconnect structure 331 is formed, changing the position of the first electrical connection 120 at the wafer plane while enabling packaging of the device wafer 100.

The cap is made by using an integrated circuit manufacturing technology, the exposed position of the second electrical connection portion 331a can be protected by using a dielectric layer (not labeled) to prevent short circuit, and in the wafer level packaging method of the MEMS device, the dielectric layer is etched to expose the second electrical connection portion 331a, and the surface of the second electrical connection portion 331a is lower than the surface of the dielectric layer, i.e., a groove is formed.

The interconnection structure 331 is made of copper, the resistivity of the copper is low, and the copper material is selected, so that the conductivity of the interconnection structure 331 is improved; moreover, the interconnection structure 331 is formed in the interconnection structure hole, and the copper filling property is better, so that the formation quality of the interconnection structure 331 in the interconnection structure hole is improved. In other embodiments, the material of the interconnect structure may also be other applicable conductive materials, such as: nickel, zinc, tin, gold, tungsten, magnesium.

In another embodiment, the material of the enclosing wall 200 may be a metal, and in the packaging process, a metal layer is first deposited on the first surface of the device wafer 100, then the metal layer is etched, and the remaining metal layer is used as the enclosing wall, or a dielectric layer is deposited on the first surface of the device wafer 100, and the dielectric layer on the part of the surface of the first electrical connection structure 120 close to the first chip 100 and the edge of the first chip 110 is etched, so as to form a filling hole, and the metal is filled in the filling hole, and the remaining dielectric layer is removed, so as to obtain the enclosing wall; in other embodiments, the material of the fence may also be a photosensitive material, so that patterning can be achieved through a photolithography process, and damage to the electrode or the external interconnection line can be reduced.

The material of the first conductive block 410 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium, and the first conductive block may be generated by an electroplating process, which may be electroless plating (i.e., electroless plating). Specifically, the bonded cap and device substrate are placed in a solution containing metal ions (e.g., a solution such as electroless silver plating, nickel plating, or copper plating), without being energized, and the metal ions are reduced to metal by a strong reducing agent according to the redox reaction principle and deposited on the surfaces of the first electrical connection portion 120 and the second electrical connection portion 331a to form a dense metal plating layer, and after a certain reaction time, the metal plating layer fills up the electrical connection cavity 400 (shown in fig. 5), thereby forming the first conductive bump 410.

In another specific implementation manner, in the MEMS device package structure provided in the embodiment of the present invention, the interconnect structure 331 may include a second electrical connection portion 331a and a third electrical connection portion 331c respectively located on two opposite surfaces of the cap, and a plug 331b electrically connecting the second electrical connection portion 331a and the third electrical connection portion 331c, and of course, a redistribution layer (RDL) structure (not shown in the drawings) may also be included, and the MEMS device package structure further includes:

a second conductive block 420, the second conductive block 420 electrically connecting the third electrical connection portion 331 c. The material of the second conductive bump 420 includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium, and the second conductive bump 420 may enable connection of the first chip 110 with other circuits.

In another specific implementation manner, the MEMS device packaging structure provided by the embodiment of the present invention further includes a packaging layer 500, where the packaging layer 500 covers at least a surface of the first conductive block.

When having the second conductive bumps 420, the encapsulation layer 500 may also provide protection and insulation for the second conductive bumps 420, while in order to simultaneously satisfy protection of the second conductive bumps 420 and facilitate connection of the second conductive bumps 420 with other circuitry, the encapsulation layer 500 may cover a portion of the second conductive bumps 420.

In other embodiments, the encapsulation layer 500 may also completely cover the top surface of the second conductive block 420, or be flush with the top surface of the second conductive block 420, for which purpose the encapsulation layer may be planarized until the second conductive block 420 is exposed. In other embodiments, the encapsulation layer above the second conductive blocks may be etched after the encapsulation layer 500 is formed, so as to expose the second conductive blocks.

The MEMS device packaging structure provided by the embodiment of the invention comprises a sealing cover and an MEMS device substrate which are mutually bonded and provided with interconnection structures, wherein a first electric connection part of the device substrate is electrically connected with a second electric connection part of the sealing cover through a first conductive block, so that the interconnection between an MEMS device and an external signal can be realized, and the device substrate and the sealing cover are connected through a fence, so that a cavity working environment is provided for an MEMS device working area, and the performance of the device is improved.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A wafer-level packaging method for MEMS devices is characterized by comprising the following steps:

2. The wafer-level packaging method for the MEMS device as recited in claim 1, wherein the step of forming the cap includes:

providing a substrate;

forming a release layer on the substrate, the release layer covering the substrate;

forming a dielectric layer on the release layer, and forming an interconnection structure in the dielectric layer;

after the step of forming the interconnection structure in the dielectric layer, the method further comprises:

and releasing the release layer and removing the substrate.

3. The MEMS device wafer level packaging method of claim 2, wherein the material of the release layer comprises at least one of germanium, carbon, a pyrolytic film, and a photolytic film.

4. The wafer-level packaging method of claim 1, wherein the lid comprises a chip-level lid;

the step of bonding the cap to the device wafer comprises:

bonding each of the chip scale cap and the first chip.

5. The MEMS device wafer-level packaging method of claim 1, wherein the cap comprises a wafer-level cap;

after the bonding the cap and the device wafer, further comprising:

and cutting the seal cover along the cutting path.

6. The wafer-level packaging method for the MEMS device, as recited in claim 1, wherein the interconnect structure further comprises a third electrical connection portion electrically connected to the second electrical connection portion, the third electrical connection portion and the second electrical connection portion being respectively located on two surfaces of the cap opposite to each other;

the wafer-level packaging method of the MEMS device further comprises the following steps:

and forming a second conductive block which is electrically connected with the third electric connection part while forming the first conductive block, or planting balls on the third electric connection part to form the second conductive block.

7. The wafer level packaging method for the MEMS device as claimed in claim 1, wherein the material of the fence comprises a dry film or a metal.

8. The wafer level packaging method for the MEMS device as recited in any of claims 1-7, wherein the step of forming the first conductive bump is further followed by:

and filling the openings to form an encapsulation layer.

9. The MEMS device wafer level packaging method of claim 8, wherein the filling after forming the opening of the first conductive block further comprises:

and cutting the device wafer bonded with the interconnection structure, and separating each first chip of the device wafer.

10. The wafer level packaging method for the MEMS device as claimed in any one of claims 1 to 7, wherein the process of forming the first conductive block is an electroplating process.

11. The wafer level packaging method for the MEMS device, as recited in any of claims 1 to 7, wherein the material of the first conductive block is one or more of copper, nickel, zinc, tin, gold, tungsten and magnesium.

12. The MEMS device wafer level packaging method of any one of claims 1-7, wherein the MEMS device comprises at least one of a bulk acoustic wave filter, a surface acoustic wave filter, a solid state mounted resonator, a microphone, and a fingerprint identification device.

13. The wafer level packaging method for the MEMS device, as recited in any of claims 1-7, wherein the thickness of the fence is in a range of 5 microns to 50 microns.

14. A MEMS device package structure, comprising:

15. The MEMS device package of claim 14, wherein the interconnect structure further comprises a third electrical connection electrically connected to the second electrical connection, the third electrical connection and the second electrical connection being located on opposite surfaces of the cap, respectively;

the MEMS device packaging structure further includes: a second conductive block electrically connected to the third electrical connection portion.

16. The MEMS device package structure of claim 14 or 15, wherein the cap comprises a wafer-level cap or a chip-level cap.

17. The MEMS device package of claim 14 or 15, wherein the perimeter wall has a thickness in a range from 5 microns to 50 microns.

18. The MEMS device package structure of claim 14 or 15, wherein the material of the first conductive block is one or more of copper, nickel, zinc, tin, gold, tungsten, and magnesium.

19. The MEMS device package structure of claim 14 or 15, further comprising an encapsulation layer covering at least a surface of the first conductive block.

20. The MEMS device package structure of claim 14 or 15, wherein the MEMS device comprises a bulk acoustic wave filter, a surface acoustic wave filter, a solid state mounted resonator, a microphone, a fingerprint recognition device.