CN102024801B - Ultrathin chip perpendicular interconnection packaging structure and manufacture method thereof - Google Patents
Ultrathin chip perpendicular interconnection packaging structure and manufacture method thereof Download PDFInfo
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- CN102024801B CN102024801B CN201010513048.4A CN201010513048A CN102024801B CN 102024801 B CN102024801 B CN 102024801B CN 201010513048 A CN201010513048 A CN 201010513048A CN 102024801 B CN102024801 B CN 102024801B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses an ultrathin chip perpendicular interconnection packaging structure and a manufacture method thereof. The structure comprises a top layer, an intermediate layer and a bottom layer which are orderly overlapped together from top to bottom. The intermediate layer is provided with a TSV (Through Silicon Via) perpendicular interconnection structure, and the front surface and the back surface of the intermediate layer are respectively provided with at least one interconnection layer laid out again and respectively provided with micro solder balls or solder pads. The active layer of the top layer is provided with micro solder balls or solder pads, and faces the front surface of the intermediate layer. The active layer of the bottom layer is provided with micro solder balls or solder pads, and faces the back surface of the intermediate layer. The front surfaces of the top layer chip and the bottom layer chip are respectively arranged on the front surface and the back surface of the intermediate layer chip, therefore, TSV interconnections are avoided being manufactured on the top layer chip and the bottom layer chip, the damage to the top layer chip and the bottom layer chip is effectively reduced, and the chip reliability is improved.
Description
Technical field
The present invention relates to semiconductor and microsensor manufacture technology field, particularly relate to a kind of ultra-thin chip vertical interconnect encapsulating structure and manufacturing approach thereof.
Background technology
Based on the silicon through hole (Through-Silicon-Via, TSV) interconnected three-dimensional integrated technology can reduce package dimension and weight, increases packaging density, makes and holds more microelectronic component in the unit volume; The vertical interconnect technology can replace two-dimentional interconnection technique and connect distance with the circuit that shortens assembly, and then reduces parasitic capacitance and power consumption; Can component technology of different nature (RF, Memory, Logic, Sensors, Imagers) be incorporated into a packaging body, therefore receive the attention of researcher and industrial quarters.Yet the performance of these technical advantages how, largely depends on factors such as 3-D stacks chip thickness and TSV physical dimension.In general, chip thickness is 30 microns-150 microns in the industrial quarters expectation lamination, and the TSV aperture is 20 microns-100 microns.In this case, the making of TSV, TSV insulation and TSV electroplate and fill, and especially ultra-thin wafers is handled and faced bigger challenge, and this also is to make a higher key factor of the silicon interconnected three-dimensional integrated technology cost of through hole TSV.At present disclosed piling up in the technical scheme adopted the interim bonding techniques of ultra-thin wafers more, adopts secondary wafer, is bonded in ultra-thin wafers on the secondary wafer, accomplishes photoetching, etching, thin film deposition, piles up after the technological operation such as bonding, peels off secondary wafer.Adopt the interim bonding techniques of ultra-thin wafers to increase cost on the one hand, in addition, in its stripping process, still can face big technical difficulty, rate of finished products is low.
Present disclosed piling up in the technical scheme, it is interconnected all to contain TSV in the chip layer in the lamination, and this performance to chip especially impacts the reliability aspect; The physical dimension, the I/O layout that also are unfavorable for realizing chip differ bigger chip-stacked combination.
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve is how to reduce to pile up in the technical scheme the operation of ultra-thin wafers, reduces the damage of a large amount of TSV interconnect architecture manufacturing process to existing microelectronic component, improves reliability, rate of finished products.
Another technical problem that the present invention will solve is the interconnected mismatch problems that how to solve between the stacked chips of different size, layout, realizes the chip interconnect of difference in functionality flexibly.
(2) technical scheme
For solving the problems of the technologies described above; A kind of ultra-thin chip vertical interconnect encapsulating structure is provided; Comprise the top layer, intermediary layer and the bottom that are stacked together successively from top to bottom; Said intermediary layer has TSV vertical interconnect structure, and the obverse and reverse of said intermediary layer has at least one deck layout interconnection layer again respectively, and has microbonding ball or weld pad respectively; The active layer of said top layer has microbonding ball or weld pad, and towards the front of said intermediary layer; The active layer of said bottom has microbonding ball or weld pad, and towards the back side of said intermediary layer.
Preferably, said intermediary layer is that intermediary layer is the chip that is manufactured with integrated circuit or microsensor, and said chip is a silicon base chip.
Preferably, said top layer is the chip that is manufactured with microelectronic component.
Preferably, said top layer is be manufactured with microelectronic component chip-stacked.
Preferably, said bottom is the chip that is manufactured with microelectronic component.
Preferably, said bottom is same matrix chip combination or the different substrates chip portfolio that is manufactured with microelectronic component.
The present invention also provides a kind of manufacturing approach of ultra-thin chip vertical interconnect encapsulating structure, comprises step:
S1 makes blind hole or through hole at the crystal column surface of intermediary layer, depositing insulating layer, plating barrier layer, Seed Layer, and electroplate and fill blind hole or through hole;
S2 makes layout interconnection layer again at the crystal column surface of said intermediary layer, electric interconnected with the integrated circuit of realizing blind hole or through hole and intermediary layer or microsensor, and making microbonding ball or weld pad;
S3 makes microbonding ball or weld pad on the pad of the output/input port of the microelectronic component of the wafer of top layer;
S4 is with the positive face and the bonding of the front of the wafer of said intermediary layer and the wafer of searching the book top layer and to form bonding right;
S5, the thinning back side to 30 of the intermediary layer that said bonding is right microns-300 microns is made layout interconnection layer again in the one side of this attenuate, and makes microbonding ball or weld pad;
S6 is loaded into the one side of said attenuate with bottom wafer or chip, accomplishes being electrically connected, and forms wafer or chip-stacked;
S7 is to said wafer or chip-stacked cutting apart.
Preferably, between step S5-S6, also comprise the step that detects said top layer chip.
Preferably, in said step S4, comprise the bonding that forms behind the para-linkage to carrying out the step that resin is filled.
Preferably, comprise that also repeating step S6 accomplishes different wafers or chip and right being electrically connected of bonding.
Preferably, in step S5, with bonding to the thinning back side to 30 of top layer microns-300 microns.
(3) beneficial effect
Through ultra-thin chip being designed to the sandwich laminated construction; Can effectively solve the interconnected mismatch between the stacked chips of different size, layout; Realize the chip interconnect of top layer, bottom difference in functionality, matrix flexibly; Help inheriting the domain of ripe planar integrated circuit chip, the technological accumulation of traditional microelectronic integrated circuit, protection chip supplier's intellectual property, the three dimension system of the chip of realization difference in functionality, matrix is integrated.The front of top layer chip, bottom chip is loaded in front, the back side of intermediary layer chip respectively, it is interconnected to have avoided on top layer, bottom chip making TSV, has reduced the damage of top layer, bottom chip effectively, has improved chip reliability.Manufacture process adopts behind intermediary layer and top layer wafer or the bottom wafer bonding method of attenuate again, has avoided in the manufacture process clamping to ultra-thin wafers to operate, and has improved rate of finished products, has reduced cost.
Description of drawings
Fig. 1 (a)-(c) is according to the sketch map that on the intermediary layer wafer, prepares the TSV blind hole in the manufacturing approach of the embodiment of the invention;
Fig. 2 is according to making again the layout interconnection layer and make the sketch map of soldered ball in the intermediary layer wafer frontside in the manufacturing approach of the embodiment of the invention;
Fig. 3 (a) is according to the sketch map of on the pad of the output/input port of the microelectronic component of top layer wafer, making microbonding ball or weld pad in the manufacturing approach of the embodiment of the invention;
Fig. 3 (b) is according to the sketch map of on the pad of the input/output end port of the microelectronic chip of bottom, making microbonding ball or weld pad in the manufacturing approach of the embodiment of the invention;
Fig. 4 aims at the sketch map with bonding according to intermediary layer wafer frontside in the manufacturing approach of the embodiment of the invention with the top layer wafer frontside;
Fig. 5 (a) is according to the intermediary layer back side being thinned to the sketch map that exposes the TSV through hole intermediary layer wafer-top layer wafer bonding centering in the manufacturing approach of the embodiment of the invention;
Fig. 5 (b) simultaneously makes the sketch map of layout interconnection layer again according to that goes out TSV in the intermediary layer Wafer exposure in the manufacturing approach of the embodiment of the invention;
Fig. 6 is according to loading the sketch map of bottom chip at the intermediary layer wafer rear in the manufacturing approach of the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment, specific embodiments of the invention describes in further detail.Following examples are used to explain the present invention, but are not used for limiting scope of the present invention.
The invention provides a kind of ultra-thin chip vertical interconnect encapsulating structure, comprise top layer, intermediary layer and bottom, from top to bottom be stacked together successively.Intermediary layer is bare silicon wafer, glass wafer, semiconductor crystal wafer or is manufactured with integrated circuit or the Silicon Wafer of microsensor or chip; Has TSV vertical interconnect structure; Obverse and reverse has at least one deck layout interconnection layer again respectively, and has microbonding ball or weld pad respectively on the layout interconnection layer again.Top layer is the chip that is manufactured with microelectronic component, perhaps chip-stacked (3DIC Module), and the active layer of top layer has microbonding ball or weld pad, and towards the front of intermediary layer.Bottom is the wafer that is manufactured with microelectronic component, and perhaps for being manufactured with the combination of same matrix chip or the different substrates chip portfolio of microelectronic component, the active layer of bottom has microbonding ball or weld pad, and towards the back side of intermediary layer.
The present invention also provides a kind of manufacturing approach of ultra-thin chip vertical interconnect encapsulating structure, and this method comprises the steps:
Step 1 at intermediary layer wafer W1 photomask surface, is made the mask that is used for TSV blind hole etching, etching TSV blind hole 110 (Fig. 1 (a)).Depositing insulating layer, plating barrier layer, Seed Layer 111, sidewall and bottom (Fig. 1 (b)) of covering TSV blind hole 110; TSV blind hole 110 (Fig. 1 (c)) are filled in electro-coppering; Remove plate surface copper more than needed, carry out planarization.Also can make the TSV through hole, accomplish the deposition of insulating barrier, plating barrier layer, Seed Layer equally, accomplish the plating of TSV through hole and fill.Intermediary layer wafer W1 can be a Silicon Wafer of making microelectronic components such as integrated circuit or microsensor, and intermediary layer wafer W1 front integrated circuit or other microelectronic component surface passivation layers 100 are contained in the surface, and metal interconnection layer 101; Intermediary layer wafer W1 also can be semiconductor crystal wafers such as glass wafer or germanium, GaAs.Mask can adopt photoresist, also can adopt materials such as aluminium, silicon dioxide.The etching of TSV blind hole 110 or through hole adopt active-ion-etch (Reactive ion etching, RIE) or deep reaction ion etching (Deep reactive ion etching, DRIE) technology.
Step 2 is made again layout interconnection layer 120 (Fig. 2) in the front of intermediary layer wafer W1, comprises metal interconnection layer 121, can use electric conducting materials such as aluminium, copper, gold, silver; Dielectric layer can use polyimides, BCB, epoxy resin, silicon dioxide etc.Make microbonding ball or micro welded pad above the pad 122 of the output/input port (I/O) of the microelectronic component in the front of interlayer wafer W1.
Step 3; On the pad 202 (Pad) of the output/input port (I/O) of the microelectronic component of top layer wafer W2, make microbonding ball or micro welded pad (Fig. 3 (a)), also show top layer wafer W2 front integrated circuit or other microelectronic component surface passivation layers 200, top layer wafer W2 front integrated circuit or other microelectronic component surface metal interconnection layers 201 among the figure.On the pad 302 (Pad) of the output/input port (I/O) of the microelectronic component of bottom chip C3, make microbonding ball or micro welded pad (Fig. 3 (b)), bottom chip C3 front integrated circuit or other microelectronic component surface passivation layers 300, the positive IC of bottom chip C3 or other microelectronic component surface metal interconnection layers 301 have been shown among the figure.
Step 4, the positive face of the front of intermediary layer wafer W1 and top layer wafer W2, bonding (Fig. 4) under certain temperature (200 ℃-800 ℃), pressure condition.
In this step, can fill carrying out filler by para-linkage, material can use semiconductor machining industry material commonly used.
Step 5, the one side that the right intermediary layer wafer W1 of attenuate W1-W2 bonding exposes is thinned to 30 microns-300 microns (Fig. 5 (a)), and attenuate can adopt chemico-mechanical polishing (CMP) technology.One side behind attenuate is made the interconnection layer of layout again 130 that is positioned at the intermediary layer back side, comprises metal interconnection layer 131 and dielectric layer; On the pad 132 at the intermediary layer wafer W1 back side, make microbonding ball or micro welded pad (Fig. 5 (b)).Metal interconnection layer 131 can use electric conducting materials such as aluminium, copper, gold, silver; Dielectric layer can use polyimides, BCB, epoxy resin, silicon dioxide etc.
Can carry out the performance test step of the internal microelectronic component of W1-W2 bonding in this step.
Step 6 bottom chip C3, is welded on the W1-W2 bonding on microbonding ball or the micro welded pad 122, accomplishes to be electrically connected (Fig. 6).Wherein bottom chip C3 is a microelectronic chip, has accomplished the making (Fig. 3 (b)) of microbonding ball or weld pad above the pad (Pad) 302 of its I/O (I/O) port.
Equally, can be welded on the W1-W2 bonding to chip C4, C5 etc. on microbonding ball or the micro welded pad, chip C4, C5 etc. can be with the base material chip, also can be the different substrate materials chips, and chip C3, C4, C5 are on same plane.
In this step, can comprise attenuate is carried out on the two sides of piling up wafer that thinning technique can adopt the CMP technology, also can use other wet methods or dry etching technology.
Step 7 is piled up the ultra-thin wafers that is formed by step 1-6 and to be cut apart.Cut apart and to adopt scribing process traditional in the semiconductor machining.
Microbonding ball or bonding pad materials comprise copper, tungsten, gold, silver, tin, indium, nickel, palladium, signal bronze, SAC alloy, sn-ag alloy, gold-tin alloy, indium billon, terne metal, Ni-Pd alloy, nickel billon or NiPdAu alloy.
Can find out by above embodiment; The embodiment of the invention is through being designed to ultra-thin chip the sandwich laminated construction; Can effectively solve the interconnected mismatch between the stacked chips of different size, layout, realize the chip interconnect of top layer, bottom difference in functionality, matrix flexibly, help inheriting the domain of ripe planar integrated circuit chip, the technological accumulation of traditional microelectronic integrated circuit; Protection chip supplier's intellectual property, the three dimension system of the chip of realization difference in functionality, matrix is integrated.The front of top layer chip, bottom chip is loaded in front, the back side of intermediary layer chip respectively, it is interconnected to have avoided on top layer, bottom chip making TSV, has reduced the damage of top layer, bottom chip effectively, has improved chip reliability.Manufacture process adopts behind intermediary layer and top layer wafer or the bottom wafer bonding method of attenuate again, has avoided in the manufacture process clamping to ultra-thin wafers to operate, and has improved rate of finished products, has reduced cost.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from know-why of the present invention; Can also make some improvement and modification, these improve and modification also should be regarded as protection scope of the present invention.
Claims (11)
1. ultra-thin chip vertical interconnect encapsulating structure; It is characterized in that; Comprise the top layer, intermediary layer and the bottom that are stacked together successively from top to bottom; Said intermediary layer has TSV vertical interconnect structure, and the obverse and reverse of said intermediary layer has at least one deck layout interconnection layer again respectively, and has microbonding ball or weld pad respectively; Said TSV vertical interconnect structure runs through the part except that the said interconnection layer of layout again in the said intermediary layer; The active layer of said top layer has microbonding ball or weld pad, and towards the front of said intermediary layer; The active layer of said bottom has microbonding ball or weld pad, and towards the back side of said intermediary layer.
2. ultra-thin chip vertical interconnect encapsulating structure as claimed in claim 1 is characterized in that said intermediary layer is the chip that is manufactured with integrated circuit or microsensor, and said chip is a silicon base chip.
3. ultra-thin chip vertical interconnect encapsulating structure as claimed in claim 1 is characterized in that said top layer is the chip that is manufactured with microelectronic component.
4. ultra-thin chip vertical interconnect encapsulating structure as claimed in claim 1 is characterized in that said top layer is be manufactured with microelectronic component chip-stacked.
5. ultra-thin chip vertical interconnect encapsulating structure as claimed in claim 1 is characterized in that said bottom is the chip that is manufactured with microelectronic component.
6. ultra-thin chip vertical interconnect encapsulating structure as claimed in claim 1 is characterized in that, said bottom is same matrix chip combination or the different substrates chip portfolio that is manufactured with microelectronic component.
7. the manufacturing approach of each said ultra-thin chip vertical interconnect encapsulating structure of claim 1-6 is characterized in that, comprises step:
S1 makes blind hole or through hole at the crystal column surface of intermediary layer, depositing insulating layer, plating barrier layer, Seed Layer, and electroplate and fill blind hole or through hole;
S2 makes layout interconnection layer again at the crystal column surface of said intermediary layer, electric interconnected with the integrated circuit of realizing blind hole or through hole and intermediary layer or microsensor, and on the said interconnection layer of layout again making microbonding ball or weld pad;
S3 makes microbonding ball or weld pad on the pad of the output/input port of the microelectronic component of the wafer of top layer;
S4, it is right that the positive face of the wafer of the front of the wafer of said intermediary layer and said top layer and bonding are formed bonding;
S5, the thinning back side to 30 of the intermediary layer that said bonding is right microns-300 microns is made layout interconnection layer again in the one side of this attenuate, and on the said interconnection layer of layout again, makes microbonding ball or weld pad;
S6 is loaded into the one side of said attenuate with bottom chip, accomplishes being electrically connected, and forms wafer or chip-stacked;
S7 is to said wafer or chip-stacked cutting apart.
8. manufacturing approach as claimed in claim 7 is characterized in that, between step S5-S6, also comprises the step that detects said bottom chip.
9. like claim 7 or 8 described manufacturing approaches, it is characterized in that, in said step S4, comprise the bonding that forms behind the para-linkage carrying out the step that resin is filled.
10. like claim 7 or 8 described manufacturing approaches, it is characterized in that, comprise that also repeating step S6 accomplishes different wafers or chip and right being electrically connected of bonding.
11. like claim 7 or 8 described manufacturing approaches, it is characterized in that, in step S5, with bonding to the thinning back side to 30 of top layer microns-300 microns.
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| CN103280449B (en) * | 2013-05-16 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | A kind of manufacture method carrying on the back photograph image sensor |
| US9425125B2 (en) * | 2014-02-20 | 2016-08-23 | Altera Corporation | Silicon-glass hybrid interposer circuitry |
| CN106783847A (en) * | 2016-12-21 | 2017-05-31 | 中国电子科技集团公司第五十五研究所 | For the three-dimensional bonding stacked interconnected integrated manufacturing method of radio frequency micro-system device |
| CN108364948B (en) * | 2018-02-09 | 2020-09-25 | 上海珏芯光电科技有限公司 | Radio frequency front end micro system module and manufacturing method thereof |
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| US7446420B1 (en) * | 2007-06-20 | 2008-11-04 | Hynix Semiconductor Inc. | Through silicon via chip stack package capable of facilitating chip selection during device operation |
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| CN101379892A (en) * | 2008-03-27 | 2009-03-04 | 香港应用科技研究院有限公司 | Pulsed laser bonding method for stacking electric elements based on silicon throughhole |
| CN101626015A (en) * | 2008-07-11 | 2010-01-13 | 南茂科技股份有限公司 | Package structure and method for forming and manufacturing thereof, chip piling structure |
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| US7446420B1 (en) * | 2007-06-20 | 2008-11-04 | Hynix Semiconductor Inc. | Through silicon via chip stack package capable of facilitating chip selection during device operation |
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| CN101626015A (en) * | 2008-07-11 | 2010-01-13 | 南茂科技股份有限公司 | Package structure and method for forming and manufacturing thereof, chip piling structure |
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