CN102593110A - Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method - Google Patents
Laminated inverted chip packaging structure of ultra-fine spacing welding plates and bottom filling material preparation method Download PDFInfo
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- CN102593110A CN102593110A CN2012100120625A CN201210012062A CN102593110A CN 102593110 A CN102593110 A CN 102593110A CN 2012100120625 A CN2012100120625 A CN 2012100120625A CN 201210012062 A CN201210012062 A CN 201210012062A CN 102593110 A CN102593110 A CN 102593110A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
Abstract
The invention discloses a laminated inverted chip packaging structure of ultra-fine spacing welding plates and a preparation method thereof. According to the embodiment of the invention, the laminated inverted chip packaging structure comprises a substrate, a plurality of vertically-stacked chips and a plurality of conducting columns, wherein a plurality of welding plates are arranged on the substrate; one welding plate is arranged on each chip; and the conducting columns are arranged between the chips and the substrate; a part of the conducting columns are vertically stacked together; and the welding plates on the substrate and the welding plates on the chips are electrically connected through the conducting columns. Bottom filling materials are filled in gaps among the chips and gaps between the chips and the substrate and cover solder on each layer and the conducting columns. With the adoption of the laminated inverted chip packaging structure of the ultra-fine spacing welding plates disclosed by the embodiment of the invention, the requirements on the ultra-fine spacing welding plates on the vertically-stacked chips can be satisfied.
Description
Technical field
The present invention relates to a kind of lamination flip chip packaging structure and manufacturing approach, relate in particular to a kind of manufacturing approach of slim encapsulating structure of lamination flip-chip small size and employing underfill thereof of ultra fine-pitch pad.
Background technology
As shown in Figure 1; In traditional stacked package structure that comprises two-layer flip-chip; Interconnection between chip bonding pad and the substrate pads normally second chip 2 (position is leaned on last, apart from substrate chip far away) is connected with substrate 100 pads through bigger spherical solder bump, and first chip 1 (position by under chip) is connected with substrate pads through less spherical solder bump.
In the stacked package structure that overcomes traditional two-layer flip-chip; Solder bump can't be applicable to the problem of ultra fine-pitch pad; The conductive pole interconnection structure has appearred in recent years; Can on first chip 1, use this conductive pole interconnection structure, perhaps first chip 1 and second chip 2 use the conductive pole interconnection structure simultaneously.
Iff uses the interconnection of this novel conductive pole on first chip 1, and second chip 2 can't be applied to the ultra fine-pitch pad less than 150um when still using spherical solder bump interconnect.
If, have problems conductive pole interconnection being used simultaneously in first chip 1 and 2 last times of second chip.Because prior art generally can only be accomplished the conductive pole of about 70um height, deduct after the thickness of chip surface protection insulating barrier and substrate surface insulating barrier, the gap d between chip and the substrate will be less than 50um (referring to Fig. 3).But the space (d2) that simultaneously need keep 10um at least between the surface of the back side of first chip 1 and second chip 2 is for being connected the perhaps filling of underfill.The existing chip thinning technology that can realize volume production is generally the thinnest to be 30um thickness, so the thickness T c of lower floor's chip 1 has 30um at least, causes 1 of gap d between lower floor's chip 1 and the substrate 100 to be left less than 10um.This structure is difficult to realize at present.
Summary of the invention
The object of the present invention is to provide a kind of flip-chip stacked package structure of ultra fine-pitch pad, can satisfy the requirement of the ultra fine-pitch pad of lamination flip-chip up and down simultaneously.
To achieve these goals, according to embodiments of the invention, a kind of lamination flip chip packaging structure is provided, wherein, said lamination flip chip packaging structure comprises: substrate, substrate are provided with a plurality of pads; A plurality of chips of stacked on top are provided with pad on each chip; A plurality of conductive poles; Be arranged between bonding pads and the substrate; Be electrically connected through said a plurality of conductive poles between substrate pads and the chip bonding pad, a part of stacked on top in said a plurality of conductive poles together, the chip of the superiors is electrically connected with substrate through the multilayer conductive post; Underfill is filled in the gap between each chip.
The number of plies of the conductive pole that is provided with on the chip bonding pad is more than or equal to the number of plies of the conductive pole that is provided with on the chip bonding pad that is positioned at this chip below.
Undermost chip is electrically connected with substrate through one deck conductive pole.
Each layer chip all includes the pad of spacing less than 150um.
Said a plurality of conductive pole comprises first conductive pole, second conductive pole and the 3rd conductive pole, and second conductive pole is stacked on first conductive pole top, and the 3rd conductive pole is arranged on the undermost chip.
Be connected through scolder between first conductive pole and second conductive pole and between first conductive pole and the 3rd conductive pole and the substrate pads, scolder comprises first scolder, second scolder and the 3rd scolder.
Substrate pads is connected with an end of first conductive pole through first scolder, and substrate pads is passed through the 3rd scolder and is connected with the 3rd conductive pole one end, is connected through second scolder between first conductive pole and second conductive pole.
The fusing point of first scolder is higher more than 50 ℃ than the fusing point of second scolder and the 3rd scolder.
The material of first scolder and second scolder and the 3rd scolder is lead-free solder.
This encapsulating structure be used between each layer conductive pole connecting and being used for all scolders that conductive pole is connected with substrate pads, be minimum at fusing point with the set scolder in the direct-connected conductive pole of each layer chip lower end.
Underfill also is filled in the gap between chip and the substrate, and has coated each layer scolder and conductive pole.
The material of first conductive pole and second conductive pole and the 3rd conductive pole all is a copper.
Be provided with the UBM layer between bonding pads and a part of conductive pole.
According to a further aspect in the invention; A kind of method of making aforesaid lamination flip chip packaging structure also is provided; Wherein, Said method comprises: after the carrier that will preset first conductive pole is connected on the substrate through Reflow Soldering, separate first conductive pole and carrier, first conductive pole is connected through first scolder be retained on the substrate pads; With first chip attachment that presets the 3rd conductive pole to the substrate on the corresponding pad; Second chip attachment that presets second conductive pole on corresponding first conductive pole, is made chip and substrate form once more and interconnects to the substrate after the Reflow Soldering, be filled in the gap and the gap between chip and the substrate between chip and the chip with underfill then.
Wherein, on the surface of carrier protective layer is set, before separating first conductive pole and carrier, first conductive pole is plated on the protective layer of carrier.
Wherein, adhesion between first conductive pole and first scolder and the adhesion between first scolder and the substrate pads are greater than the adhesion between the protective layer of first conductive pole and carrier.
Use the flip-chip stacked package structure of ultra fine-pitch pad according to an embodiment of the invention, can satisfy the requirement of the ultra fine-pitch pad of lamination flip-chip up and down simultaneously.
Description of drawings
Through below in conjunction with the description carried out of accompanying drawing that an example exemplarily is shown, of the present invention above-mentionedly will become apparent with other purposes and characteristics, wherein:
Fig. 1 all uses the flip chip structure sketch map of spherical solder bump for traditional layers of chips;
Fig. 2 uses spherical solder bump for second chip on upper strata, and first chip of lower floor uses the conductive pole structural representation;
Fig. 3 all uses the structural representation of individual layer conductive pole for layers of chips up and down;
Fig. 4 is the sketch map of stacked package structure according to an embodiment of the invention;
Fig. 5 mounts the sketch map on the substrate for the carrier that will preset first conductive pole;
Fig. 6 is that the carrier that has preset first conductive pole forms the sketch map that is connected with substrate after refluxing for the first time;
The sketch map of Fig. 7 for carrier is separated with first conductive pole, wherein, first conductive pole is stayed on the substrate pads;
Fig. 8 for carrier with after first conductive pole separates, the sketch map at the first conductive pole top of substrate one side;
Fig. 9 for carrier with after first conductive pole separates, the sketch map of carrier one side;
Figure 10 for first chip attachment to the substrate that has first conductive pole corresponding pad locations on sketch map;
Figure 11 is with second chip attachment corresponding locational sketch map of first conductive pole to the substrate;
Figure 12 is reflux for the second time first chip of back formation and the interconnection sketch map of substrate and second chip and substrate;
Figure 13 is for to be filled into second chip with underfill, the sketch map in the gap between first chip and the substrate.
Embodiment
Can use the relation of coming easily element shown in the description figure or characteristic and other elements or characteristic such as spatial relationship terms such as " in ... below ", " lower floor ", " in ... top ", " upper stratas " in the present invention.Should be appreciated that the orientation of in accompanying drawing, describing that the spatial relationship term also is intended to comprise the different azimuth of device in using or operating.For example, if the device in accompanying drawing upset, then be described as be in other elements or characteristic " below " or " under " the orientation of element will be positioned in " top " of other elements or characteristic subsequently.Therefore, exemplary term " in ... below " can comprise " in ... top " and " in ... below " two kinds of orientation.Device can be positioned at other orientation (revolve and turn 90 degrees perhaps in other orientation), and then spatial relationship descriptor used herein should correspondingly be explained.
Below, specify embodiments of the invention with reference to accompanying drawing.
Fig. 4 is stacked package structural representation according to an embodiment of the invention.As shown in Figure 4, the stacked package structure comprises according to an embodiment of the invention: substrate 100, and substrate 100 is provided with a plurality of pads; Two chips 1,2 of stacked on top (are not limited to two; Can have the upper and lower chip more than three that piles up according to encapsulating structure of the present invention; Can be called first chip, second chip, the 3rd chip etc. successively from top to bottom), be provided with a plurality of pads on first chip 1 and second chip 2; Conductive pole is arranged between first chip 1 and the substrate 100 and between second chip 2 and the substrate 100, is electrically connected through said conductive pole between substrate pads and the chip bonding pad.
Further; According to one embodiment of present invention; First chip, 1 to the second chip 2 is more near substrate 100 (also can be described as first chip 1 below second chip 2); Only be provided with one deck the 3rd conductive pole 5 between first chip 1 and the substrate 100, and the following of second chip 2 can be provided with two-layer conductive pole, is respectively first conductive pole 3 and second conductive pole 4.
If this stacked package structure comprises more chip, the position leans on more the chip of top to be connected with substrate through the conductive pole of multilayer more.According to embodiments of the invention, the chip of the superiors is electrically connected with substrate through the multilayer conductive post at least.The number of plies of the conductive pole that the number of plies of the conductive pole that is provided with on arbitrary layer of bonding pads is provided with more than or equal to the chip that is positioned at this layer chip below.
The conductive pole cross sectional shape can be for square or circular, and have no special requirements.
Substrate pads is connected with the 3rd conductive pole 5 one ends through the 3rd scolder 8, and the 3rd conductive pole 5 other ends are connected with the pad of first chip 1.
In addition, can be distributed with soldered ball in the lower surface of substrate, to be electrically connected with other components and parts.
The material of the first conductive pole material 3 and second conductive pole 4 and the 3rd conductive pole 5 all can be Cu.
The first and second and the 3rd solder material all can be unleaded (that is, lead content must reduce to the level that is lower than 1000ppm).
UBM layer 10 (salient point bottom metal layer, under bump metal) is arranged between the pad of second chip 2 and/or first chip 1 and the partially conductive post.The UBM layer can guarantee the adhibit quality of flange and pad and prevent intermetallic counterdiffusion mutually.
Can be than the fusing point of second scolder 4 and the 3rd scolder 8 high 50 ℃ or more of the fusing point of first scolder 6.
Fig. 5-Figure 13 shows the manufacturing approach of the flip-chip stacked package structure of ultra fine-pitch pad according to an embodiment of the invention.
Fig. 5 mounts the sketch map on the substrate for the carrier that will preset first conductive pole; Fig. 6 is that the carrier that has preset first conductive pole forms the sketch map that is connected with substrate after refluxing for the first time; The sketch map of Fig. 7 for carrier is separated with first conductive pole, wherein, first conductive pole is stayed on the substrate pads.
As shown in Figure 5, the conductive pole carrier 9 that presets first conductive pole 3 and first scolder 6 is mounted on the substrate.Existing ripe flipchip-bumped manufacture craft can be implemented in and plates conductive pole and scolder on the carrier 9 one by one; Specifically; The protective layer that does not produce metallurgical binding with metal is set on the surface of carrier 9 in advance; Behind polymeric coating layers such as coating polyimide, carry out the flipchip-bumped manufacture craft again, can make and keep extremely low adhesion between the protective layer of first conductive pole 3 and carrier 9.Form the firm metallurgical binding between first scolder 6 and first conductive pole 3 through technologies such as Reflow Solderings again.
Then, as shown in Figure 6, after refluxing once more, make the carrier 9 that has first conductive pole 3 and first scolder 6 form scolder and be connected with substrate 100.
As shown in Figure 7, the carrier of separating 9 and first conductive pole 3.Specifically; Through behind the reflow soldering process, between first conductive pole 3 and first scolder 6, and between first scolder 6 and the substrate pads; All formed firm metallurgical binding; Adhesion between them is far longer than the adhesion between the protective layer of first conductive pole 3 and carrier 9, so just is easy to realize separating between first conductive pole 3 and the carrier 9, and the conductive pole 3 of winning is retained on the substrate pads.Fig. 8 for carrier with after first conductive pole 3 separates, the sketch map at first conductive pole, 3 tops of substrate one side, Fig. 9 for carrier 9 with after first conductive pole 3 separates, the sketch map of carrier 9 one sides.Fig. 8 and Fig. 9 only are examples, and the distribution of first conductive pole 3 is not limited to the shape shown in Fig. 8 and Fig. 9.
Figure 10 for first chip attachment to the substrate that has first conductive pole corresponding pad locations on sketch map; Figure 11 is with second chip attachment corresponding locational sketch map of first conductive pole to the substrate; Figure 12 is reflux for the second time first chip of back formation and the interconnection sketch map of substrate and second chip and substrate; Figure 13 is for to be filled into second chip with underfill, the sketch map in the gap between first chip and the substrate.
Shown in Figure 10-13, first chip 1 that has preset the 3rd conductive pole 5 is mounted on the substrate that has first conductive pole 3.Second chip 2 that will preset second conductive pole 4 then mounts on the substrate that has first conductive pole 3, and the process of mounting should be noted the conductive pole that aligns.After Reflow Soldering, the pad of chip 1, chip 2 and the pad of substrate form interconnection.
Melt in the process of this Reflow Soldering for fear of first scolder 6 and to cause first conductive pole 3 crooked and can not align with second conductive pole 4, the fusing point that possibly make first scolder 6 is higher 50 ℃ or more than the fusing point of second scolder 4 and the 3rd scolder 8.
Be filled in the gap between each chip with underfill at last, also be filled in the gap between chip and the substrate, and coated first scolder 6; First conductive pole, 3, the second scolders, 7, the second conductive poles 4; The 3rd scolder 8, the three conductive poles 5, thereby final molding.
Make three layers or the stacked package structure of multilayer chiop more if desired, then on substrate, need the conductive pole of stacked multilayer, place first chip, second chip, the 3rd chip, four-core sheet then successively, the rest may be inferred, fills underfill material at last.This wherein will experience the multiple tracks reflux technique, know according to foregoing reason, with the direct-connected conductive pole of each layer chip on the fusing point of set scolder in all scolders, be minimum because they are in the last reflow process.
In addition, can be distributed with soldered ball in the lower surface of substrate, to be electrically connected with other components and parts.
Though described exemplary embodiment of the present invention above in detail, have common practise person in spirit that does not break away from the utility model and scope in the technical field under the present invention, can make various modifications, retouching and modification to embodiments of the invention.But should be appreciated that In the view of those skilled in the art these modifications, retouching and modification will fall in the spirit and scope of the exemplary embodiment of the present invention that claim limits.
At last, only if point out here or other and the obvious contradiction of context, otherwise the step of all methods described herein can be carried out with the order of any appropriate.
Claims (16)
1. lamination flip chip packaging structure, wherein, said lamination flip chip packaging structure comprises:
Substrate, substrate are provided with a plurality of pads;
A plurality of chips of stacked on top are provided with pad on each chip;
A plurality of conductive poles; Be arranged between bonding pads and the substrate; Be electrically connected through said a plurality of conductive poles between substrate pads and the chip bonding pad, a part of stacked on top in said a plurality of conductive poles together, the chip of the superiors is electrically connected with substrate through the multilayer conductive post;
Underfill is filled in the gap between each chip.
2. lamination flip chip packaging structure according to claim 1, wherein,
The number of plies of the conductive pole that is provided with on the chip bonding pad is more than or equal to the number of plies of the conductive pole that is provided with on the chip bonding pad that is positioned at this chip below.
3. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Undermost chip is electrically connected with substrate through one deck conductive pole.
4. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Each layer chip all includes the pad of spacing less than 150um.
5. lamination flip chip packaging structure according to claim 1 and 2; Said a plurality of conductive pole comprises first conductive pole, second conductive pole and the 3rd conductive pole; Second conductive pole is stacked on first conductive pole top, and the 3rd conductive pole is arranged on the undermost chip.
6. lamination flip chip packaging structure according to claim 5, wherein,
Be connected through scolder between first conductive pole and second conductive pole and between first conductive pole and the 3rd conductive pole and the substrate pads, scolder comprises first scolder, second scolder and the 3rd scolder.
7. lamination flip chip packaging structure according to claim 6, wherein,
Substrate pads is connected with an end of first conductive pole through first scolder, and substrate pads is passed through the 3rd scolder and is connected with the 3rd conductive pole one end, is connected through second scolder between first conductive pole and second conductive pole.
8. according to claim 6 or 7 described lamination flip chip packaging structures, wherein,
The fusing point of first scolder is higher more than 50 ℃ than the fusing point of second scolder and the 3rd scolder.
9. according to claim 6 or 7 described lamination flip chip packaging structures, wherein,
The material of first scolder and second scolder and the 3rd scolder is lead-free solder.
10. lamination flip chip packaging structure according to claim 1 and 2, wherein,
This encapsulating structure be used between each layer conductive pole connecting and being used for all scolders that conductive pole is connected with substrate pads, be minimum at fusing point with the set scolder in the direct-connected conductive pole of each layer chip lower end.
11. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Underfill also is filled in the gap between chip and the substrate, and has coated each layer scolder and conductive pole.
12. lamination flip chip packaging structure according to claim 1 and 2, wherein,
The material of first conductive pole and second conductive pole and the 3rd conductive pole all is a copper.
13. lamination flip chip packaging structure according to claim 1 and 2, wherein,
Be provided with the UBM layer between bonding pads and a part of conductive pole.
14. the method for each described lamination flip chip packaging structure among manufacturing such as the claim 1-13, wherein, said method comprises:
After being connected on the substrate through Reflow Soldering the carrier that presets first conductive pole, separate first conductive pole and carrier, first conductive pole connected through first scolder be retained on the substrate pads,
First chip attachment that presets the 3rd conductive pole to the substrate on the corresponding pad, on corresponding first conductive pole, is made second chip attachment that presets second conductive pole chip and substrate form once more and interconnects to the substrate after the Reflow Soldering,
Be filled in the gap and the gap between chip and the substrate between chip and the chip with underfill then.
15. method according to claim 14 wherein, is provided with protective layer on the surface of carrier, before separating first conductive pole and carrier, first conductive pole is plated on the protective layer of carrier.
16. method according to claim 15, wherein, adhesion between first conductive pole and first scolder and the adhesion between first scolder and the substrate pads are greater than the adhesion between the protective layer of first conductive pole and carrier.
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| CN103281874A (en) * | 2013-05-08 | 2013-09-04 | 无锡江南计算技术研究所 | Welding method of pasted electronic element |
| CN103390563A (en) * | 2013-08-06 | 2013-11-13 | 江苏长电科技股份有限公司 | Metal circuit board structure and technique of flip chip of firstly-packaged and then-etched three-dimensional system level |
| CN103681606A (en) * | 2012-08-29 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Three dimensional (3D) fan-out packaging mechanisms |
| CN103762185A (en) * | 2013-12-20 | 2014-04-30 | 南通富士通微电子股份有限公司 | Laminated packaging method for semiconductor |
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| CN106601631A (en) * | 2016-12-21 | 2017-04-26 | 江苏长电科技股份有限公司 | Technique for first-packaging second-etching electroplated copper column conduction once-for-all three-dimensional packaged structure |
| CN107195613A (en) * | 2017-06-23 | 2017-09-22 | 华进半导体封装先导技术研发中心有限公司 | Three-dimension packaging structure and its manufacture method based on different height copper post |
| CN107768351A (en) * | 2016-08-18 | 2018-03-06 | 台湾积体电路制造股份有限公司 | Semiconductor package part with heat engine electrical chip and forming method thereof |
| CN108336053A (en) * | 2018-03-20 | 2018-07-27 | 桂林电子科技大学 | The manufacturing method of packaging and packaging |
| CN111192863A (en) * | 2020-01-10 | 2020-05-22 | 张正 | Chip stacking and packaging structure and preparation method thereof |
| CN111554657A (en) * | 2020-04-30 | 2020-08-18 | 通富微电子股份有限公司 | Semiconductor packaging device |
| CN113594119A (en) * | 2021-06-25 | 2021-11-02 | 苏州汉天下电子有限公司 | Semiconductor package and method of manufacturing the same |
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