TW201717342A - DRAM chip package structure - Google Patents
DRAM chip package structure Download PDFInfo
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- TW201717342A TW201717342A TW104136793A TW104136793A TW201717342A TW 201717342 A TW201717342 A TW 201717342A TW 104136793 A TW104136793 A TW 104136793A TW 104136793 A TW104136793 A TW 104136793A TW 201717342 A TW201717342 A TW 201717342A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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Abstract
Description
本發明是有關於一種具有多晶片堆疊式封裝結構的隨機動態記憶體晶片封裝結構。The present invention relates to a random dynamic memory chip package structure having a multi-wafer stacked package structure.
隨著行動多媒體產品的普及以及它們對更高數位訊號處理、具有更高儲存容量和靈活性的新型儲存架構的迫切需求,多晶片堆疊的晶片封裝結構,其應用正快速成長。With the proliferation of mobile multimedia products and their urgent need for higher digital signal processing, new storage architectures with higher storage capacity and flexibility, the application of multi-chip stacked chip package structures is growing rapidly.
在現行的隨機動態記憶體雙晶片封裝(dual die package)結構中,上部晶片的主動表面與下部晶片的主動表面之配置方向是相反的。一般來說,下部晶片的主動表面是朝向線路基板,而上部晶片的主動表面則是遠離線路基板。當上部晶片與下部晶片為雙列接墊設計時,為了使上部晶片與下部晶片的同一邊的接墊可與其相對應邊的銲球電性連接,可將上部晶片與下部晶片之接墊設計為互為鏡像。然而,生產具有鏡像配置接墊之兩種晶片會提高製造成本。In the current random dynamic memory dual die package structure, the active surface of the upper wafer and the active surface of the lower wafer are arranged oppositely. Generally, the active surface of the lower wafer is toward the circuit substrate, while the active surface of the upper wafer is away from the wiring substrate. When the upper wafer and the lower wafer are designed as double-row pads, the pads of the upper wafer and the lower wafer can be designed so that the pads on the same side of the upper wafer and the lower wafer can be electrically connected to the corresponding solder balls. For each other as a mirror. However, producing two wafers with mirrored mounting pads increases manufacturing costs.
或者是,亦可在晶片上進行重新佈線製程,使上部晶片的接墊與下部晶片的接墊具有相同配置方式。然而,在晶片上進行重新佈線製程不僅會提高製造成本,且會增加佈線面積。Alternatively, the rewiring process can be performed on the wafer so that the pads of the upper wafer and the pads of the lower wafer have the same configuration. However, performing the rewiring process on the wafer not only increases the manufacturing cost but also increases the wiring area.
本發明提供一種隨機動態記憶體晶片封裝結構,其藉由上部晶片與下部晶片之間的線路基板來連接上部晶片及下部晶片下方的線路基板。The present invention provides a random dynamic memory chip package structure in which a wiring substrate under an upper wafer and a lower wafer is connected by a wiring substrate between an upper wafer and a lower wafer.
本發明提出一種隨機動態記憶體晶片封裝結構,其包括第一線路基板、第一晶片、第二線路基板、第二晶片、多個銲球、多個第一凸塊、多條第一銲線以及封裝膠體。第一線路基板,具有相對的第一表面與第二表面。第一晶片,具有第一主動表面、第一列接墊以及第二列接墊,其中第一列接墊與第二列接墊平行配置在第一主動表面上,第一晶片以第一主動表面朝向第一表面的方式配置於第一線路基板上,且第一晶片藉由第一列接墊與第二列接墊電性連接至第一線路基板。多個銲球,配置於第二表面上。第二線路基板,具有相對的第三表面與第四表面,第二線路基板配置於第一晶片上。第二晶片,具有第二主動表面、第三列接墊以及第四列接墊,其中第三列接墊與第四列接墊平行配置於第二主動表面上,第二晶片以第二主動表面朝向第三表面的方式配置於第二線路基板上,第二晶片藉由第三接墊列與第四接墊列電性連接至第二線路基板。多個第一凸塊,連接第三列接墊與第二線路基板且第四列接墊與第二線路基板。多條第一銲線,連接第一線路基板與第二線路基板。封裝膠體,至少配置於第一表面上,且包覆第一晶片、第二晶片、第二線路基板以及第一銲線。The present invention provides a random dynamic memory chip package structure including a first circuit substrate, a first wafer, a second circuit substrate, a second wafer, a plurality of solder balls, a plurality of first bumps, and a plurality of first bonding wires And encapsulation colloids. The first circuit substrate has opposite first and second surfaces. The first wafer has a first active surface, a first column of pads and a second column of pads, wherein the first column of pads is disposed in parallel with the second column of pads on the first active surface, and the first wafer is first active The surface is disposed on the first circuit substrate in a manner of facing the first surface, and the first wafer is electrically connected to the first circuit substrate by the first column pad and the second column pad. A plurality of solder balls are disposed on the second surface. The second circuit substrate has opposite third and fourth surfaces, and the second circuit substrate is disposed on the first wafer. a second wafer having a second active surface, a third column of pads, and a fourth column of pads, wherein the third column of pads is disposed on the second active surface in parallel with the fourth column of pads, and the second wafer is in a second active The surface is disposed on the second circuit substrate in a manner of facing the third surface, and the second wafer is electrically connected to the second circuit substrate through the third pad row and the fourth pad row. The plurality of first bumps connect the third row of pads and the second circuit substrate and the fourth column of pads and the second circuit substrate. A plurality of first bonding wires connect the first circuit substrate and the second circuit substrate. The encapsulant is disposed on at least the first surface and covers the first wafer, the second wafer, the second wiring substrate, and the first bonding wire.
在本發明之一實施例中,上述的第一晶片藉由多條第二銲線與第一線路基板電性連接,且第一線路基板具有暴露第一列接墊與第二列接墊的開槽,第二銲線穿過開槽以連接第一列接墊與第一線路基板以及連接第二列接墊與第一線路基板。封裝膠體包覆第二銲線、第一列接墊與第二列接墊。In one embodiment of the present invention, the first wafer is electrically connected to the first circuit substrate by a plurality of second bonding wires, and the first circuit substrate has a first row of pads and a second column of pads. Slotting, the second bonding wire passes through the slot to connect the first row of pads with the first circuit substrate and the second column of pads and the first circuit substrate. The encapsulant covers the second bonding wire, the first column pad and the second column pad.
在本發明之一實施例中,晶片封裝結構更包括黏著層,配置於第一線路基板與第一晶片之間。In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the first circuit substrate and the first wafer.
在本發明之一實施例中,上述的第一晶片藉由多個第二凸塊與第一線路基板電性連接,第二凸塊連接第一列接墊與第一線路基板且連接第二列接墊與第一線路基板。In one embodiment of the present invention, the first wafer is electrically connected to the first circuit substrate by the plurality of second bumps, and the second bump is connected to the first row of pads and the second circuit substrate and is connected to the second substrate. The column pads are connected to the first circuit substrate.
在本發明之一實施例中,晶片封裝結構更包括黏著層,配置於第一線路基板與第一晶片之間。In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the first circuit substrate and the first wafer.
在本發明之一實施例中,上述的黏著層具有異方導電性且包覆第一列接墊、第二列接墊以及第二凸塊。In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the first row of pads, the second column of pads, and the second bumps.
在本發明之一實施例中,晶片封裝結構更包括黏著層,配置於第二線路基板與第二晶片之間。In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the second circuit substrate and the second wafer.
在本發明之一實施例中,上述的黏著層具有異方導電性且包覆第三列接墊、第四列接墊以及第一凸塊。In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the third row of pads, the fourth row of pads, and the first bumps.
本發明提出一種隨機動態記憶體晶片封裝結構,其包括第一線路基板、第一晶片、第二線路基板、第二晶片、多個銲球、多個第一凸塊、多個第二凸塊、多條第一銲線以及封裝膠體。第一線路基板,具有相對的第一表面與第二表面。第一晶片,具有第一主動表面、第一列接墊以及第二列接墊,其中第一列接墊與第二列接墊平行配置在第一主動表面上,第一晶片以第一主動表面遠離第一表面的方式配置於第一線路基板上。多個銲球,配置於第二表面上。第二線路基板,具有相對的第三表面與第四表面,第二線路基板以第四表面朝向第一主動表面的方式配置於第一晶片上,且第一晶片藉由第一列接墊與第二列接墊電性連接至第二線路基板。第二晶片,具有第二主動表面、第三列接墊以及第四列接墊,其中第三列接墊與第四列接墊平行配置於第二主動表面上,第二晶片以第二主動表面朝向第三表面的方式配置於第二線路基板上,第二晶片藉由第三接墊列與第四接墊列電性連接至第二線路基板。多個第一凸塊,連接第三列接墊與第二線路基板且連接第四列接墊與第二線路基板。多個第二凸塊,連接第一列接墊與第二線路基板且連接第二列接墊與第二線路基板。多條第一銲線,電性連接第一線路基板與第二線路基板。封裝膠體,配置於第一表面上,且包覆第一晶片、第二晶片、第二線路基板以及第一銲線。The present invention provides a random dynamic memory chip package structure including a first circuit substrate, a first wafer, a second circuit substrate, a second wafer, a plurality of solder balls, a plurality of first bumps, and a plurality of second bumps , a plurality of first bonding wires and a package colloid. The first circuit substrate has opposite first and second surfaces. The first wafer has a first active surface, a first column of pads and a second column of pads, wherein the first column of pads is disposed in parallel with the second column of pads on the first active surface, and the first wafer is first active The surface is disposed on the first circuit substrate in such a manner as to be away from the first surface. A plurality of solder balls are disposed on the second surface. a second circuit substrate having opposite third and fourth surfaces, the second circuit substrate being disposed on the first wafer with the fourth surface facing the first active surface, and the first wafer is coupled to the first wafer by the first row of pads The second column of pads is electrically connected to the second circuit substrate. a second wafer having a second active surface, a third column of pads, and a fourth column of pads, wherein the third column of pads is disposed on the second active surface in parallel with the fourth column of pads, and the second wafer is in a second active The surface is disposed on the second circuit substrate in a manner of facing the third surface, and the second wafer is electrically connected to the second circuit substrate through the third pad row and the fourth pad row. The plurality of first bumps connect the third row of pads and the second circuit substrate and connect the fourth column of pads and the second circuit substrate. The plurality of second bumps connect the first column of pads and the second circuit substrate and connect the second column of pads and the second circuit substrate. The plurality of first bonding wires are electrically connected to the first circuit substrate and the second circuit substrate. The encapsulant is disposed on the first surface and covers the first wafer, the second wafer, the second wiring substrate, and the first bonding wire.
在本發明之一實施例中,晶片封裝結構更包括黏著層,配置於第一線路基板與第一晶片之間。In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the first circuit substrate and the first wafer.
在本發明之一實施例中,晶片封裝結構更包括黏著層,配置於第二線路基板與第一晶片之間。In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the second circuit substrate and the first wafer.
在本發明之一實施例中,上述的黏著層具有異方導電性且包覆第一列接墊、第二列接墊以及第二凸塊。In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the first row of pads, the second column of pads, and the second bumps.
在本發明之一實施例中,晶片封裝結構更包括黏著層,配置於第二線路基板與第二晶片之間。 在本發明之一實施例中,上述的黏著層具有異方導電性且包覆第三列接墊、第四列接墊以及第一凸塊。In an embodiment of the invention, the chip package structure further includes an adhesive layer disposed between the second circuit substrate and the second wafer. In an embodiment of the invention, the adhesive layer has an anisotropic conductivity and covers the third row of pads, the fourth row of pads, and the first bumps.
基於上述,在本發明的隨機動態記憶體晶片封裝結構中,由於在上部晶片與下部晶片之間具有線路基板,且具有雙列接墊設計之上部晶片藉由覆晶接合的方式與此線路基板電性連接,因此可使其與同具有雙列接墊設計之下部晶片之配置方向相同,進而簡化製程複雜度。或者是,具有雙列接墊設計之上部晶片與下部晶片可利用各自的雙列接墊與其之間的線路基板連接,且上部晶片與下部晶片可藉由線路基板中的內連線來與線路基板周邊的接墊電性連接,因此不需製造接墊互為鏡像的晶片或是額外在晶片上進行重新佈線製程來解決上部晶片與下部晶片配置方向相反的問題。Based on the above, in the random dynamic memory chip package structure of the present invention, since the circuit substrate is provided between the upper wafer and the lower wafer, and the upper wafer having the double-row pad design is flip-chip bonded to the circuit substrate Electrically connected, it can be placed in the same direction as the wafer with the lower row of the double-row pad design, which simplifies process complexity. Alternatively, the upper wafer and the lower wafer having the double-row pad design can be connected to the circuit substrate therebetween by using the respective double-row pads, and the upper wafer and the lower wafer can be connected to the wiring by the interconnections in the circuit substrate. The pads around the substrate are electrically connected, so that it is not necessary to fabricate the wafers with the mirrors mirrored each other or to perform a rewiring process on the wafers to solve the problem that the upper wafers are opposite to the lower wafers.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1是依照本發明之第一實施例的晶片封裝結構的剖面示意圖。請參照圖1,本實施例的晶片封裝結構10包括線路基板100、晶片110、線路基板120、晶片130、銲球140、銲線150、封裝膠體160、黏著層170、黏著層180以及黏著層190。線路基板100例如是印刷線路板。線路基板100具有彼此相對的表面100a與表面100b。接墊102a與接墊102b分別配置在表面100a與表面100b上。接墊102a與接墊102b的材料例如是銅、金、銀、鋁或上述金屬的合金。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a wafer package structure in accordance with a first embodiment of the present invention. Referring to FIG. 1 , the chip package structure 10 of the present embodiment includes a circuit substrate 100 , a wafer 110 , a circuit substrate 120 , a wafer 130 , solder balls 140 , a bonding wire 150 , an encapsulant 160 , an adhesive layer 170 , an adhesive layer 180 , and an adhesive layer . 190. The circuit substrate 100 is, for example, a printed wiring board. The circuit substrate 100 has surfaces 100a and surfaces 100b opposed to each other. The pad 102a and the pad 102b are disposed on the surface 100a and the surface 100b, respectively. The material of the pad 102a and the pad 102b is, for example, copper, gold, silver, aluminum or an alloy of the above metals.
銲球140配置於表面100b上,且與表面100b上的接墊102b連接。銲球140的材料例如是錫。晶片封裝結構10可透過這些銲球140與外部電路或其他電子元件電性連接。The solder balls 140 are disposed on the surface 100b and are connected to the pads 102b on the surface 100b. The material of the solder ball 140 is, for example, tin. The chip package structure 10 can be electrically connected to external circuits or other electronic components through the solder balls 140.
晶片110具有主動表面110a、背面110b、第一列接墊112以及第二列接墊114,其中第一列接墊112與第二列接墊114平行配置在主動表面110a上。在本實施例中,第一列接墊112與第二列接墊114平行配置在主動表面110a的中間區域。晶片110以主動表面110a朝向表面100a的方式配置於線路基板100上。凸塊116連接第一列接墊112以及接墊102a且連接第二列接墊114以及接墊102a連接,以電性連接晶片110與線路基板100。換言之,晶片110透過覆晶接合的方式而與線路基板100電性連接。凸塊116的材料例如是金、銅、錫或上述金屬的合金。The wafer 110 has an active surface 110a, a back surface 110b, a first column of pads 112, and a second column of pads 114. The first column of pads 112 are disposed in parallel with the second column of pads 114 on the active surface 110a. In the present embodiment, the first row of pads 112 are disposed in parallel with the second row of pads 114 in the intermediate region of the active surface 110a. The wafer 110 is disposed on the circuit substrate 100 such that the active surface 110a faces the surface 100a. The bumps 116 are connected to the first row of pads 112 and the pads 102a and are connected to the second column pads 114 and the pads 102a to electrically connect the wafer 110 and the circuit substrate 100. In other words, the wafer 110 is electrically connected to the circuit substrate 100 by flip chip bonding. The material of the bumps 116 is, for example, gold, copper, tin or an alloy of the above metals.
晶片110透過黏著層170而固定至線路基板100。在本實施例中,黏著層170具有絕緣性。黏著層170例如是絕緣膠層、絕緣膠膜或絕緣散熱膠。黏著層170配置於線路基板100與晶片110之間且暴露第一列接墊112、第二列接墊114、凸塊116及與其連接的接墊102a。此外,可藉由底膠(underfill)118填滿由表面100a、主動表面110a與黏著層170所形成的空間,且包覆第一列接墊112、第二列接墊114、凸塊116及與其連接的接墊102a。底膠118的材料例如是環氧樹脂。The wafer 110 is fixed to the wiring substrate 100 through the adhesive layer 170. In the present embodiment, the adhesive layer 170 has an insulating property. The adhesive layer 170 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 170 is disposed between the circuit substrate 100 and the wafer 110 and exposes the first row of pads 112, the second column of pads 114, the bumps 116, and the pads 102a connected thereto. In addition, the space formed by the surface 100a, the active surface 110a and the adhesive layer 170 may be filled by an underfill 118, and the first row of pads 112, the second row of pads 114, the bumps 116 and A pad 102a connected thereto. The material of the primer 118 is, for example, an epoxy resin.
線路基板120配置於晶片110的背面110b上。線路基板120例如是印刷電路板。線路基板120具有彼此相對的表面120a與表面120b。接墊122配置在表面120a上。接墊112的材料例如是銅、金、銀、鋁或上述金屬的合金。The circuit substrate 120 is disposed on the back surface 110b of the wafer 110. The circuit substrate 120 is, for example, a printed circuit board. The circuit substrate 120 has surfaces 120a and 120b opposed to each other. The pads 122 are disposed on the surface 120a. The material of the pad 112 is, for example, copper, gold, silver, aluminum or an alloy of the above metals.
線路基板120藉由黏著層180而固定至晶片110。黏著層180例如是絕緣膠層、絕緣膠膜或絕緣散熱膠。The wiring substrate 120 is fixed to the wafer 110 by the adhesive layer 180. The adhesive layer 180 is, for example, an insulating layer, an insulating film or an insulating heat sink.
晶片130具有主動表面130a、背面130b、第三列接墊132以及第四列接墊134,其中第三列接墊132與第四列接墊134平行配置在主動表面130a上。在本實施例中,第三列接墊132與第四列接墊134平行配置在主動表面130a的中間區域。晶片130以主動表面130a朝向表面120a的方式配置於線路基板120上。凸塊136連接第三列接墊132以及接墊122且連接第四列接墊134以及接墊122,以電性連接晶片130以及線路基板120。換言之,晶片130透過覆晶接合的方式而與線路基板120電性連接。凸塊136的材料例如是金、銅、錫或上述金屬的合金。The wafer 130 has an active surface 130a, a back surface 130b, a third row of pads 132, and a fourth row of pads 134, wherein the third row of pads 132 are disposed in parallel with the fourth column of pads 134 on the active surface 130a. In the present embodiment, the third row of pads 132 are disposed in parallel with the fourth row of pads 134 in the intermediate region of the active surface 130a. The wafer 130 is disposed on the circuit substrate 120 such that the active surface 130a faces the surface 120a. The bumps 136 are connected to the third column pads 132 and the pads 122 and connect the fourth column pads 134 and the pads 122 to electrically connect the wafers 130 and the circuit substrate 120. In other words, the wafer 130 is electrically connected to the circuit substrate 120 by flip chip bonding. The material of the bumps 136 is, for example, gold, copper, tin or an alloy of the above metals.
晶片130藉由黏著層190而固定線路基板120。在本實施例中,黏著層190具有絕緣性。黏著層190例如是絕緣膠層、絕緣膠膜或絕緣散熱膠。黏著層190配置於線路基板120與晶片130之間且暴露第三列接墊132、第四列接墊134、凸塊136及與其連接的接墊122。可藉由底膠138填滿由表面120a、主動表面130a與黏著層190所形成的空間,且包覆第三列接墊132、第四列接墊134、凸塊136及與其連接的接墊122。The wafer 130 is fixed to the wiring substrate 120 by the adhesive layer 190. In the present embodiment, the adhesive layer 190 has an insulating property. The adhesive layer 190 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 190 is disposed between the circuit substrate 120 and the wafer 130 and exposes the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads 122 connected thereto. The space formed by the surface 120a, the active surface 130a and the adhesive layer 190 may be filled by the primer 138, and the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads connected thereto may be covered. 122.
銲線150的兩端分別連接表面120a上之接墊122與表面上100a之接墊102a,以使線路基板120與線路基板100電性連接。銲線150的材料例如是銅、金、銀或上述金屬的合金。The two ends of the bonding wire 150 are respectively connected to the pad 122 on the surface 120a and the pad 102a on the surface 100a to electrically connect the circuit substrate 120 to the circuit substrate 100. The material of the bonding wire 150 is, for example, copper, gold, silver or an alloy of the above metals.
封裝膠體160配置於表面100a上,且包覆晶片110、晶片130、線路基板120以及銲線150。封裝膠體160的材料例如是環氧樹脂。The encapsulant 160 is disposed on the surface 100a and covers the wafer 110, the wafer 130, the wiring substrate 120, and the bonding wires 150. The material of the encapsulant 160 is, for example, an epoxy resin.
在本實施例中,由於晶片封裝結構10包括線路基板120,具有雙列接墊設計之晶片130藉由覆晶接合的方式與線路基板120電性連接且與同樣具有雙列接墊設計之晶片110之配置方向相同,因此不需製造接墊互為鏡像的晶片或是額外在晶片上進行重新佈線製程來解決上部晶片與下部晶片的配置方向相反的問題。In this embodiment, since the chip package structure 10 includes the circuit substrate 120, the wafer 130 having the double-row pad design is electrically connected to the circuit substrate 120 by flip-chip bonding and the wafer having the double-row pad design. The arrangement direction of the 110 is the same, so that it is not necessary to manufacture a wafer in which the pads are mirror images or an additional rewiring process on the wafer to solve the problem that the arrangement of the upper wafer and the lower wafer is opposite.
圖2是依照本發明之第二實施例之一種晶片封裝結構的示意圖。圖2的晶片封裝結構20與圖1的晶片封裝結構10大致相似。在圖2中,與圖1相同的元件將以相同的標號表示,於此不另行對其進行說明。請參照圖2,圖2之晶片封裝結構20與圖1之晶片封裝結構10的主要差異在於:在本實施例中,黏著層170與黏著層190為具有異方導電性的黏著層。黏著層170、190例如是異方性導電膜(Anisotropic Conductive Film;ACF)。黏著層170配置於線路基板100與晶片110之間且包覆第一列接墊112、第二列接墊114、凸塊116及與其連接的接墊102a。黏著層190配置於線路基板120與晶片130之間且包覆第三列接墊132、第四列接墊134、凸塊136及與其連接的接墊122。2 is a schematic view of a chip package structure in accordance with a second embodiment of the present invention. The wafer package structure 20 of FIG. 2 is substantially similar to the wafer package structure 10 of FIG. In FIG. 2, the same elements as those in FIG. 1 will be denoted by the same reference numerals and will not be separately described. Referring to FIG. 2, the main difference between the chip package structure 20 of FIG. 2 and the chip package structure 10 of FIG. 1 is that in the embodiment, the adhesive layer 170 and the adhesive layer 190 are adhesive layers having an opposite conductivity. The adhesive layers 170 and 190 are, for example, an anisotropic conductive film (ACF). The adhesive layer 170 is disposed between the circuit substrate 100 and the wafer 110 and covers the first row of pads 112, the second row of pads 114, the bumps 116, and the pads 102a connected thereto. The adhesive layer 190 is disposed between the circuit substrate 120 and the wafer 130 and covers the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads 122 connected thereto.
由於在本實施例中是直接利用黏著層170來取代底膠包覆第一列接墊112、第二列接墊114、凸塊116及與其連接的接墊102a,以及利用黏著層190來取代底膠包覆第三列接墊132、第四列接墊134、凸塊136及與其連接的接墊122,因此可避免因在填充底膠過程中可能發生填充底膠不完全的問題。In this embodiment, the first layer of the pad 112, the second row of pads 114, the bumps 116, and the pads 102a connected thereto are directly replaced by the adhesive layer 170, and the adhesive layer 190 is used instead. The primer covers the third row of pads 132, the fourth row of pads 134, the bumps 136, and the pads 122 connected thereto, thereby avoiding the problem that the filling primer may be incomplete during the filling of the primer.
在本實施例中,黏著層170與黏著層190皆為具有異方導電性的黏著層。但本發明不限於此,在一實施例中,黏著層170可為具有異方導電性的黏著層,而黏著層190可為具有絕緣性的黏著層。在另一實施例中,亦可黏著層170為具有絕緣性的黏著層,而黏著層190為具有異方導電性的黏著層。In this embodiment, the adhesive layer 170 and the adhesive layer 190 are both adhesive layers having an opposite conductivity. However, the present invention is not limited thereto. In one embodiment, the adhesive layer 170 may be an adhesive layer having an isotropic conductivity, and the adhesive layer 190 may be an insulating adhesive layer. In another embodiment, the adhesive layer 170 may be an insulating adhesive layer, and the adhesive layer 190 is an adhesive layer having an isotropic conductivity.
圖3是依照本發明之第三實施例之一種晶片封裝結構的示意圖。圖3的晶片封裝結構30與圖1的晶片封裝結構10大致相似。在圖3中,與圖1相同的元件將以相同的標號表示,於此不另行對其進行說明。請同時參照圖1與圖3,圖3之晶片封裝結構30與圖1之晶片封裝結構10的主要差異在於,在圖1中,晶片110是以凸塊116電性連接至線路基板100,也就是說,晶片110是以覆晶接合的方式與線路基板100電性連接。而在圖3中,晶片110是藉由銲線316電性連接至線路基板100,也就是說,晶片110是以打線接合的方式與線路基板100電性連接。3 is a schematic diagram of a chip package structure in accordance with a third embodiment of the present invention. The wafer package structure 30 of FIG. 3 is substantially similar to the wafer package structure 10 of FIG. In FIG. 3, the same components as those in FIG. 1 will be denoted by the same reference numerals and will not be described herein. Referring to FIG. 1 and FIG. 3 simultaneously, the main difference between the chip package structure 30 of FIG. 3 and the chip package structure 10 of FIG. 1 is that, in FIG. 1, the wafer 110 is electrically connected to the circuit substrate 100 by bumps 116. That is, the wafer 110 is electrically connected to the circuit substrate 100 in a flip chip bonding manner. In FIG. 3, the wafer 110 is electrically connected to the circuit substrate 100 by a bonding wire 316, that is, the wafer 110 is electrically connected to the circuit substrate 100 by wire bonding.
詳細地說,在圖3中,線路基板100具有暴露第一列接墊112與第二列接墊114的開槽318,銲線316穿過開槽318以連接第一列接墊112與表面100b上之接墊102b以及連接第二列接墊114與表面100b上之接墊102b。封裝膠體160填滿開槽318且包覆銲線316、第一列接墊112、第二列接墊114以及與銲線316連接的接墊102b。In detail, in FIG. 3, the circuit substrate 100 has a slot 318 exposing the first row of pads 112 and the second row of pads 114, and the bonding wires 316 pass through the slots 318 to connect the first row of pads 112 to the surface. The pad 102b on the 100b and the pad 102b on the surface 100b are connected to the second row of pads 114b. The encapsulant 160 fills the trench 318 and covers the bonding wires 316, the first column pads 112, the second column pads 114, and the pads 102b connected to the bonding wires 316.
同樣地,在其他實施例中,亦可將圖3中的絕緣黏著層190替換為具有異方導電性的黏著層。Similarly, in other embodiments, the insulating adhesive layer 190 of FIG. 3 can also be replaced with an adhesive layer having an anisotropic conductivity.
圖4是依照本發明之第四實施例之一種晶片封裝結構的示意圖。請參照圖4,本實施例的晶片封裝結構40包括線路基板400、晶片410、線路基板420、晶片430、銲球440、銲線450、封裝膠體460、黏著層470、黏著層480以及黏著層490。線路基板400例如是印刷電路板。線路基板400具有彼此相對的表面400a與表面400b。接墊402a與接墊402b分別配置在表面400a與表面400b上。接墊402a與接墊402b的材料例如是銅、金、銀、鋁或上述金屬的合金。4 is a schematic view of a chip package structure in accordance with a fourth embodiment of the present invention. Referring to FIG. 4 , the chip package structure 40 of the present embodiment includes a circuit substrate 400 , a wafer 410 , a circuit substrate 420 , a wafer 430 , solder balls 440 , a bonding wire 450 , an encapsulant 460 , an adhesive layer 470 , an adhesive layer 480 , and an adhesive layer . 490. The circuit substrate 400 is, for example, a printed circuit board. The circuit substrate 400 has surfaces 400a and 400b opposed to each other. The pads 402a and the pads 402b are disposed on the surface 400a and the surface 400b, respectively. The material of the pad 402a and the pad 402b is, for example, copper, gold, silver, aluminum or an alloy of the above metals.
銲球440配置於表面400b上,且與表面400b上的接墊402b連接。銲球440的材料例如是錫。晶片封裝結構40可透過這些銲球440與外部電路或其他電子元件電性連接。Solder balls 440 are disposed on surface 400b and are coupled to pads 402b on surface 400b. The material of the solder balls 440 is, for example, tin. The chip package structure 40 can be electrically connected to external circuits or other electronic components through the solder balls 440.
晶片410具有主動表面410a、背面410b、第一列接墊412以及第二列接墊414,其中第一列接墊412與第二列接墊414平行配置在主動表面410a上。在本實施例中,第一列接墊412與第二列接墊414平行配置在主動表面410a的中間區域。晶片410以背面410b朝向表面400a的方式(即以主動表面410a遠離表面400a的方式)配置於線路基板400上。The wafer 410 has an active surface 410a, a back surface 410b, a first row of pads 412, and a second column of pads 414, wherein the first column of pads 412 are disposed in parallel with the second column of pads 414 on the active surface 410a. In the present embodiment, the first row of pads 412 are disposed in parallel with the second row of pads 414 in the intermediate region of the active surface 410a. The wafer 410 is disposed on the circuit substrate 400 in such a manner that the back surface 410b faces the surface 400a (ie, the active surface 410a is away from the surface 400a).
晶片410透過黏著層470而固定至線路基板400。黏著層470例如是絕緣膠層、絕緣膠膜或絕緣散熱膠。The wafer 410 is fixed to the wiring substrate 400 through the adhesive layer 470. The adhesive layer 470 is, for example, an insulating layer, an insulating film or an insulating heat sink.
線路基板420具有彼此相對的表面420a與表面420b。線路基板420以表面420b朝向主動表面410a的方式配置於晶片410上。線路基板420例如是印刷電路板。接墊422a與接墊422b分別配置在表面420a與表面420b上。接墊422a與接墊422b的材料例如是銅、金、銀、鋁或上述金屬的合金。The wiring substrate 420 has surfaces 420a and 420b opposed to each other. The wiring substrate 420 is disposed on the wafer 410 such that the surface 420b faces the active surface 410a. The circuit substrate 420 is, for example, a printed circuit board. The pads 422a and the pads 422b are disposed on the surface 420a and the surface 420b, respectively. The material of the pads 422a and the pads 422b is, for example, copper, gold, silver, aluminum or an alloy of the above metals.
凸塊416連接第一列接墊412以及接墊422b且連接第二列接墊414以及接墊422b,以電性連接晶片410與線路基板420。凸塊416的材料例如是金、銅、錫或上述金屬的合金。The bump 416 is connected to the first column pad 412 and the pad 422b and connects the second column pad 414 and the pad 422b to electrically connect the wafer 410 and the circuit substrate 420. The material of the bumps 416 is, for example, gold, copper, tin or an alloy of the above metals.
線路基板420透過黏著層480而固定至晶片410。在本實施例中,黏著層480具有絕緣性。黏著層480例如是絕緣膠層、絕緣膠膜或絕緣散熱膠。黏著層480配置於線路基板420與晶片410之間且暴露第一列接墊412、第二列接墊414、凸塊416及與其連接的接墊422b。底膠418填滿由表面420b、主動表面410a與黏著層480所形成的空間,且包覆第一列接墊412、第二列接墊414、凸塊416及與其連接的接墊422b。底膠418的材料例如是環氧樹脂。The wiring substrate 420 is fixed to the wafer 410 through the adhesive layer 480. In the present embodiment, the adhesive layer 480 has insulation properties. The adhesive layer 480 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 480 is disposed between the circuit substrate 420 and the wafer 410 and exposes the first row of pads 412, the second column of pads 414, the bumps 416, and the pads 422b connected thereto. The primer 418 fills the space formed by the surface 420b, the active surface 410a and the adhesive layer 480, and covers the first row of pads 412, the second row of pads 414, the bumps 416, and the pads 422b connected thereto. The material of the primer 418 is, for example, an epoxy resin.
晶片430具有主動表面430a、背面430b、第三列接墊432以及第四列接墊434,其中第三列接墊432與第四列接墊434平行配置在主動表面430a上。在本實施例中,第三列接墊432與第四列接墊434平行配置在主動表面430a的中間區域。晶片430以主動表面430a朝向表面420a的方式配置於線路基板420上。凸塊436連接第三列接墊432以及接墊422連接且連接第四列接墊434以及接墊422。換言之,晶片430透過覆晶接合的方式而與線路基板420電性連接。凸塊436的材料例如是金、銅、錫或上述金屬的合金。The wafer 430 has an active surface 430a, a back surface 430b, a third row of pads 432, and a fourth column of pads 434, wherein the third column of pads 432 are disposed in parallel with the fourth column of pads 434 on the active surface 430a. In the present embodiment, the third row of pads 432 are disposed in parallel with the fourth row of pads 434 in the intermediate region of the active surface 430a. The wafer 430 is disposed on the wiring substrate 420 with the active surface 430a facing the surface 420a. The bumps 436 are connected to the third row of pads 432 and the pads 422 are connected and connected to the fourth row of pads 434 and the pads 422. In other words, the wafer 430 is electrically connected to the circuit substrate 420 by flip chip bonding. The material of the bump 436 is, for example, gold, copper, tin or an alloy of the above metals.
晶片430透過黏著層490而固定至線路基板420。在本實施例中,黏著層490具有絕緣性。黏著層490例如是絕緣膠層、絕緣膠膜或絕緣散熱膠。黏著層490配置於線路基板420與晶片430之間且暴露第三列接墊432、第四列接墊434、凸塊436及與其連接的接墊422a。底膠438填滿由表面420a、主動表面430a與黏著層490所形成的空間,且包覆第三列接墊432、第四列接墊434、凸塊436及與其連接的接墊422a。The wafer 430 is fixed to the wiring substrate 420 through the adhesive layer 490. In the present embodiment, the adhesive layer 490 has insulation properties. The adhesive layer 490 is, for example, an insulating layer, an insulating film or an insulating heat sink. The adhesive layer 490 is disposed between the circuit substrate 420 and the wafer 430 and exposes the third row of pads 432, the fourth row of pads 434, the bumps 436, and the pads 422a connected thereto. The primer 438 fills the space formed by the surface 420a, the active surface 430a and the adhesive layer 490, and covers the third row of pads 432, the fourth row of pads 434, the bumps 436, and the pads 422a connected thereto.
銲線450的兩端分別連接表面420a上之接墊422a與表面400a上之接墊402a,以使線路基板420與線路基板400電性連接。The two ends of the bonding wire 450 are respectively connected to the pads 422a on the surface 420a and the pads 402a on the surface 400a to electrically connect the circuit substrate 420 and the circuit substrate 400.
封裝膠體460配置於表面400a上,且包覆晶片410、晶片430、線路基板420以及銲線450。封裝膠體460的材料例如是環氧樹脂。The encapsulant 460 is disposed on the surface 400a and covers the wafer 410, the wafer 430, the wiring substrate 420, and the bonding wires 450. The material of the encapsulant 460 is, for example, an epoxy resin.
在本實施例中,由於晶片封裝結構40包括線路基板420,因此即使在晶片410與晶片430的配置方向是相反的情況下,晶片410的第一列接墊412與晶片430之第三列接墊432可藉由線路基板420的內連線而電性連接至圖4中左半邊的接墊422a,再進一步藉由銲線450電性連接至線路基板400。同樣地,晶片410的第二列接墊414與晶片430的第四列接墊434可藉由線路基板420的內連線而電性連接至圖4中右半邊的接墊422a,再進一步藉由銲線450電性連接至線路基板400,因此不需製造接墊互為鏡像的晶片或是額外在晶片上進行重新佈線製程來解決上部晶片與下部晶片的配置方向相反的問題。此外,由於晶片410與晶片430皆是先與線路基板420電性連接,再藉由銲線450連接線路基板400與線路基板420,因此可避免因上部晶片與下部晶片的線路不等長所產生的問題。In the present embodiment, since the chip package structure 40 includes the circuit substrate 420, even in the case where the arrangement direction of the wafer 410 and the wafer 430 is opposite, the first row of pads 412 of the wafer 410 and the third row of the wafer 430 are connected. The pad 432 can be electrically connected to the pad 422a of the left half of FIG. 4 by the interconnection of the circuit substrate 420, and further electrically connected to the circuit substrate 400 by the bonding wire 450. Similarly, the second row of pads 414 of the wafer 410 and the fourth row of pads 434 of the wafer 430 can be electrically connected to the pads 422a of the right half of FIG. 4 by the interconnection of the circuit substrate 420, and further borrowed. The bonding wire 450 is electrically connected to the circuit substrate 400. Therefore, it is not necessary to manufacture a wafer in which the pads are mirror images or to perform a rewiring process on the wafer to solve the problem that the arrangement direction of the upper wafer and the lower wafer is opposite. In addition, since both the wafer 410 and the wafer 430 are electrically connected to the circuit substrate 420 first, and then the circuit substrate 400 and the circuit substrate 420 are connected by the bonding wire 450, it is possible to avoid the unequal length of the upper wafer and the lower wafer. problem.
在本實施例中,黏著層480與黏著層490皆為具有絕緣性的黏著層。但本發明不限於此,在一實施例中,黏著層480與黏著層490可皆為具有異方導電性的黏著層。在另一實施例中,黏著層480可為具有絕緣性的黏著層,而黏著層490可為具有異方導電性的黏著層。再又一實施例中,黏著層490可為具有絕緣性的黏著層,而黏著層480可為具有異方導電性的黏著層。In this embodiment, the adhesive layer 480 and the adhesive layer 490 are both insulating adhesive layers. However, the present invention is not limited thereto. In an embodiment, the adhesive layer 480 and the adhesive layer 490 may both be adhesive layers having an opposite conductivity. In another embodiment, the adhesive layer 480 can be an insulating adhesive layer, and the adhesive layer 490 can be an adhesive layer having an isotropic conductivity. In still another embodiment, the adhesive layer 490 can be an insulating adhesive layer, and the adhesive layer 480 can be an adhesive layer having an isotropic conductivity.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
10、20、30、40‧‧‧晶片封裝結構
100、120、400、420‧‧‧線路基板
100a、100b、120a、120b、400a、400b、420a、420b‧‧‧表面
102a、102b、122、402a、402b、422a、422b‧‧‧接墊
110、130、410、430‧‧‧晶片
110a、130a、410a、430a‧‧‧主動表面
110b、130b、410b、430b‧‧‧背面
112、412‧‧‧第一列接墊
114、414‧‧‧第二列接墊
116、136、416、436‧‧‧凸塊
118、138、418、438‧‧‧底膠
132、432‧‧‧第三列接墊
134、434‧‧‧第四列接墊
140、440‧‧‧銲球
150、316、450‧‧‧銲線
160、360‧‧‧封裝膠體
170、180、190、470、480、490‧‧‧黏著層
318‧‧‧開槽10, 20, 30, 40‧‧‧ chip package structure
100, 120, 400, 420‧‧‧ circuit substrates
100a, 100b, 120a, 120b, 400a, 400b, 420a, 420b‧‧‧ surface
102a, 102b, 122, 402a, 402b, 422a, 422b‧‧‧ pads
110, 130, 410, 430‧‧‧ wafers
110a, 130a, 410a, 430a‧‧‧ active surface
110b, 130b, 410b, 430b‧‧‧ back
112, 412‧‧‧first row of pads
114, 414‧‧‧second row of pads
116, 136, 416, 436‧‧ ‧ bumps
118, 138, 418, 438‧‧ ‧ primer
132, 432‧‧‧ third row of pads
134, 434‧‧‧ fourth row of pads
140, 440‧‧‧ solder balls
150, 316, 450‧‧‧ welding line
160, 360‧‧‧Package colloid
170, 180, 190, 470, 480, 490‧‧ ‧ adhesive layer
318‧‧‧ slotting
圖1是依照本發明之第一實施例的晶片封裝結構的剖面示意圖。 圖2是依照本發明之第二實施例的晶片封裝結構的剖面示意圖。 圖3是依照本發明之第三實施例的晶片封裝結構的剖面示意圖。 圖4是依照本發明之第四實施例的晶片封裝結構的剖面示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross-sectional view showing a wafer package structure in accordance with a first embodiment of the present invention. 2 is a cross-sectional view showing a wafer package structure in accordance with a second embodiment of the present invention. 3 is a cross-sectional view showing a wafer package structure in accordance with a third embodiment of the present invention. 4 is a cross-sectional view showing a wafer package structure in accordance with a fourth embodiment of the present invention.
30‧‧‧晶片封裝結構 30‧‧‧ Chip package structure
100、120‧‧‧線路基板 100, 120‧‧‧ circuit substrate
100a、100b、120a、120b‧‧‧表面 100a, 100b, 120a, 120b‧‧‧ surface
102a、102b、122‧‧‧接墊 102a, 102b, 122‧‧‧ pads
110、130‧‧‧晶片 110, 130‧‧‧ wafer
110a、130a‧‧‧主動表面 110a, 130a‧‧‧ active surface
110b、130b‧‧‧背面 110b, 130b‧‧‧ back
112‧‧‧第一列接墊 112‧‧‧first row of pads
114‧‧‧第二列接墊 114‧‧‧Second row of pads
136‧‧‧凸塊 136‧‧‧Bumps
138‧‧‧底膠 138‧‧‧Bottom glue
132‧‧‧第三列接墊 132‧‧‧ third row of pads
134‧‧‧第四列接墊 134‧‧‧fourth row of pads
140‧‧‧銲球 140‧‧‧ solder balls
150、316‧‧‧銲線 150, 316‧‧‧ welding line
160‧‧‧封裝膠體 160‧‧‧Package colloid
170、180、190‧‧‧黏著層 170, 180, 190‧‧ ‧ adhesive layer
318‧‧‧開槽 318‧‧‧ slotting
Claims (15)
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