CN104241153A - Packaging method for board level fan-out structures - Google Patents
Packaging method for board level fan-out structures Download PDFInfo
- Publication number
- CN104241153A CN104241153A CN201410473259.8A CN201410473259A CN104241153A CN 104241153 A CN104241153 A CN 104241153A CN 201410473259 A CN201410473259 A CN 201410473259A CN 104241153 A CN104241153 A CN 104241153A
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- Prior art keywords
- copper foil
- double
- blind hole
- chip
- fan
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Abstract
The invention relates to the technical field of electronic packaging, in particular to a packaging method for board level fan-out structures. The method includes the steps of copper foil pressing fit, chip surface mounting, medium layer pressing fit, blind hole manufacturing, circuit manufacturing, installed and welded layer pressing fit, ball attachment, stripping and others. According to the packaging method for the board level fan-out structure, two fan-out packaging structures are symmetrically designed on the upper side and the lower side of a core board, and in the manufacturing process, because the upper end and the lower end of the core board are symmetrically and evenly stressed, and a high-temperature annealing mode is adopted for eliminating internal stress before a first double-layer copper foil structure and a second double-layer copper foil structure are stripped, the problem of warping and other mechanical deformation problems will not occur, and the quality and performance of the fan-out structures are guaranteed. In addition, the packaging method for the board level fan-out structures can be used for manufacturing the two fan-out structures at the same time, and therefore production efficiency is improved.
Description
Technical field
The present invention relates to technical field of electronic encapsulation, particularly a kind of method for packing of plate level fan-out-type structure.
Background technology
Electronics high-density packages is paid attention to widely by industrial circle.Chip three-dimensional stacked, effectively decrease the three-dimensional dimension of device, the stack manner of chip chamber is also in continuous improvement.(Through Silicon Via) through hole interconnection technique from Flip Chip to silica-based TSV, the three-dimensional dimension of device becomes more and more less.Packaging technology, also from original bonding, paster, plastic packaging, develops into RDL, Flip Chip, wafer bonding, TSV etc. the key process technology introducing FEOL, and larger, that size the is less encapsulating structure of chip density is continued to bring out.In the fabrication process, easily there is the problems such as warpage in existing fan-out-type structure, has had a strong impact on quality and the performance of fan-out-type structure.In addition, also there is the inefficient problem of manufacture in existing fan-out-type structure.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of plate level fan-out-type structure that can solve and easily produces mechanical warpage issues in the fabrication process and manufacture the method for packing of inefficient plate level fan-out-type structure.
For solving the problems of the technologies described above, the invention provides a kind of method for packing of plate level fan-out-type structure, comprising:
At the double-deck Copper Foil of upside pressing first of central layer, at the double-deck Copper Foil of downside pressing second of described central layer; Described first double-deck Copper Foil and described second double-deck Copper Foil are peelable structure.
Outside described first double-deck Copper Foil, mount the first chip, mount the second chip outside described second double-deck Copper Foil, the active face of described first chip and described second chip outwardly.
At the outside pressing first medium layer of described first chip, the outside pressing second dielectric layer of described second chip.
Described first medium layer makes the first blind hole, and described first blind hole runs through described first medium layer and is communicated with the salient point on described first chip; Described second dielectric layer makes the second blind hole, and described second blind hole runs through described second dielectric layer and is communicated with the salient point on described second chip.
In described first blind hole, the second blind hole and on described first medium layer and described second dielectric layer, change the Seed Layer of the thin copper of one deck as plating, then electroplate on described dielectric layer, described first blind hole and described second blind hole are filled.
Described first medium layer and described first blind hole carry out the making of fan-out circuit or multilayer laminated circuit; Described second dielectric layer and described second blind hole are carried out the making of fan-out circuit or multilayer laminated circuit.
Pressing first solder mask on circuit outside described first medium layer, making the first pad for planting ball at described first solder mask uplifting window, then on described first pad, carrying out surface-coated; Pressing second solder mask on circuit outside described second dielectric layer, making the second pad for planting ball at described second solder mask uplifting window, then on described second pad, carrying out surface-coated.
First soldered ball is planted on described first pad, the second soldered ball is planted on described second pad.
The high temperature anneal is carried out to the double-deck Copper Foil of described first core and described second double-deck Copper Foil, the double-deck Copper Foil of described first core and described second double-deck Copper Foil is peeled off respectively, obtains two fan-out package structures.
Further, the thickness of the outer copper foil in described first double-deck Copper Foil is greater than the thickness of internal layer Copper Foil; The thickness of the outer copper foil in described second double-deck Copper Foil is greater than the thickness of internal layer Copper Foil.
Further, the thickness of described first medium layer is greater than the thickness of described first chip; The thickness of described second dielectric layer is greater than the thickness of described second chip.
Further, described first chip is mounted on the outside of described first double-deck Copper Foil by heat-conducting glue; Described second chip is mounted on the outside of described second double-deck Copper Foil by heat-conducting glue.
Further, adopt the method for electroless plating in described first blind hole, the second blind hole and on described first medium layer and described second dielectric layer, change the Seed Layer of the thin copper of one deck as plating.
Further, described central layer adopts the organic substrate of prepreg or double-sided copper-clad.
The method for packing of plate level fan-out-type structure provided by the invention, in upper and lower side symmetric design two fan-out package structures of central layer, the upper and lower end due to central layer in the process manufactured is symmetrically and evenly stressed; Before the double-deck copper foil structure of stripping first and the second double-deck copper foil structure, adopt the mode of high annealing to eliminate internal stress, therefore can not produce the mechanical deformation problems such as warpage, ensure that quality and the performance of fan-out-type structure.In addition, the method for packing of plate level fan-out-type structure provided by the invention can manufacture two fan-out-type structures simultaneously, improves production efficiency.
Accompanying drawing explanation
Step 1 operation chart that Fig. 1 provides for the embodiment of the present invention;
Step 2 operation chart that Fig. 2 provides for the embodiment of the present invention;
Step 3 operation chart that Fig. 3 provides for the embodiment of the present invention;
Step 4 operation chart that Fig. 4 provides for the embodiment of the present invention;
Step 5 operation chart that Fig. 5 provides for the embodiment of the present invention;
Step 6 operation chart that Fig. 6 provides for the embodiment of the present invention;
Step 7 operation chart that Fig. 7 provides for the embodiment of the present invention;
Step 8 operation chart that Fig. 8 provides for the embodiment of the present invention;
Step 9 operation chart that Fig. 9 provides for the embodiment of the present invention;
Embodiment
See Fig. 1, embodiments provide a kind of method for packing of plate level fan-out-type structure, comprising:
Step 1: see Fig. 1, at the double-deck Copper Foil 2 of upside pressing first of central layer 1 (adopting the organic substrate of prepreg or double-sided copper-clad), at the double-deck Copper Foil 3 of the downside pressing second of central layer 1; First double-deck Copper Foil 2 and the second double-deck Copper Foil 3 are peelable structure.The thickness of the outer copper foil in the first double-deck Copper Foil 2 is greater than the thickness of internal layer Copper Foil; The thickness of the outer copper foil in the second double-deck Copper Foil 3 is greater than the thickness of internal layer Copper Foil.
Step 2: see Fig. 2, mount outside the first double-deck Copper Foil 2 mount the second chip 5, first chip 4 and the second chip 5 outside the double-deck Copper Foil 3 of first chip 4, second active face outwardly.
Step 3: see Fig. 3, in the outside pressing second dielectric layer 7 of outside pressing first medium layer 6, second chip 5 of the first chip 4.Wherein, the thickness of first medium layer 6 is greater than the thickness of the first chip 4, and the thickness of second dielectric layer 7 is greater than the thickness of the second chip 5.
Step 4: see Fig. 4, first medium layer 6 makes the first blind hole 8, first blind hole 8 and runs through first medium layer 6 and be communicated with the salient point on the first chip 4; Second dielectric layer 7 makes the second blind hole 9, second blind hole 9 run through second dielectric layer 7 and be communicated with the salient point on the second chip 5.
Step 5: see Fig. 4 and Fig. 5, adopt the method for electroless plating in the first blind hole 8, second blind hole 9 and on first medium layer 6 and second dielectric layer 7, change the Seed Layer 10 of the thin copper of one deck as plating, then electroplate on dielectric layer, the first blind hole 8 and the second blind hole 9 are filled.
Step 6: see Fig. 4-Fig. 6, first medium layer 6 and the first blind hole 8 carry out the making of fan-out circuit or multilayer laminated circuit; Second dielectric layer 7 and the second blind hole 9 are carried out the making of fan-out circuit or multilayer laminated circuit.
Step 7: see Fig. 4-Fig. 7, pressing first solder mask 11 on the circuit outside first medium layer 6, making the first pad for planting ball at the first solder mask 11 uplifting window, then on the first pad, carrying out surface-coated; Pressing second solder mask 12 on circuit outside second dielectric layer 7, making the second pad for planting ball at the second solder mask 12 uplifting window, then on the second pad, carrying out surface-coated.
Step 8: see Fig. 8, plants the first soldered ball 13 on the first pad, plants the second soldered ball 14 on the second pad.
Step 9: see Fig. 1 and Fig. 9, carries out the high temperature anneal to the double-deck Copper Foil 2 of the first core and the second double-deck Copper Foil 3, double-deck for the first core Copper Foil 2 and the second double-deck Copper Foil 3 is peeled off respectively, obtains two fan-out-type structures.
The method for packing of the plate level fan-out-type structure that the embodiment of the present invention provides, in upper and lower side symmetric design two fan-out package structures of central layer, the upper and lower end due to central layer in the process manufactured is symmetrically and evenly stressed; Before the double-deck copper foil structure of stripping first and the second double-deck copper foil structure, adopt the mode of high annealing to eliminate internal stress, therefore can not produce the mechanical deformation problems such as warpage, ensure that quality and the performance of fan-out-type structure.In addition, the method for packing of the plate level fan-out-type structure that the embodiment of the present invention provides can manufacture two fan-out-type structures simultaneously, improves production efficiency.
It should be noted last that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to example to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (6)
1. a method for packing for plate level fan-out-type structure, is characterized in that, comprising:
At the double-deck Copper Foil of upside pressing first of central layer, at the double-deck Copper Foil of downside pressing second of described central layer; Described first double-deck copper foil structure and described second double-deck copper foil structure are peelable structure;
Outside described first double-deck Copper Foil, mount the first chip, mount the second chip outside described second double-deck Copper Foil, the active face of described first chip and described second chip outwardly;
At the outside pressing first medium layer of described first chip, the outside pressing second dielectric layer of described second chip;
Described first medium layer makes the first blind hole, and described first blind hole runs through described first medium layer and is communicated with the salient point on described first chip; Described second dielectric layer makes the second blind hole, and described second blind hole runs through described second dielectric layer and is communicated with the salient point on described second chip;
In described first blind hole, the second blind hole and on described first medium layer and described second dielectric layer, change the Seed Layer of the thin copper of one deck as plating, then electroplate on described dielectric layer, described first blind hole and described second blind hole are filled;
Described first medium layer and described first blind hole carry out the making of fan-out circuit or multilayer laminated circuit; Described second dielectric layer and described second blind hole are carried out the making of fan-out circuit or multilayer laminated circuit;
Pressing first solder mask on circuit outside described first medium layer, making the first pad for planting ball at described first solder mask uplifting window, then on described first pad, carrying out surface-coated; Pressing second solder mask on circuit outside described second dielectric layer, making the second pad for planting ball at described second solder mask uplifting window, then on described second pad, carrying out surface-coated;
First soldered ball is planted on described first pad, the second soldered ball is planted on described second pad;
The high temperature anneal is carried out to the double-deck Copper Foil of described first core and described second double-deck Copper Foil, the double-deck Copper Foil of described first core and described second double-deck Copper Foil is peeled off respectively, obtains two fan-out-type structures.
2. the method for packing of plate level fan-out-type structure according to claim 1, is characterized in that, the thickness of the outer copper foil in described first double-deck Copper Foil is greater than the thickness of internal layer Copper Foil;
The thickness of the outer copper foil in described second double-deck Copper Foil is greater than the thickness of internal layer Copper Foil.
3. the method for packing of plate level fan-out-type structure according to claim 1, is characterized in that, the thickness of described first medium layer, second dielectric layer is greater than the thickness of described chip.
4. the method for packing of plate level fan-out-type structure according to claim 1, is characterized in that, described first chip is mounted on the outside of described first double-deck Copper Foil by heat-conducting glue;
Described second chip is mounted on the outside of described second double-deck Copper Foil by heat-conducting glue.
5. the method for packing of plate level fan-out-type structure according to claim 1, it is characterized in that, adopt the method for electroless plating in described first blind hole, the second blind hole and on described first medium layer and described second dielectric layer, change the Seed Layer of the thin copper of one deck as plating.
6. the method for packing of plate level fan-out-type structure according to claim 1, is characterized in that, described central layer adopts the organic substrate of prepreg or double-sided copper-clad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410473259.8A CN104241153B (en) | 2014-09-16 | The method for packing of plate level fan-out-type structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410473259.8A CN104241153B (en) | 2014-09-16 | The method for packing of plate level fan-out-type structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104241153A true CN104241153A (en) | 2014-12-24 |
| CN104241153B CN104241153B (en) | 2017-01-04 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105140189A (en) * | 2015-07-08 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | Board-level fan-out chip packaging device and preparation method thereof |
| CN106783796A (en) * | 2016-12-07 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip-packaging structure and preparation method thereof |
| CN107785329A (en) * | 2016-08-30 | 2018-03-09 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
| CN110459510A (en) * | 2019-08-08 | 2019-11-15 | 广东芯华微电子技术有限公司 | Big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070059866A1 (en) * | 2003-12-03 | 2007-03-15 | Advanced Chip Engineering Technology Inc. | Fan out type wafer level package structure and method of the same |
| CN203491244U (en) * | 2013-09-26 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure |
| CN103985695A (en) * | 2014-05-19 | 2014-08-13 | 中国科学院微电子研究所 | Fan-out type packaging structure and manufacturing process thereof |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070059866A1 (en) * | 2003-12-03 | 2007-03-15 | Advanced Chip Engineering Technology Inc. | Fan out type wafer level package structure and method of the same |
| CN203491244U (en) * | 2013-09-26 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure |
| CN103985695A (en) * | 2014-05-19 | 2014-08-13 | 中国科学院微电子研究所 | Fan-out type packaging structure and manufacturing process thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105140189A (en) * | 2015-07-08 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | Board-level fan-out chip packaging device and preparation method thereof |
| CN105140189B (en) * | 2015-07-08 | 2019-04-26 | 华进半导体封装先导技术研发中心有限公司 | Plate grade fan-out-type chip package device and preparation method thereof |
| CN107785329A (en) * | 2016-08-30 | 2018-03-09 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
| CN106783796A (en) * | 2016-12-07 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip-packaging structure and preparation method thereof |
| CN106783796B (en) * | 2016-12-07 | 2019-04-26 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip-packaging structure and preparation method thereof |
| CN110459510A (en) * | 2019-08-08 | 2019-11-15 | 广东芯华微电子技术有限公司 | Big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof |
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Effective date of registration: 20180530 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Institute of Microelectronics, Chinese Academy of Sciences Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: National Center for Advanced Packaging Co.,Ltd. Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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Effective date of registration: 20180712 Address after: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee after: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |
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Effective date of registration: 20180816 Address after: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee after: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Beijing Zhongke micro Investment Management Co.,Ltd. Effective date of registration: 20180816 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics, Chinese Academy of Sciences Effective date of registration: 20180816 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Institute of Microelectronics, Chinese Academy of Sciences Address before: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee before: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. |
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