CN104241153A - Packaging method of board-level fan-out structure - Google Patents
Packaging method of board-level fan-out structure Download PDFInfo
- Publication number
- CN104241153A CN104241153A CN201410473259.8A CN201410473259A CN104241153A CN 104241153 A CN104241153 A CN 104241153A CN 201410473259 A CN201410473259 A CN 201410473259A CN 104241153 A CN104241153 A CN 104241153A
- Authority
- CN
- China
- Prior art keywords
- copper foil
- double
- chip
- blind hole
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 title abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 64
- 239000011889 copper foil Substances 0.000 claims abstract description 51
- 238000003825 pressing Methods 0.000 claims abstract description 21
- 238000012856 packing Methods 0.000 claims description 15
- 229910000679 solder Inorganic materials 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 238000000137 annealing Methods 0.000 abstract description 3
- 238000004100 electronic packaging Methods 0.000 abstract 1
- 238000003466 welding Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410473259.8A CN104241153B (en) | 2014-09-16 | Packaging method of board-level fan-out structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410473259.8A CN104241153B (en) | 2014-09-16 | Packaging method of board-level fan-out structure |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104241153A true CN104241153A (en) | 2014-12-24 |
CN104241153B CN104241153B (en) | 2017-01-04 |
Family
ID=
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105140189A (en) * | 2015-07-08 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | Board-level fan-out chip packaging device and preparation method thereof |
CN106783796A (en) * | 2016-12-07 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip-packaging structure and preparation method thereof |
CN107785329A (en) * | 2016-08-30 | 2018-03-09 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
CN110459510A (en) * | 2019-08-08 | 2019-11-15 | 广东芯华微电子技术有限公司 | Big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070059866A1 (en) * | 2003-12-03 | 2007-03-15 | Advanced Chip Engineering Technology Inc. | Fan out type wafer level package structure and method of the same |
CN203491244U (en) * | 2013-09-26 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure |
CN103985695A (en) * | 2014-05-19 | 2014-08-13 | 中国科学院微电子研究所 | Fan-out type packaging structure and manufacturing process thereof |
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070059866A1 (en) * | 2003-12-03 | 2007-03-15 | Advanced Chip Engineering Technology Inc. | Fan out type wafer level package structure and method of the same |
CN203491244U (en) * | 2013-09-26 | 2014-03-19 | 华进半导体封装先导技术研发中心有限公司 | Packaging structure |
CN103985695A (en) * | 2014-05-19 | 2014-08-13 | 中国科学院微电子研究所 | Fan-out type packaging structure and manufacturing process thereof |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105140189A (en) * | 2015-07-08 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | Board-level fan-out chip packaging device and preparation method thereof |
CN105140189B (en) * | 2015-07-08 | 2019-04-26 | 华进半导体封装先导技术研发中心有限公司 | Plate grade fan-out-type chip package device and preparation method thereof |
CN107785329A (en) * | 2016-08-30 | 2018-03-09 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
CN106783796A (en) * | 2016-12-07 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip-packaging structure and preparation method thereof |
CN106783796B (en) * | 2016-12-07 | 2019-04-26 | 华进半导体封装先导技术研发中心有限公司 | A kind of chip-packaging structure and preparation method thereof |
CN110459510A (en) * | 2019-08-08 | 2019-11-15 | 广东芯华微电子技术有限公司 | Big plate fan-out-type two-sided antenna encapsulating structure and preparation method thereof |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180530 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Institute of Microelectronics of the Chinese Academy of Sciences Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: National Center for Advanced Packaging Co.,Ltd. Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180712 Address after: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee after: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180816 Address after: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee after: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Beijing Zhongke micro Investment Management Co.,Ltd. Effective date of registration: 20180816 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Beijing Zhongke micro Investment Management Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences Effective date of registration: 20180816 Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Patentee after: Institute of Microelectronics of the Chinese Academy of Sciences Address before: 221000 the east side of Gaoxin Road, Xuzhou economic and Technological Development Zone, Jiangsu, and the south side of Chuang Chuang road. Patentee before: JIANGSU ZHONGKE ZHIXIN INTEGRATION TECHNOLOGY Co.,Ltd. |
|
TR01 | Transfer of patent right |