CN203491244U - Packaging structure - Google Patents

Packaging structure Download PDF

Info

Publication number
CN203491244U
CN203491244U CN201320598271.2U CN201320598271U CN203491244U CN 203491244 U CN203491244 U CN 203491244U CN 201320598271 U CN201320598271 U CN 201320598271U CN 203491244 U CN203491244 U CN 203491244U
Authority
CN
China
Prior art keywords
chip
organic substrate
interarea
utility
model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN201320598271.2U
Other languages
Chinese (zh)
Inventor
郭学平
于中尧
谢慧琴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN201320598271.2U priority Critical patent/CN203491244U/en
Application granted granted Critical
Publication of CN203491244U publication Critical patent/CN203491244U/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Wire Bonding (AREA)

Abstract

The utility model discloses a packaging structure comprising an organic substrate, a chip, a chip support plate, external pins, internal wires and solder mask layers. A metal groove is formed on the first main surface of the organic substrate, the chip is disposed inside the metal groove, the chip support plate is arranged on the end surface of the chip and on the first main surface, the external pins are arranged on one side of the second main surface of the organic substrate, the internal wires are electrically connected with corresponding connecting pads of the chip and the corresponding external pins, the internal wires extend and penetrate the organic substrate, and the solder mask layers are arranged on one side of the second main surface of the organic substrate and obstruct the internal wires. According to the utility model, the packaging is achieved via a substrate manufacturing technology and the packaging is totally compatible with the substrate manufacturing technology, problems expected in later mass production are solved via the packaging technology at a certain degree, and industrialization of the packaging technology is further promoted.

Description

A kind of encapsulating structure
Technical field
The utility model relates to semiconductor packages field, relates in particular to a kind of encapsulating structure based on organic substrate technology.
Background technology
Along with the development of information technology, mobile phone and various electronic product are more and more to compact future development, and the performance of portable computer is more and more higher, and it is more and more less that volume becomes, and to the integrated level of chip and device, require also more and more higher.Along with development and the innovation of large scale integrated circuit, live width has approached 22 nanometers, and integrated level reaches unprecedented level.Requirement for technology and equipment has also reached a new high.The difficulty that live width further diminishes is increasing, and the lifting difficulty of the working ability of technology and equipment is larger, and the development of technology and equipment level is tending towards slowing down.
In this case, 3D high-density packages is paid attention to by industrial circle widely, and the chip in a device is no longer one, but a plurality of, and is no longer only at one deck, to arrange, but is stacked into the micro-assembling chip of three-dimensional high-density.The three-dimensional stacked effective three-dimensional dimension that reduces device of chip, the stack manner of chip chamber is also in continuous improvement.From FLIP CHIP to silica-based TSV(Through Silicon Via) through hole interconnection technique, the three-dimensional dimension of device becomes more and more less.Packaging technology is also from original bonding, paster, plastic packaging, develops into RDL, Flip Chip, wafer bonding, TSV etc. the key process technology of introducing FEOL, and more chip density encapsulating structure larger, that size is less is continued to bring out.
In the manufacture method of existing circuit board and organic base plate for packaging, in the application of metal loading plate, there is the problem incompatible with organic substrate technique, and high cost, each road processing technology difficulty is very large, and crudy is not high, and stability is very poor.
Utility model content
The object of this part is to summarize some aspects of embodiment of the present utility model and briefly introduces some preferred embodiments.In this part and the application's specification digest and utility model title, may do a little simplification or omit to avoid the making object of this part, specification digest and utility model title fuzzy, and this simplification or omit can not be for limiting scope of the present utility model.
Problem in view of existing in above-mentioned and/or existing semiconductor packages, has proposed the utility model.
Therefore, the purpose of this utility model is to provide a kind of novel package structure, and this encapsulating structure can be realized its circuit board level output (panel level fan-out) encapsulation, can be completely compatible mutually with substrate process technology.
For solving the problems of the technologies described above, the utility model provides following technical scheme: a kind of encapsulating structure, comprise, and organic substrate, described organic substrate has the first interarea and the second interarea, on the first interarea of described organic substrate, is formed with metallic channel; Chip, it is arranged in described metallic channel, and it has end face and the another side relative with described end face, and described chip includes the some connection pads that are positioned at the another side relative with described end face; Chip support plate, described chip support plate is arranged on the end face and described the first interarea of described chip; Be formed at the external terminal of the second interarea one side of described organic substrate; With the interconnector that corresponding connection pad and the corresponding external terminal of described chip are electrically connected, described interconnector extends through described organic substrate; Be positioned at the solder mask of each interconnector of obstruct of the second interarea one side of described organic substrate.
As a kind of preferred version of encapsulating structure described in the utility model, wherein: the thickness of described chip support plate is 10 μ m～100 μ m.
As a kind of preferred version of encapsulating structure described in the utility model, wherein: described chip is arranged in described metallic channel, the end face of described chip and described the first interarea are in same level.
The utility model is the circuit board level output encapsulating structure that the Manufacturing Techniques based on organic substrate is carried out, with respect to based on wafer process, carry out the encapsulation of wafer scale output main advantage have following some:
(1) this encapsulating structure based on the technique of organic substrate with respect to wafer scale technique, to equipment and environment etc., require lower, the price of material has very large advantage, so its price advantage of output technique based on organic substrate is obvious, is more suitable in large-scale production;
(2) in this technical scheme of manufacturing process, the mechanical stress problems such as warpage of whole module are had more to advantage;
(3) technique with respect to this technical scheme the traditional output based on organic substrate (fan-out) technology is the conventional technique in its organic substrate manufacturing technology, is more adapted to this technology in popularization and the scale of mass production of substrate volume production manufacturer.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1～Figure 11 is the schematic diagram of the product that obtains of each step of a kind of packaging technology based on organic substrate technology described in the utility model;
Figure 12 is the generalized section of the encapsulating structure of the packaging technology making based on organic substrate technology described in the utility model;
Figure 13 is the packaging technology based on organic substrate technology in the utility model schematic flow sheet in one embodiment.
Embodiment
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail.
A lot of details have been set forth in the following description so that fully understand the utility model, but the utility model can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization without prejudice to the utility model intension in the situation that, so the utility model is not subject to the restriction of following public specific embodiment.
Secondly, the utility model is described in detail in conjunction with schematic diagram, when the utility model embodiment is described in detail in detail; for ease of explanation; the profile that represents device architecture can be disobeyed general ratio and be done local amplification, and described schematic diagram is example, and it should not limit the scope of the utility model protection at this.The three-dimensional space that should comprise in addition, length, width and the degree of depth in actual fabrication.
The utility model proposes a kind of packaging technology 700 based on organic substrate technology, please refer to shown in Figure 13, this packaging technology comprises the steps.
Step 710, first needs to provide an organic substrate, and this organic substrate has the first interarea and the second interarea.
Concrete, described organic substrate comprises organic layer and clamps the first interarea side that lays respectively at described organic layer of described organic layer and two metal levels of the second interarea side.
In one embodiment, for example, if the metal layer thickness on organic substrate is enough,, the thickness of described metal level is greater than the thickness sum of chip thickness and Heraeus, so, can directly in described organic substrate the first interarea one side, form metallic channel, with packaged chip.As shown in Figure 3.
In another embodiment, if the metal layer thickness on organic substrate is not enough to form metallic channel to encapsulate described chip, so, as shown in Figure 1, the organic substrate adopting in the present embodiment can be the double face copper of double-sided copper-clad core (Core) plate or prepreg and Copper Foil pressing formation.Described organic substrate comprises the first interarea S1 and the second interarea S2.Then, referring to Fig. 2, Fig. 2 is for carrying out two-sided electric plating of whole board to the double face copper of double-sided copper-clad core (Core) plate or prepreg and Copper Foil pressing formation, and the thickness of plating is greater than chip thickness, and requires to have reasonable uniformity.When the mode that adopts the upside-down mounting of some glue to paste chip is carried out the encapsulation of chip, the thickness of plating is greater than the thickness sum of chip thickness and Heraeus.As depicted in figs. 1 and 2, Fig. 2 is with respect to Fig. 1, and the first interarea S1 and the second interarea S2 of described organic substrate increase after process for copper, cover copper layer and obviously thicken.
Step 720, forms metallic channel at organic substrate the first interarea, as shown in Figure 3.Conventionally, to electroplating the copper-clad plate increasing after metal, carry out the etching of pad pasting exposure imaging, form the metallic channel 100 of pasting chip, the shape requirement of metallic channel 100 is met to the paster requirement of chip, the size that is described metallic channel 100 all adapts with the size of chip to be packaged, and the length and width of metallic channel length and width high and chip are high matches.
Step 730, shown in Fig. 3 and Fig. 4, is installed on described chip 200 in described metallic channel 100, and this chip 200 has end face M, and is provided with connection pad 201 in the opposite of described end face M.Concrete, chip 200 is pasted in the upside-down mounting of some glue, requires the glue 202 of pasting chip 200 to be all filled in metallic channel 100, and flattens processing, requiring chip 200 end face M is more smooth planes, and the end face M of described chip 200 and described the first interarea S1 are in same level.
Step 740 shown in Fig. 5, forms chip support plate 300 on the end face M of described chip 200 and described the first interarea S1.
Concrete, justifying copper to be electroplated and formed chip support plate 300, chip support plate 300 thickness General Requirements are within 10 μ m～100 μ m scopes.
Step 750, form to connect the package pins of connection pad 201 of the relative side of end face M of chip 200 in the second interarea one side of organic substrate.
Fig. 6～Figure 11 shows a specific embodiment of described package pins formation method.The formation method of described package pins comprises:
Step 1, shown in Fig. 6, by the chip of double face copper 200 opposites, the copper of the second interarea S2 carries out etching and is thinned to 3 about μ m, and the face copper of chip 200 end face M is protected.
Step 2, as shown in Figure 7, carries out the making of blind hole 400 from described the second interarea S2, make several blind holes 400, and described blind hole 400 aligns and extend to described connection pad 201 with the pad 201 that is connected on described chip 200 by the mode of boring.
Step 3, shown in Fig. 8, electroplates the filling perforation of described the second full plate of interarea S2ization copper and described blind hole 400.
Step 4, in conjunction with shown in 9, carry out the graphic making of outer-layer circuit layer.
Step 5, in conjunction with shown in Figure 10, carry out the welding resistance of outer-layer circuit layer and process.Concrete, the green oil welding resistance of application organic substrate is windowed and is carried out anti-welding resistance processing and top layer coating processing outer-layer circuit and BGA Package weld pad (BGA pad), forms solder mask 500.
Step 6, last, as shown in figure 11, at the peripheral interface face of output, plant I/O soldered ball 600(and also can be referred to as external terminal 600).
The described package pins of the common formation of metal inside line in described external terminal 600 and described blind hole, this package pins can be electrical connected connection pad and the external electronic of described chip.
The encapsulating structure of making by above-mentioned technique, as shown in figure 12, organic substrate, chip 200, chip support plate 300, external terminal, interconnector and solder mask 500 have been comprised, chip 200 is arranged in the metallic channel (not shown) of organic substrate the first interarea formation, it has end face and the another side relative with described end face, and described chip 200 includes the some connection pads 201 that are positioned at the another side relative with described end face; Chip support plate 300 is arranged on the end face and described the first interarea of chip 200, and the thickness of chip support plate 300 is 10 μ m～100 μ m; Described external terminal 600 is formed at the second interarea one side of described organic substrate; And the interconnector being electrically connected with corresponding connection pad 201 and the corresponding external terminal of described chip 200 extends through described organic substrate; Described solder mask 500 is between each interconnector of the second interarea one side of described organic substrate.
It should be noted that, above embodiment is only unrestricted in order to the technical solution of the utility model to be described, although the utility model is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify or be equal to replacement the technical solution of the utility model, and not departing from the spirit and scope of technical solutions of the utility model, it all should be encompassed in the middle of claim scope of the present utility model.

Claims (3)

1. an encapsulating structure, is characterized in that: comprises,
Organic substrate, described organic substrate has the first interarea and the second interarea, on the first interarea of described organic substrate, is formed with metallic channel;
Chip, it is arranged in described metallic channel, and it has end face and the another side relative with described end face, and described chip includes the some connection pads that are positioned at the another side relative with described end face;
Chip support plate, described chip support plate is arranged on the end face and described the first interarea of described chip;
Be formed at the external terminal of the second interarea one side of described organic substrate;
With the interconnector that corresponding connection pad and the corresponding external terminal of described chip are electrically connected, described interconnector extends through described organic substrate;
Be positioned at the solder mask of each interconnector of obstruct of the second interarea one side of described organic substrate.
2. encapsulating structure according to claim 1, is characterized in that: the thickness of described chip support plate is 10 μ m～100 μ m.
3. encapsulating structure according to claim 1, is characterized in that: described chip is arranged in described metallic channel, and the end face of described chip and described the first interarea are in same level.
CN201320598271.2U 2013-09-26 2013-09-26 Packaging structure Expired - Lifetime CN203491244U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201320598271.2U CN203491244U (en) 2013-09-26 2013-09-26 Packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201320598271.2U CN203491244U (en) 2013-09-26 2013-09-26 Packaging structure

Publications (1)

Publication Number Publication Date
CN203491244U true CN203491244U (en) 2014-03-19

Family

ID=50262054

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201320598271.2U Expired - Lifetime CN203491244U (en) 2013-09-26 2013-09-26 Packaging structure

Country Status (1)

Country Link
CN (1) CN203491244U (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474363A (en) * 2013-09-26 2013-12-25 华进半导体封装先导技术研发中心有限公司 Packaging technology based on organic substrate technology and packaging structure
CN104241153A (en) * 2014-09-16 2014-12-24 中国科学院微电子研究所 Packaging method for board level fan-out structures
CN105140189A (en) * 2015-07-08 2015-12-09 华进半导体封装先导技术研发中心有限公司 Board-level fan-out chip packaging device and preparation method thereof
CN104241153B (en) * 2014-09-16 2017-01-04 中国科学院微电子研究所 The method for packing of plate level fan-out-type structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103474363A (en) * 2013-09-26 2013-12-25 华进半导体封装先导技术研发中心有限公司 Packaging technology based on organic substrate technology and packaging structure
CN103474363B (en) * 2013-09-26 2016-09-21 华进半导体封装先导技术研发中心有限公司 A kind of packaging technology based on organic substrate technology and encapsulating structure
CN104241153A (en) * 2014-09-16 2014-12-24 中国科学院微电子研究所 Packaging method for board level fan-out structures
CN104241153B (en) * 2014-09-16 2017-01-04 中国科学院微电子研究所 The method for packing of plate level fan-out-type structure
CN105140189A (en) * 2015-07-08 2015-12-09 华进半导体封装先导技术研发中心有限公司 Board-level fan-out chip packaging device and preparation method thereof
CN105140189B (en) * 2015-07-08 2019-04-26 华进半导体封装先导技术研发中心有限公司 Plate grade fan-out-type chip package device and preparation method thereof

Similar Documents

Publication Publication Date Title
CN103474361B (en) A kind of embedded active packaging process and encapsulation structure imbedding function substrate
CN102386104B (en) Quadrilateral flat pin-free encapsulation method
CN104952828A (en) Flip chip package on package structure and method for fabricating the same
KR20090055316A (en) Semiconductor package and electronic device, and method for manufacturing semiconductor package
CN103779235A (en) Fan-out wafer level package structure
CN104769713A (en) Semiconductor device including independent film layer for embedding and/or spacing semiconductor die
CN107646141A (en) The integrated circuit structure with depression electrically conducting contact for stacked package
CN105304584B (en) Interposer substrate and method of manufacturing the same
CN103985695B (en) A kind of fan-out package structure and its manufacture craft
TW201301463A (en) Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
CN102386105B (en) Four limit flat non-connection pin method for packing and the structure made thereof
CN105489565B (en) Package structure of embedded device and method for fabricating the same
CN105514053B (en) Semiconductor package and fabrication method thereof
CN102403275A (en) Package on package structure and fabricating method for same
CN108962840A (en) Electronic package and manufacturing method thereof
CN206179848U (en) PoP stacked package structure
CN103227164A (en) Semiconductor package structure and manufacturing method thereof
CN208655635U (en) Stack embedded packaging structure
CN102299081B (en) Method for manufacturing packaging substrate and packaging substrate
CN203491244U (en) Packaging structure
CN107845610B (en) Board structure and preparation method thereof
CN112928035A (en) Board-level flip chip packaging structure with electromagnetic shielding function and preparation method thereof
CN103474363B (en) A kind of packaging technology based on organic substrate technology and encapsulating structure
CN101211792A (en) Semi-conductor package and its manufacture method and stacking structure
CN115513168A (en) Packaging structure, preparation method of packaging structure and electronic equipment

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20140319