CN105140189B - Plate grade fan-out-type chip package device and preparation method thereof - Google Patents

Plate grade fan-out-type chip package device and preparation method thereof Download PDF

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Publication number
CN105140189B
CN105140189B CN201510398269.4A CN201510398269A CN105140189B CN 105140189 B CN105140189 B CN 105140189B CN 201510398269 A CN201510398269 A CN 201510398269A CN 105140189 B CN105140189 B CN 105140189B
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chip
recessed
loading plate
fan
dielectric layer
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CN105140189A (en
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郭学平
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Guangdong Fozhixin Microelectronics Technology Research Co ltd
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National Center for Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

Embodiments of the present invention are related to plate grade fan-out-type chip package device and preparation method thereof.Recessed in the one side setting of the loading plate for carrying chip, the size of the recessed size and chip back matches, then by chip attachment in the recessed position.When by chip attachment to loading plate, the recessed proper back side for accommodating chip on loading plate, so that chip to be packaged is kept to be more easier and facilitate in place.According to the present invention, fan-out package is obviated to the breadth of chip mounter and the dependence of patch precision, and the fan-out-type chip package process for making it possible to carry out large format is carried out.

Description

Plate grade fan-out-type chip package device and preparation method thereof
Technical field
The present invention relates to the technical fields of chip package, more specifically, are related to fan-out-type chip package device and its system Preparation Method.
Background technique
With the continuous development of information technology and semiconductor technology, the electronic equipments such as mobile phone, PAD, smartwatch are gradually in The trend that existing lightness and function mutually merge.This is higher and higher to the integrated level requirement of chip, and then to the packaging belt of chip Carry out unprecedented challenge.The various chips with different function are added and same in the mismatch of ever-increasing interconnection spacing It has been innovation insertion encapsulation skill that package dimension is reduced under the area occupied of sample to increase battery sizes to extend using time etc. Art opens window.
The exploitation of 3D through silicon via (TSV) technology is benefited from, fan-out-type wafer-level packaging (FOWLP) is presently considered to be most suitable for Movement/wireless market of high request, and to the market of other concern high-performance and small size, it may have very strong attraction. Fan-out-type wafer-level packaging is the embedded encapsulation of wafer level processing, it does not have to substrate and realizes vertical and water in a package Square to multi-chip it is integrated.
In the fan-out-type wafer-level packaging of current mainstream, chip is surrounded by suitable material, these materials will encapsulate institute Area is accounted for expand to other than chip.Chip wafer scale flip-clip is embedded in synthetic plastic wafer (recombination wafer).Then it uses Preceding road insulation and metallization process, are fanned out to peripheral region for interconnection with wafer scale photoetching and drafting method.Again on wafer Using soldered ball and carry out concurrent testing.Then recombination wafer is cut into separate unit, is packed and is shipped.However, utilizing This heat management performance based on chip package device made by the fan-out package of plastic packaging mode on the basis of wafer process has Very big limitation, in addition process aspect is also to have the deficiencies of at high cost, complex process, so resulting at high cost and performance not The defects of high.
The CN of the public patent application 104241153A of inventor discloses a kind of chip package of plate grade fan-out-type structure Method solves the warpage etc. that the fan-out-type wafer-level packaging of chip is easy to appear in the fabrication process to a certain extent and asks Topic, and manufacture efficiency is improved.As disclosed in the patent application, the chip packaging method of plate grade fan-out-type structure It needs chip attachment on loading plate (such as copper foil).And in actual production, the face of equal wide cut on one in length and breadth direction Multiple chips are encapsulated simultaneously on plate, form the cutter unit of multiple chip packages.However, current many chip mounters (DB equipment) are no It can satisfy the continuous increase and the higher and higher demand of required precision of present plate grade size, which has limited the further of the technology The reduction of development and cost.
Summary of the invention
In view of this, an object of the present invention aims to solve the problem that the plate grade fan-out-type chip package process process in large format In patch problem.
According to one embodiment of the present invention, a kind of plate grade fan-out-type chip package device is provided.The plate grade fan-out-type core Piece packaging includes: loading plate, be provided with it is recessed, the recessed size be suitable for accommodate chip；Chip, the back side are logical Cross adhesive be mounted on the loading plate it is described it is recessed in；And in the recessed side of the loading plate, arrangement Dielectric layer on the loading plate and the chip.By pressing the loading plate and the dielectric layer, so that institute The material for stating dielectric layer can be filled into the gap between the recessed and described chip of the loading plate.
Another embodiment according to the present invention provides a kind of preparation method of plate grade fan-out-type chip package device, should Include: offer loading plate, be provided on the loading plate it is recessed, the recessed size be suitable for accommodate chip；Utilize adhesive By the attachment of the back side of the chip and the loading plate it is described it is recessed in；In the recessed side of the loading plate, in institute It states and arranges dielectric layer on loading plate and the chip；And by pressing the loading plate and the dielectric layer, so that The material of the dielectric layer can be filled into the gap between the recessed and described chip of the loading plate.
Embodiment according to the present invention provides a kind of method of patch artoregistration, obviate patch precision etc. for The dependence of patch device, to obviate dependence of the breadth for chip mounter of plate grade, the fan-out-type suitable for large format is sealed Dress technique.In addition, it is poor for the heat management performance of the fan-out package of traditional technique, so embodiments of the present invention The heat dissipation performance of chip will be greatly enhanced in the back side attachment to the metal backing of high thermal conductivity of chip, mention The high whole performance of chip.In addition, the technique of embodiment of the present invention is mainly based upon the process route of encapsulating carrier plate, energy It is enough adapted to the technique of substrate, further reduced on the basis of technique cost of manufacture and also improve the performance of device.
According to the described in detail below of this specification in conjunction with attached drawing, these and other of the various embodiments of the present invention are excellent Point and feature all will be apparent.
Detailed description of the invention
Fig. 1-Fig. 9 shows the step cross section to form the grade chip packaging device of plate according to one embodiment of the present invention Figure.
Specific embodiment
Present disclosure is described in more detail below hereinafter with reference to attached drawing, wherein showing the reality of present disclosure in the accompanying drawings Apply mode.But these embodiments can be realized with many different forms and be should not be construed as being limited to described herein Embodiment.On the contrary, provide these examples so that present disclosure will be thorough and complete, and will comprehensively to Those skilled in the art expression scope of the present disclosure.Although it should be noted that be described below one it is relatively complete The manufacture craft of whole chip package device, but the processing step wherein having is embodiment party that is optional, and there is replacement Formula.
Through present disclosure, similar appended drawing reference indicates similar element.For example, appended drawing reference 10 is also possible to Indicate the appended drawing reference 1003,1004,1008,1009 etc. with different suffix.
The core idea of embodiment of the present invention includes: to be set on one side for carrying the loading plate of chip when encapsulating chip Set recessed, the size matching of the recessed size and chip back；Then by chip attachment in the recessed position.In this way, When by chip attachment to loading plate, the recessed proper back side for accommodating chip on loading plate, so that keeping chip to be packaged It is more easier and facilitates in place.Hereby it is achieved that the chip artoregistration in pasting chip, obviates patch precision etc. for patch The dependence of piece equipment makes it possible to carry out the fan of large format to obviate dependence of the breadth for chip mounter of plate grade Type packaging technology is carried out out.In addition, embodiment according to the present invention, recessed loading plate is arranged can be by the material of high-termal conductivity Material is made, and the heat dissipation problem of chip is made to be improved to a certain extent.
Process flow for manufacturing plate grade fan-out-type chip package device 10 is described below with reference to Fig. 1-Fig. 9.Fig. 1- Fig. 9 shows the step cross-sectional view to form the chip packaging device of embodiment according to the present invention.
In fig. 1 and 2, the first step of the process flow is executed, the loading plate 51 and core that are used for pasting chip are prepared Piece 71.Loading plate 50 is equipped with recessed 52, and being recessed 52 has the size to match with the back side of chip 71.
In Fig. 1 and example shown in Fig. 2, it is trapezoidal be recessed that the loading plate 51 of chip attachment, which has a cross section, 52.Can be identical as the angle on inclined-plane 78 that the back side of chip 71 makes in the angle of trapezoidal recessed 52 bevel edge, and it is most The size of bottom can be small with the size of chip 71, so as to enable chip automatic during carrying out chip attachment Contraposition to its accurate position.
In Fig. 1 and example shown in Fig. 2, recessed 52 cross section be it is trapezoidal, the cross section of chip 71 be rectangle simultaneously And chamfering 78 is waited in side, but it is to be understood that embodiment according to the present invention, recessed 72 cross section are also possible to rectangle Or other polygons.Those skilled in the art will become apparent from as a result, and recessed 73 shape such as can be rotary table, rectangular Body etc., the present invention to recessed shape with no restrictions.Those skilled in the art also will become apparent from, and the cross section of chip 71 is also possible to Rectangle, the proper shapes such as trapezoidal without chamfering, as long as its back side and recessed 52 sizes match.
Embodiment according to the present invention, loading plate 51 can be by having the characteristics that high-termal conductivity and material easy to process Material is made, such as metal or resin (for example, BT resin) material of high-termal conductivity etc..Embodiment according to the present invention, carrying Being recessed in plate 51 can be formed by techniques such as machining, laser processing, chemical etchings.
Although Fig. 1 illustrate only loading plate 51 a part and thereon recessed 52, but it is to be understood that loading plate 51 can To be the loading plate of large format on direction in length and breadth, and can have multiple recessed 52 thereon, for once mounting multiple chips 71.
In figs. 3 and 4, the attachment of chip 71 is arrived carrying using adhesive 81 by the second step for executing the process flow In recessed the 52 of plate 51, and dielectric layer pressing is carried out using the positive dielectric layer 82 for being arranged in chip 71.
In the example depicted in fig. 3, the attachment for carrying out chip 71 carries out chip using the TIM material 81 of high-termal conductivity Attachment, during carrying out patch, the upper sufficient adhesive of point first in recessed the 52 of loading plate, then application can be propped up The chip mounter for supportting big plate carries out patch.
According to embodiment of the present invention, adhesive 81 can make it possible to for liquid since mobility is relatively good More smoothly meet position adjustment when its chip carries out artoregistration.
In the example depicted in fig. 4, the pressing for carrying out dielectric layer 81 carries out chip using high temperature press or vacuum press The pressing of dielectric layer above 71, so that chip 71 is embedded into loading plate 51 and dielectric layer 81.
In the example depicted in fig. 4, dielectric layer 81 can use layer of prepreg (PP piece).Prepreg mostly uses greatly Glass fabric does reinforcing material, and treated glass fabric impregnates upper resin adhesive liquid, then made of thermally treated preliminary drying Sheeting is known as prepreg, can soften under heating pressurization, can react solidification after cooling.Dielectric layer also can be used The ABF resin layer of pure colloid, FR resin etc..Specifically used dielectric layer can be needed according to application and be selected.
In Fig. 3 and example shown in Fig. 4, the lamination of dielectric layer is carried out using high temperature press or vacuum film pressing machine, is made Be filled the peripheral clearance 58 of chip with dielectric layers such as the prepreg of its attachment and ABF, FR, in turn, It being capable of the chip 71 of stabilization package therebetween after cooling and solidifying.
In Fig. 3 and example shown in Fig. 4, chip 71 is partially embedded into recessed the 52 of loading plate 51, but should be managed Solution, chip 71 can also be fully inserted into this in attachment and be recessed in 52.The feelings in recessed 52 are fully inserted into chip 71 Under shape, as previously mentioned, by the pressing of dielectric layer, it is also possible that being embedded into the chip in loading plate 51 and dielectric layer 81 71 keep stablizing.
In Fig. 5, execute the third step of the process flow, be related to the chip-packaging structure 1004 currently formed just The operation in face carries out the drilling production of blind hole 74 in the front of chip 71, and the metal that made blind hole 74 is directed at chip 71 is convex Point 72, and pass through dielectric layer 81 and reach metal salient point 72.The mode of machine drilling or laser drill can be used in chip 71 front production blind hole.
According to embodiment of the present invention, blind hole 74 can end on the metal salient point of chip or be embedded into metal 1-5 μm in salient point, under this situation, the metal salient point on chip requires thickness at least at 10 μm.
In figure 6 and figure 7, the four steps for executing the process flow is related in the chip-packaging structure currently formed 1005 positive operation, metalized blind vias 74 form surface lines metal in the front of the chip-packaging structure currently formed Layer 54, and fan-out circuit production is carried out in the front of the chip-packaging structure currently formed, form metallic circuit pattern 55.
As shown in fig. 6, progress plates one layer of seed layer, such as chemistry in blind hole 74 in the front of encapsulating structure 1005 Copper facing, and the electroplating technology for carrying out blind hole carries out filling out copper in blind hole, is formed through copper-plated blind hole 75, then forms surface lines copper Layer 55, so that the I/O of chip is drawn out on the route of outer layer.
As shown in fig. 7, carrying out the production of fan-out circuit 55 in the front of chip-packaging structure 1006.The production of fan-out circuit It can be carried out using techniques such as exposure, development, etchings, be fanned out to sandwich circuit 55 so as to form what is drawn outside chip.
In fig. 8, the 5th step for executing the process flow, be related to the chip-packaging structure 1007 currently formed just The operation in face makes solder mask 56.
In the example depicted in fig. 8, one layer of solder mask 56, such as welding resistance green oil are made on the fan-out circuit of formation, Prevent the oxidation of route.Then, multiple windowings are carried out on solder mask 56, and it is (golden under salient point that UBM is made on multiple windowing Categoryization) layer, being formed, which can be used for, plants the pad 57 of ball grid array (BGA) soldered ball in subsequent step.
In Fig. 9, execute the 6th step of the process flow, be related to the chip-packaging structure 1008 currently formed just BGA ball 59 is planted in the operation in face on the pad 57 that the 5th step is formed.
Through the above steps, the preferred plate grade fan-out-type chip-packaging structure of embodiment according to the present invention is formed.It answers Work as understanding, although carrying the foregoing describe by an attachment of chip 71 and one recessed 52 process on loading plate 51 Plate 51 can have multiple recessed, and embodiments of the present invention are suitable for once by multiple chip attachment on the loading plate It is multiple it is recessed in.
It should be noted that embodiments of the present invention are notably directed to the operation of chip back, and involved in above description The sequence of maneuvers for finally plant BGA ball of chip front side, is that plate grade fan-out package structure is installed to pcb board for subsequent And the operation that is electrically connected of the fan-out package structure with pcb board is carried out, skilled artisans appreciate that other equivalent realities The mode of applying is also possible.
To the preparation method packet of plate grade fan-out-type chip package device provided by embodiment according to the present invention It includes: loading plate is provided, be provided with recessed, recessed size and be suitable for accommodating chip；The back side of chip is pasted using adhesive Dress and loading plate it is recessed in；Dielectric layer is arranged in the recessed side of loading plate, on loading plate and chip；And pass through Loading plate and dielectric layer are pressed, the material of dielectric layer is enabled to be filled into the recessed gap between chip of loading plate In.
The structure of the chip packaging device 10 of embodiment obtains in the introduction of process above process according to the present invention To embody, such as its cross section shown in Fig. 9 Fig. 3-.As shown in figure 4, plate grade fan-out-type chip package device 1004 includes: to hold Support plate is provided with recessed, recessed size and is suitable for accommodating chip；Chip, the back side are mounted on carrying by adhesive Plate it is recessed in；And the recessed side of loading plate, be arranged in loading plate and chip on dielectric layer.Pass through pressing Loading plate and dielectric layer enable the material of dielectric layer to be filled into the recessed gap between chip of loading plate.
The Heterosis of embodiment of the present invention exists:
(1) it due to obviating dependence of the patch precision of the pasting chip on panel for patch device, thus can fit For the application of arbitrary big small panel, it will not be limited by the technology acuracy of sealed in unit, and its process costs is relatively low.Face The increase of plate can largely reduce the cost being packaged to chip.
(2) since the loading plate of chip back attachment can select the material of high-termal conductivity, to solve to a certain extent The problem of heat dissipation of high-power component, improve the heat management performance of chip-packaging structure.
(3) then blind by changing copper plating due to being embedded into encapsulation by the way of metal salient point for encapsulation chip The mode in hole is fanned out to, and can be good at the yield and reliability that control resulting chip-packaging structure in this way.
(4) carried out using the technique based on encapsulating carrier plate, the technique for making it possible to be adapted to substrate further reduced work Skill cost of manufacture also improves the performance of device.
The those skilled in the art for benefiting from the introduction provided in aforementioned specification and associated drawings will be easy Expect many improvement and other embodiments of present disclosure.It is understood, therefore, that the foregoing is merely a prefered embodiment of the invention , it is not intended to limit the invention, all within the spirits and principles of the present invention, made any modification, equivalent replacement etc., It should all be included in the protection scope of the present invention.

Claims (8)

1. a kind of plate grade fan-out-type chip package device (1004), comprising:
Loading plate (51) is provided with recessed (52), and the size of recessed (52) is suitable for accommodating chip；
Chip (71), the back side is mounted in recessed (52) of the loading plate (51) by adhesive (81), described The cross section of recessed (52) of loading plate (51) is trapezoidal, and the back side of the chip (71) is provided with chamfering (78), The gradient of the chamfering is identical as the trapezoidal gradient, the back of the size of the bottom of recessed (52) than the chip (71) The size in face is small；And
Described recessed (52) side of the loading plate (51), be arranged in the loading plate (51) and the chip (71) it On dielectric layer (82),
Wherein, by pressing the loading plate (51) and the dielectric layer (82), enable the material of the dielectric layer It is filled into the gap between recessed (52) of the loading plate (51) and the chip (71).
2. plate grade fan-out-type chip package device according to claim 1, wherein the loading plate (51) is described recessed (52) size of bottom is more slightly smaller than the size at the back side of the chip (71).
3. plate grade fan-out-type chip package device according to claim 1 or 2, further includes:
It is formed in setting on positive, the described dielectric layer (82) of structure for the chip (71) and the loading plate (51) Fan-out circuit layer (55).
4. plate grade fan-out-type chip package device according to claim 3, wherein forming fan-out circuit layer (55) packet It includes:
In the dielectric layer (82), blind hole (74) corresponding with metal salient point (72) of the chip is prepared, to described blind Hole carries out electroless copper and electroplating processes and forms the fan-out circuit layer (80) on the dielectric layer (82).
5. a kind of preparation method of plate grade fan-out-type chip package device, comprising:
It provides loading plate (51), is provided with recessed (52) on the loading plate (51), the size of recessed (52) is suitable for accommodating The cross section of chip (71), recessed (52) of the loading plate (51) is trapezoidal, and the back side of the chip (71) is set It is equipped with chamfering (78), the gradient of the chamfering is identical as the trapezoidal gradient, and the size of the bottom of recessed (52) compares institute The size for stating the back side of chip (71) is small；
The back side of the chip (71) is mounted in recessed (52) of the loading plate (51) using adhesive (81)；
It is arranged in described recessed (52) side of the loading plate (51), on the loading plate (51) and the chip (71) Dielectric layer (82)；And
By pressing the loading plate (51) and the dielectric layer (82), the material of the dielectric layer is filled into In gap between recessed (52) of the loading plate (51) and the chip (71).
6. according to the method described in claim 5, the wherein size ratio of the bottom of recessed (52) of the loading plate (51) The size at the back side of the chip (71) is slightly smaller.
7. method according to claim 5 or 6, further includes:
It is formed in the front for setting structure of the chip (71) and the loading plate (51), on the dielectric layer (82) Fan-out circuit layer (55).
8. according to the method described in claim 7, wherein forming the fan-out circuit layer (55) and including:
In the dielectric layer (82), blind hole (74) corresponding with metal salient point (72) of the chip is prepared, to described blind Hole carries out electroless copper and electroplating processes and forms the fan-out circuit layer (80) on the dielectric layer (82).
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