TWI682692B - Fan-out semiconductor package and method of manufacturing the same - Google Patents

Fan-out semiconductor package and method of manufacturing the same Download PDF

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Publication number
TWI682692B
TWI682692B TW105114045A TW105114045A TWI682692B TW I682692 B TWI682692 B TW I682692B TW 105114045 A TW105114045 A TW 105114045A TW 105114045 A TW105114045 A TW 105114045A TW I682692 B TWI682692 B TW I682692B
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Taiwan
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layer
insulating layer
electronic component
redistribution
wiring layer
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TW105114045A
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Chinese (zh)
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TW201709777A (en
Inventor
朴大賢
金漢
許康憲
高永寬
沈正虎
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南韓商三星電子股份有限公司
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Publication of TW201709777A publication Critical patent/TW201709777A/en
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Publication of TWI682692B publication Critical patent/TWI682692B/en

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A fan-out semiconductor package and a method of manufacturing the same are provided. The fan-out semiconductor package includes a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad. The first connection member includes a first insulating layer, a first redistribution layer disposed on a surface of the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a second redistribution layer disposed on the second insulating layer, and the first and second redistribution layers are electrically connected to the connection pad.

Description

扇出半導體封裝及其製造方法 Fan-out semiconductor package and manufacturing method thereof [相關申請案的交叉參考] [Cross-reference to related applications]

本申請案主張於2015年5月11日在韓國智慧財產局提出申請的韓國專利申請案第10-2015-0065177號的優先權、於2015年10月5日在韓國智慧財產局提出申請的韓國專利申請案第10-2015-0139682號的優先權、及於2016年4月19日在韓國智慧財產局提出申請的韓國專利申請案第10-2016-0047455號的優先權，所述韓國專利申請案的揭露內容併入本案供參考。 This application claims the priority of Korean Patent Application No. 10-2015-0065177 filed with the Korean Intellectual Property Office on May 11, 2015, and South Korea filed with the Korean Intellectual Property Office on October 5, 2015 The priority of Patent Application No. 10-2015-0139682 and the priority of Korean Patent Application No. 10-2016-0047455 filed with the Korean Intellectual Property Office on April 19, 2016, said Korean Patent Application The disclosure content of the case is incorporated into this case for reference.

本發明是有關於一種扇出半導體封裝及其製造方法。 The invention relates to a fan-out semiconductor package and a manufacturing method thereof.

電子元件封裝被定義成用於將電子元件電性連接至例如電子裝置的主板等印刷電路板(printed circuit board，PCB)、並保護電子元件不受外部衝擊的封裝技術，並且與將電子元件嵌置於例如插板基板(interposer substrate)等印刷電路板中的嵌置技術有所區別。同時，與電子元件相關的技術發展中的當前主要趨勢之一是減小電子元件的尺寸。因而，在封裝領域中，且隨著對緊湊電子元件等的需求的快速增加，已經需要實作具有小的尺寸且 包括多個引腳的電子元件封裝。 Electronic component packaging is defined as a packaging technology for electrically connecting electronic components to a printed circuit board (PCB), such as a motherboard of an electronic device, and protecting the electronic components from external impacts, and to embed electronic components The embedding technology placed in a printed circuit board such as an interposer substrate is different. At the same time, one of the current main trends in the development of technology related to electronic components is to reduce the size of electronic components. Therefore, in the field of packaging, and with the rapid increase in demand for compact electronic components, etc., it has been required to implement a small size and Electronic component package including multiple pins.

為滿足上述技術需求，所建議的一種封裝技術為利用晶圓上所形成的電子元件的電極焊墊的重新分配配線的晶圓級封裝(wafer level package，WLP)。所述晶圓級封裝的實例包括扇入(fan-in)式晶圓級封裝及扇出(fan-out)式晶圓級封裝。具體而言，扇出式晶圓級封裝具有緊湊的尺寸且有利於實作多個引腳。因而，近來，扇出式晶圓級封裝已得到積極開發。 To meet the above technical requirements, a proposed packaging technology is a wafer level package (WLP) that utilizes redistribution wiring of electrode pads of electronic components formed on a wafer. Examples of the wafer-level packaging include fan-in wafer-level packaging and fan-out wafer-level packaging. Specifically, the fan-out wafer-level package has a compact size and facilitates the implementation of multiple pins. Therefore, recently, fan-out wafer-level packaging has been actively developed.

同時，由於晶圓級封裝的結構特性，因此重新分配部是在電子元件安置於晶圓上之後被固定。在此種情形中，在安置電子元件之後的製程中發生的缺陷會導致電子元件的良率降低。 At the same time, due to the structural characteristics of the wafer-level package, the redistribution section is fixed after the electronic components are placed on the wafer. In this case, defects that occur in the manufacturing process after the placement of the electronic component will cause the yield of the electronic component to decrease.

本發明的態樣可提供一種可解決電子元件的良率降低問題的電子元件封裝、其製造方法、及堆疊式封裝(package-on-package)結構。 The aspect of the present invention can provide an electronic component package, a manufacturing method thereof, and a package-on-package structure that can solve the problem of reducing the yield of electronic components.

根據本發明的態樣，可提供一種可在安置電子元件之前引入能夠執行電子元件的重新分配功能的配線層的新式封裝結構。 According to the aspect of the present invention, it is possible to provide a new packaging structure that can introduce a wiring layer capable of performing a redistribution function of an electronic component before placing the electronic component.

根據本發明的態樣，一種電子元件封裝可包括：框架，具有貫穿孔及一或多個第一配線層；電子元件，安置於所述框架的所述貫穿孔中；以及重新分配部，安置於所述框架及所述電子元件的一側上，其中所述一或多個第一配線層經由所述重新分配部而電性連接至所述電子元件。 According to an aspect of the present invention, an electronic component package may include: a frame having a through hole and one or more first wiring layers; an electronic component disposed in the through hole of the frame; and a redistribution portion, disposed On one side of the frame and the electronic component, the one or more first wiring layers are electrically connected to the electronic component via the redistribution portion.

根據本發明的另一態樣，一種電子元件封裝可包括：框架，包括第一絕緣層、安置於所述第一絕緣層下的二或更多個配線層、及安置於所述二或更多個配線層之間的第二絕緣層；電子元件，安置於穿透過所述框架的貫穿孔中；以及重新分配部，電性連接至所述二或更多個配線層及所述電子元件且安置於所述電子元件上，其中所述二或更多個配線層及所述第二絕緣層安置於所述重新分配部與所述第一絕緣層之間。 According to another aspect of the present invention, an electronic component package may include: a frame including a first insulating layer, two or more wiring layers disposed under the first insulating layer, and the two or more wiring layers A second insulating layer between a plurality of wiring layers; an electronic component, disposed in a through hole penetrating through the frame; and a redistribution portion, electrically connected to the two or more wiring layers and the electronic component And disposed on the electronic component, wherein the two or more wiring layers and the second insulating layer are disposed between the redistribution portion and the first insulating layer.

根據本發明的另一態樣，一種製造電子元件封裝的方法可包括：藉由製備第一絕緣層、在所述第一絕緣層的一側形成第一配線層、在所述第一絕緣層的一側形成其中嵌置有所述第一配線層的第二絕緣層、以及形成穿透過所述第一絕緣層及所述第二絕緣層的貫穿孔而形成框架；將電子元件安置於所述框架的所述貫穿孔中；以及在所述框架及所述電子元件的一側形成重新分配部，其中所述第一配線層是在所述電子元件的所述安置之前形成。 According to another aspect of the present invention, a method of manufacturing an electronic component package may include: by preparing a first insulating layer, forming a first wiring layer on one side of the first insulating layer, and forming the first insulating layer One side of which is formed a second insulating layer in which the first wiring layer is embedded, and a through hole penetrating through the first insulating layer and the second insulating layer is formed to form a frame; In the through hole of the frame; and a redistribution portion is formed on one side of the frame and the electronic component, wherein the first wiring layer is formed before the placement of the electronic component.

根據本發明的另一態樣，一種製造電子元件封裝的方法可包括：製備包括多個絕緣層及多個配線層的框架；形成穿透過整個所述框架的貫穿孔；將所述框架及電子元件貼附至臨時基板上，其中所述電子元件位於所述框架的所述貫穿孔內；藉由將囊封劑至少填充至所述框架的所述貫穿孔中而囊封所述電子元件；將所述臨時基板自所述框架的表面、所述囊封劑的表面及所述電子元件的表面分離；以及將重新分配部形成至所述框架的所述表面、所述囊封劑的所述表面及所述電子元件的所述表面上，且因 此所述重新分配部將所述電子元件電性連接至所述框架的所述多個配線層。 According to another aspect of the present invention, a method of manufacturing an electronic component package may include: preparing a frame including a plurality of insulating layers and a plurality of wiring layers; forming a through hole penetrating the entire frame; connecting the frame and the electronics The component is attached to the temporary substrate, wherein the electronic component is located in the through hole of the frame; the electronic component is encapsulated by filling at least the encapsulant into the through hole of the frame; Separating the temporary substrate from the surface of the frame, the surface of the encapsulant, and the surface of the electronic component; and forming a redistribution portion to the surface of the frame, the surface of the encapsulant On the surface and on the surface of the electronic component, and because The redistribution portion electrically connects the electronic component to the plurality of wiring layers of the frame.

100、100A、100B、100C、100D、100E、100F、100G、100H、100I、100J、100K、100L、100M、100N、100O、100P、100Q、100R、100S、100T‧‧‧電子元件封裝 100, 100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K, 100L, 100M, 100N, 100O, 100P, 100Q, 100R, 100S, 100T

110‧‧‧框架 110‧‧‧Frame

110A‧‧‧上表面 110A‧‧‧Top surface

110B‧‧‧下表面 110B‧‧‧Lower surface

110X、110X1、110X2、111Y‧‧‧貫穿孔 110X, 110X1, 110X2, 111Y‧‧‧through hole

111A‧‧‧第一絕緣層 111A‧‧‧First insulation layer

111B、111B1、111B2‧‧‧第二絕緣層 111B, 111B1, 111B2 ‧‧‧ second insulating layer

111C‧‧‧第三絕緣層 111C‧‧‧The third insulation layer

112、112A、112A1、112A2、112B‧‧‧第一配線層 112, 112A, 112A1, 112A2, 112B‧‧‧First wiring layer

113、113A、113A1、113A2、113B‧‧‧通孔 113, 113A, 113A1, 113A2, 113B

113Y‧‧‧通孔洞 113Y‧‧‧Through hole

115‧‧‧內部通孔 115‧‧‧Internal through hole

120、122、124‧‧‧電子元件 120、122、124‧‧‧Electronic components

120P、122P‧‧‧電極焊墊 120P, 122P‧‧‧ electrode pad

131‧‧‧第三配線層 131‧‧‧ Third wiring layer

132‧‧‧第二配線層 132‧‧‧Second wiring layer

135‧‧‧金屬層 135‧‧‧Metal layer

135A‧‧‧第一金屬層 135A‧‧‧First metal layer

135B‧‧‧第二金屬層 135B‧‧‧Second metal layer

140、150、155‧‧‧重新分配部 140, 150, 155‧‧‧ Redistribution Department

141、151、156‧‧‧絕緣層 141, 151, 156‧‧‧ Insulation

142、152、157‧‧‧配線層 142, 152, 157‧‧‧ wiring layer

143、153、158‧‧‧通孔 143, 153, 158

160‧‧‧囊封劑 160‧‧‧Encapsulating agent

161‧‧‧第二開口部 161‧‧‧Second opening

162‧‧‧外配線層 162‧‧‧Outer wiring layer

163‧‧‧外通孔 163‧‧‧External through hole

165‧‧‧第四開口部 165‧‧‧The fourth opening

170‧‧‧保護層 170‧‧‧Protective layer

171‧‧‧第一開口部 171‧‧‧First opening

172‧‧‧凸塊下金屬層 172‧‧‧ under bump metal layer

175‧‧‧第一外部連接端子 175‧‧‧First external connection terminal

180‧‧‧覆蓋層 180‧‧‧overlay

181‧‧‧第三開口部 181‧‧‧ third opening

185‧‧‧第二外部連接端子 185‧‧‧Second external connection terminal

190‧‧‧黏合膜 190‧‧‧ Adhesive film

191‧‧‧連接端子 191‧‧‧Connecting terminal

200A‧‧‧電子元件封裝 200A‧‧‧Electronic component packaging

210‧‧‧配線基板 210‧‧‧ wiring board

212A‧‧‧結合焊墊 212A‧‧‧Combined pad

212B‧‧‧覆晶焊墊 212B‧‧‧ flip chip solder pad

222‧‧‧第一電子元件 222‧‧‧The first electronic component

224‧‧‧第二電子元件 224‧‧‧Second electronic component

230‧‧‧囊封樹脂 230‧‧‧encapsulated resin

240‧‧‧底部填充樹脂 240‧‧‧Bottom filling resin

251‧‧‧凸塊 251‧‧‧Bump

252‧‧‧結合配線 252‧‧‧Combined wiring

1000‧‧‧電子裝置 1000‧‧‧Electronic device

1010‧‧‧母板 1010‧‧‧Motherboard

1020‧‧‧晶片相關元件 1020‧‧‧chip related components

1030‧‧‧網路相關元件 1030‧‧‧Network-related components

1040‧‧‧其他元件 1040‧‧‧Other components

1050‧‧‧照相機 1050‧‧‧Camera

1060‧‧‧天線 1060‧‧‧ Antenna

1070‧‧‧顯示器 1070‧‧‧Monitor

1080‧‧‧電池 1080‧‧‧Battery

1090‧‧‧訊號線 1090‧‧‧Signal line

1100‧‧‧智慧型電話 1100‧‧‧Smartphone

1101‧‧‧主體 1101‧‧‧Main

1110‧‧‧主板 1110‧‧‧ Motherboard

1120‧‧‧電子元件 1120‧‧‧Electronic components

1130‧‧‧照相機 1130‧‧‧Camera

C2‧‧‧第一配線層 C2‧‧‧First wiring layer

G’、G”、G'''‧‧‧路徑 G’, G”, G’''‧‧‧ path

I-I’、II-II’、III-III’、IV-IV’、V-V’、VI-VI’、VII-VII’、VIII-VIII’、IX-IX’、X-X’、XI-XI’、XII-XII’、XIII-XIII’‧‧‧線 I-I', II-II', III-III', IV-IV', V-V', VI-VI', VII-VII', VIII-VIII', IX-IX', X-X', XI-XI', XII-XII', XIII-XIII' ‧‧‧ line

M1‧‧‧第二配線層 M1‧‧‧Second wiring layer

M2、M3‧‧‧配線層 M2, M3‧‧‧Wiring layer

P‧‧‧焊墊圖案 P‧‧‧pad pattern

R‧‧‧重新分配圖案 R‧‧‧Reassign pattern

RP‧‧‧返回路徑 RP‧‧‧Return path

S’、S”、S'''‧‧‧路徑 S’, S”, S’''‧‧‧ path

藉由結合附圖閱讀以下詳細說明，將更清楚地理解本發明的以上及其他態樣、特徵及優點，在附圖中：圖1是示意性地說明電子裝置系統的實例的方塊圖。 The above and other aspects, features, and advantages of the present invention will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings. In the drawings: FIG. 1 is a block diagram that schematically illustrates an example of an electronic device system.

圖2是示意性地說明用於電子裝置中的電子元件封裝的實例的圖。 2 is a diagram schematically illustrating an example of an electronic component package used in an electronic device.

圖3是示意性地說明電子元件封裝的實例的剖視圖。 3 is a cross-sectional view schematically illustrating an example of electronic component packaging.

圖4是電子元件封裝沿圖3所示的線I-I’截取的示意性平面圖。 4 is a schematic plan view of the electronic component package taken along line I-I' shown in FIG. 3.

圖5A至圖5L是說明製造圖3所示電子元件封裝的製程的實例的示意圖。 5A to 5L are schematic diagrams illustrating an example of the manufacturing process of the electronic component package shown in FIG. 3.

圖6是示意性地說明電子元件封裝的另一實例的剖視圖。 6 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖7是電子元件封裝沿圖6所示的線II-II’截取的示意性平面圖。 7 is a schematic plan view of the electronic component package taken along the line II-II' shown in FIG. 6.

圖8A至圖8M是說明製造圖6所示電子元件封裝的製程的實例的示意圖。 8A to 8M are schematic diagrams illustrating an example of a manufacturing process of the electronic component package shown in FIG. 6.

圖9是示意性地說明電子元件封裝的另一實例的剖視圖。 9 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖10是電子元件封裝沿圖9所示的線III-III’截取的示意性平面圖。 FIG. 10 is a schematic plan view of the electronic component package taken along line III-III' shown in FIG. 9.

圖11A至圖11M是說明製造圖9所示電子元件封裝的製程的 實例的示意圖。 11A to 11M illustrate the manufacturing process of the electronic component package shown in FIG. 9 Schematic diagram of an example.

圖12是示意性地說明電子元件封裝的另一實例的剖視圖。 12 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖13是電子元件封裝沿圖12所示的線IV-IV’截取的示意性平面圖。 Fig. 13 is a schematic plan view of the electronic component package taken along line IV-IV' shown in Fig. 12.

圖14A至圖14L是說明製造圖12所示電子元件封裝的製程的實例的示意圖。 14A to 14L are schematic diagrams illustrating an example of a manufacturing process of the electronic component package shown in FIG. 12.

圖15是示意性地說明電子元件封裝的另一實例的剖視圖。 15 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖16是電子元件封裝沿圖15所示的線V-V’截取的示意性平面圖。 Fig. 16 is a schematic plan view of the electronic component package taken along the line V-V' shown in Fig. 15.

圖17A至圖17M是說明製造圖15所示電子元件封裝的製程的實例的示意圖。 17A to 17M are schematic diagrams illustrating an example of a manufacturing process of the electronic component package shown in FIG. 15.

圖18是示意性地說明電子元件封裝的另一實例的剖視圖。 18 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖19是電子元件封裝沿圖18所示的線VI-VI’截取的示意性平面圖。 19 is a schematic plan view of the electronic component package taken along line VI-VI' shown in FIG. 18.

圖20A至圖20M是說明製造圖18所示電子元件封裝的製程的實例的示意圖。 20A to 20M are schematic diagrams illustrating an example of a manufacturing process of the electronic component package shown in FIG. 18.

圖21是示意性地說明電子元件封裝的另一實例的剖視圖。 21 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖22是電子元件封裝沿圖21所示的線VII-VII’截取的示意性平面圖。 Fig. 22 is a schematic plan view of the electronic component package taken along line VII-VII' shown in Fig. 21.

圖23是示意性地說明電子元件封裝的另一實例的剖視圖。 23 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖24是電子元件封裝沿圖23所示的線VIII-VIII’截取的示意性平面圖。 24 is a schematic plan view of the electronic component package taken along line VIII-VIII' shown in FIG. 23.

圖25是示意性地說明電子元件封裝的另一實例的剖視圖。 25 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖26是電子元件封裝沿圖25所示的線IX-IX’截取的示意性平面圖。 Fig. 26 is a schematic plan view of the electronic component package taken along line IX-IX' shown in Fig. 25.

圖27是示意性地說明電子元件封裝的另一實例的剖視圖。 FIG. 27 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖28是電子元件封裝沿圖27所示的線X-X’截取的示意性平面圖。 28 is a schematic plan view of the electronic component package taken along line X-X' shown in FIG. 27.

圖29是示意性地說明電子元件封裝的另一實例的剖視圖。 29 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖30是電子元件封裝沿圖29所示的線XI-XI’截取的示意性平面圖。 Fig. 30 is a schematic plan view of the electronic component package taken along line XI-XI' shown in Fig. 29.

圖31是示意性地說明電子元件封裝的另一實例的剖視圖。 31 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖32是電子元件封裝沿圖31所示的線XII-XII’截取的示意性平面圖。 32 is a schematic plan view of the electronic component package taken along the line XII-XII' shown in FIG. 31.

圖33是示意性地說明電子元件封裝的另一實例的剖視圖。 33 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖34是電子元件封裝沿圖33所示的線XIII-XIII’截取的示意性平面圖。 34 is a schematic plan view of the electronic component package taken along the line XIII-XIII' shown in FIG. 33.

圖35是示意性地說明電子元件封裝的另一實例的剖視圖。 35 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖36是示意性地說明電子元件封裝的另一實例的剖視圖。 36 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖37是示意性地說明電子元件封裝的另一實例的剖視圖。 37 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖38是示意性地說明電子元件封裝的另一實例的剖視圖。 38 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖39是示意性地說明電子元件封裝的訊號傳遞的實例的圖。 39 is a diagram schematically illustrating an example of signal transmission of an electronic component package.

圖40是示意性地說明電子元件封裝的另一實例的剖視圖。 40 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖41是示意性地說明電子元件封裝的另一實例的剖視圖。 41 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖42是示意性地說明電子元件封裝的另一實例的剖視圖。 42 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖43是示意性地說明電子元件封裝的另一實例的剖視圖。 43 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖44是示意性地說明電子元件封裝的另一實例的剖視圖。 44 is a cross-sectional view schematically illustrating another example of electronic component packaging.

在下文中，將參照附圖對本發明的實施例進行如下闡述。 Hereinafter, embodiments of the present invention will be explained as follows with reference to the drawings.

然而，本發明可被示例成諸多不同的形式，而不應被視為僅限於本文中所述的具體實施例。確切而言，提供該些實施例是為了使此揭露內容將透徹及完整，並將向熟習此項技術者充分傳達本發明的範圍。 However, the present invention can be exemplified in many different forms and should not be considered as limited to the specific embodiments described herein. Specifically, the embodiments are provided so that the disclosure content will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

在本說明書通篇中，應理解，當稱一組件(例如，層、區、或晶圓(基板))位於另一組件「上」、「連接至」、或「耦合至」另一組件時，所述組件可直接位於所述另一組件「上」、直接「連接至」、或直接「耦合至」所述另一組件、抑或其間可存在其他中間組件。相比之下，當稱一組件「直接位於」另一組件「上」、「直接連接至」、或「直接耦合至」另一組件時，其間可不存在中間組件或層。在通篇中相同的編號指代相同的組件。本文中所使用的用語「及/或」包含相關列出項其中一或多個項的任意及所有組合。 Throughout this specification, it should be understood that when a component (eg, layer, region, or wafer (substrate)) is referred to as being “on”, “connected to”, or “coupled to” another component The component may be directly "on", directly "connected to", or directly "coupled" to the other component, or there may be other intermediate components in between. In contrast, when a component is referred to as being "directly on," "directly connected to," or "directly coupled to" another component, there may be no intervening components or layers present. The same numbers refer to the same components throughout. The term "and/or" as used herein includes any and all combinations of one or more of the listed items.

將顯而易見，儘管本文中可能使用「第一」、「第二」、「第三」等用語來闡述各種構件、元件、區、層及/或區段，然而該些構件、元件、區、層及/或區段不應受限於該些用語。該些用語僅用於區分各個構件、元件、區、層或區段。因而，在不背離示例 性實施例的教示內容的條件下，以下所論述的第一構件、元件、區、層或區段可被稱為第二構件、元件、區、層或區段。 It will be apparent that although the terms "first", "second", and "third" may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, layers And/or sections should not be limited to these terms. These terms are only used to distinguish individual components, elements, regions, layers or sections. Thus, without departing from the example Subject to the teachings of the exemplary embodiments, the first member, element, region, layer or section discussed below may be referred to as the second member, element, region, layer or section.

在本文中，為易於說明，可使用例如「在…之上(above)」、「上方的(upper)」、「在…之下(below)」、及「下方的(lower)」等空間相對性用語來闡述圖中所示的一個組件相對於另一(其他)組件的關係。應理解，該些空間相對性用語旨在除圖中所繪示定向以外亦囊括裝置在使用或操作中的不同定向。舉例而言，若圖中的裝置被翻轉，則被闡述為在其他組件「之上」或「上方」的組件此時將被定向為在其他組件或特徵「之下」或「下方」。因此，依圖的具體方向而定，用語「在...之上」可囊括上方與下方兩種定向。所述裝置亦可具有其他定向(例如，旋轉90度或處於其他定向)，且本文中所用的空間相對性描述語可相應地進行解釋。 In this article, for ease of explanation, spatial relative such as "above", "upper", "below", and "lower" can be used. Sexual terms to explain the relationship between one component shown in the figure relative to another (other) component. It should be understood that these spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figure is turned over, components described as "above" or "above" other components will now be oriented "below" or "below" other components or features. Therefore, depending on the specific direction of the picture, the term "above" can encompass both upper and lower orientations. The device may also have other orientations (eg, rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

本文所用術語僅用於闡述具體實施例，且本發明並不受其限制。除非上下文中清楚地另外指明，否則本文所用的單數形式「一」及「所述」旨在亦包含複數形式。更應理解，當在本說明書中使用用語「包括(comprises及/或comprising)」時，是指明所陳述特徵、整數、步驟、操作、構件、組件及/或其群組的存在，但不排除一或多個其他特徵、整數、步驟、操作、構件、組件及/或其群組的存在或添加。 The terminology used herein is only for explaining specific embodiments, and the present invention is not limited thereto. Unless the context clearly dictates otherwise, the singular forms "a" and "said" as used herein are intended to include the plural forms as well. It should be further understood that when the term "comprises and/or comprising" is used in this specification, it indicates the existence of the stated features, integers, steps, operations, components, components, and/or groups thereof, but does not exclude The presence or addition of one or more other features, integers, steps, operations, components, components, and/or groups thereof.

在下文中，將參照說明本發明實施例的示意圖來闡述本發明的實施例。在圖式中，可估計會因例如製造技術及/或容差而 造成對所示形狀的修改。因此，本發明的實施例不應被視為僅限於本文中所示區的特定形狀，而是例如包含由製造而引起的形狀變化。以下實施例亦可由其中的一者或其組合構成。 Hereinafter, embodiments of the present invention will be explained with reference to schematic diagrams illustrating embodiments of the present invention. In the drawings, it can be estimated that due to manufacturing technology and/or tolerance, for example Resulting in modifications to the shape shown. Therefore, the embodiments of the present invention should not be considered limited to the specific shapes of the regions shown herein, but include, for example, shape changes caused by manufacturing. The following embodiments may also be composed of one of them or a combination thereof.

以下所闡述的本發明的內容可具有多種構型且在本文中可僅提出所需要的構型，但並非僅限於此。 The content of the present invention set forth below may have various configurations and only the required configurations may be proposed herein, but it is not limited thereto.

電子裝置Electronic device

圖1是示意性地說明電子裝置系統的實例的方塊圖。 FIG. 1 is a block diagram schematically illustrating an example of an electronic device system.

參照圖1，電子裝置1000中可容置有母板1010。晶片相關元件1020、網路相關元件1030、其他元件1040等可物理地連接至及/或電性連接至母板1010。該些元件可經由各種訊號線1090而連接至以下將闡述的其他元件。 Referring to FIG. 1, a motherboard 1010 may be accommodated in the electronic device 1000. The chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically connected and/or electrically connected to the motherboard 1010. These components can be connected to other components described below through various signal lines 1090.

晶片相關元件1020可包括：記憶體晶片，例如揮發性記憶體(例如，動態隨機存取記憶體(dynamic random access memory，DRAM))、非揮發性記憶體(例如，唯讀記憶體(read only memory，ROM))、快閃記憶體等；應用處理器晶片，例如中央處理器(例如，中央處理單元(central processing unit，CPU))、圖形處理器(例如，圖形處理單元(graphic processing unit，GPU))、數位訊號處理器、密碼學處理器(cryptographic processor)、微處理器、微控制器等；邏輯晶片，例如類比-數位轉換器(analog-to-digital converter)、應用專用積體電路(application-specific integrated circuit，ASIC)等；以及類似元件。然而，晶片相關元件1020並非僅限於此，而是亦可包括其他類型 的晶片相關元件。此外，該些元件1020可彼此組合。 Chip-related components 1020 may include: memory chips, such as volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory) memory, ROM)), flash memory, etc.; application processor chips, such as a central processing unit (eg, central processing unit (CPU)), a graphics processor (eg, graphic processing unit, GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; logic chips, such as analog-to-digital converters, application-specific integrated circuits (application-specific integrated circuit, ASIC), etc.; and similar components. However, the chip-related component 1020 is not limited to this, but may also include other types Related components. In addition, these elements 1020 may be combined with each other.

網路相關元件1030可包括例如以下協定：無線保真(wireless fidelity，Wi-Fi)(電氣及電子工程師學會(Institute of Electrical and Electronics Engineers，IEEE)802.11家族等)、全球互通微波存取(worldwide interoperability for microwave access，WiMAX)(IEEE 802.16家族等)、IEEE 802.20、長期演進(long term evolution，LTE)、僅支援資料的演進(evolution data only，Ev-DO)、高速封包存取+(high speed packet access +，HSPA+)、高速下行封包存取+(high speed downlink packet access +，HSDPA+)、高速上行封包存取+(high speed uplink packet access +，HSUPA+)、增強型資料GSM環境(enhanced data GSM environment，EDGE)、全球行動通訊系統(global system for mobile communications，GSM)、全球定位系統(global positioning system，GPS)、通用封包無線電服務(general packet radio service，GPRS)、分碼多重存取(code division multiple access，CDMA)、分時多重存取(time division multiple access，TDMA)、數位增強型無線電訊(digital enhanced cordless telecommunications，DECT)、藍芽、3G協定、4G協定、5G協定及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關元件1030並非僅限於此，且亦可包括多個其他無線標準或協定或者有線標準或協定中的任一者。此外，該些元件1030可與上述晶片相關元件1020一起相互組合。 The network-related components 1030 may include, for example, the following protocols: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family, etc.), global interoperable microwave access (worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packet access + (high speed packet access +, HSPA+), high speed downlink packet access + (HSDPA+), high speed uplink packet access + (HSUPA+), enhanced data GSM environment (enhanced data GSM environment, EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement, 4G agreement, 5G agreement and subsequent agreements Any other wireless protocol and wire protocol specified later. However, the network-related component 1030 is not limited to this, and may include any of a number of other wireless standards or protocols or wired standards or protocols. In addition, these elements 1030 can be combined with the wafer-related elements 1020 described above.

其他元件1040可包括高頻電感器、鐵氧體電感器(ferrite inductor)、功率電感器、鐵氧體珠粒、低溫共燒陶瓷(low temperature co-firing ceramic，LTCC)、電磁干擾(electromagnetic interference，EMI)濾波器、多層陶瓷電容器(multilayer ceramic capacitor，MLCC)等。然而，其他元件1040並非僅限於此，而是亦可包括用於各種其他目的的被動元件等。此外，該些其他元件1040可與以上所述晶片相關元件1020及/或網路相關元件1030一起相互組合。 Other components 1040 may include high-frequency inductors, ferrite inductors (ferrite inductors) inductor), power inductor, ferrite beads, low temperature co-firing ceramic (LTCC), electromagnetic interference (EMI) filter, multilayer ceramic capacitor (MLCC), etc. . However, other elements 1040 are not limited to this, but may also include passive elements for various other purposes. In addition, the other components 1040 can be combined with the chip-related components 1020 and/or the network-related components 1030 described above.

依其種類而定，電子裝置1000可包括可物理地連接至及/或電性連接至母板1010或可不物理地連接至及/或不電性連接至母板1010的其他元件。該些其他元件可包括例如照相機1050、天線1060、顯示器1070、電池1080、音訊編解碼器(圖中未示出)、視訊編解碼器(圖中未示出)、功率放大器(圖中未示出)、羅盤(圖中未示出)、加速度計(圖中未示出)、陀螺儀(圖中未示出)、揚聲器(圖中未示出)、大容量儲存器(例如，硬碟驅動機)(圖中未示出)、光碟(compact disk，CD)(圖中未示出)、數位多功能光碟(digital versatile disk，DVD)(圖中未示出)等。然而，該些其他元件並非僅限於此，而是依電子裝置1000的類型而定亦可包括用於各種目的的其他元件。 Depending on the type, the electronic device 1000 may include other elements that may be physically connected to and/or electrically connected to the motherboard 1010 or may not be physically connected to and/or electrically connected to the motherboard 1010. These other components may include, for example, camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown) Out), compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage (eg hard drive) Drive) (not shown in the figure), compact disk (CD) (not shown in the figure), digital versatile disk (DVD) (not shown in the figure), etc. However, these other elements are not limited thereto, but may also include other elements for various purposes depending on the type of the electronic device 1000.

電子裝置1000可為智慧型電話、個人數位助理、數位攝影機、數位照相機(digital still camera)、網路系統、電腦、監視器、平板電腦(tablet)、膝上型電腦、隨身型易網機(netbook)、電視、視訊遊戲機(video game console)、智慧型手錶等。然而， 電子裝置1000並非僅限於此，而是亦可為用於處理資料的任何其他電子裝置。 The electronic device 1000 may be a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a portable e-net machine ( netbook), TVs, video game consoles, smart watches, etc. however, The electronic device 1000 is not limited to this, but may be any other electronic device for processing data.

圖2是示意性地說明用於電子裝置中的電子元件封裝的實例的圖。 2 is a diagram schematically illustrating an example of an electronic component package used in an electronic device.

所述電子元件封裝可出於各種目的而用於如上所述的各種電子裝置1000中。舉例而言，主板1110可容置於智慧型電話1100的主體1101中，且各種電子元件1120可物理地連接至及/或電性連接至主板1110。此外，可物理地連接至及/或電性連接至主板1110或可不物理地連接至及/或不電性連接至主板1110的另一元件(例如，照相機1130)可容置於主體1101中。此處，電子元件1120中的某些電子元件1120可為如上所述的晶片相關元件，且電子元件封裝100可為例如晶片相關元件中的應用處理器，但並非僅限於此。 The electronic component package may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 may be accommodated in the main body 1101 of the smartphone 1100, and various electronic components 1120 may be physically connected to and/or electrically connected to the motherboard 1110. In addition, another element (eg, camera 1130) that may be physically connected to and/or electrically connected to the main board 1110 or may not be physically connected to and/or electrically connected to the main board 1110 may be accommodated in the main body 1101. Here, some of the electronic components 1120 may be chip related components as described above, and the electronic component package 100 may be, for example, an application processor in chip related components, but it is not limited thereto.

電子元件封裝Electronic component packaging

圖3是示意性地說明電子元件封裝的實例的剖視圖。 3 is a cross-sectional view schematically illustrating an example of electronic component packaging.

圖4是電子元件封裝沿圖3所示的線I-I’截取的示意性平面圖。 4 is a schematic plan view of the electronic component package taken along line I-I' shown in FIG. 3.

參照圖3及圖4，根據實例的電子元件封裝100A可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層 111A與第二絕緣層111B之間的第一配線層112、安置於第一絕緣層111A的上表面上的金屬層135、安置於第二絕緣層111B的下表面上的第二配線層132、及穿透過第二絕緣層111B的通孔113。貫穿孔110X可依序穿透過金屬層135、第一絕緣層111A、第一配線層112、第二絕緣層111B、及第二配線層132。 Referring to FIGS. 3 and 4, an electronic component package 100A according to an example may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a redistribution disposed under the frame 110 and the electronic component 120 Parts 140 and 150, and an encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, and be disposed on the first insulating layer The first wiring layer 112 between 111A and the second insulating layer 111B, the metal layer 135 disposed on the upper surface of the first insulating layer 111A, the second wiring layer 132 disposed on the lower surface of the second insulating layer 111B, And a through hole 113 penetrating through the second insulating layer 111B. The through hole 110X may sequentially penetrate the metal layer 135, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132.

如上所述，近來，已積極地開發出具有小的尺寸且有利於實作多個引腳的扇出式晶圓級封裝。此處，一般而言，晶圓級封裝具有其中電子元件的周圍僅利用例如環氧樹脂模製化合物(epoxy molding compound，EMC)等囊封劑進行模製及封閉的結構，且在所述晶圓級封裝下形成重新分配部以實作電子元件的重新分配。此處，隨著用於實作重新分配部的層的數目增加，將在形成所述重新分配部的製程中發生缺陷的幾率增大，此導致電子元件的良率降低，乃因電子元件一般而言是在重新分配部形成之前安置於所述電子元件封裝中。 As described above, recently, a fan-out wafer-level package having a small size and facilitating implementation of multiple pins has been actively developed. Here, in general, a wafer-level package has a structure in which the periphery of an electronic component is molded and sealed only with an encapsulant such as epoxy molding compound (EMC), and the A redistribution section is formed under the round-level package to implement the redistribution of electronic components. Here, as the number of layers used to implement the redistribution section increases, the probability of defects occurring in the process of forming the redistribution section increases, which leads to a decrease in the yield of electronic components because electronic components generally In particular, it is placed in the electronic component package before the redistribution portion is formed.

此外，由於電子元件的周圍僅利用囊封劑進行囊封及封閉，因此難以控制因各種原因造成的翹曲、在固定電子元件方面受限、且難以利用囊封區作為路由區，並且因此降低設計的自由度等。 In addition, since only the encapsulant is used to encapsulate and seal the surroundings of the electronic components, it is difficult to control the warpage due to various reasons, it is limited in fixing the electronic components, and it is difficult to use the encapsulation area as the routing area, and thus reduce Design freedom, etc.

相反地，在其中在安置電子元件120之前將可執行電子元件的重新分配功能的框架110引入至用於囊封電子元件120的囊封劑160中的情形中，如在根據實例的電子元件封裝100A中，在安置電子元件120之後形成的重新分配部140及150的層的數 目可減小。因而，可解決其中電子元件120的良率因在安置電子元件120之後所造成的製程缺陷而降低的問題。 On the contrary, in the case where the frame 110 that can perform the redistribution function of the electronic component is introduced into the encapsulant 160 for encapsulating the electronic component 120 before the electronic component 120 is placed, as in the electronic component packaging according to the example In 100A, the number of layers of the redistribution sections 140 and 150 formed after the electronic component 120 is placed The head can be reduced. Thus, the problem in which the yield of the electronic component 120 is reduced due to process defects caused after the electronic component 120 is placed can be solved.

此外，由於電子元件封裝100A的剛性可藉由框架110而得到改善，因此可更易於控制翹曲，且由於電子元件120安置於框架110的貫穿孔110X中，因此電子元件120可藉由壁面黏合(wall-surface adhesion)而更牢固地固定。此外，由於框架110的上表面110A及下表面110B可用作路由區，因此設計的自由度可得到提升。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖3中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於金屬層135的上表面下、或者位於與金屬層135的上表面相同的位階處或位於金屬層135的上表面之上，只要金屬層135及電子元件120均被囊封劑160覆蓋即可。 In addition, since the rigidity of the electronic component package 100A can be improved by the frame 110, warpage can be more easily controlled, and because the electronic component 120 is disposed in the through hole 110X of the frame 110, the electronic component 120 can be bonded by the wall surface (wall-surface adhesion) and more firmly fixed. In addition, since the upper surface 110A and the lower surface 110B of the frame 110 can be used as routing areas, the degree of freedom in design can be improved. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 3, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 with respect to the redistribution portions 140 and 150 or above the upper surface 110A of the frame 110 but below the upper surface of the metal layer 135, or between The upper surface of the metal layer 135 is at the same level or above the upper surface of the metal layer 135, as long as the metal layer 135 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據實例的電子元件封裝100A中的相應元件。 Hereinafter, the respective components included in the electronic component package 100A according to the example will be explained in more detail.

使用框架110的目的可為基本維持電子元件封裝100A的剛性。框架110可具有用於封閉電子元件120的周圍的貫穿孔110X，且可因電子元件120安置於貫穿孔110X中而達成對電子元件120進行的壁面黏合。框架110可包括第一配線層112及第二 配線層132。由於第一配線層112及第二配線層132是在安置電子元件120之前形成，因此其可解決其中電子元件120的良率降低的問題。框架110可為電子元件封裝100A提供更寬的路由區，藉此進一步提升電子元件封裝100A的設計的自由度。此外，用於囊封電子元件封裝100A中的電子元件120的囊封劑160的相對平坦的外部表面及電子元件封裝100A(不包括以下將闡述的第一外部連接端子175的突起)的厚度的均勻性可藉由框架110而得以確保。 The purpose of using the frame 110 may be to substantially maintain the rigidity of the electronic component package 100A. The frame 110 may have a through hole 110X for closing the periphery of the electronic component 120, and the wall surface bonding to the electronic component 120 may be achieved because the electronic component 120 is disposed in the through hole 110X. The frame 110 may include a first wiring layer 112 and a second Wiring layer 132. Since the first wiring layer 112 and the second wiring layer 132 are formed before the electronic component 120 is placed, it can solve the problem in which the yield of the electronic component 120 is reduced. The frame 110 may provide a wider routing area for the electronic component package 100A, thereby further improving the design freedom of the electronic component package 100A. In addition, the relatively flat outer surface of the encapsulant 160 for encapsulating the electronic component 120 in the electronic component package 100A and the thickness of the electronic component package 100A (excluding protrusions of the first external connection terminal 175 to be explained below) Uniformity can be ensured by the frame 110.

框架110可具有上表面110A及與上表面110A相對的下表面110B。第一絕緣層111A、第二絕緣層111B及第一配線層112可安置於上表面110A與下表面110B之間。框架110可具有穿透於上表面110A與下表面110B之間的貫穿孔110X。第二配線層132可安置於框架的下表面110B上。框架110可包括將第一配線層112與第二配線層132電性連接至彼此的通孔113。框架110可為一包括安置於上表面110A與下表面110B之間的元件、及安置於上表面110A及下表面110B上的元件的概念。作為實例，框架110可為一包括第一絕緣層111A、第二絕緣層111B、第一配線層112、第二配線層132及通孔113的上位概念(upper concept)。貫穿孔110X可依序穿透過金屬層135、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。 The frame 110 may have an upper surface 110A and a lower surface 110B opposite to the upper surface 110A. The first insulating layer 111A, the second insulating layer 111B, and the first wiring layer 112 may be disposed between the upper surface 110A and the lower surface 110B. The frame 110 may have a through hole 110X penetrating between the upper surface 110A and the lower surface 110B. The second wiring layer 132 may be disposed on the lower surface 110B of the frame. The frame 110 may include a through hole 113 that electrically connects the first wiring layer 112 and the second wiring layer 132 to each other. The frame 110 may be a concept including elements disposed between the upper surface 110A and the lower surface 110B, and elements disposed on the upper surface 110A and the lower surface 110B. As an example, the frame 110 may be an upper concept including a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112, a second wiring layer 132, and a via 113. The through hole 110X may penetrate the metal layer 135, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in sequence.

第一絕緣層111A可實質上維持電子元件封裝100A的剛性且第一絕緣層111A的材料並無特別限制，只要其可支撐電子元 件封裝100A即可。舉例而言，可使用絕緣材料作為第一絕緣層111A的材料。此處，所述絕緣材料可為：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；具有例如浸入於所述熱固性樹脂及所述熱塑性樹脂中的玻璃纖維及/或無機填料等加強材料的樹脂，例如預浸體(pre-preg)、味之素構成膜(Ajinomoto Build up Film，ABF)、FR-4、雙馬來醯亞胺三嗪(Bismaleimide Triazine，BT)等。作為另一選擇，可使用具有優異剛性及熱傳導性的金屬作為第一絕緣層111A的材料。此處，所述金屬可為Fe-Ni系合金。在此種情形中，在所述Fe-Ni系合金的表面上亦可形成有鍍Cu，以確保所述Fe-Ni系合金與所述囊封劑、層間絕緣材料等之間的黏合。除上述材料以外，亦可使用玻璃、陶瓷、塑膠等作為第一絕緣層111A的材料。第一絕緣層111A的厚度並無特別限制，但可依電子元件120的厚度來設計。舉例而言，依電子元件120的類型而定，第一絕緣層111A的厚度可為100微米至500微米左右。 The first insulating layer 111A can substantially maintain the rigidity of the electronic device package 100A and the material of the first insulating layer 111A is not particularly limited as long as it can support the electronic element The package is 100A. For example, an insulating material may be used as the material of the first insulating layer 111A. Here, the insulating material may be: thermosetting resin, such as epoxy resin; thermoplastic resin, such as polyimide resin; having, for example, glass fiber and/or inorganic filler immersed in the thermosetting resin and the thermoplastic resin Resin of other reinforcing materials, such as pre-preg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), etc. Alternatively, a metal having excellent rigidity and thermal conductivity may be used as the material of the first insulating layer 111A. Here, the metal may be an Fe-Ni alloy. In this case, Cu plating may also be formed on the surface of the Fe-Ni-based alloy to ensure adhesion between the Fe-Ni-based alloy and the encapsulant, interlayer insulating material, and the like. In addition to the above materials, glass, ceramics, plastics, etc. can also be used as the material of the first insulating layer 111A. The thickness of the first insulating layer 111A is not particularly limited, but can be designed according to the thickness of the electronic component 120. For example, depending on the type of electronic component 120, the thickness of the first insulating layer 111A may be about 100 microns to 500 microns.

第二絕緣層111B可為一種用於引入第一配線層112及第二配線層132的構成層，且第二絕緣層111B的材料並無特別限制，只要其為絕緣材料即可。此處，所述絕緣材料可為：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；具有例如浸入於所述熱固性樹脂及所述熱塑性樹脂中的玻璃纖維或無機填料等加強材料的樹脂，例如預浸體、味之素構成膜、FR-4、雙馬來醯亞胺三嗪等。同時，在其中使用例如感光成像介電(photo imagable dielectric，PID)樹脂等感光性絕緣材料作為第二絕緣層 111B的材料的情形中，第二絕緣層111B可被形成為更小的厚度，且可藉由光刻方法而形成通孔洞。因而，通孔的尺寸可減小，且因此可易於實作精細的節距(例如，30微米或小於30微米)。第二絕緣層111B的厚度並無特別限制，但依設計特定細節而定可進行各種設計。舉例而言，第二絕緣層111B的除第一配線層112以外的厚度可為5微米至20微米左右，且當慮及第一配線層112的厚度時，第二絕緣層111B的厚度可為15微米至70微米左右。 The second insulating layer 111B may be a constituent layer for introducing the first wiring layer 112 and the second wiring layer 132, and the material of the second insulating layer 111B is not particularly limited as long as it is an insulating material. Here, the insulating material may be: thermosetting resin, such as epoxy resin; thermoplastic resin, such as polyimide resin; reinforced with, for example, glass fiber or inorganic filler immersed in the thermosetting resin and the thermoplastic resin Material resin, such as prepreg, Ajinomoto film, FR-4, bismaleimide triazine, etc. At the same time, a photosensitive insulating material such as a photo imagable dielectric (PID) resin is used as the second insulating layer In the case of the material of 111B, the second insulating layer 111B can be formed to a smaller thickness, and the via hole can be formed by a photolithography method. Thus, the size of the through hole can be reduced, and thus a fine pitch (for example, 30 microns or less) can be easily implemented. The thickness of the second insulating layer 111B is not particularly limited, but various designs can be made depending on the specific details of the design. For example, the thickness of the second insulating layer 111B other than the first wiring layer 112 may be about 5 to 20 microns, and when considering the thickness of the first wiring layer 112, the thickness of the second insulating layer 111B may be 15 microns to 70 microns.

第一絕緣層111A及第二絕緣層111B可由不同的材料形成。舉例而言，第一絕緣層111A可由具有極佳剛性的材料形成，而第二絕緣層111B可由感光性絕緣材料形成而無論剛性如何。如上所述，可選擇並使用適宜用作電子元件封裝中的相應第一絕緣層111A及第二絕緣層111B的材料。舉例而言，第一絕緣層111A可具有較第二絕緣層111B大的彈性模量。此外，第一絕緣層111A可具有較第二絕緣層111B大的厚度。相應第一絕緣層111A及第二絕緣層111B的彈性模量及厚度亦可與相應第一絕緣層111A及第二絕緣層111B在電子元件封裝中的作用相關，因第一絕緣層111A具有相對大的厚度，其可有利於維持電子元件封裝的剛性並固定電子元件120，且因第二絕緣層111B具有減小的厚度，其可有利於減小通孔113的尺寸並縮短電性路徑。然而，第一絕緣層111A及第二絕緣層111B並非僅限於此，而是亦可由相同的材料形成且具有相同的厚度。 The first insulating layer 111A and the second insulating layer 111B may be formed of different materials. For example, the first insulating layer 111A may be formed of a material having excellent rigidity, and the second insulating layer 111B may be formed of a photosensitive insulating material regardless of rigidity. As described above, materials suitable for the corresponding first insulating layer 111A and second insulating layer 111B in the electronic component package can be selected and used. For example, the first insulating layer 111A may have a larger elastic modulus than the second insulating layer 111B. In addition, the first insulating layer 111A may have a larger thickness than the second insulating layer 111B. The elastic modulus and thickness of the corresponding first insulating layer 111A and the second insulating layer 111B can also be related to the role of the corresponding first insulating layer 111A and the second insulating layer 111B in the packaging of electronic components, because the first insulating layer 111A has a relative The large thickness can help maintain the rigidity of the electronic component package and fix the electronic component 120, and because the second insulating layer 111B has a reduced thickness, it can help reduce the size of the through hole 113 and shorten the electrical path. However, the first insulating layer 111A and the second insulating layer 111B are not limited thereto, but may be formed of the same material and have the same thickness.

第一配線層112可安置於第一絕緣層111A與第二絕緣層 111B之間。舉例而言，第一配線層112可安置於第一絕緣層111A的下表面上並嵌置於第二絕緣層111B中。亦即，第一配線層112可安置於框架110中。此處，第一配線層112安置於框架110中的含義為第一配線層112安置於框架110的上表面110A與下表面110B之間。依對應層的設計而定，第一配線層112可執行各種功能。舉例而言，第一配線層可充當接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等而作為重新分配圖案。此處，訊號(S)圖案可包括除接地(GND)圖案、功率(PWR)圖案等以外的各種訊號，例如資料訊號等。此外，第一配線層112可充當通孔焊墊等而作為焊墊圖案。如上所述，由於第一配線層112可執行重新分配功能，因此第一配線層112可分擔重新分配部140及150的重新分配功能。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作第一配線層112的材料。第一配線層112的厚度亦無特別限制，但可為例如10微米至50微米左右。 The first wiring layer 112 may be disposed on the first insulating layer 111A and the second insulating layer Between 111B. For example, the first wiring layer 112 may be disposed on the lower surface of the first insulating layer 111A and embedded in the second insulating layer 111B. That is, the first wiring layer 112 may be disposed in the frame 110. Here, the meaning that the first wiring layer 112 is disposed in the frame 110 means that the first wiring layer 112 is disposed between the upper surface 110A and the lower surface 110B of the frame 110. The first wiring layer 112 can perform various functions depending on the design of the corresponding layer. For example, the first wiring layer may serve as a ground (GND) pattern, power (PWR) pattern, signal (S) pattern, etc. as a redistribution pattern. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, etc., such as a data signal. In addition, the first wiring layer 112 may serve as a via pad or the like as a pad pattern. As described above, since the first wiring layer 112 can perform the redistribution function, the first wiring layer 112 can share the redistribution function of the redistribution sections 140 and 150. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or their alloys can be used as the first wiring layer 112 materials. The thickness of the first wiring layer 112 is not particularly limited, but may be, for example, about 10 to 50 microns.

第二配線層132可安置於第二絕緣層111B的下表面110B上。亦即，第二配線層132可安置於框架110之外。此處，第二配線層132可安置於框架110之外的含義為第二配線層132不安置於框架110的上表面110A與下表面110B之間。第二配線層132亦可充當重新分配圖案及/或焊墊圖案。舉例而言，第二配線層132可充當接地圖案而作為重新分配圖案。此外，第二配線層132可充當通孔焊墊等而作為焊墊圖案。由於第二配線層132亦是在安 置電子元件120之前形成，因此第二配線層132可解決其中電子元件120的良率降低的問題。金屬層135的厚度及第二配線層132的厚度並無特別限制，但依設計特定細節而定可進行各種設計。舉例而言，金屬層135的厚度及第二配線層132的厚度可為10微米至50微米左右。 The second wiring layer 132 may be disposed on the lower surface 110B of the second insulating layer 111B. That is, the second wiring layer 132 may be disposed outside the frame 110. Here, the meaning that the second wiring layer 132 can be disposed outside the frame 110 means that the second wiring layer 132 is not disposed between the upper surface 110A and the lower surface 110B of the frame 110. The second wiring layer 132 may also serve as a redistribution pattern and/or a pad pattern. For example, the second wiring layer 132 may serve as a ground pattern as a redistribution pattern. In addition, the second wiring layer 132 may serve as a via pad or the like as a pad pattern. Because the second wiring layer 132 is also It is formed before the electronic component 120 is placed, so the second wiring layer 132 can solve the problem in which the yield of the electronic component 120 is reduced. The thickness of the metal layer 135 and the thickness of the second wiring layer 132 are not particularly limited, but various designs can be made depending on the specific details of the design. For example, the thickness of the metal layer 135 and the thickness of the second wiring layer 132 may be about 10-50 microns.

通孔113可將形成於不同的層上的第一配線層112及第二配線層132電性連接至彼此，藉此在電子元件封裝100A內形成電性路徑。通孔113可穿透過第二絕緣層111B。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作通孔113的材料。通孔113可被完全填充以傳導性材料。作為另一選擇，傳導性材料可沿通孔的壁形成。此外，通孔113可具有先前技術中所習知的所有形狀，例如其中通孔的直徑朝下表面變得更小的錐形形狀、其中通孔的直徑朝下表面變得更大的倒錐形形狀、圓柱形形狀等。 The through hole 113 may electrically connect the first wiring layer 112 and the second wiring layer 132 formed on different layers to each other, thereby forming an electrical path in the electronic component package 100A. The through hole 113 may penetrate through the second insulating layer 111B. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or alloys thereof can be used as the via 113 material. The through hole 113 may be completely filled with conductive material. Alternatively, the conductive material may be formed along the wall of the through hole. In addition, the through hole 113 may have all shapes known in the prior art, such as a tapered shape in which the diameter of the through hole becomes smaller toward the lower surface, and an inverted cone in which the diameter of the through hole becomes larger toward the lower surface Shape, cylindrical shape, etc.

金屬層135可安置於框架110的上表面110A上。金屬層135可為用於改善熱輻射特性及/或阻擋電磁波的附加元件，且金屬層135的材料並無特別限制，只要其為具有高熱傳導性的金屬即可。舉例而言，金屬層135的材料可為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金，但並非僅限於此。 The metal layer 135 may be disposed on the upper surface 110A of the frame 110. The metal layer 135 may be an additional element for improving heat radiation characteristics and/or blocking electromagnetic waves, and the material of the metal layer 135 is not particularly limited as long as it is a metal having high thermal conductivity. For example, the material of the metal layer 135 may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or an alloy thereof, But it is not limited to this.

電子元件120可為各種主動元件(例如，二極體、真空管、電晶體等)或被動元件(例如，電感器、電容器、電阻器等)。 作為另一選擇，電子元件120可為指示其中將數百至數百萬個或更多個組件整合於一起的晶片的積體電路(integrated circuit，IC)。若需要，則電子元件120可為其中將積體電路以覆晶(flip-chip)形式封裝的電子元件。所述積體電路可為例如中央處理器(例如，中央處理單元)、圖形處理器(例如，圖形處理單元)、數位訊號處理器、密碼學處理器、微處理器、微控制器等應用處理器晶片，但並非僅限於此。 The electronic component 120 may be various active components (eg, diodes, vacuum tubes, transistors, etc.) or passive components (eg, inductors, capacitors, resistors, etc.). As another option, the electronic component 120 may be an integrated circuit (IC) indicating a wafer in which hundreds to millions of components or more are integrated together. If necessary, the electronic component 120 may be an electronic component in which an integrated circuit is packaged in a flip-chip form. The integrated circuit may be application processing such as a central processor (eg, central processing unit), a graphics processor (eg, graphics processing unit), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc. Chip, but not limited to this.

電子元件120可具有在電子元件120的下表面上形成的電極焊墊120P。電極焊墊120P可將電子元件120電性連接至電子元件封裝內的另一元件或位於所述電子元件封裝之外的元件，且電極焊墊120P的材料並無特別限制，只要其為傳導性材料即可。所述傳導性材料可為銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金，但並非僅限於此。電極焊墊120P可藉由第一配線層112、第二配線層132、重新分配部140及150等而重新分配。電極焊墊120P可具有嵌置形式或突出形式。當電極焊墊120P具有嵌置形式時，電子元件120的下表面是其最外表面。當電極焊墊120P具有突出形式時，電子元件120的下表面是其供電極焊墊120P自其突出的表面。電子元件120的橫截面的厚度並無特別限制，且依電子元件120的類型而定可有所變化。舉例而言，在其中所述電子元件為積體電路的情形中，電子元件的厚度可為100微米至480微米左右，但並非僅限於此。 The electronic component 120 may have an electrode pad 120P formed on the lower surface of the electronic component 120. The electrode pad 120P can electrically connect the electronic component 120 to another component within the electronic component package or a component located outside the electronic component package, and the material of the electrode pad 120P is not particularly limited as long as it is conductive The material is sufficient. The conductive material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or an alloy thereof, but it is not limited to this. The electrode pad 120P can be redistributed by the first wiring layer 112, the second wiring layer 132, the redistribution portions 140 and 150, and the like. The electrode pad 120P may have an embedded form or a protruding form. When the electrode pad 120P has an embedded form, the lower surface of the electronic component 120 is its outermost surface. When the electrode pad 120P has a protruding form, the lower surface of the electronic component 120 is the surface from which the electrode pad 120P protrudes. The thickness of the cross section of the electronic component 120 is not particularly limited, and may vary depending on the type of the electronic component 120. For example, in the case where the electronic component is an integrated circuit, the thickness of the electronic component may be about 100 microns to 480 microns, but it is not limited to this.

在其中電子元件120為積體電路的情形中，所述電子元 件可具有主體(未由參考編號表示)、保護層(圖中未示出)、及電極焊墊120P。所述主體可基於例如主動晶圓而形成。在此種情形中，可使用矽(Si)、鍺(Ge)、砷化鎵(GaAs)等作為主體的基材(basic material)。所述保護層可用於保護主體不受外部因素影響，且可由例如氧化物層、氮化物層等形成，或者可由氧化物層與氮化物層形成的雙層形成。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作電極焊墊120P的材料。其上形成有電極焊墊120P的層可變為主動層。 In the case where the electronic component 120 is an integrated circuit, the electronic element The piece may have a main body (not represented by a reference number), a protective layer (not shown in the figure), and an electrode pad 120P. The body may be formed based on, for example, an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like can be used as a basic material for the main body. The protective layer may be used to protect the body from external factors, and may be formed of, for example, an oxide layer, a nitride layer, or the like, or may be formed of a double layer formed of an oxide layer and a nitride layer. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or their alloys can be used as electrode pads 120P s material. The layer on which the electrode pad 120P is formed may become an active layer.

第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖3中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於金屬層135的上表面下、或者位於與金屬層135的上表面相同的位階處或位於金屬層135的上表面之上，只要金屬層135及電子元件120均被囊封劑160覆蓋即可。 At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 3, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 with respect to the redistribution portions 140 and 150 or above the upper surface 110A of the frame 110 but below the upper surface of the metal layer 135, or between The upper surface of the metal layer 135 is at the same level or above the upper surface of the metal layer 135, as long as the metal layer 135 and the electronic component 120 are covered by the encapsulant 160.

使用重新分配部140及150的目的可為基本重新分配電子元件120的電極焊墊120P。具有各種功能的數十至數百個電極焊墊120P可藉由重新分配部140及150而重新分配，且依其功能而定，可藉由以下將闡述的第一外部連接端子175而物理地連接 至及/或電性連接至外部。重新分配部140及150可連接至電子元件120。亦即，重新分配部140及150可支撐電子元件120。 The purpose of using the redistribution parts 140 and 150 may be to substantially redistribute the electrode pads 120P of the electronic component 120. Dozens to hundreds of electrode pads 120P with various functions can be redistributed by the redistribution parts 140 and 150, and depending on their functions, they can be physically relied on by the first external connection terminal 175, which will be explained below connection To and/or electrically connected to the outside. The redistribution parts 140 and 150 may be connected to the electronic component 120. That is, the redistribution portions 140 and 150 can support the electronic component 120.

重新分配部140及150可包括交替地堆疊於一起的重新分配部絕緣層141及151與重新分配部配線層142及152，以及穿透過重新分配部絕緣層141及151以藉此分別電性連接至重新分配部配線層142及152的重新分配部通孔143及153。儘管重新分配部140及150分別是由多個層形成，然而在根據實例的電子元件封裝100A中，重新分配部140及150並非僅限於此，且依電子元件120的類型而定可不同於圖式中所示而分別由單個層形成。作為另一選擇，重新分配部亦可由較所述多個層更多的層形成。 The redistribution portions 140 and 150 may include redistribution portion insulation layers 141 and 151 and redistribution portion wiring layers 142 and 152 alternately stacked together, and penetrate through the redistribution portion insulation layers 141 and 151 to thereby be electrically connected respectively The redistribution part through holes 143 and 153 to the redistribution part wiring layers 142 and 152. Although the redistribution portions 140 and 150 are respectively formed of multiple layers, in the electronic component package 100A according to the example, the redistribution portions 140 and 150 are not limited to this, and may differ from the figure depending on the type of the electronic component 120 They are each formed by a single layer as shown in the formula. As another option, the redistribution portion may be formed of more layers than the plurality of layers.

重新分配部絕緣層141及151的材料亦無特別限制，只要其為絕緣材料即可，舉例而言，所述絕緣材料為：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；具有例如浸入於所述熱固性樹脂及所述熱塑性樹脂中的玻璃纖維或無機填料等加強材料的樹脂，例如預浸體、味之素構成膜、FR-4、雙馬來醯亞胺三嗪等。在其中使用例如感光成像介電樹脂等感光性絕緣材料作為重新分配部絕緣層141及151的材料的情形中，重新分配部絕緣層141及151可被形成為具有減小的厚度，且可易於實作精細節距。若需要，則重新分配部絕緣層141及151的材料可彼此相同或可彼此不同。重新分配部絕緣層141及151的厚度亦無特別限制。舉例而言，重新分配部絕緣層141及151的除重新分配部配線層142及152以外的厚度可為約5微米至20微米左右， 且當慮及重新分配部配線層142及152的厚度時，重新分配部絕緣層141及151的厚度可為約15微米至70微米左右。 The material of the insulating layers 141 and 151 of the redistribution section is also not particularly limited, as long as it is an insulating material, for example, the insulating material is: thermosetting resin, such as epoxy resin; thermoplastic resin, such as polyimide resin ; Resins with reinforcing materials such as glass fibers or inorganic fillers immersed in the thermosetting resin and the thermoplastic resin, such as prepregs, Ajinomoto film, FR-4, bismaleimide triazine Wait. In the case where a photosensitive insulating material such as a photosensitive imaging dielectric resin is used as the material of the redistribution portion insulating layers 141 and 151, the redistribution portion insulating layers 141 and 151 can be formed to have a reduced thickness, and can be easily Implement fine detail. If necessary, the materials of the redistribution portion insulating layers 141 and 151 may be the same as each other or may be different from each other. The thickness of the insulating layers 141 and 151 of the redistribution part is also not particularly limited. For example, the thickness of the redistribution portion insulating layers 141 and 151 except the redistribution portion wiring layers 142 and 152 may be about 5 to 20 microns, And when considering the thickness of the redistribution portion wiring layers 142 and 152, the thickness of the redistribution portion insulation layers 141 and 151 may be about 15 to 70 microns.

重新分配部配線層142及152亦可充當重新分配圖案及/或焊墊圖案，且例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作重新分配部配線層142及152的材料。依對應層的設計而定，重新分配部配線層142及152可執行各種功能。舉例而言，重新分配部配線層142及152可充當接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等而作為重新分配圖案。此處，訊號(S)圖案可包括除接地(GND)圖案、功率(PWR)圖案等以外的各種訊號，例如資料訊號等。此外，重新分配部配線層142及152可充當通孔焊墊、外部連接端子焊墊等而作為焊墊圖案。重新分配部配線層142及152的厚度亦無特別限制，且可為例如約10微米至50微米左右。若需要，則可在重新分配部配線層152的被暴露出的圖案上形成表面處理層。所述表面處理層並無特別限制，只要其為先前技術中所習知者即可，且可藉由例如電解鍍金、無電鍍金、有機可焊性保護劑(organic solderability preservative，OSP)、或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金(substituted gold plating)、直接浸金(direct immersion gold，DIG)鍍覆、熱空氣焊料均塗(hot air solder leveling，HASL)等而形成。 The redistribution portion wiring layers 142 and 152 may also serve as redistribution patterns and/or pad patterns, and for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel ( Conductive materials such as Ni), lead (Pb), or their alloys can be used as the material for the redistribution portion wiring layers 142 and 152. Depending on the design of the corresponding layer, the redistribution section wiring layers 142 and 152 can perform various functions. For example, the redistribution portion wiring layers 142 and 152 may serve as a redistribution pattern as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and so on. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, etc., such as a data signal. In addition, the redistribution portion wiring layers 142 and 152 may serve as via pads, external connection terminal pads, and the like as pad patterns. The thickness of the redistribution portion wiring layers 142 and 152 is also not particularly limited, and may be, for example, about 10 to 50 microns. If necessary, a surface treatment layer may be formed on the exposed pattern of the redistribution portion wiring layer 152. The surface treatment layer is not particularly limited as long as it is known in the prior art, and may be, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP), or It is formed by electroless tin, electroless silver, electroless nickel/substituted gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), etc.

重新分配部通孔143及153可將第二配線層132、重新分配部配線層142及152與形成於不同的層上的電極焊墊120P電性 連接至彼此，藉此在電子元件封裝100A內形成電性路徑。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作重新分配部通孔143及153的材料。重新分配部通孔143及153亦可被完全填充以傳導性材料。作為另一選擇，可沿重新分配部通孔143及153的壁形成傳導性材料。此外，重新分配部通孔143及153可具有先前技術中所習知的所有形狀，例如其中通孔的直徑朝下表面變得更小的錐形形狀、其中通孔(via)的直徑朝下表面變得更大的倒錐形形狀、圓柱形形狀等。 The redistribution portion through holes 143 and 153 can electrically connect the second wiring layer 132, the redistribution portion wiring layers 142 and 152 and the electrode pads 120P formed on different layers Connect to each other, thereby forming an electrical path within the electronic component package 100A. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or their alloys can be used as redistribution Material of holes 143 and 153. The redistribution portion through holes 143 and 153 may also be completely filled with conductive material. Alternatively, a conductive material may be formed along the walls of the redistribution portion through holes 143 and 153. In addition, the redistribution portion through holes 143 and 153 may have all shapes known in the prior art, such as a tapered shape in which the diameter of the through hole becomes smaller toward the lower surface, and in which the diameter of the through hole (via) is downward Inverted conical shape, cylindrical shape, etc. whose surface becomes larger.

重新分配部140及150可將框架110與電子元件120連接至彼此。此處，框架110與電子元件120經由重新分配部140及150而連接至彼此的含義為框架110與電子元件120彼此間隔開，但重新分配部140及150連接至框架110與電子元件120兩者，且因此框架110與電子元件120經由重新分配部140及150而連接至彼此。 The redistribution portions 140 and 150 may connect the frame 110 and the electronic component 120 to each other. Here, the connection of the frame 110 and the electronic component 120 to each other via the redistribution sections 140 and 150 means that the frame 110 and the electronic component 120 are spaced apart from each other, but the redistribution sections 140 and 150 are connected to both the frame 110 and the electronic component 120 , And therefore the frame 110 and the electronic component 120 are connected to each other via the redistribution parts 140 and 150.

框架110可經由旁路(bypass)而電性連接至電子元件120。重新分配部140及150可直接電性連接至電子元件120。亦即，由於框架110位於電子元件的側部部分處，因此其可經由重新分配部140及150而電性連接至電子元件120。亦即，框架110的第一配線層112及第二配線層132可經由重新分配部140及150而電性連接至電子元件120，且重新分配部140及150可直接電性連接至電子元件120。框架110的第一配線層112及第二配線層 132可不直接電性連接至電子元件120。 The frame 110 may be electrically connected to the electronic component 120 via a bypass. The redistribution parts 140 and 150 can be directly electrically connected to the electronic component 120. That is, since the frame 110 is located at the side portion of the electronic component, it can be electrically connected to the electronic component 120 through the redistribution portions 140 and 150. That is, the first wiring layer 112 and the second wiring layer 132 of the frame 110 may be electrically connected to the electronic component 120 through the redistribution portions 140 and 150, and the redistribution portions 140 and 150 may be directly electrically connected to the electronic component 120 . The first wiring layer 112 and the second wiring layer of the frame 110 132 may not be directly electrically connected to the electronic component 120.

使用囊封劑160的目的可為保護電子元件120。為此，囊封劑160可囊封框架110的及電子元件120的至少部分。囊封形式並無特別限制，但可為封閉電子元件120的形式。舉例而言，囊封劑160可覆蓋電子元件120，且可設置於框架110的貫穿孔110X內的其餘空間中。此外，囊封劑160亦可覆蓋框架110。囊封劑160可設置於貫穿孔110X中，藉此在充當黏合劑的同時用於減少電子元件120的屈曲(buckling)。囊封劑160可覆蓋電子元件120的除電子元件120的下表面以外的所有表面。依電子元件120的電極焊墊120P的突出形式而定，囊封劑160可覆蓋電子元件120的下表面的僅一部分。 The purpose of using the encapsulant 160 may be to protect the electronic component 120. To this end, the encapsulant 160 may encapsulate at least part of the frame 110 and the electronic component 120. The form of the encapsulation is not particularly limited, but may be a form in which the electronic component 120 is enclosed. For example, the encapsulant 160 may cover the electronic component 120 and may be disposed in the remaining space in the through hole 110X of the frame 110. In addition, the encapsulant 160 can also cover the frame 110. The encapsulant 160 may be disposed in the through-hole 110X, thereby serving to reduce buckling of the electronic component 120 while acting as an adhesive. The encapsulant 160 may cover all surfaces of the electronic component 120 except the lower surface of the electronic component 120. Depending on the protruding form of the electrode pad 120P of the electronic component 120, the encapsulant 160 may cover only a part of the lower surface of the electronic component 120.

囊封劑160可包括由多個材料形成的多個層。舉例而言，貫穿孔110X內的空間可被填充以第一囊封劑，且框架110及電子元件120可被覆蓋以第二囊封劑。作為另一選擇，可在使用第一囊封劑填充貫穿孔110X內的空間的同時以預定厚度覆蓋框架110及電子元件120，且可在第一囊封劑上再次以預定厚度覆蓋第二囊封劑。除上述形式以外，亦可使用各種形式。被填充以囊封劑160的貫穿孔110X內的空間的間距並無特別限制，且可被熟習此項技術者最佳化。舉例而言，被填充以囊封劑160的貫穿孔110X內的空間的間距可為約10微米至150微米左右，但並非僅限於此。 The encapsulant 160 may include multiple layers formed of multiple materials. For example, the space inside the through hole 110X may be filled with the first encapsulant, and the frame 110 and the electronic component 120 may be covered with the second encapsulant. As another option, the frame 110 and the electronic component 120 may be covered with a predetermined thickness while filling the space in the through hole 110X with the first encapsulant, and the second bladder may be covered with the predetermined thickness on the first encapsulant again Sealant. In addition to the above forms, various forms can also be used. The pitch of the space in the through hole 110X filled with the encapsulant 160 is not particularly limited, and can be optimized by those skilled in the art. For example, the pitch of the space in the through hole 110X filled with the encapsulant 160 may be about 10 μm to 150 μm, but it is not limited to this.

囊封劑160的詳細材料並無特別限制。舉例而言，可使用絕緣材料作為囊封劑160的材料。此處，所述絕緣材料可為： 熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；具有例如浸入於所述熱固性樹脂及所述熱塑性樹脂中的玻璃纖維及/或無機填料等加強材料的樹脂，例如預浸體、味之素構成膜等。此外，亦可使用例如環氧樹脂模製化合物等習知的模製材料。使用例如玻璃纖維及/或無機填料等絕緣樹脂作為囊封劑160的材料可更有效地控制翹曲。 The detailed material of the encapsulant 160 is not particularly limited. For example, an insulating material may be used as the material of the encapsulant 160. Here, the insulating material may be: Thermosetting resins such as epoxy resins; thermoplastic resins such as polyimide resins; resins with reinforcing materials such as glass fibers and/or inorganic fillers impregnated in the thermosetting resins and the thermoplastic resins, such as prepregs , Ajinomoto constitutes a film, etc. In addition, conventional molding materials such as epoxy resin molding compounds can also be used. Using an insulating resin such as glass fiber and/or inorganic filler as the material of the encapsulant 160 can more effectively control warpage.

囊封劑160可具有較框架110的第一絕緣層111A的材料低的彈性模量。舉例而言，囊封劑160的彈性模量可為15千兆帕(GPa)或小於15千兆帕，例如為50兆帕至15千兆帕左右。隨著囊封劑160的彈性模量變得相對小，電子元件封裝100A的翹曲可藉由對電子元件120的屈曲效應(buckling effect)及應力分散效應(stress dispersing effect)而減少。詳言之，由於囊封劑160設置於貫穿孔110X的空間中，因此囊封劑160可對電子元件120具有屈曲效應，且由於囊封劑160覆蓋電子元件120，因此囊封劑160可分散並減輕在電子元件120中產生的應力。然而，在其中囊封劑160的彈性模量過度小的情形中，囊封劑160可過度變形，且因此囊封劑160可能無法發揮囊封劑的基本作用。所述彈性模量被定義為應力與變形之間的比率，且可藉由KS M 3001、KS M 527-3、ASTM D882等中規定的張力試驗來量測。 The encapsulant 160 may have a lower elastic modulus than the material of the first insulating layer 111A of the frame 110. For example, the elastic modulus of the encapsulant 160 may be 15 gigapascals (GPa) or less, for example, about 50 gigapascals to 15 gigapascals. As the elastic modulus of the encapsulant 160 becomes relatively small, the warpage of the electronic device package 100A can be reduced by the buckling effect and stress dispersing effect on the electronic device 120. In detail, since the encapsulant 160 is disposed in the space of the through hole 110X, the encapsulant 160 may have a buckling effect on the electronic component 120, and since the encapsulant 160 covers the electronic component 120, the encapsulant 160 may be dispersed And reduce the stress generated in the electronic component 120. However, in the case where the elastic modulus of the encapsulating agent 160 is excessively small, the encapsulating agent 160 may be excessively deformed, and therefore the encapsulating agent 160 may not be able to exert the basic function of the encapsulating agent. The elastic modulus is defined as the ratio between stress and deformation, and can be measured by a tensile test specified in KS M 3001, KS M 527-3, ASTM D882, and the like.

若需要，則囊封劑160可含有傳導性粒子以阻擋電磁波。舉例而言，所述傳導性粒子可為可阻擋電磁波的任意材料，例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛 (Pb)、焊料等，但並非特別地限定於此。 If necessary, the encapsulant 160 may contain conductive particles to block electromagnetic waves. For example, the conductive particles can be any material that can block electromagnetic waves, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, etc., but it is not particularly limited thereto.

根據實例的電子元件封裝100A可更包括安置於重新分配部140及150下的保護層170。使用保護層170的目的可為保護重新分配部140及150不受外部的物理或化學損害等。保護層170可具有第一開口部171，第一開口部171暴露出重新分配部140及150的重新分配部配線層152的至少部分。儘管第一開口部171可暴露出重新分配部配線層152的上表面的部分，然而在某些情形中第一開口部171亦可暴露出重新分配部配線層152的側表面。 The electronic component package 100A according to the example may further include a protective layer 170 disposed under the redistribution parts 140 and 150. The purpose of using the protective layer 170 may be to protect the redistribution portions 140 and 150 from external physical or chemical damage and the like. The protective layer 170 may have a first opening 171 that exposes at least a portion of the redistribution portion wiring layer 152 of the redistribution portions 140 and 150. Although the first opening portion 171 may expose a portion of the upper surface of the redistribution portion wiring layer 152, the first opening portion 171 may also expose the side surface of the redistribution portion wiring layer 152 in some cases.

保護層170的材料並無特別限制。舉例而言，可使用阻焊劑(solder resist)作為保護層170的材料。此外，可使用與框架110的第二絕緣層111B及/或重新分配部140及150的重新分配部絕緣層141及151相同的材料(例如，同一種感光成像介電樹脂、味之素構成膜等)作為保護層170的材料。保護層170一般而言為單個層，但若需要，則亦可由多個層形成。使用味之素構成膜作為保護層170的材料可有效地提高所述電子元件封裝的可靠性。 The material of the protective layer 170 is not particularly limited. For example, solder resist can be used as the material of the protective layer 170. In addition, the same material as the second insulating layer 111B of the frame 110 and/or the redistribution portion insulating layers 141 and 151 of the redistribution portions 140 and 150 (for example, the same photosensitive imaging dielectric resin and Ajinomoto can be used to form the film Etc.) as the material of the protective layer 170. The protective layer 170 is generally a single layer, but if necessary, it may be formed of multiple layers. The use of the Ajinomoto film as the material of the protective layer 170 can effectively improve the reliability of the electronic component package.

根據實例的電子元件封裝100A可更包括安置於保護層170的第一開口部171中以藉此暴露於外部的第一外部連接端子175。使用第一外部連接端子175的目的可為將電子元件封裝100A物理地連接至及/或電性連接至外部。舉例而言，電子元件封裝100A可藉由第一外部連接端子175而安裝於所述電子元件的主板上。第一外部連接端子175可安置於第一開口部171中，並可連 接至經由第一開口部171而暴露出的重新分配部配線層152。因而，第一外部連接端子175亦可電性連接至電子元件120。 The electronic component package 100A according to the example may further include a first external connection terminal 175 disposed in the first opening portion 171 of the protective layer 170 to thereby be exposed to the outside. The purpose of using the first external connection terminal 175 may be to physically and/or electrically connect the electronic component package 100A to the outside. For example, the electronic component package 100A can be mounted on the motherboard of the electronic component through the first external connection terminal 175. The first external connection terminal 175 may be placed in the first opening portion 171 and may be connected It is connected to the redistribution wiring layer 152 exposed through the first opening 171. Therefore, the first external connection terminal 175 can also be electrically connected to the electronic component 120.

第一外部連接端子175可由例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、焊料等傳導性材料形成，但並非特別地限定於此。第一外部連接端子175可為焊盤(land)、球、引腳等。第一外部連接端子175可由多個層或單個層形成。在其中第一外部連接端子175由多個層形成的情形中，第一外部連接端子175可含有銅柱及焊料，而在其中第一外部連接端子175由單個層形成的情形中，第一外部連接端子175可含有錫-銀焊料或銅。然而，此僅為實例，且第一外部連接端子175並非僅限於此。 The first external connection terminal 175 may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, etc. However, it is not particularly limited to this. The first external connection terminal 175 may be a land, a ball, a pin, or the like. The first external connection terminal 175 may be formed of multiple layers or a single layer. In the case where the first external connection terminal 175 is formed of multiple layers, the first external connection terminal 175 may contain copper pillars and solder, and in the case where the first external connection terminal 175 is formed of a single layer, the first external The connection terminal 175 may contain tin-silver solder or copper. However, this is only an example, and the first external connection terminal 175 is not limited to this.

第一外部連接端子175中的至少一者可安置於扇出區中。所述扇出區被定義為除其中安置有所述電子元件的區以外的區。亦即，根據實例的電子元件封裝100A可為扇出式封裝。所述扇出式封裝可具有較扇入式封裝高的可靠性、可實作多個I/O端子、且可易於執行3D互連。此外，由於扇出式封裝相較於球柵陣列(ball grid array，BGA)封裝、焊盤柵陣列(land grid array，LGA)封裝等而言可無需使用獨立的基板而安裝於所述電子裝置上，因此所述扇出式封裝可被製造成具有減小的厚度，且可具有優異的價格競爭力。 At least one of the first external connection terminals 175 may be disposed in the fan-out area. The fan-out area is defined as an area other than the area in which the electronic component is disposed. That is, the electronic component package 100A according to the example may be a fan-out package. The fan-out package can have higher reliability than the fan-in package, can implement multiple I/O terminals, and can easily perform 3D interconnection. In addition, the fan-out package can be mounted on the electronic device without using a separate substrate compared to ball grid array (BGA) package, land grid array (LGA) package, etc. Therefore, the fan-out package can be manufactured to have a reduced thickness, and can have excellent price competitiveness.

第一外部連接端子175的數目、間距、配置形式等並無特別限制，且可由熟習此項技術者依設計特定細節充分地進行修 改。舉例而言，依電子元件120的電極焊墊120P的數目而定，第一外部連接端子175的數目可為數十至數千個。然而，第一外部連接端子175的數目並非僅限於此，且亦可為幾十至幾千個或更多個、或者幾十至幾千個或更少個。 The number, spacing, and configuration of the first external connection terminals 175 are not particularly limited, and can be sufficiently repaired by those skilled in the art according to specific design details change. For example, depending on the number of electrode pads 120P of the electronic component 120, the number of the first external connection terminals 175 may be tens to thousands. However, the number of the first external connection terminals 175 is not limited to this, and may be tens to thousands or more, or tens to thousands or less.

圖5A至圖5L是說明製造電子元件封裝100A的製程的實例的示意圖。 5A to 5L are schematic diagrams illustrating an example of the manufacturing process of the electronic component package 100A.

參照圖5A，可製備第一絕緣層111A。可以各種尺寸來製造及使用第一絕緣層111A，以便於大量生產。亦即，在製備出具有大尺寸的第一絕緣層111A之後，可藉由以下將闡述的製程來製造多個電子元件封裝100A。接著，可藉由鋸切(sawing)製程而將所述多個電子元件封裝100A分割成獨立的單位封裝。若需要，則可在第一絕緣層111A中呈現優異拾取及放置(pick-and-place，P&P)的基準標記(fiducial mark)。由於安裝有電子元件120的位置可藉由所述基準標記而更清楚地辨識，因此可提高製造的完整性。例如敷銅積層板(copper clad laminate，CCL)(未由參考編號表示)等薄金屬層可形成於第一絕緣層111A的上表面及下表面上，並可在後續製程中充當用於形成配線層等的基礎晶種層。 Referring to FIG. 5A, a first insulating layer 111A may be prepared. The first insulating layer 111A can be manufactured and used in various sizes to facilitate mass production. That is, after the first insulating layer 111A having a large size is prepared, a plurality of electronic component packages 100A can be manufactured by the process described below. Then, the plurality of electronic component packages 100A can be divided into independent unit packages by a sawing process. If necessary, fiducial marks of excellent pick-and-place (P&P) can be presented in the first insulating layer 111A. Since the position where the electronic component 120 is mounted can be more clearly identified by the reference mark, the manufacturing integrity can be improved. For example, a thin metal layer such as a copper clad laminate (CCL) (not represented by a reference number) can be formed on the upper and lower surfaces of the first insulating layer 111A, and can be used to form wiring in subsequent processes The basic seed layer of layers.

參照圖5B，可在第一絕緣層111A的上表面及下表面上分別形成金屬層135及第一配線層112。可藉由習知的方法來形成金屬層135及第一配線層112。舉例而言，可使用乾膜圖案(dry film pattern)藉由電解鍍銅、無電鍍銅等來形成金屬層135及第一配線層112。更詳言之，可使用例如化學氣相沈積(chemical vapor deposition，CVD)、物理氣相沈積(physical vapor deposition，PVD)、濺鍍、減性製程、加性製程、半加性製程(semi-additive process，SAP)、經修改半加性製程(modified semi-additive process，MSAP)等方法來形成金屬層135及第一配線層112，但並非僅限於此。 Referring to FIG. 5B, a metal layer 135 and a first wiring layer 112 may be formed on the upper and lower surfaces of the first insulating layer 111A, respectively. The metal layer 135 and the first wiring layer 112 can be formed by a conventional method. For example, a dry film pattern may be used to form the metal layer 135 and the first wiring layer 112 by electrolytic copper plating, electroless copper plating, or the like. More specifically, for example, chemical vapor deposition (chemical vapor deposition) deposition, CVD), physical vapor deposition (PVD), sputtering, subtractive process, additive process, semi-additive process (semi-additive process, SAP), modified semi-additive process (modified semi -an additive process (MSAP) method to form the metal layer 135 and the first wiring layer 112, but it is not limited to this.

參照圖5C，可在第一絕緣層111A的下表面上形成第二絕緣層111B。亦可藉由習知的方法來形成第二絕緣層111B。舉例而言，可藉由將第二絕緣層111B的前驅物積層於第一絕緣層111A的下表面上並接著硬化所述前驅物的方法、將用於形成第二絕緣層111B的材料施加至第一絕緣層111A的下表面上並接著硬化所述材料的方法等來形成第二絕緣層111B，但並非僅限於此。可使用例如以下方法等作為積層所述前驅物的方法：執行在高溫下對前驅物壓製預定時間的熱壓製(hot press)製程、對所述前驅物進行減壓、並且接著將所述前驅物冷卻至室溫、在冷壓製(cold press)製程中冷卻所述前驅物、並且接著分離作業工具。可使用例如利用刮板(squeegee)施加油墨的網版印刷方法、以霧形式施加油墨的噴霧印刷方法等作為施加所述材料的方法。所述硬化製程-其為後置製程-可為使材料乾燥以不被完全硬化從而使用光刻(photolithography)方法等的製程。 Referring to FIG. 5C, a second insulating layer 111B may be formed on the lower surface of the first insulating layer 111A. The second insulating layer 111B can also be formed by a conventional method. For example, the material for forming the second insulating layer 111B may be applied to the second insulating layer 111B by stacking the precursor of the second insulating layer 111B on the lower surface of the first insulating layer 111A and then hardening the precursor The second insulating layer 111B is formed on the lower surface of the first insulating layer 111A and then hardened the material, etc., but it is not limited to this. For example, the following method may be used as a method of laminating the precursor: performing a hot press process for pressing the precursor at a high temperature for a predetermined time, depressurizing the precursor, and then applying the precursor Cool to room temperature, cool the precursor in a cold press process, and then separate the work tool. As the method of applying the material, for example, a screen printing method of applying ink using a squeegee, a spray printing method of applying ink in the form of mist, or the like can be used. The hardening process, which is a post-process, may be a process in which the material is dried so as not to be completely hardened to use a photolithography method or the like.

參照圖5D，可在第二絕緣層111B之下形成第二配線層132，且可在第二絕緣層111B中形成通孔113。可使用機械鑽孔及/或雷射鑽孔來形成通孔洞(圖中未示出)。此處，所述雷射鑽孔可 為CO2雷射或YAG雷射，但並非僅限於此。在其中使用機械鑽孔及/或雷射鑽孔形成通孔洞(圖中未示出)的情形中，可對通孔洞(via hole)執行除汙製程，以移除通孔洞(圖中未示出)中的樹脂污垢。可使用例如高錳酸鹽方法來執行所述除汙製程。在其中第二絕緣層111B含有感光成像介電樹脂等的情形中，亦可藉由光刻方法來形成通孔洞。在通孔洞形成之後，亦可使用乾膜圖案而藉由電解鍍銅、無電鍍銅等來形成第二配線層132及通孔113。更詳言之，可使用例如化學氣相沈積、物理氣相沈積、濺鍍、減性製程、加性製程、半加性製程、經修改半加性製程等方法來形成第二配線層132及通孔113，但並非僅限於此。 Referring to FIG. 5D, a second wiring layer 132 may be formed under the second insulating layer 111B, and a through hole 113 may be formed in the second insulating layer 111B. Through holes can be formed using mechanical drilling and/or laser drilling (not shown). Here, the laser borehole may be a CO 2 laser or a YAG laser, but it is not limited to this. In the case where mechanical drilling and/or laser drilling are used to form a via hole (not shown in the figure), a decontamination process may be performed on the via hole to remove the via hole (not shown in the figure) Out) in the resin dirt. The decontamination process can be performed using, for example, a permanganate method. In the case where the second insulating layer 111B contains a photosensitive imaging dielectric resin or the like, the via hole can also be formed by a photolithography method. After the formation of the via hole, the second wiring layer 132 and the via hole 113 may also be formed by electrolytic copper plating, electroless copper plating, etc. using a dry film pattern. More specifically, methods such as chemical vapor deposition, physical vapor deposition, sputtering, subtractive process, additive process, semi-additive process, modified semi-additive process, etc. may be used to form the second wiring layer 132 and Through hole 113, but not limited to this.

參照圖5E，可形成穿透過框架110的上表面110A及下表面110B的貫穿孔110X。形成貫穿孔110X的方法亦無特別限制。可藉由例如機械鑽孔及/或雷射鑽孔、使用研磨顆粒的噴砂方法、使用電漿的乾式蝕刻方法等來形成貫穿孔110X。同樣地，在其中使用機械鑽孔及/或雷射鑽孔來形成貫穿孔110X情形中，可執行例如高錳酸鹽方法等除汙製程，以移除貫穿孔110X中的樹脂污垢。可根據欲安裝的電子元件120的尺寸、形狀、數目等來設計貫穿孔110X的尺寸、形狀等。可藉由一系列製程來形成具有貫穿孔110X的框架110。 Referring to FIG. 5E, a through hole 110X may be formed through the upper surface 110A and the lower surface 110B of the frame 110. The method of forming the through hole 110X is also not particularly limited. The through hole 110X may be formed by, for example, mechanical drilling and/or laser drilling, a sandblasting method using abrasive particles, a dry etching method using plasma, or the like. Likewise, in the case where mechanical drilling and/or laser drilling is used to form the through hole 110X, a decontamination process such as a permanganate method may be performed to remove resin dirt in the through hole 110X. The size, shape, etc. of the through hole 110X may be designed according to the size, shape, number, etc. of the electronic component 120 to be mounted. The frame 110 having the through hole 110X can be formed through a series of processes.

參照圖5F，可將黏合膜190貼附至第二配線層132。可使用可固定第二配線層132的任意材料作為黏合膜190。作為此材料的非限制性實例，可使用此項技術中習知的膠帶等。所述習知 膠帶的實例可包括其黏度被熱處理弱化的熱固性黏合膠帶、其黏度被紫外線輻射弱化的可紫外光固化的黏合膠帶等。 Referring to FIG. 5F, the adhesive film 190 may be attached to the second wiring layer 132. Any material that can fix the second wiring layer 132 can be used as the adhesive film 190. As a non-limiting example of this material, tape and the like conventionally known in the art can be used. The knowledge Examples of the adhesive tape may include thermosetting adhesive tape whose viscosity is weakened by heat treatment, ultraviolet-curable adhesive tape whose viscosity is weakened by ultraviolet radiation, and the like.

參照圖5G，可在貫穿孔110X中安置電子元件120。詳言之，可將電子元件120貼附至並安置於經由框架110的貫穿孔110X而暴露出的黏合膜190上。電子元件120可被安置成面朝下的形式，從而使電極焊墊120P貼附至黏合膜190。在其中電子元件120的電極焊墊120P具有嵌置形式的情形中，電子元件120的下表面與第二配線層132的下表面可實質上彼此共面。舉例而言，電子元件120的下表面與第二配線層132的下表面之間的距離可小於第二配線層132的厚度。在其中電子元件120的電極焊墊120P具有突出形式的情形中，第二配線層132的下表面與電極焊墊120P的下表面可實質上彼此共面。舉例而言，第二配線層132的下表面與電極焊墊120P的下表面之間的距離可小於第二配線層132的厚度。 Referring to FIG. 5G, the electronic component 120 may be disposed in the through hole 110X. In detail, the electronic component 120 may be attached to and disposed on the adhesive film 190 exposed through the through hole 110X of the frame 110. The electronic component 120 may be arranged in a face-down manner, so that the electrode pad 120P is attached to the adhesive film 190. In the case where the electrode pad 120P of the electronic component 120 has an embedded form, the lower surface of the electronic component 120 and the lower surface of the second wiring layer 132 may be substantially coplanar with each other. For example, the distance between the lower surface of the electronic component 120 and the lower surface of the second wiring layer 132 may be smaller than the thickness of the second wiring layer 132. In the case where the electrode pad 120P of the electronic component 120 has a protruding form, the lower surface of the second wiring layer 132 and the lower surface of the electrode pad 120P may be substantially coplanar with each other. For example, the distance between the lower surface of the second wiring layer 132 and the lower surface of the electrode pad 120P may be smaller than the thickness of the second wiring layer 132.

參照圖5H，可使用囊封劑160對電子元件120進行囊封。囊封劑160可覆蓋框架110及電子元件120，且可設置於貫穿孔110X內的空間中。可藉由習知的方法來形成囊封劑160。舉例而言，可藉由對囊封劑160的前驅物進行積層並接著硬化所述前驅物的方法來形成囊封劑160。作為另一選擇，可藉由將前體囊封劑施加至黏合膜190上以囊封電子元件120並接著硬化所述前驅囊封劑的方法來形成囊封劑160。可藉由所述硬化來固定電子元件120。可使用例如以下方法等作為積層所述前驅物的方法：執行在 高溫下對前驅物壓製預定時間的熱壓製製程、對所述前驅物進行減壓、並且接著將所述前驅物冷卻至室溫、在冷壓製製程中冷卻所述前驅物、並且接著分離作業工具。可使用例如利用刮板施加油墨的網版印刷方法、以霧形式施加油墨的噴霧印刷方法等作為施加所述前驅囊封劑的方法。 Referring to FIG. 5H, the encapsulant 160 may be used to encapsulate the electronic component 120. The encapsulant 160 may cover the frame 110 and the electronic component 120, and may be disposed in the space within the through hole 110X. The encapsulant 160 can be formed by a conventional method. For example, the encapsulant 160 may be formed by laminating the precursor of the encapsulant 160 and then hardening the precursor. Alternatively, the encapsulant 160 may be formed by a method of applying a precursor encapsulant to the adhesive film 190 to encapsulate the electronic component 120 and then hardening the precursor encapsulant. The electronic component 120 can be fixed by the hardening. For example, the following method can be used as a method for stacking the precursor: A hot pressing process for pressing the precursor at a high temperature for a predetermined time, depressurizing the precursor, and then cooling the precursor to room temperature, cooling the precursor in the cold pressing process, and then separating the working tool . As the method of applying the precursor encapsulant, for example, a screen printing method of applying ink using a squeegee, a spray printing method of applying ink in the form of mist, or the like can be used.

參照圖5I，可剝除黏合膜190。剝除黏合膜190的方法並無特別限制，且可為習知的方法。舉例而言，在其中使用其黏度被熱處理弱化的熱固性黏合膠帶、其黏度被紫外線輻射弱化的可紫外光固化黏合膠帶等作為黏合膜190的情形中，可在黏合膜190的黏度藉由對黏合膜190進行的熱處理而弱化之後剝除黏合膜190，或者可在黏合膜190的黏度藉由利用紫外線對黏合膜190進行的輻射而弱化之後剝除黏合膜190。 5I, the adhesive film 190 can be peeled off. The method of peeling the adhesive film 190 is not particularly limited, and may be a conventional method. For example, in the case where a thermosetting adhesive tape whose viscosity is weakened by heat treatment, an ultraviolet curable adhesive tape whose viscosity is weakened by ultraviolet radiation, or the like is used as the adhesive film 190, the viscosity of the adhesive film 190 can be bonded by The adhesive film 190 is peeled off after the heat treatment of the film 190 is weakened, or the adhesive film 190 may be peeled off after the viscosity of the adhesive film 190 is weakened by irradiation of the adhesive film 190 with ultraviolet rays.

參照圖5J，可在框架110及電子元件120下首先形成重新分配部絕緣層141，並可形成重新分配部配線層142及重新分配部通孔143，以形成重新分配部140。接下來，可在重新分配部絕緣層141下再次形成重新分配部絕緣層151，並可形成重新分配部配線層152及重新分配部通孔153，以形成重新分配部150。形成重新分配部140及150的詳細方法相同於上述方法。重新分配部絕緣層141與囊封劑160之間的介面可和第二配線層132的下表面實質上共面。舉例而言，所述介面與第二配線層132的下表面之間的距離可小於第二配線層132的厚度。依電子元件120的電極焊墊120P是否突出而定，所述介面可與電子元件120的下表面 或電極焊墊120P的下表面實質上共面。舉例而言，所述介面與電子元件120的下表面或電極焊墊120P的下表面之間的距離可小於第二配線層132的厚度。所述介面可存在於其中重新分配部絕緣層141及囊封劑160由不同的材料形成的情形中、或可存在於其中重新分配部絕緣層141及囊封劑160由相同的材料形成但是以不同的步驟或製程形成的情形中。 Referring to FIG. 5J, the redistribution portion insulating layer 141 may be formed under the frame 110 and the electronic component 120 first, and the redistribution portion wiring layer 142 and the redistribution portion through hole 143 may be formed to form the redistribution portion 140. Next, the redistribution portion insulating layer 151 may be formed again under the redistribution portion insulation layer 141, and the redistribution portion wiring layer 152 and the redistribution portion through hole 153 may be formed to form the redistribution portion 150. The detailed method of forming the redistribution sections 140 and 150 is the same as the above method. The interface between the redistribution portion insulating layer 141 and the encapsulant 160 may be substantially coplanar with the lower surface of the second wiring layer 132. For example, the distance between the interface and the lower surface of the second wiring layer 132 may be smaller than the thickness of the second wiring layer 132. Depending on whether the electrode pad 120P of the electronic component 120 protrudes, the interface may be connected to the lower surface of the electronic component 120 Or the lower surface of the electrode pad 120P is substantially coplanar. For example, the distance between the interface and the lower surface of the electronic component 120 or the lower surface of the electrode pad 120P may be smaller than the thickness of the second wiring layer 132. The interface may exist in the case where the redistribution portion insulating layer 141 and the encapsulant 160 are formed of different materials, or may exist in the redistribution portion insulating layer 141 and the encapsulant 160 are formed of the same material but with Different steps or processes are formed.

參照圖5K，可形成安置於重新分配部140及150下的保護層170。亦可藉由對保護層170的前驅物進行積層並接著硬化所述前驅物的方法、施加用於形成保護層170的材料並接著硬化所述材料的方法等來形成保護層170。可使用例如以下方法等作為積層所述前驅物的方法：執行在高溫下對前驅物壓製預定時間的熱壓製製程、對所述前驅物進行減壓、並且接著將所述前驅物冷卻至室溫、在冷壓製製程中冷卻所述前驅物、並且接著分離作業工具。可使用例如利用刮板施加油墨的網版印刷方法、以霧形式施加油墨的噴霧印刷方法等作為施加所述前驅囊封劑的方法。所述硬化製程-其為後置製程-可為使材料乾燥以不被完全硬化從而使用光刻方法等的製程。 Referring to FIG. 5K, a protective layer 170 disposed under the redistribution portions 140 and 150 may be formed. The protective layer 170 may also be formed by a method of laminating the precursor of the protective layer 170 and then hardening the precursor, a method of applying a material for forming the protective layer 170 and then hardening the material, and the like. For example, the following method may be used as a method of laminating the precursor: performing a hot pressing process for pressing the precursor at a high temperature for a predetermined time, depressurizing the precursor, and then cooling the precursor to room temperature 1. Cooling the precursor in the cold pressing process, and then separating the working tools. As the method of applying the precursor encapsulant, for example, a screen printing method of applying ink using a squeegee, a spray printing method of applying ink in the form of mist, or the like can be used. The hardening process-which is a post-process-may be a process in which the material is dried so as not to be completely hardened to use a photolithography method or the like.

參照圖5L，可在保護層170中形成第一開口部171，以暴露出重新分配部配線層152的至少部分。可使用機械鑽孔及/或雷射鑽孔來形成第一開口部171。作為另一選擇，可藉由光刻方法來形成第一開口部171。在其中使用機械鑽孔及/或雷射鑽孔形成第一開口部171的情形中，可利用高錳酸鹽方法等對第一開口部 171執行除汙製程，以移除樹脂污垢。接著，可形成安置於第一開口部171中的第一外部連接端子175。形成第一外部連接端子175的方法並無特別限制。亦即，依第一外部連接端子175的結構或形式而定，可藉由先前技術中眾所習知的方法來形成第一外部連接端子175。可藉由回焊(reflow)來固定第一外部連接端子175，且第一外部連接端子175的部分可嵌置於保護層170中以增強固定力，且第一外部連接端子175的其餘部分可暴露於外部，藉此可提高可靠性。在某些情形中，可僅形成第一開口部171，且若需要，則可藉由由購買電子元件封裝100A的客戶進行的單獨製程而形成第一外部連接端子175。 Referring to FIG. 5L, a first opening 171 may be formed in the protective layer 170 to expose at least a portion of the redistribution wiring layer 152. The first opening 171 may be formed using mechanical drilling and/or laser drilling. As another option, the first opening 171 may be formed by a photolithography method. In the case where the first opening portion 171 is formed using mechanical drilling and/or laser drilling, the first opening portion may be made using a permanganate method or the like 171 Perform a decontamination process to remove resin dirt. Next, the first external connection terminal 175 disposed in the first opening portion 171 may be formed. The method of forming the first external connection terminal 175 is not particularly limited. That is, depending on the structure or form of the first external connection terminal 175, the first external connection terminal 175 may be formed by a method known in the prior art. The first external connection terminal 175 may be fixed by reflow, and a portion of the first external connection terminal 175 may be embedded in the protective layer 170 to enhance the fixing force, and the remaining portion of the first external connection terminal 175 may be Exposure to the outside can improve reliability. In some cases, only the first opening portion 171 may be formed, and if necessary, the first external connection terminal 175 may be formed by a separate process performed by a customer who purchases the electronic component package 100A.

圖6是示意性地說明電子元件封裝的另一實例的剖視圖。 6 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖7是電子元件封裝沿圖6所示的線II-II’截取的示意性平面圖。 7 is a schematic plan view of the electronic component package taken along the line II-II' shown in FIG. 6.

參照圖6及圖7，根據另一實例的電子元件封裝100B可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、以及安置於第二絕緣層111B的下表面110B上的第二配線層132。 Referring to FIGS. 6 and 7, an electronic component package 100B according to another example may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a battery 110 disposed under the frame 110 and the electronic component 120 The redistribution parts 140 and 150 and the encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖6中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 6, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 with respect to the redistribution portions 140 and 150, or It is located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131 as long as both the third wiring layer 131 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100B中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100B according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

第二配線層132可安置於第二絕緣層111B的下表面110B上。亦即，第二配線層132可安置於框架110之外。第三配線層131可安置於第一絕緣層111A的上表面110A上。亦即，第三配線層131亦可安置於框架110之外。此處，第二配線層132或第三配線層131安置於框架110之外的含義為第二配線層132或第三配線層131不安置於框架110的上表面110A與下表面110B之間。第三配線層131及第二配線層132亦可充當重新分配圖案及/或焊墊圖案，且例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金 (Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作第三配線層131的及第二配線層132的材料。第三配線層131及第二配線層132可依對應層的設計而定執行各種功能。舉例而言，第三配線層131及第二配線層132可充當接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案、焊線導引(bond finger，BF)圖案等而作為重新分配圖案。此處，訊號(S)圖案可包括除接地(GND)圖案、功率(PWR)圖案、焊線導引(BF)圖案等以外的各種訊號，例如資料訊號等。此外，第三配線層131及第二配線層132可充當通孔焊墊、內部通孔焊墊、外部連接端子焊墊等而作為焊墊圖案。由於充當內部通孔的焊墊的焊墊圖案安置於框架110中，因此不需要在重新分配部140及150上形成內部通孔的焊墊，且因而可增大設計面積，藉此可提升設計的自由度。第三配線層131的厚度及第二配線層132的厚度亦無特別限制，且可為例如10微米至50微米左右。若需要，則可在第三配線層131的被暴露出的圖案上進一步形成表面處理層。所述表面處理層可藉由例如電解鍍金、無電鍍金、有機可焊性保護劑、或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金鍍覆、熱空氣焊料均塗等來形成。 The second wiring layer 132 may be disposed on the lower surface 110B of the second insulating layer 111B. That is, the second wiring layer 132 may be disposed outside the frame 110. The third wiring layer 131 may be disposed on the upper surface 110A of the first insulating layer 111A. That is, the third wiring layer 131 can also be disposed outside the frame 110. Here, the meaning that the second wiring layer 132 or the third wiring layer 131 is disposed outside the frame 110 means that the second wiring layer 132 or the third wiring layer 131 is not disposed between the upper surface 110A and the lower surface 110B of the frame 110. The third wiring layer 131 and the second wiring layer 132 may also serve as redistribution patterns and/or pad patterns, and for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold Conductive materials such as (Au), nickel (Ni), lead (Pb), or their alloys can be used as the material of the third wiring layer 131 and the second wiring layer 132. The third wiring layer 131 and the second wiring layer 132 can perform various functions according to the design of the corresponding layer. For example, the third wiring layer 131 and the second wiring layer 132 may serve as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, a bond wire (BF) pattern, etc. Assign patterns. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, a bonding wire guide (BF) pattern, etc., such as a data signal. In addition, the third wiring layer 131 and the second wiring layer 132 may serve as via pads, internal via pads, external connection terminal pads, and the like as pad patterns. Since the pad pattern serving as the pad of the internal through hole is disposed in the frame 110, there is no need to form the pad of the internal through hole on the redistribution portions 140 and 150, and thus the design area can be increased, thereby improving the design Degrees of freedom. The thickness of the third wiring layer 131 and the thickness of the second wiring layer 132 are also not particularly limited, and may be, for example, about 10 to 50 microns. If necessary, a surface treatment layer may be further formed on the exposed pattern of the third wiring layer 131. The surface treatment layer can be coated by, for example, electrolytic gold plating, electroless gold plating, organic solderability protectant, or electroless tin plating, electroless silver plating, electroless nickel plating/displacement gold plating, direct gold plating, hot air solder Wait to form.

穿透過第一絕緣層111A的內部通孔115可用於將安置於不同的層中的第三配線層131及第一配線層112電性連接至彼此，且例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作內部通孔115的材料。內部通孔115可直接連接至在第三配線層131及第一配 線層112中充當內部通孔的焊墊的焊墊圖案。內部通孔115的數目、間距、配置形式等並無特別限制，且可由熟習此項技術者依設計特定細節充分地進行修改。舉例而言，依安裝於電子元件封裝100B上的另一電子元件封裝的形式而定，內部通孔115可僅在第一絕緣層111A的如圖6及圖7中所示的特定區中分散成彼此間隔開或可在第一絕緣層111A的整個表面上方分散成彼此間隔開。在其中使用例如Fe-Ni系合金等金屬作為第一絕緣層111A的材料的情形中，絕緣材料可安置於所述金屬與內部通孔115及/或第三配線層131及第一配線層112之間，以使所述金屬與內部通孔115及/或第三配線層131及第一配線層112之間電性絕緣。內部通孔115可具有較通孔113大的直徑。內部通孔115可具有較通孔113大的直徑，但並非僅限於此。依第一絕緣層111A而定，內部通孔115可具有與通孔113實質上相同的形狀、直徑等。 The internal via 115 penetrating through the first insulating layer 111A may be used to electrically connect the third wiring layer 131 and the first wiring layer 112 disposed in different layers to each other, and for example, copper (Cu), aluminum (Al) Conductive materials such as silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or alloys thereof can be used as the material of the internal via 115. The internal via 115 can be directly connected to the third wiring layer 131 and the first The pad pattern in the wire layer 112 that serves as a pad for internal through holes. The number, spacing, configuration, etc. of the internal through holes 115 are not particularly limited, and can be fully modified by those skilled in the art according to specific design details. For example, depending on the form of another electronic component package mounted on the electronic component package 100B, the internal via 115 may only be dispersed in a specific area of the first insulating layer 111A as shown in FIGS. 6 and 7 May be spaced apart from each other or may be dispersed over the entire surface of the first insulating layer 111A. In the case where a metal such as Fe-Ni-based alloy is used as the material of the first insulating layer 111A, an insulating material may be disposed on the metal and the internal via 115 and/or the third wiring layer 131 and the first wiring layer 112 To electrically isolate the metal from the internal via 115 and/or the third wiring layer 131 and the first wiring layer 112. The inner through hole 115 may have a larger diameter than the through hole 113. The inner through hole 115 may have a larger diameter than the through hole 113, but it is not limited thereto. Depending on the first insulating layer 111A, the internal via 115 may have substantially the same shape, diameter, etc. as the via 113.

在根據另一實例的電子元件封裝100B中，囊封劑160可具有第二開口部161，第二開口部161暴露出安置於框架110的上表面110A上的第三配線層131的至少部分。此外，根據另一實例的電子元件封裝100B可更包括安置於囊封劑160的第二開口部161中以藉此暴露於外部的第二外部連接端子185。使用第二外部連接端子185的目的可為將電子元件封裝100B上的另一電子元件、另一電子元件封裝等物理地連接至及/或電性連接至電子元件封裝100B。舉例而言，另一電子元件封裝可經由第二外部連接端子185而安裝於電子元件封裝100B上，且因此可形成堆疊式封裝 結構。第二外部連接端子185可安置於囊封劑160的第二開口部161中，且可連接至經由第二開口部161而暴露出的第三配線層131。因而，第二外部連接端子185亦可電性連接至電子元件120。 In the electronic component package 100B according to another example, the encapsulant 160 may have a second opening portion 161 that exposes at least a portion of the third wiring layer 131 disposed on the upper surface 110A of the frame 110. In addition, the electronic component package 100B according to another example may further include a second external connection terminal 185 disposed in the second opening portion 161 of the encapsulant 160 to thereby be exposed to the outside. The purpose of using the second external connection terminal 185 may be to physically connect and/or electrically connect another electronic component on the electronic component package 100B, another electronic component package, and the like to the electronic component package 100B. For example, another electronic component package may be mounted on the electronic component package 100B via the second external connection terminal 185, and thus may form a stacked package structure. The second external connection terminal 185 may be disposed in the second opening portion 161 of the encapsulant 160, and may be connected to the third wiring layer 131 exposed through the second opening portion 161. Therefore, the second external connection terminal 185 can also be electrically connected to the electronic component 120.

第二外部連接端子185可由例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、焊料等傳導性材料形成，但並非特別地限定於此。第二外部連接端子185可為焊盤、球、引腳等。第二外部連接端子185可由多個層或單個層形成。在其中第二外部連接端子185由多個層形成的情形中，第二外部連接端子185可含有銅柱及焊料，且在其中第二外部連接端子185由單個層形成的情形中，第二外部連接端子185可含有錫銀焊料或銅。然而，此僅為實例，且第二外部連接端子185並非僅限於此。 The second external connection terminal 185 may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, etc. However, it is not particularly limited to this. The second external connection terminal 185 may be a pad, a ball, a pin, or the like. The second external connection terminal 185 may be formed of multiple layers or a single layer. In the case where the second external connection terminal 185 is formed of multiple layers, the second external connection terminal 185 may contain copper pillars and solder, and in the case where the second external connection terminal 185 is formed of a single layer, the second external The connection terminal 185 may contain tin-silver solder or copper. However, this is only an example, and the second external connection terminal 185 is not limited to this.

圖8A至圖8M是說明製造電子元件封裝100B的製程的實例的示意圖。 8A to 8M are schematic diagrams illustrating an example of the manufacturing process of the electronic component package 100B.

在對製造電子元件封裝100B的製程的實例的說明中，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the description of the example of the manufacturing process of the electronic component package 100B, the content that is the same as the above content will not be explained again, and the content that is different from the above content will be mainly explained.

參照圖8A，可製備第一絕緣層111A。參照圖8B，可形成穿透過第一絕緣層111A的上表面及下表面的貫穿孔111Y。可使用機械鑽孔及/或雷射鑽孔來形成貫穿孔111Y。此處，所述雷射鑽孔可為CO2雷射鑽孔或YAG雷射鑽孔，但並非僅限於此。在其中使用機械鑽孔及/或雷射鑽孔形成貫穿孔111Y的情形中，可對 貫穿孔111Y執行除汙製程，以移除貫穿孔111Y中的樹脂污垢。可使用例如高錳酸鹽方法來執行所述除汙製程。在某些情形中，亦可藉由光刻方法來形成所述貫穿孔111Y。參照圖8C，可在第一絕緣層111A的上表面及下表面上分別形成第三配線層131及第一配線層112。此外，可以傳導性材料填充貫穿孔111Y，以形成內部通孔115。亦可藉由習知的方法來形成內部通孔115。舉例而言，可使用乾膜圖案藉由電解鍍銅、無電鍍銅等來形成內部通孔115。更詳言之，可使用例如化學氣相沈積、物理氣相沈積、濺鍍、減性製程、加性製程、半加性製程、經修改半加性製程等方法來形成內部通孔115，但並非僅限於此。參照圖8D，可在第一絕緣層111A的下表面上形成第二絕緣層111B。參照圖8E，可在第二絕緣層111B之下形成第二配線層132，且可在第二絕緣層111B中形成通孔113。參照圖8F，可形成穿透過第一絕緣層111A及第二絕緣層111B的貫穿孔110X。因此，可形成具有貫穿孔110X的框架110。 Referring to FIG. 8A, a first insulating layer 111A may be prepared. Referring to FIG. 8B, a through hole 111Y penetrating through the upper and lower surfaces of the first insulating layer 111A may be formed. The through hole 111Y may be formed using mechanical drilling and/or laser drilling. Here, the laser drilling may be a CO 2 laser drilling or a YAG laser drilling, but it is not limited to this. In the case where mechanical drilling and/or laser drilling is used to form the through hole 111Y, a decontamination process may be performed on the through hole 111Y to remove resin dirt in the through hole 111Y. The decontamination process can be performed using, for example, a permanganate method. In some cases, the through hole 111Y can also be formed by a photolithography method. Referring to FIG. 8C, a third wiring layer 131 and a first wiring layer 112 may be formed on the upper and lower surfaces of the first insulating layer 111A, respectively. In addition, the through hole 111Y may be filled with a conductive material to form the internal through hole 115. The internal via 115 can also be formed by a conventional method. For example, the internal via 115 may be formed by electrolytic copper plating, electroless copper plating, etc. using a dry film pattern. More specifically, methods such as chemical vapor deposition, physical vapor deposition, sputtering, subtractive process, additive process, semi-additive process, modified semi-additive process, etc. may be used to form the internal via 115, but Not limited to this. Referring to FIG. 8D, a second insulating layer 111B may be formed on the lower surface of the first insulating layer 111A. Referring to FIG. 8E, a second wiring layer 132 may be formed under the second insulating layer 111B, and a through hole 113 may be formed in the second insulating layer 111B. Referring to FIG. 8F, a through hole 110X may be formed through the first insulating layer 111A and the second insulating layer 111B. Therefore, the frame 110 having the through hole 110X can be formed.

參照圖8G，可將黏合膜190貼附至第二配線層132。參照圖8H，可在貫穿孔110X中安置電子元件120。參照圖8I，可使用囊封劑160對電子元件120進行囊封。參照圖8J，可剝除黏合膜190。參照圖8K，可形成包括重新分配部絕緣層141、重新分配部配線層142、及重新分配部通孔143的重新分配部140。接著，可形成包括重新分配部絕緣層151、重新分配部配線層152、及重新分配部通孔153的重新分配部150。參照圖8L，可形成連 接至重新分配部140及150的保護層170。參照圖8M，可形成保護層170的第一開口部171及安置於第一開口部171中的第一外部連接端子175。此外，可在囊封劑160的外表面中形成第二開口部161以便暴露出第三配線層131的至少部分，且可形成安置於第二開口部161中的第二外部連接端子185。可使用機械鑽孔及/或雷射鑽孔來形成第二開口部161。作為另一選擇，可藉由光刻方法來形成第二開口部161。在其中使用機械鑽孔及/或雷射鑽孔形成第二開口部161的情形中，可使用高錳酸鹽方法等對第二開口部161執行除汙製程，以移除樹脂污垢。依第二外部連接端子185的結構或形式而定，可藉由先前技術中眾所習知的方法來形成第二外部連接端子185。可藉由回焊來固定第二外部連接端子185，且可將第二外部連接端子185的部分嵌置於囊封劑160中以增強固定力，且第二外部連接端子185的其餘部分可暴露於外部，藉此可提高可靠性。在某些情形中，可僅形成安置於囊封劑160的第二開口部161中的第二外部連接端子185，且可在保護層170中僅形成第一開口部171，並且若需要，則可藉由由購買電子元件封裝100B的客戶進行的單獨製程形成安置於第一開口部171中的第一外部連接端子175。 Referring to FIG. 8G, the adhesive film 190 may be attached to the second wiring layer 132. Referring to FIG. 8H, the electronic component 120 may be disposed in the through hole 110X. Referring to FIG. 8I, the encapsulant 160 may be used to encapsulate the electronic component 120. 8J, the adhesive film 190 can be peeled off. Referring to FIG. 8K, a redistribution portion 140 including a redistribution portion insulating layer 141, a redistribution portion wiring layer 142, and a redistribution portion through hole 143 may be formed. Next, the redistribution portion 150 including the redistribution portion insulating layer 151, the redistribution portion wiring layer 152, and the redistribution portion through hole 153 may be formed. Referring to FIG. 8L, a joint can be formed It is connected to the protective layer 170 of the redistribution parts 140 and 150. Referring to FIG. 8M, the first opening 171 of the protective layer 170 and the first external connection terminal 175 disposed in the first opening 171 may be formed. In addition, a second opening portion 161 may be formed in the outer surface of the encapsulant 160 so as to expose at least a portion of the third wiring layer 131, and a second external connection terminal 185 disposed in the second opening portion 161 may be formed. The second opening 161 may be formed using mechanical drilling and/or laser drilling. As another option, the second opening 161 may be formed by a photolithography method. In the case where the second opening 161 is formed using mechanical drilling and/or laser drilling, a permanganate method or the like may be used to perform a decontamination process on the second opening 161 to remove resin dirt. Depending on the structure or form of the second external connection terminal 185, the second external connection terminal 185 may be formed by a method known in the prior art. The second external connection terminal 185 may be fixed by reflow, and a part of the second external connection terminal 185 may be embedded in the encapsulant 160 to enhance the fixing force, and the remaining part of the second external connection terminal 185 may be exposed Externally, this can improve reliability. In some cases, only the second external connection terminal 185 disposed in the second opening 161 of the encapsulant 160 may be formed, and only the first opening 171 may be formed in the protective layer 170, and if necessary, The first external connection terminal 175 disposed in the first opening 171 may be formed by a separate process performed by a customer who purchases the electronic component package 100B.

圖9是示意性地說明電子元件封裝的另一實例的剖視圖。 9 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖10是電子元件封裝沿圖9所示的線III-III’截取的示意性平面圖。 FIG. 10 is a schematic plan view of the electronic component package taken along line III-III' shown in FIG. 9.

參照圖9及圖10，根據另一實例的電子元件封裝100C 可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、用於囊封電子元件120的囊封劑160、安置於囊封劑160上的外配線層162、以及穿透過囊封劑160的外通孔163。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、及安置於第二絕緣層111B的下表面110B上的第二配線層132。 9 and 10, an electronic component package 100C according to another example It may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a redistribution portion 140 and 150 disposed under the frame 110 and the electronic component 120, and a capsule for encapsulating the electronic component 120 The encapsulant 160, the outer wiring layer 162 disposed on the encapsulant 160, and the outer through hole 163 penetrating through the encapsulant 160. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖9中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 9, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 with respect to the redistribution portions 140 and 150, or It is located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131 as long as both the third wiring layer 131 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子 元件封裝100C中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the electronic contained in another example will be explained in more detail Corresponding elements in the component package 100C will no longer explain the contents that are duplicated with the above contents, and will mainly explain the contents that are different from the above contents.

穿透過第一絕緣層111A的內部通孔115的數目、間距、配置形式等並無特別限制，且可由熟習此項技術者依設計特定細節充分地進行修改。舉例而言，依安裝於電子元件封裝100C上的另一電子元件封裝的形式而定，內部通孔115可如圖9及圖10中所示在第一絕緣層111A的整個表面上方分散成彼此間隔開、或可在第一絕緣層111A的僅特定區中分散成間隔開。 The number, spacing, and configuration of the internal vias 115 penetrating through the first insulating layer 111A are not particularly limited, and can be sufficiently modified by those skilled in the art according to specific design details. For example, depending on the form of another electronic component package mounted on the electronic component package 100C, the internal through holes 115 may be dispersed into each other over the entire surface of the first insulating layer 111A as shown in FIGS. 9 and 10 They may be spaced apart, or may be spaced apart in only certain regions of the first insulating layer 111A.

安置於囊封劑160上的外配線層162亦可充當重新分配圖案及/或焊墊圖案，且例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作外配線層162的材料。以上已闡述了詳細實例。外配線層162可依對應層的設計而定執行各種功能。舉例而言，外配線層162可充當接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等而作為重新分配圖案。此處，訊號(S)圖案可包括除接地(GND)圖案、功率(PWR)圖案等以外的各種訊號，例如資料訊號等。此外，外配線層162可充當通孔焊墊、外部連接端子焊墊等而作為焊墊圖案。由於外配線層162的圖案可在囊封劑160的整個表面上方分散成彼此間隔開且第二外部連接端子185亦可在以下將闡述的覆蓋層180的整個表面上方分散成彼此間隔開，因此可存在各種設計。外配線層162的厚度亦無特別限制，但可為例如約10微米至50微米左右。若需要，則可在外配線層162的被暴露出的部分 上進一步形成表面處理層。所述表面處理層可藉由例如電解鍍金、無電鍍金、有機可焊性保護劑、或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金鍍覆、熱空氣焊料均塗等而形成。 The outer wiring layer 162 disposed on the encapsulant 160 may also serve as a redistribution pattern and/or a pad pattern, and for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au) ), nickel (Ni), lead (Pb), or alloys thereof and other conductive materials can be used as the material of the outer wiring layer 162. Detailed examples have been explained above. The outer wiring layer 162 can perform various functions according to the design of the corresponding layer. For example, the outer wiring layer 162 may serve as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. as a redistribution pattern. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, etc., such as a data signal. In addition, the outer wiring layer 162 may serve as a via pad, an external connection terminal pad, or the like as a pad pattern. Since the pattern of the outer wiring layer 162 may be dispersed to be spaced apart from each other over the entire surface of the encapsulant 160 and the second external connection terminals 185 may also be dispersed to be spaced apart from each other over the entire surface of the cover layer 180 to be explained below, Various designs can exist. The thickness of the outer wiring layer 162 is also not particularly limited, but may be, for example, about 10 to 50 microns. If necessary, the exposed portion of the outer wiring layer 162 can be A surface treatment layer is further formed thereon. The surface treatment layer can be coated by, for example, electrolytic gold plating, electroless gold plating, organic solderability protectant, or electroless tin plating, electroless silver plating, electroless nickel plating/displacement gold plating, direct gold plating, hot air solder And so on.

局部地穿透過囊封劑160的外通孔163可將形成於不同的層上的第三配線層131及外配線層162電性連接至彼此，藉此在電子元件封裝100C內形成電性路徑。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作外通孔163的材料。外通孔163可被完全填充以傳導性材料。作為另一選擇，傳導性材料可沿通孔的壁形成。此外，外通孔163可具有先前技術中習知的所有形狀，例如其中通孔的直徑朝下表面變得更小的錐形形狀、其中通孔的直徑朝下表面變得更大的倒錐形形狀、圓柱形形狀等。 The external through hole 163 partially penetrating through the encapsulant 160 may electrically connect the third wiring layer 131 and the outer wiring layer 162 formed on different layers to each other, thereby forming an electrical path in the electronic component package 100C . Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or their alloys can be used as the external through holes 163 s material. The outer through hole 163 may be completely filled with a conductive material. Alternatively, the conductive material may be formed along the wall of the through hole. In addition, the outer through hole 163 may have all shapes known in the prior art, such as a tapered shape in which the diameter of the through hole becomes smaller toward the lower surface, and an inverted cone in which the diameter of the through hole becomes larger toward the lower surface Shape, cylindrical shape, etc.

根據另一實例的電子元件封裝100C可更包括安置於囊封劑160之上的覆蓋層180。使用覆蓋層180的目的可為保護囊封劑160、外配線層162等不受外部的物理或化學損害等。覆蓋層180可具有第三開口部181，第三開口部181暴露出安置於囊封劑160上的外配線層162的至少部分。儘管第三開口部181可暴露出外配線層162的上表面的部分，然而在某些情形中第三開口部181亦可暴露出外配線層162的側表面。覆蓋層180的材料並無特別限制。舉例而言，可使用阻焊劑作為覆蓋層180的材料。此外，可使用各種感光成像介電樹脂、味之素構成膜等作為覆蓋層180的材料。若需要，則覆蓋層180亦可由多個層形成。 The electronic component package 100C according to another example may further include a cover layer 180 disposed on the encapsulant 160. The purpose of using the cover layer 180 may be to protect the encapsulant 160, the outer wiring layer 162, etc. from external physical or chemical damage and the like. The cover layer 180 may have a third opening portion 181 that exposes at least a portion of the outer wiring layer 162 disposed on the encapsulant 160. Although the third opening portion 181 may expose a portion of the upper surface of the outer wiring layer 162, the third opening portion 181 may also expose the side surface of the outer wiring layer 162 in some cases. The material of the cover layer 180 is not particularly limited. For example, solder resist may be used as the material of the cover layer 180. In addition, various photosensitive imaging dielectric resins, Ajinomoto constituting films, and the like can be used as the material of the cover layer 180. If necessary, the cover layer 180 may also be formed of multiple layers.

根據另一實例的電子元件封裝100C可更包括安置於覆蓋層180的第三開口部181中的第二外部連接端子185。第二外部連接端子185可安置於第三開口部181中，且可連接至經由第三開口部181而暴露出的外配線層162。亦即，第二外部連接端子185可如在電子元件封裝100B中般安置於囊封劑160的第二開口部161中，或可如在電子元件封裝100C中般安置於覆蓋層180的第三開口部181中。 The electronic component package 100C according to another example may further include the second external connection terminal 185 disposed in the third opening portion 181 of the cover layer 180. The second external connection terminal 185 may be disposed in the third opening portion 181 and may be connected to the outer wiring layer 162 exposed through the third opening portion 181. That is, the second external connection terminal 185 may be disposed in the second opening portion 161 of the encapsulant 160 as in the electronic component package 100B, or may be disposed in the third of the cover layer 180 as in the electronic component package 100C In the opening 181.

圖11A至圖11M是說明製造電子元件封裝100C的製程的實例的示意圖。 11A to 11M are schematic diagrams illustrating an example of the manufacturing process of the electronic component package 100C.

在對製造電子元件封裝100C的製程的實例的說明中，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the description of the example of the manufacturing process of the electronic component package 100C, the content that is the same as the above content will not be explained again, and the content that is different from the above content will be mainly explained.

參照圖11A，可製備第一絕緣層111A。參照圖11B，可形成穿透過第一絕緣層111A的上表面及下表面的貫穿孔111Y。參照圖11C，可在第一絕緣層111A的上表面及下表面上分別形成第三配線層131及第一配線層112。此外，可以傳導性材料填充貫穿孔111Y，以形成內部通孔115。參照圖11D，可在第一絕緣層111A的下表面上形成第二絕緣層111B。參照圖11E，可在第二絕緣層111B之下形成第二配線層132，且可在第二絕緣層111B中形成通孔113。參照圖11F，可形成穿透過第一絕緣層111A及第二絕緣層111B的貫穿孔110X。因此，可形成具有貫穿孔110X的框架110。 Referring to FIG. 11A, a first insulating layer 111A may be prepared. Referring to FIG. 11B, a through hole 111Y penetrating through the upper and lower surfaces of the first insulating layer 111A may be formed. Referring to FIG. 11C, the third wiring layer 131 and the first wiring layer 112 may be formed on the upper and lower surfaces of the first insulating layer 111A, respectively. In addition, the through hole 111Y may be filled with a conductive material to form the internal through hole 115. Referring to FIG. 11D, a second insulating layer 111B may be formed on the lower surface of the first insulating layer 111A. Referring to FIG. 11E, a second wiring layer 132 may be formed under the second insulating layer 111B, and a through hole 113 may be formed in the second insulating layer 111B. Referring to FIG. 11F, a through hole 110X may be formed through the first insulating layer 111A and the second insulating layer 111B. Therefore, the frame 110 having the through hole 110X can be formed.

參照圖11G，可將黏合膜190貼附至第二配線層132。參照圖11H，可在貫穿孔110X中安置電子元件120。參照圖11I，可使用囊封劑160對電子元件120進行囊封。參照圖11J，可剝除黏合膜190。參照圖11K，可形成包括重新分配部絕緣層141、重新分配部配線層142、及重新分配部通孔143的重新分配部140。接著，可形成包括重新分配部絕緣層151、重新分配部配線層152、及重新分配部通孔153的重新分配部150。此外，可形成安置於囊封劑160上的外配線層162及穿透過囊封劑160的外通孔163。亦可使用機械鑽孔及/或雷射鑽孔來形成用於形成外通孔163的通孔洞，或亦可藉由光刻方法來形成所述通孔洞。在其中使用機械鑽孔及/或雷射鑽孔形成通孔洞的情形中，可利用高錳酸鹽方法等對所述通孔洞執行除汙製程，以移除樹脂污垢。亦可使用乾膜圖案藉由電解鍍銅、無電鍍銅等來形成外配線層162及外通孔163。更詳言之，可使用例如化學氣相沈積、物理氣相沈積、濺鍍、減性製程、加性製程、半加性製程、經修改半加性製程等方法來形成外配線層162及外通孔163。參照圖11L，可形成連接至重新分配部140及150的保護層170以及連接至囊封劑160的覆蓋層180。亦可藉由對覆蓋層180的前驅物進行積層並接著硬化所述前驅物的方法、施加用於形成覆蓋層180的材料並接著硬化所述材料的方法等來形成覆蓋層180。可使用例如以下方法等作為積層所述前驅物的方法：執行在高溫下對前驅物壓製預定時間的熱壓製製程、對所述前驅物進行減壓、並且接著將所述前驅物冷卻至室溫、 在冷壓製製程中冷卻所述前驅物、並且接著分離作業工具。可使用例如利用刮板施加油墨的網版印刷方法、以霧形式施加油墨的噴霧印刷方法等作為施加所述材料的方法。所述硬化製程-其為後置製程-可為使材料乾燥以不被完全硬化從而使用光刻方法等的製程。參照圖11M，可在覆蓋層180的外表面中形成第三開口部181，從而暴露出外配線層162的至少部分，且可形成安置於第三開口部181中的第二外部連接端子185。此外，可形成保護層170的第一開口部171及安置於第一開口部171中的第一外部連接端子175。可使用機械鑽孔及/或雷射鑽孔來形成第三開口部181。作為另一選擇，可藉由光刻方法來形成第三開口部181。在其中使用機械鑽孔及/或雷射鑽孔形成第三開口部181的情形中，可利用高錳酸鹽方法等對第三開口部181執行除汙製程，以移除樹脂污垢。依第二外部連接端子185的結構或形式而定，可藉由在先前技術中眾所習知的方法來形成第二外部連接端子185。可藉由回焊來固定第二外部連接端子185，且第二外部連接端子185的部分可嵌置於覆蓋層180中以增強固定力，且第二外部連接端子185的其餘部分可暴露於外部，藉此可提高可靠性。在某些情形中，可僅形成安置於覆蓋層180的第三開口部181中的第二外部連接端子185，且可在保護層170中僅形成第一開口部171，並且若需要，則可藉由由購買電子元件封裝100C的客戶進行的單獨製程而形成安置於第一開口部171中的第一外部連接端子175。 Referring to FIG. 11G, the adhesive film 190 may be attached to the second wiring layer 132. Referring to FIG. 11H, the electronic component 120 may be placed in the through hole 110X. Referring to FIG. 11I, the encapsulant 160 may be used to encapsulate the electronic component 120. 11J, the adhesive film 190 can be peeled off. Referring to FIG. 11K, a redistribution portion 140 including a redistribution portion insulating layer 141, a redistribution portion wiring layer 142, and a redistribution portion through hole 143 may be formed. Next, the redistribution portion 150 including the redistribution portion insulating layer 151, the redistribution portion wiring layer 152, and the redistribution portion through hole 153 may be formed. In addition, an outer wiring layer 162 disposed on the encapsulant 160 and an outer through hole 163 penetrating through the encapsulant 160 may be formed. Mechanical drilling and/or laser drilling may also be used to form the through hole for forming the outer through hole 163, or the through hole may also be formed by a photolithography method. In the case where mechanical drilling and/or laser drilling are used to form the through holes, a permanganate method or the like may be used to perform a decontamination process on the through holes to remove resin dirt. The outer wiring layer 162 and the outer through hole 163 may also be formed by electrolytic copper plating, electroless copper plating, etc. using a dry film pattern. More specifically, methods such as chemical vapor deposition, physical vapor deposition, sputtering, subtractive process, additive process, semi-additive process, modified semi-additive process, etc. may be used to form the outer wiring layer 162 and the outer layer Through hole 163. Referring to FIG. 11L, a protective layer 170 connected to the redistribution parts 140 and 150 and a cover layer 180 connected to the encapsulant 160 may be formed. The cover layer 180 may also be formed by a method of laminating the precursor of the cover layer 180 and then hardening the precursor, a method of applying a material for forming the cover layer 180 and then hardening the material, and the like. For example, the following method may be used as a method of laminating the precursor: performing a hot pressing process for pressing the precursor at a high temperature for a predetermined time, depressurizing the precursor, and then cooling the precursor to room temperature , The precursor is cooled in the cold pressing process, and then the work tool is separated. As the method of applying the material, for example, a screen printing method of applying ink using a squeegee, a spray printing method of applying ink in the form of mist, or the like can be used. The hardening process-which is a post-process-may be a process in which the material is dried so as not to be completely hardened to use a photolithography method or the like. Referring to FIG. 11M, a third opening portion 181 may be formed in the outer surface of the cover layer 180 so that at least part of the outer wiring layer 162 is exposed, and a second external connection terminal 185 disposed in the third opening portion 181 may be formed. In addition, the first opening 171 of the protective layer 170 and the first external connection terminal 175 disposed in the first opening 171 may be formed. The third opening 181 may be formed using mechanical drilling and/or laser drilling. As another option, the third opening 181 may be formed by a photolithography method. In the case where mechanical drilling and/or laser drilling are used to form the third opening 181, a decontamination process may be performed on the third opening 181 using a permanganate method or the like to remove resin dirt. Depending on the structure or form of the second external connection terminal 185, the second external connection terminal 185 may be formed by a method known in the prior art. The second external connection terminal 185 may be fixed by reflow, and a portion of the second external connection terminal 185 may be embedded in the cover layer 180 to enhance the fixing force, and the remaining part of the second external connection terminal 185 may be exposed to the outside , Which can improve reliability. In some cases, only the second external connection terminal 185 disposed in the third opening 181 of the cover layer 180 may be formed, and only the first opening 171 may be formed in the protective layer 170, and if necessary, The first external connection terminal 175 disposed in the first opening 171 is formed by a separate process performed by a customer who purchases the electronic component package 100C.

圖12是示意性地說明電子元件封裝的另一實例的剖視 圖。 12 is a cross-sectional view schematically illustrating another example of electronic component packaging Figure.

圖13是電子元件封裝沿圖12所示的線IV-IV’截取的示意性平面圖。 Fig. 13 is a schematic plan view of the electronic component package taken along line IV-IV' shown in Fig. 12.

參照圖12及圖13，根據另一實例的電子元件封裝100D可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第一金屬層135A、安置於第二絕緣層111B的下表面110B上的第二配線層132、以及安置於貫穿孔110X的內表面上的第二金屬層135B。 Referring to FIGS. 12 and 13, an electronic component package 100D according to another example may include a frame 110 having a through-hole 110X, an electronic component 120 disposed in the through-hole 110X of the frame 110, a battery 110 disposed under the frame 110 and the electronic component 120 The redistribution parts 140 and 150 and the encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, a through hole 113 penetrating through the second insulating layer 111B, The first metal layer 135A disposed on the upper surface 110A of the first insulating layer 111A, the second wiring layer 132 disposed on the lower surface 110B of the second insulating layer 111B, and the first metal layer disposed on the inner surface of the through hole 110X Two metal layers 135B.

貫穿孔110X可依序穿透過第一金屬層135A、第一絕緣層111A、第一配線層112、第二絕緣層111B、及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖12中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第一金屬層135A的上表面下、或者位於與第一金屬層135A的上表 面相同的位階處或位於第一金屬層135A的上表面之上，只要第一金屬層135A及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may sequentially penetrate the first metal layer 135A, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 12, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the first metal layer 135A with respect to the redistribution portions 140 and 150, or Located on the upper table with the first metal layer 135A At the same level or on the upper surface of the first metal layer 135A, as long as the first metal layer 135A and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100D中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100D according to another example will be explained in more detail, and the contents that are duplicated with the above will not be explained, and the contents that are different from the above will be mainly explained.

使用安置於貫穿孔110X的內表面上的第二金屬層135B的目的可為改善熱輻射特性及/或阻擋電磁波。第二金屬層135B的材料並無特別限制，只要其為例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等具有高熱傳導性的金屬即可。第一金屬層135A可連接至第二金屬層135B。在此種情形中，自電子元件120發出的熱可經由第二金屬層135B而傳導至第一金屬層135A，以藉此分散至電子元件封裝100D的上部部分。第二金屬層135B可連接至在第二配線層132中充當接地圖案的重新分配圖案。此外，第二金屬層135B亦可連接至在第一配線層112中充當接地(GND)圖案的重新分配圖案。自電子元件120發出的熱可經由第二金屬層135B而傳導至第一配線層112及第三配線層132中的接地(GND)圖案，以藉此分散至電子元件封裝100D的下部部分。所述接地(GND)圖案亦可用於阻擋電磁波。作為另一選擇，可藉由對流或輻射來分散熱。 The purpose of using the second metal layer 135B disposed on the inner surface of the through hole 110X may be to improve heat radiation characteristics and/or block electromagnetic waves. The material of the second metal layer 135B is not particularly limited as long as it is, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Or an alloy such as a metal having high thermal conductivity. The first metal layer 135A may be connected to the second metal layer 135B. In this case, the heat emitted from the electronic component 120 may be conducted to the first metal layer 135A through the second metal layer 135B, thereby being distributed to the upper portion of the electronic component package 100D. The second metal layer 135B may be connected to a redistribution pattern that serves as a ground pattern in the second wiring layer 132. In addition, the second metal layer 135B may also be connected to a redistribution pattern that serves as a ground (GND) pattern in the first wiring layer 112. The heat emitted from the electronic component 120 may be conducted to the ground (GND) patterns in the first wiring layer 112 and the third wiring layer 132 via the second metal layer 135B, thereby being dispersed to the lower portion of the electronic component package 100D. The ground (GND) pattern can also be used to block electromagnetic waves. As another option, heat can be dispersed by convection or radiation.

圖14A至圖14L是說明製造電子元件封裝100D的製程的實例的示意圖。 14A to 14L are schematic diagrams illustrating an example of the manufacturing process of the electronic component package 100D.

在對製造電子元件封裝100D的製程的實例的說明中，將 不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the description of an example of the manufacturing process of the electronic component package 100D, the No repetition of the above content will be described, and the content that differs from the above content will be mainly described.

參照圖14A，可製備第一絕緣層111A。參照圖14B，可在第一絕緣層111A的上表面及下表面上分別形成第一金屬層135A及第一配線層112。參照圖14C，可在第一絕緣層111A的下表面上形成第二絕緣層111B。參照圖14D，可形成穿透過第一絕緣層111A及第二絕緣層111B的貫穿孔110X。此外，可形成穿透過第二絕緣層111B的通孔洞113Y。參照圖14E，可在第二絕緣層111B之下形成第二配線層132，且可在第二絕緣層111B中形成通孔113。此外，可在貫穿孔110X的內表面上形成第二金屬層135B。舉例而言，可使用乾膜圖案藉由電解鍍銅、無電鍍銅等來形成第二金屬層135B。詳言之，可使用例如化學氣相沈積、物理氣相沈積、濺鍍、減性製程、加性製程、半加性製程、經修改半加性製程等方法來形成第二金屬層135B，但並非僅限於此。如此一來，可形成具有貫穿孔110X的框架110。 Referring to FIG. 14A, a first insulating layer 111A may be prepared. Referring to FIG. 14B, a first metal layer 135A and a first wiring layer 112 may be formed on the upper and lower surfaces of the first insulating layer 111A, respectively. Referring to FIG. 14C, a second insulating layer 111B may be formed on the lower surface of the first insulating layer 111A. Referring to FIG. 14D, a through hole 110X may be formed through the first insulating layer 111A and the second insulating layer 111B. In addition, a through hole 113Y penetrating through the second insulating layer 111B may be formed. Referring to FIG. 14E, a second wiring layer 132 may be formed under the second insulating layer 111B, and a through hole 113 may be formed in the second insulating layer 111B. In addition, a second metal layer 135B may be formed on the inner surface of the through hole 110X. For example, the second metal layer 135B may be formed by electrolytic copper plating, electroless copper plating, etc. using a dry film pattern. In detail, methods such as chemical vapor deposition, physical vapor deposition, sputtering, subtractive process, additive process, semi-additive process, modified semi-additive process, etc. may be used to form the second metal layer 135B, but Not limited to this. In this way, the frame 110 having the through hole 110X can be formed.

與圖中所示者不同，可藉由封孔方法(tenting method)等而首先在第一絕緣層111A的僅下表面上形成第一配線層112，可在第一絕緣層111A的下表面上形成第二絕緣層111B，且可形成通孔洞113Y及貫穿孔110X。接著，在藉由以傳導性材料填充通孔洞113Y而形成通孔113的同時可在貫穿孔110X的內壁上形成第二金屬層135B。同時，可在第一絕緣層111A的上表面及第二絕緣層111B的下表面上分別形成第一金屬層135A及第二配線 層132。 Unlike the ones shown in the figure, the first wiring layer 112 may be formed on only the lower surface of the first insulating layer 111A by a tenting method or the like, and may be formed on the lower surface of the first insulating layer 111A The second insulating layer 111B is formed, and the through hole 113Y and the through hole 110X can be formed. Next, the second metal layer 135B may be formed on the inner wall of the through hole 110X while forming the through hole 113 by filling the through hole 113Y with a conductive material. Meanwhile, the first metal layer 135A and the second wiring may be formed on the upper surface of the first insulating layer 111A and the lower surface of the second insulating layer 111B, respectively 层132。 Layer 132.

參照圖14F，可將黏合膜190貼附至第二配線層132。參照圖14G，可在貫穿孔110X中安置電子元件120。參照圖14H，可使用囊封劑160對電子元件120進行囊封。參照圖14I，可剝除黏合膜190。參照圖14J，可形成包括重新分配部絕緣層141、重新分配部配線層142、及重新分配部通孔143的重新分配部140。接著，可形成包括重新分配部絕緣層151、重新分配部配線層152、及重新分配部通孔153的重新分配部150。參照圖14K，可形成連接至重新分配部140及150的保護層170。參照圖14L，可在保護層170中形成第一開口部171。接著，可形成安置於第一開口部171中的第一外部連接端子175。在某些情形中，可僅形成第一開口部171，且若需要，則可藉由由購買電子元件封裝100D的客戶進行的單獨製程而形成第一外部連接端子175。 Referring to FIG. 14F, the adhesive film 190 may be attached to the second wiring layer 132. Referring to FIG. 14G, the electronic component 120 may be disposed in the through hole 110X. Referring to FIG. 14H, the encapsulant 160 may be used to encapsulate the electronic component 120. Referring to FIG. 14I, the adhesive film 190 can be peeled off. Referring to FIG. 14J, the redistribution portion 140 including the redistribution portion insulating layer 141, the redistribution portion wiring layer 142, and the redistribution portion through hole 143 may be formed. Next, the redistribution portion 150 including the redistribution portion insulating layer 151, the redistribution portion wiring layer 152, and the redistribution portion through hole 153 may be formed. Referring to FIG. 14K, a protective layer 170 connected to the redistribution portions 140 and 150 may be formed. Referring to FIG. 14L, the first opening 171 may be formed in the protective layer 170. Next, the first external connection terminal 175 disposed in the first opening portion 171 may be formed. In some cases, only the first opening portion 171 may be formed, and if necessary, the first external connection terminal 175 may be formed by a separate process performed by a customer who purchases the electronic component package 100D.

圖15是示意性地說明電子元件封裝的另一實例的剖視圖。 15 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖16是電子元件封裝沿圖15所示的線V-V’截取的示意性平面圖。 Fig. 16 is a schematic plan view of the electronic component package taken along the line V-V' shown in Fig. 15.

參照圖15及圖16，根據另一實例的電子元件封裝100E可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一 絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、安置於第二絕緣層111B的下表面110B上的第二配線層132、以及安置於貫穿孔110X的內表面上的金屬層135。 15 and 16, an electronic component package 100E according to another example may include a frame 110 having a through-hole 110X, an electronic component 120 disposed in the through-hole 110X of the frame 110, a frame 110 disposed under the frame 110 and the electronic component 120 The redistribution parts 140 and 150 and the encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, disposed on the first The first wiring layer 112 between the insulating layer 111A and the second insulating layer 111B, the internal via 115 passing through the first insulating layer 111A, the via 113 passing through the second insulating layer 111B, and being disposed on the first insulating layer 111A The third wiring layer 131 on the upper surface 110A, the second wiring layer 132 disposed on the lower surface 110B of the second insulating layer 111B, and the metal layer 135 disposed on the inner surface of the through hole 110X.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B、及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖15中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 15, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 with respect to the redistribution portions 140 and 150, or It is located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131 as long as both the third wiring layer 131 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100E中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100E according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

安置於貫穿孔110X的內表面上的金屬層135可連接至在第三配線層131中充當接地(GND)圖案的重新分配圖案。在此種情形中，自電子元件120發出的熱可經由金屬層135而傳導至 第三配線層131中的接地(GND)圖案，以藉此分散至電子元件封裝100E的上部部分。金屬層135可連接至在第二配線層132中充當接地(GND)圖案的重新分配圖案。金屬層135亦可連接至在第一配線層112中充當接地(GND)圖案的重新分配圖案。在此種情形中，自電子元件120發出的熱可經由金屬層135而傳導至第一配線層112及第三配線層132中的接地(GND)圖案，以藉此分散至電子元件封裝100E的下部部分。接地(GND)圖案亦可用於阻擋電磁波。作為另一選擇，可藉由對流或輻射來分散熱。 The metal layer 135 disposed on the inner surface of the through hole 110X may be connected to a redistribution pattern that serves as a ground (GND) pattern in the third wiring layer 131. In this case, the heat emitted from the electronic component 120 can be conducted to the metal layer 135 to The ground (GND) pattern in the third wiring layer 131 is thereby dispersed to the upper portion of the electronic component package 100E. The metal layer 135 may be connected to a redistribution pattern that serves as a ground (GND) pattern in the second wiring layer 132. The metal layer 135 may also be connected to a redistribution pattern that serves as a ground (GND) pattern in the first wiring layer 112. In this case, the heat emitted from the electronic component 120 may be conducted to the ground (GND) patterns in the first wiring layer 112 and the third wiring layer 132 through the metal layer 135 to thereby be distributed to the electronic component package 100E Lower part. The ground (GND) pattern can also be used to block electromagnetic waves. As another option, heat can be dispersed by convection or radiation.

圖17A至圖17M是說明製造電子元件封裝100E的製程的實例的示意圖。 17A to 17M are schematic diagrams illustrating an example of the manufacturing process of the electronic component package 100E.

在對製造電子元件封裝100E的製程的實例的說明中，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the description of the example of the manufacturing process of the electronic component package 100E, the content that is the same as the above content will not be explained again, and the content that is different from the above content will be mainly explained.

參照圖17A，可製備第一絕緣層111A。參照圖17B，可形成穿透過第一絕緣層111A的上表面及下表面的貫穿孔111Y。參照圖17C，可在第一絕緣層111A的上表面及下表面上分別形成第三配線層131及第一配線層112。此外，可以傳導性材料填充貫穿孔111Y，以形成內部通孔115。參照圖17D，可在第一絕緣層111A的下表面上形成第二絕緣層111B。參照圖17E，可形成穿透過第一絕緣層111A及第二絕緣層111B的貫穿孔110X。此外，可形成穿透過第二絕緣層111B的通孔洞113Y。參照圖17F，可在第二絕緣層111B之下形成第二配線層132，且可在第二絕緣層111B 中形成通孔113。此外，可在貫穿孔110X的內表面上形成金屬層135。如此一來，可形成具有貫穿孔110X的框架110。 Referring to FIG. 17A, a first insulating layer 111A may be prepared. Referring to FIG. 17B, a through hole 111Y penetrating through the upper and lower surfaces of the first insulating layer 111A may be formed. Referring to FIG. 17C, a third wiring layer 131 and a first wiring layer 112 may be formed on the upper and lower surfaces of the first insulating layer 111A, respectively. In addition, the through hole 111Y may be filled with a conductive material to form the internal through hole 115. Referring to FIG. 17D, a second insulating layer 111B may be formed on the lower surface of the first insulating layer 111A. Referring to FIG. 17E, a through hole 110X may be formed through the first insulating layer 111A and the second insulating layer 111B. In addition, a through hole 113Y penetrating through the second insulating layer 111B may be formed. Referring to FIG. 17F, a second wiring layer 132 may be formed under the second insulating layer 111B, and may be formed on the second insulating layer 111B 中 formed through hole 113. In addition, a metal layer 135 may be formed on the inner surface of the through hole 110X. In this way, the frame 110 having the through hole 110X can be formed.

與圖中所示者不同，可藉由封孔方法等而首先在第一絕緣層111A的僅下表面上形成第一配線層112，可在第一絕緣層111A的下表面上形成第二絕緣層111B，且可形成通孔洞113Y、貫穿孔111Y及貫穿孔110X。接著，在藉由以傳導性材料填充通孔洞113Y及貫穿孔111Y而形成通孔113及內部通孔115的同時可在貫穿孔110X的內壁上形成金屬層135。同時，可在第一絕緣層111A的上表面及第二絕緣層111B的下表面上分別形成第三配線層131及第二配線層132。 Unlike the ones shown in the figure, the first wiring layer 112 can be formed on only the lower surface of the first insulating layer 111A by a hole sealing method, etc., and the second insulation can be formed on the lower surface of the first insulating layer 111A Layer 111B, and may form a through hole 113Y, a through hole 111Y, and a through hole 110X. Next, the metal layer 135 may be formed on the inner wall of the through hole 110X while forming the through hole 113 and the inner through hole 115 by filling the through hole 113Y and the through hole 111Y with a conductive material. Meanwhile, a third wiring layer 131 and a second wiring layer 132 may be formed on the upper surface of the first insulating layer 111A and the lower surface of the second insulating layer 111B, respectively.

參照圖17G，可將黏合膜190貼附至第二配線層132。參照圖17H，可在貫穿孔110X中安置電子元件120。參照圖17I，可使用囊封劑160對電子元件120進行囊封。參照圖17J，可剝除黏合膜190。參照圖17K，可形成包括重新分配部絕緣層141、重新分配部配線層142、及重新分配部通孔143的重新分配部140。接著，可形成包括重新分配部絕緣層151、重新分配部配線層152、及重新分配部通孔153的重新分配部150。參照圖17L，可形成連接至重新分配部140及150的保護層170。參照圖17M，可在保護層170中形成第一開口部171，且可形成安置於第一開口部171中的第一外部連接端子175。此外，可在囊封劑160的外表面中形成第二開口部161，以便暴露出第三配線層131的至少部分，且可形成安置於第二開口部161中的第二外部連接端子185。在某些情 形中，可僅形成安置於囊封劑160的第二開口部161中的第二外部連接端子185，且可在保護層170中僅形成第一開口部171，並且若需要，則可藉由由購買電子元件封裝100E的客戶進行的單獨製程而形成安置於第一開口部171中的第一外部連接端子175。 Referring to FIG. 17G, the adhesive film 190 may be attached to the second wiring layer 132. Referring to FIG. 17H, the electronic component 120 may be disposed in the through hole 110X. Referring to FIG. 17I, the encapsulant 160 may be used to encapsulate the electronic component 120. Referring to FIG. 17J, the adhesive film 190 can be peeled off. Referring to FIG. 17K, a redistribution portion 140 including a redistribution portion insulating layer 141, a redistribution portion wiring layer 142, and a redistribution portion through hole 143 may be formed. Next, the redistribution portion 150 including the redistribution portion insulating layer 151, the redistribution portion wiring layer 152, and the redistribution portion through hole 153 may be formed. Referring to FIG. 17L, a protective layer 170 connected to the redistribution portions 140 and 150 may be formed. Referring to FIG. 17M, the first opening portion 171 may be formed in the protective layer 170, and the first external connection terminal 175 disposed in the first opening portion 171 may be formed. In addition, a second opening portion 161 may be formed in the outer surface of the encapsulant 160 so as to expose at least a portion of the third wiring layer 131, and a second external connection terminal 185 disposed in the second opening portion 161 may be formed. In certain situations In the shape, only the second external connection terminal 185 disposed in the second opening 161 of the encapsulant 160 may be formed, and only the first opening 171 may be formed in the protective layer 170, and if necessary, by The first external connection terminal 175 disposed in the first opening 171 is formed by a separate process performed by a customer who purchases the electronic component package 100E.

圖18是示意性地說明電子元件封裝的另一實例的剖視圖。 18 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖19是電子元件封裝沿圖18所示的線VI-VI’截取的示意性平面圖。 19 is a schematic plan view of the electronic component package taken along line VI-VI' shown in FIG. 18.

參照圖18及圖19，根據另一實例的電子元件封裝100F可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、用於囊封電子元件120的囊封劑160、安置於囊封劑160上的外配線層162、及穿透過囊封劑160的外通孔163。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、安置於第二絕緣層111B的下表面110B上的第二配線層132、及安置於貫穿孔110X的內表面上的金屬層135。 Referring to FIGS. 18 and 19, an electronic component package 100F according to another example may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a battery 110 disposed under the frame 110 and the electronic component 120 The redistribution portions 140 and 150, the encapsulant 160 for encapsulating the electronic component 120, the outer wiring layer 162 disposed on the encapsulant 160, and the outer through hole 163 penetrating through the encapsulant 160. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer 132 disposed on the lower surface 110B of the second insulating layer 111B And a metal layer 135 disposed on the inner surface of the through hole 110X.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B、及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件 120的上表面與下表面之間的位階處。如圖18中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located in the electronic device 120 at the level between the upper surface and the lower surface. As shown in FIG. 18, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 with respect to the redistribution portions 140 and 150, or It is located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131 as long as both the third wiring layer 131 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100F中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100F according to another example will be explained in more detail, and the contents that are duplicated with the above will not be explained, and the contents that are different from the above will be mainly explained.

外配線層162的安置於囊封劑160上的一部分可為充當接地(GND)圖案的重新分配圖案。此處，金屬層135亦可經由在第三配線層131中充當接地(GND)圖案的重新分配圖案而連接至安置於囊封劑160上的外配線層162。此處，安置於囊封劑160上的外配線層162可以板形式安置於由囊封劑160所囊封的電子元件120之上。在此種情形中，由於電子元件120的上部部分、下部部分、及側部部分的絕大部分被金屬覆蓋，因此熱輻射特性及電磁波阻擋效果可為優異的。作為另一選擇，可藉由對流或輻射來分散熱。 A portion of the outer wiring layer 162 disposed on the encapsulant 160 may be a redistribution pattern that serves as a ground (GND) pattern. Here, the metal layer 135 may also be connected to the outer wiring layer 162 disposed on the encapsulant 160 through a redistribution pattern that serves as a ground (GND) pattern in the third wiring layer 131. Here, the outer wiring layer 162 disposed on the encapsulant 160 may be disposed on the electronic component 120 encapsulated by the encapsulant 160 in the form of a board. In this case, since most of the upper portion, the lower portion, and the side portion of the electronic component 120 are covered with metal, the heat radiation characteristics and the electromagnetic wave blocking effect can be excellent. As another option, heat can be dispersed by convection or radiation.

圖20A至圖20M是說明製造電子元件封裝100F的製程的實例的示意圖。 20A to 20M are schematic diagrams illustrating an example of the manufacturing process of the electronic component package 100F.

在對製造電子元件封裝100F的製程的實例的說明中，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the description of an example of the manufacturing process of the electronic component package 100F, the content that is the same as the above content will not be explained again, and the content that is different from the above content will be mainly explained.

參照圖20A，可製備第一絕緣層111A。參照圖20B，可形成穿透過第一絕緣層111A的上表面及下表面的貫穿孔111Y。參照圖20C，可在第一絕緣層111A的上表面及下表面上分別形成第三配線層131及第一配線層112。此外，可以傳導性材料填充貫穿孔111Y，以形成內部通孔115。參照圖20D，可在第一絕緣層111A的下表面上形成第二絕緣層111B。參照圖20E，可形成穿透過第一絕緣層111A及第二絕緣層111B的貫穿孔110X。此外，可形成穿透過第二絕緣層111B的通孔洞113Y。參照圖20F，可在第二絕緣層111B之下形成第二配線層132，且可在第二絕緣層111B中形成通孔113。此外，可在貫穿孔110X的內表面上形成金屬層135。如此一來，可形成具貫穿孔110X的框架110。 Referring to FIG. 20A, a first insulating layer 111A may be prepared. Referring to FIG. 20B, a through hole 111Y penetrating through the upper and lower surfaces of the first insulating layer 111A may be formed. Referring to FIG. 20C, the third wiring layer 131 and the first wiring layer 112 may be formed on the upper and lower surfaces of the first insulating layer 111A, respectively. In addition, the through hole 111Y may be filled with a conductive material to form the internal through hole 115. Referring to FIG. 20D, a second insulating layer 111B may be formed on the lower surface of the first insulating layer 111A. Referring to FIG. 20E, a through hole 110X may be formed through the first insulating layer 111A and the second insulating layer 111B. In addition, a through hole 113Y penetrating through the second insulating layer 111B may be formed. Referring to FIG. 20F, a second wiring layer 132 may be formed under the second insulating layer 111B, and a through hole 113 may be formed in the second insulating layer 111B. In addition, a metal layer 135 may be formed on the inner surface of the through hole 110X. In this way, the frame 110 with the through hole 110X can be formed.

與圖中所示者不同，可藉由封孔方法等而首先在第一絕緣層111A的僅下表面上形成第一配線層112，可在第一絕緣層111A的下表面上形成第二絕緣層111B，且可形成通孔洞113Y、貫穿孔111Y、及貫穿孔110X。接著，在藉由以傳導性材料填充通孔洞113Y及貫穿孔111Y而形成通孔113及內部通孔115的同時可在貫穿孔110X的內壁上形成金屬層135。同時，可在第一絕緣層111A的上表面及第二絕緣層111B的下表面上分別形成第三配線層131及第二配線層132。 Unlike the ones shown in the figure, the first wiring layer 112 can be formed on only the lower surface of the first insulating layer 111A by a hole sealing method, etc., and the second insulation can be formed on the lower surface of the first insulating layer 111A Layer 111B, and may form a through hole 113Y, a through hole 111Y, and a through hole 110X. Next, the metal layer 135 may be formed on the inner wall of the through hole 110X while forming the through hole 113 and the inner through hole 115 by filling the through hole 113Y and the through hole 111Y with a conductive material. Meanwhile, a third wiring layer 131 and a second wiring layer 132 may be formed on the upper surface of the first insulating layer 111A and the lower surface of the second insulating layer 111B, respectively.

參照圖20G，可將黏合膜190貼附至第二配線層132。參照圖20H，可在貫穿孔110X中安置電子元件120。參照圖20I，可使用囊封劑160對電子元件120進行囊封。參照圖20J，可剝除黏合膜190。參照圖20K，可形成包括重新分配部絕緣層141、重新分配部配線層142、及重新分配部通孔143的重新分配部140。接著，可形成包括重新分配部絕緣層151、重新分配部配線層152、及重新分配部通孔153的重新分配部150。參照圖20L，可形成連接至重新分配部140及150的保護層170以及連接至囊封劑160的覆蓋層180。參照圖20M，可在覆蓋層180的外表面中形成第三開口部181，以便暴露出外配線層162的至少部分，且可形成安置於第三開口部181中的第二外部連接端子185。此外，可形成保護層170的第一開口部171及安置於第一開口部171中的第一外部連接端子175。在某些情形中，可僅形成安置於覆蓋層180的第三開口部181中的第二外部連接端子185，且可在保護層170中僅形成第一開口部171，並且若需要，則可藉由由購買電子元件封裝100F的客戶進行的單獨製程而形成安置於第一開口部171中的第一外部連接端子175。 Referring to FIG. 20G, the adhesive film 190 may be attached to the second wiring layer 132. Referring to FIG. 20H, the electronic component 120 may be disposed in the through hole 110X. Referring to FIG. 20I, the encapsulant 160 may be used to encapsulate the electronic component 120. Referring to FIG. 20J, the adhesive film 190 can be peeled off. Referring to FIG. 20K, a redistribution portion 140 including a redistribution portion insulating layer 141, a redistribution portion wiring layer 142, and a redistribution portion through hole 143 may be formed. Next, the redistribution portion 150 including the redistribution portion insulating layer 151, the redistribution portion wiring layer 152, and the redistribution portion through hole 153 may be formed. Referring to FIG. 20L, a protective layer 170 connected to the redistribution parts 140 and 150 and a cover layer 180 connected to the encapsulant 160 may be formed. Referring to FIG. 20M, a third opening portion 181 may be formed in the outer surface of the cover layer 180 so as to expose at least a portion of the outer wiring layer 162, and a second external connection terminal 185 disposed in the third opening portion 181 may be formed. In addition, the first opening 171 of the protective layer 170 and the first external connection terminal 175 disposed in the first opening 171 may be formed. In some cases, only the second external connection terminal 185 disposed in the third opening 181 of the cover layer 180 may be formed, and only the first opening 171 may be formed in the protective layer 170, and if necessary, The first external connection terminal 175 disposed in the first opening 171 is formed by a separate process performed by a customer who purchases the electronic component package 100F.

圖21是示意性地說明電子元件封裝的另一實例的剖視圖。 21 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖22是電子元件封裝沿圖21所示的線VII-VII’截取的示意性平面圖。 Fig. 22 is a schematic plan view of the electronic component package taken along line VII-VII' shown in Fig. 21.

參照圖21及圖22，根據另一實例的電子元件封裝100G 可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的多個電子元件120及122、安置於框架110及所述多個電子元件120及122下的重新分配部140及150、以及用於囊封所述多個電子元件120及122的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、安置於第一絕緣層111A的上表面上的金屬層135、安置於第二絕緣層111B的下表面上的第二配線層132、及穿透過第二絕緣層111B的通孔113。 21 and 22, an electronic component package 100G according to another example It may include a frame 110 having a through hole 110X, a plurality of electronic components 120 and 122 disposed in the through hole 110X of the frame 110, a redistribution portion 140 and 150 disposed under the frame 110 and the plurality of electronic components 120 and 122 And an encapsulant 160 for encapsulating the plurality of electronic components 120 and 122. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and a first insulating layer 111A disposed on the upper surface of the first insulating layer 111A The metal layer 135, the second wiring layer 132 disposed on the lower surface of the second insulating layer 111B, and the through hole 113 penetrating through the second insulating layer 111B.

貫穿孔110X可依序穿透過金屬層135、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於所述多個電子元件120及122中的一者的上表面與下表面之間的位階處。如圖21中所示，所述多個電子元件120及122的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。所述多個電子元件120及122的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於金屬層135的上表面下、或者位於與金屬層135的上表面相同的位階處或位於金屬層135的上表面之上，只要金屬層135以及所述多個電子元件120及122皆被囊封劑160覆蓋即可。當所述多個電子元件120及122的厚度不同時，所述多個電子元件120及122的上表面可位於不同的位階處。 The through hole 110X may penetrate the metal layer 135, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in sequence. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of one of the plurality of electronic devices 120 and 122. As shown in FIG. 21, the upper surfaces of the plurality of electronic components 120 and 122 are located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surfaces of the plurality of electronic components 120 and 122 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but above the metal layer 135 relative to the redistribution portions 140 and 150. Under the surface, or at the same level as the upper surface of the metal layer 135 or above the upper surface of the metal layer 135, as long as the metal layer 135 and the plurality of electronic components 120 and 122 are covered by the encapsulant 160 . When the thicknesses of the plurality of electronic components 120 and 122 are different, the upper surfaces of the plurality of electronic components 120 and 122 may be located at different levels.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100G中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100G according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

所述多個電子元件120及122可彼此相同或彼此不同。所述多個電子元件120及122可分別具有電性連接至框架110、重新分配部140及150等的電極焊墊120P及122P。電極焊墊120P及122P可分別藉由框架110、重新分配部140及150等而重新分配。電子元件120及122的數目、間距、配置形式等並無特別限制，且可由熟習此項技術者依設計特定細節充分地進行修改。舉例而言，如圖21及圖22中所示，電子元件120及122的數目可為兩個。然而，電子元件120及122的數目並非僅限於此，且可為二或更多個，例如為三個、四個等。若需要，則可在貫穿孔110X的內表面上進一步安置金屬層135。 The plurality of electronic components 120 and 122 may be the same as each other or different from each other. The plurality of electronic components 120 and 122 may have electrode pads 120P and 122P electrically connected to the frame 110, the redistribution portions 140 and 150, etc., respectively. The electrode pads 120P and 122P can be redistributed by the frame 110, the redistribution parts 140 and 150, etc., respectively. The number, pitch, configuration, etc. of the electronic components 120 and 122 are not particularly limited, and can be sufficiently modified by those skilled in the art according to the specific details of the design. For example, as shown in FIGS. 21 and 22, the number of electronic components 120 and 122 may be two. However, the number of electronic components 120 and 122 is not limited to this, and may be two or more, such as three, four, etc. If necessary, a metal layer 135 may be further disposed on the inner surface of the through hole 110X.

由於除安置所述多個電子元件120及122以外，根據另一實例的製造電子元件封裝100G的方法與製造電子元件封裝100A及100D的方法相同，因此將不再對其予以闡述。 Since the method of manufacturing the electronic component package 100G according to another example is the same as the method of manufacturing the electronic component packages 100A and 100D except that the plurality of electronic components 120 and 122 are disposed, they will not be described again.

圖23是示意性地說明電子元件封裝的另一實例的剖視圖。 23 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖24是電子元件封裝沿圖23所示的線VIII-VIII’截取的示意性平面圖。 24 is a schematic plan view of the electronic component package taken along line VIII-VIII' shown in FIG. 23.

參照圖23及圖24，根據另一實例的電子元件封裝100H可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔 110X中的多個電子元件120及122、安置於框架110以及所述多個電子元件120及122下的重新分配部140及150、以及用於囊封所述多個電子元件120及122的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、及安置於第二絕緣層111B的下表面110B上的第二配線層132。 23 and 24, an electronic component package 100H according to another example may include a frame 110 having a through hole 110X, and a through hole disposed in the frame 110 The plurality of electronic components 120 and 122 in 110X, the redistribution portions 140 and 150 disposed under the frame 110 and the plurality of electronic components 120 and 122, and the capsule for encapsulating the plurality of electronic components 120 and 122封剂160. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於所述多個電子元件120及122中的一者的上表面與下表面之間的位階處。如圖23中所示，所述多個電子元件120及122的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。所述多個電子元件120及122的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及所述多個電子元件120及122皆被囊封劑160覆蓋即可。當所述多個電子元件120及122的厚度不同時，所述多個電子元件120及122的上表面可位於不同的位階處。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of one of the plurality of electronic devices 120 and 122. As shown in FIG. 23, the upper surfaces of the plurality of electronic components 120 and 122 are located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surfaces of the plurality of electronic components 120 and 122 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but on the third wiring layer 131 relative to the redistribution portions 140 and 150. Of the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131, as long as the third wiring layer 131 and the plurality of electronic components 120 and 122 are It is sufficient to be covered by the encapsulant 160. When the thicknesses of the plurality of electronic components 120 and 122 are different, the upper surfaces of the plurality of electronic components 120 and 122 may be located at different levels.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100H中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100H according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

另外，在其中安置有所述多個電子元件120及122的情形中，可應用分別安置於框架110的上表面110A及下表面110B上的第三配線層131及第二配線層132，以及穿透過第一絕緣層111A的內部通孔115。同樣地，囊封劑160可具有第二開口部161，第二開口部161暴露出安置於框架110的上表面110A上的第三配線層131的至少部分，且電子元件封裝100H可包括經由囊封劑160的外表面而暴露於外部的第二外部連接端子185。若需要，則可在貫穿孔110X的內表面上進一步安置金屬層135。 In addition, in the case where the plurality of electronic components 120 and 122 are disposed, the third wiring layer 131 and the second wiring layer 132 disposed on the upper surface 110A and the lower surface 110B of the frame 110, respectively, and through Through the internal via 115 of the first insulating layer 111A. Likewise, the encapsulant 160 may have a second opening 161 that exposes at least a portion of the third wiring layer 131 disposed on the upper surface 110A of the frame 110, and the electronic component package 100H may include a via The outer surface of the sealant 160 is exposed to the outside of the second external connection terminal 185. If necessary, a metal layer 135 may be further disposed on the inner surface of the through hole 110X.

由於除安置所述多個電子元件120及122以外，根據另一實例的製造電子元件封裝100H的方法與製造電子元件封裝100B及100E的方法相同，因此將不再對其予以闡述。 Since the method of manufacturing the electronic component package 100H according to another example is the same as the method of manufacturing the electronic component packages 100B and 100E except that the plurality of electronic components 120 and 122 are disposed, they will not be described again.

圖25是示意性地說明電子元件封裝的另一實例的剖視圖。 25 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖26是電子元件封裝沿圖25所示的線IX-IX’截取的示意性平面圖。 Fig. 26 is a schematic plan view of the electronic component package taken along line IX-IX' shown in Fig. 25.

參照圖25及圖26，根據另一實例的電子元件封裝100I可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的多個電子元件120及122、安置於框架110及所述多個電子元件120及122下的重新分配部140及150、用於囊封所述多 個電子元件120及122的囊封劑160、安置於囊封劑160上的外配線層162、以及穿透過囊封劑160的外通孔163。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、及安置於第二絕緣層111B的下表面110B上的第二配線層132。 25 and 26, an electronic component package 100I according to another example may include a frame 110 having a through-hole 110X, a plurality of electronic components 120 and 122 disposed in the through-hole 110X of the frame 110, a frame 110 and all The redistribution sections 140 and 150 under the multiple electronic components 120 and 122 are used to encapsulate the multiple The encapsulant 160 of the electronic components 120 and 122, the outer wiring layer 162 disposed on the encapsulant 160, and the outer through hole 163 penetrating through the encapsulant 160. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於所述多個電子元件120及122中的一者的上表面與下表面之間的位階處。如圖25中所示，所述多個電子元件120及122的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。所述多個電子元件120及122的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131以及所述多個電子元件120及122皆被囊封劑160覆蓋即可。當所述多個電子元件120及122的厚度不同時，所述多個電子元件120及122的上表面可位於不同的位階處。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of one of the plurality of electronic devices 120 and 122. As shown in FIG. 25, the upper surfaces of the plurality of electronic components 120 and 122 are located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surfaces of the plurality of electronic components 120 and 122 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but on the third wiring layer 131 relative to the redistribution portions 140 and 150. Of the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131, as long as the third wiring layer 131 and the plurality of electronic components 120 and 122 are It is sufficient to be covered by the encapsulant 160. When the thicknesses of the plurality of electronic components 120 and 122 are different, the upper surfaces of the plurality of electronic components 120 and 122 may be located at different levels.

在下文中，將更詳細地闡述包含於根據另一實例的電子 元件封裝100I中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the electronic contained in another example will be explained in more detail Corresponding components in the component package 100I will no longer explain the content that is duplicated with the above content, and will mainly explain the content that is different from the above content.

另外，在其中安置有所述多個電子元件120及122的情形中，可應用安置於囊封劑160上的外配線層162及穿透過囊封劑160的外通孔163。同樣地，電子元件封裝100I可更包括連接至囊封劑160的覆蓋層180。覆蓋層180可具有第三開口部181，第三開口部181暴露出安置於囊封劑160上的外配線層162的至少部分。此外，電子元件封裝100I可更包括經由覆蓋層180的上表面而暴露於外部的第二外部連接端子185。若需要，則可在貫穿孔110X的內表面上進一步安置金屬層135。 In addition, in the case where the plurality of electronic components 120 and 122 are disposed, the outer wiring layer 162 disposed on the encapsulant 160 and the outer through hole 163 penetrating through the encapsulant 160 may be applied. Similarly, the electronic component package 100I may further include a cover layer 180 connected to the encapsulant 160. The cover layer 180 may have a third opening portion 181 that exposes at least a portion of the outer wiring layer 162 disposed on the encapsulant 160. In addition, the electronic component package 100I may further include a second external connection terminal 185 exposed to the outside through the upper surface of the cover layer 180. If necessary, a metal layer 135 may be further disposed on the inner surface of the through hole 110X.

由於除安置所述多個電子元件120及122以外，根據另一實例的製造電子元件封裝100I的方法與製造電子元件封裝100C及100F的方法相同，因此將不再對其予以闡述。 Since the method of manufacturing the electronic component package 100I according to another example is the same as the method of manufacturing the electronic component packages 100C and 100F except that the plurality of electronic components 120 and 122 are disposed, they will not be described again.

圖27是示意性地說明電子元件封裝的另一實例的剖視圖。 FIG. 27 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖28是電子元件封裝沿圖27所示的線X-X’截取的示意性平面圖。 28 is a schematic plan view of the electronic component package taken along line X-X' shown in FIG. 27.

參照圖27及圖28，根據另一實例的電子元件封裝100J可包括具有多個貫穿孔110X1及110X2的框架110；分別安置於框架110的所述多個貫穿孔110X1及110X2中的多個電子元件120及122；安置於框架110及所述多個電子元件120及122下的重新分配部140及150；以及用於囊封所述多個電子元件120及122 的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、安置於第一絕緣層111A的上表面上的金屬層135、安置於第二絕緣層111B的下表面上的第二配線層132及穿透過第二絕緣層111B的通孔113。 27 and 28, an electronic component package 100J according to another example may include a frame 110 having a plurality of through holes 110X1 and 110X2; a plurality of electrons disposed in the plurality of through holes 110X1 and 110X2 of the frame 110, respectively Components 120 and 122; redistribution portions 140 and 150 disposed under the frame 110 and the plurality of electronic components 120 and 122; and for encapsulating the plurality of electronic components 120 and 122 的encapsulant 160. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and a first insulating layer 111A disposed on the upper surface of the first insulating layer 111A The metal layer 135, the second wiring layer 132 disposed on the lower surface of the second insulating layer 111B, and the through hole 113 penetrating through the second insulating layer 111B.

所述多個貫穿孔110X1及110X2中的每一者可依序穿透過金屬層135、第一絕緣層111A、第一配線層112、第二絕緣層111B、及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於所述多個電子元件120及122中的一者的上表面與下表面之間的位階處。如圖27中所示，所述多個電子元件120及122的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。所述多個電子元件120及122的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於金屬層135的上表面下、或者位於與金屬層135的上表面相同的位階處或位於金屬層135的上表面之上，只要金屬層135以及所述多個電子元件120及122皆被囊封劑160覆蓋即可。當所述多個電子元件120及122的厚度不同時，所述多個電子元件120及122的上表面可位於不同的位階處。 Each of the plurality of through holes 110X1 and 110X2 may sequentially pass through the metal layer 135, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of one of the plurality of electronic devices 120 and 122. As shown in FIG. 27, the upper surfaces of the plurality of electronic components 120 and 122 are located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surfaces of the plurality of electronic components 120 and 122 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but above the metal layer 135 relative to the redistribution portions 140 and 150. Under the surface, or at the same level as the upper surface of the metal layer 135 or above the upper surface of the metal layer 135, as long as the metal layer 135 and the plurality of electronic components 120 and 122 are covered by the encapsulant 160 . When the thicknesses of the plurality of electronic components 120 and 122 are different, the upper surfaces of the plurality of electronic components 120 and 122 may be located at different levels.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100J中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding elements included in the electronic component package 100J according to another example will be explained in more detail, and the contents that are duplicated with the above will not be explained, and the contents that are different from the above will be mainly explained.

所述多個貫穿孔110X1及110X2的面積、形狀等可彼此形同或彼此不同，且分別安置於貫穿孔110X1及110X2中的電子元件120及122亦可彼此相同或彼此不同。貫穿孔110X1及110X2的數目、間距、配置形式等以及分別安置於貫穿孔110X1及110X2中的電子元件120及122的數目、間距、配置形式等並無特別限制，且可由熟習此項技術者依設計特定細節充分地進行修改。舉例而言，如圖27及圖28中所示，貫穿孔110X1及110X2的數目可為兩個。然而，貫穿孔110X1及110X2的數目並非僅限於此，且可為二或更多個，例如三個、四個等。此外，如圖27及圖28中所示，分別安置於貫穿孔110X1及110X2中的電子元件120及122的數目可為一個。然而，分別安置於貫穿孔110X1及110X2中的電子元件120及122的數目並非僅限於此，且可為一或多個，例如兩個、三個等。若需要，則可在所述多個貫穿孔110X1及110X2的內表面上進一步安置金屬層135。 The areas and shapes of the plurality of through holes 110X1 and 110X2 may be the same as or different from each other, and the electronic components 120 and 122 respectively disposed in the through holes 110X1 and 110X2 may be the same as or different from each other. The number, pitch, configuration, etc. of the through holes 110X1 and 110X2 and the number, pitch, configuration, etc. of the electronic components 120 and 122 disposed in the through holes 110X1 and 110X2, respectively, are not particularly limited, and can be determined by those skilled in the art Design specific details are fully modified. For example, as shown in FIGS. 27 and 28, the number of through holes 110X1 and 110X2 may be two. However, the number of through holes 110X1 and 110X2 is not limited to this, and may be two or more, such as three, four, and so on. In addition, as shown in FIGS. 27 and 28, the number of electronic components 120 and 122 disposed in the through holes 110X1 and 110X2, respectively, may be one. However, the number of electronic components 120 and 122 disposed in the through holes 110X1 and 110X2, respectively, is not limited to this, and may be one or more, such as two, three, etc. If necessary, a metal layer 135 may be further disposed on the inner surfaces of the plurality of through holes 110X1 and 110X2.

由於除形成所述多個貫穿孔110X1及110X2並在所述多個貫穿孔110X1及110X2中分別安置所述多個電子元件120及122以外，根據另一實例的製造電子元件封裝100J的方法與製造電子元件封裝100A及100D的方法相同，因此將不再對其予以闡述。 Since in addition to forming the plurality of through holes 110X1 and 110X2 and arranging the plurality of electronic components 120 and 122 in the plurality of through holes 110X1 and 110X2, respectively, a method of manufacturing an electronic component package 100J according to another example and The methods of manufacturing the electronic component packages 100A and 100D are the same, so they will not be described again.

圖29是示意性地說明電子元件封裝的另一實例的剖視圖。 29 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖30是電子元件封裝沿圖29所示的線XI-XI’截取的示意性平面圖。 Fig. 30 is a schematic plan view of the electronic component package taken along line XI-XI' shown in Fig. 29.

參照圖29及圖30，根據另一實例的電子元件封裝100K可包括具有多個貫穿孔110X1及110X2的框架110、分別安置於框架110的所述多個貫穿孔110X1及110X2中的多個電子元件120及122、安置於框架110及所述多個電子元件120及122下的重新分配部140及150、以及用於囊封所述多個電子元件120及122的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、以及安置於第二絕緣層111B的下表面110B上的第二配線層132。 29 and 30, an electronic component package 100K according to another example may include a frame 110 having a plurality of through holes 110X1 and 110X2, and a plurality of electrons disposed in the plurality of through holes 110X1 and 110X2 of the frame 110, respectively The components 120 and 122, the redistribution portions 140 and 150 disposed under the frame 110 and the plurality of electronic components 120 and 122, and the encapsulant 160 for encapsulating the plurality of electronic components 120 and 122. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132.

所述多個貫穿孔110X1及110X2中的每一者可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於所述多個電子元件120及122中的一者的上表面與下表面之間的位階處。如圖29中所示，所述多個電子元件120及122的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。所述多個電子元件120及122的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表 面之上，只要第三配線層131以及所述多個電子元件120及122皆被囊封劑160覆蓋即可。當所述多個電子元件120及122的厚度不同時，所述多個電子元件120及122的上表面可位於不同的位階處。 Each of the plurality of through holes 110X1 and 110X2 may sequentially pass through the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of one of the plurality of electronic devices 120 and 122. As shown in FIG. 29, the upper surfaces of the plurality of electronic components 120 and 122 are located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surfaces of the plurality of electronic components 120 and 122 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but on the third wiring layer 131 relative to the redistribution portions 140 and 150. Is located under the upper surface of the third wiring layer 131 or at the same level as the upper surface of the third wiring layer 131 Above the surface, as long as the third wiring layer 131 and the plurality of electronic components 120 and 122 are covered with the encapsulant 160. When the thicknesses of the plurality of electronic components 120 and 122 are different, the upper surfaces of the plurality of electronic components 120 and 122 may be located at different levels.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100K中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100K according to another example will be explained in more detail, and the contents that are duplicated with the above will not be explained, and the contents that are different from the above will be mainly explained.

另外，在其中形成所述多個貫穿孔110X1及110X2並在所述多個貫穿孔110X1及110X2中分別安置電子元件120及122的情形中，可應用分別安置於框架110的上表面110A及下表面110B上的第三配線層131及第二配線層132、以及穿透過第一絕緣層111A的內部通孔115。第三配線層131及第二配線層132以及內部通孔115亦可形成於框架110的第一絕緣層111A的劃分所述多個貫穿孔110X1及110X2的中心部分中。同樣地，囊封劑160可具有第二開口部161，第二開口部161暴露出安置於框架110的上表面110A上的第三配線層131的至少部分，且電子元件封裝100K可包括經由囊封劑160的外表面而暴露於外部的第二外部連接端子185。第二開口部161及第二外部連接端子185亦可形成於框架110的第一絕緣層111A的劃分所述多個貫穿孔110X1及110X2的中心部分中。若需要，則可在所述多個貫穿孔110X1及110X1的內表面上進一步安置金屬層135。 In addition, in the case where the plurality of through-holes 110X1 and 110X2 are formed and the electronic components 120 and 122 are respectively disposed in the plurality of through-holes 110X1 and 110X2, it can be applied to be disposed on the upper surface 110A and the lower surface of the frame 110 The third wiring layer 131 and the second wiring layer 132 on the surface 110B, and the internal via 115 that penetrates the first insulating layer 111A. The third wiring layer 131 and the second wiring layer 132 and the internal through hole 115 may also be formed in the central portion of the first insulating layer 111A of the frame 110 that partitions the plurality of through holes 110X1 and 110X2. Likewise, the encapsulant 160 may have a second opening 161 that exposes at least a portion of the third wiring layer 131 disposed on the upper surface 110A of the frame 110, and the electronic component package 100K may include a via The outer surface of the sealant 160 is exposed to the outside of the second external connection terminal 185. The second opening 161 and the second external connection terminal 185 may also be formed in the central portion of the first insulating layer 111A of the frame 110 that partitions the plurality of through holes 110X1 and 110X2. If necessary, a metal layer 135 may be further disposed on the inner surfaces of the plurality of through holes 110X1 and 110X1.

由於除形成所述多個貫穿孔110X1及110X2並在所述多 個貫穿孔110X1及110X2中分別安置所述多個電子元件120及122以外，根據另一實例的製造電子元件封裝100K的方法與製造電子元件封裝100B及100E的方法相同，因此將不再對其予以闡述。 Due to the formation of the multiple through holes 110X1 and 110X2 and in the multiple The two through holes 110X1 and 110X2 are provided with the plurality of electronic components 120 and 122, respectively. According to another example, the method of manufacturing the electronic component package 100K is the same as the method of manufacturing the electronic component packages 100B and 100E, so it will not be Be elaborated.

圖31是示意性地說明電子元件封裝的另一實例的剖視圖。 31 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖32是電子元件封裝沿圖31所示的線XII-XII’截取的示意性平面圖。 32 is a schematic plan view of the electronic component package taken along the line XII-XII' shown in FIG. 31.

參照圖31及圖32，根據另一實例的電子元件封裝100L可包括具有多個貫穿孔110X1及110X2的框架110、分別安置於框架110的所述多個貫穿孔110X1及110X2中的多個電子元件120及122、安置於框架110及所述多個電子元件120及122下的重新分配部140及150、用於囊封所述多個電子元件120及122的囊封劑160、安置於囊封劑160上的外配線層162、以及穿透過囊封劑160的外通孔163。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、以及安置於第二絕緣層111B的下表面110B上的第二配線層132。 31 and 32, an electronic component package 100L according to another example may include a frame 110 having a plurality of through holes 110X1 and 110X2, and a plurality of electrons disposed in the plurality of through holes 110X1 and 110X2 of the frame 110, respectively Components 120 and 122, redistribution portions 140 and 150 disposed under the frame 110 and the plurality of electronic components 120 and 122, an encapsulant 160 for encapsulating the plurality of electronic components 120 and 122, disposed in the capsule The outer wiring layer 162 on the encapsulant 160 and the outer through hole 163 penetrating through the encapsulant 160. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132.

所述多個貫穿孔110X1及110X2中的每一者可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B 中的至少一者可位於所述多個電子元件120及122中的一者的上表面與下表面之間的位階處。如圖31中所示，所述多個電子元件120及122的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。所述多個電子元件120及122的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131以及所述多個電子元件120及122皆被囊封劑160覆蓋即可。當所述多個電子元件120及122的厚度不同時，所述多個電子元件120及122的上表面可位於不同的位階處。 Each of the plurality of through holes 110X1 and 110X2 may sequentially pass through the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132. The first wiring layer 112 and the second insulating layer 111B At least one of them may be located at a level between the upper surface and the lower surface of one of the plurality of electronic components 120 and 122. As shown in FIG. 31, the upper surfaces of the plurality of electronic components 120 and 122 are located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surfaces of the plurality of electronic components 120 and 122 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but on the third wiring layer 131 relative to the redistribution portions 140 and 150. Of the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131, as long as the third wiring layer 131 and the plurality of electronic components 120 and 122 are It is sufficient to be covered by the encapsulant 160. When the thicknesses of the plurality of electronic components 120 and 122 are different, the upper surfaces of the plurality of electronic components 120 and 122 may be located at different levels.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100L中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100L according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

另外，在其中形成所述多個貫穿孔110X1及110X2並在所述多個貫穿孔110X1及110X2中分別安置所述多個電子元件120及122的情形中，可應用安置於囊封劑160上的外配線層162及穿透過囊封劑160的外通孔163。外配線層162及外通孔163亦可形成於框架110的第一絕緣層111A的劃分所述多個貫穿孔110X1及110X2的中心部分中。同樣地，電子元件封裝100L可更包括連接至囊封劑160的覆蓋層180。覆蓋層180可具有第三開口 部181，第三開口部181暴露出安置於囊封劑160上的外配線層162的至少部分。此外，電子元件封裝100L可更包括經由覆蓋層180的上表面而暴露於外部的第二外部連接端子185。第三開口部181及第二外部連接端子185亦可形成於框架110的第一絕緣層111A的劃分所述多個貫穿孔110X1及110X2的中心部分中。若需要，則可在所述多個貫穿孔110X1及110X2的內表面上進一步安置金屬層135。 In addition, in the case where the plurality of through-holes 110X1 and 110X2 are formed and the plurality of electronic components 120 and 122 are respectively disposed in the plurality of through-holes 110X1 and 110X2, placement on the encapsulant 160 may be applied The outer wiring layer 162 and the outer through hole 163 penetrating through the encapsulant 160. The outer wiring layer 162 and the outer through hole 163 may also be formed in the central portion of the first insulating layer 111A of the frame 110 that partitions the plurality of through holes 110X1 and 110X2. Similarly, the electronic component package 100L may further include a cover layer 180 connected to the encapsulant 160. The cover layer 180 may have a third opening In the portion 181, the third opening 181 exposes at least a portion of the outer wiring layer 162 disposed on the encapsulant 160. In addition, the electronic component package 100L may further include a second external connection terminal 185 exposed to the outside through the upper surface of the cover layer 180. The third opening 181 and the second external connection terminal 185 may also be formed in the central portion of the first insulating layer 111A of the frame 110 that partitions the plurality of through holes 110X1 and 110X2. If necessary, a metal layer 135 may be further disposed on the inner surfaces of the plurality of through holes 110X1 and 110X2.

由於除形成所述多個貫穿孔110X1及110X2並在所述多個貫穿孔110X1及110X2中分別安置所述多個電子元件120及122以外，根據另一實例的製造電子元件封裝100L的方法與製造電子元件封裝100C及100F的方法相同，因此將不再對其予以闡述。 Since in addition to forming the plurality of through holes 110X1 and 110X2 and arranging the plurality of electronic components 120 and 122 in the plurality of through holes 110X1 and 110X2, respectively, a method of manufacturing an electronic component package 100L according to another example and The methods of manufacturing the electronic component packages 100C and 100F are the same, so they will not be described again.

圖33是示意性地說明電子元件封裝的另一實例的剖視圖。 33 is a cross-sectional view schematically illustrating another example of electronic component packaging.

圖34是電子元件封裝沿圖33所示的線XIII-XIII’截取的示意性平面圖。 34 is a schematic plan view of the electronic component package taken along the line XIII-XIII' shown in FIG. 33.

參照圖33及圖34，根據另一實例的電子元件封裝100M可包括具有貫穿孔110X的框架110、分別安置於框架110的貫穿孔110X中的多個電子元件120及124、安置於框架110及所述多個電子元件120及124下的重新分配部140及150、以及用於囊封所述多個電子元件120及124的囊封劑160。所述多個電子元件120及124中的至少一者可為積體電路，且所述多個電子元件120及124中的其他電子元件可為被動元件。框架110可包括第一絕 緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、以及安置於第二絕緣層111B的下表面110B上的第二配線層132。 Referring to FIGS. 33 and 34, an electronic component package 100M according to another example may include a frame 110 having a through hole 110X, a plurality of electronic components 120 and 124 disposed in the through holes 110X of the frame 110, and a frame 110 and Redistribution portions 140 and 150 under the plurality of electronic components 120 and 124, and an encapsulant 160 for encapsulating the plurality of electronic components 120 and 124. At least one of the plurality of electronic components 120 and 124 may be an integrated circuit, and the other electronic components of the plurality of electronic components 120 and 124 may be passive components. The frame 110 may include a first The edge layer 111A, the second insulating layer 111B, the first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, the internal via 115 penetrating through the first insulating layer 111A, penetrating the second insulation The through hole 113 of the layer 111B, the third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and the second wiring layer 132 disposed on the lower surface 110B of the second insulating layer 111B.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於所述多個電子元件120及124中的一者的上表面與下表面之間的位階處。如圖33中所示，所述多個電子元件120及124的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。所述多個電子元件120及124的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131以及所述多個電子元件120及124皆被囊封劑160覆蓋即可。當所述多個電子元件120及124的厚度不同時，所述多個電子元件120及124的上表面可位於不同的位階處。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of one of the plurality of electronic devices 120 and 124. As shown in FIG. 33, the upper surfaces of the plurality of electronic components 120 and 124 are located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surfaces of the plurality of electronic components 120 and 124 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but on the third wiring layer 131 relative to the redistribution portions 140 and 150. Is located below the upper surface of the third wiring layer 131 or at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131, as long as the third wiring layer 131 and the plurality of electronic components 120 and 124 are both It is sufficient to be covered by the encapsulant 160. When the thicknesses of the plurality of electronic components 120 and 124 are different, the upper surfaces of the plurality of electronic components 120 and 124 may be located at different levels.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100M中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100M according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

電子元件120指示其中將數百至數百萬個或更多個組件整合於一起的晶片，且可為例如：應用處理器晶片，例如中央處理器(例如，中央處理單元)、圖形處理器(例如，圖形處理單元)、數位訊號處理器、密碼學處理器、微處理器、微控制器等，但並非僅限於此。電子元件124可為例如電感器、電容器、電阻器等，但並非僅限於此。電子元件120可經由電極焊墊120P而電性連接至框架110、重新分配部140及150等。電子元件124可經由例如外部電極等電極焊墊(圖中未示出)而電性連接至框架110、重新分配部140及150等。 The electronic component 120 indicates a chip in which hundreds to millions or more components are integrated together, and may be, for example: an application processor chip, such as a central processor (eg, central processing unit), a graphics processor ( For example, graphics processing unit), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc., but not limited to this. The electronic component 124 may be, for example, an inductor, a capacitor, a resistor, etc., but it is not limited thereto. The electronic component 120 may be electrically connected to the frame 110, the redistribution portions 140 and 150, etc. via the electrode pad 120P. The electronic component 124 can be electrically connected to the frame 110, the redistribution portions 140 and 150, etc. via electrode pads (not shown) such as external electrodes.

電子元件120及124的數目、間距、配置形式等並無特別限制，且可由熟習此項技術者依設計特定細節充分地進行修改。舉例而言，電子元件120及124可安置於貫穿孔110X的中心附近及貫穿孔110X的內壁附近，但並非僅限於此。此外，電子元件120的數目可為一個且電子元件124的數目可為複數個。然而，電子元件120及124的數目並非僅限於此。舉例而言，電子元件120的數目可為複數個且電子元件124的數目可為一個，電子元件120及124二者的數目均可為一個，或者電子元件120及124二者的數目均可為複數個。若需要，則亦可應用金屬層135、保護層170、覆蓋層180、第二開口部161、第一開口部171及第三開口部181、第一外部連接端子175及第二外部連接端子185、外配線層162、外通孔163等。 The number, pitch, configuration, etc. of the electronic components 120 and 124 are not particularly limited, and can be fully modified by those skilled in the art according to the specific details of the design. For example, the electronic components 120 and 124 may be disposed near the center of the through hole 110X and near the inner wall of the through hole 110X, but it is not limited thereto. In addition, the number of electronic components 120 may be one and the number of electronic components 124 may be plural. However, the number of electronic components 120 and 124 is not limited to this. For example, the number of electronic components 120 may be plural and the number of electronic components 124 may be one, the number of both electronic components 120 and 124 may be one, or the number of both electronic components 120 and 124 may be Plural. If necessary, the metal layer 135, the protective layer 170, the cover layer 180, the second opening 161, the first opening 171 and the third opening 181, the first external connection terminal 175 and the second external connection terminal 185 can also be applied , Outer wiring layer 162, outer through hole 163, etc.

由於除將電子元件120及124彼此安置於一起以外，根 據另一實例的製造電子元件封裝100M的方法與製造電子元件封裝100A至100F的方法相同，因此將不再對其予以闡述。 Since the electronic components 120 and 124 are placed together, the root The method of manufacturing the electronic component package 100M according to another example is the same as the method of manufacturing the electronic component packages 100A to 100F, and therefore will not be described again.

圖35是示意性地說明電子元件封裝的另一實例的剖視圖。 35 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖35，根據另一實例的電子元件封裝100N可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、以及穿透過第二絕緣層111B的通孔113。第二絕緣層111B可安置於第一絕緣層111A之上。框架110可包括安置於第二絕緣層111B的上表面110A上的第三配線層131、及安置於框架110的下表面110B上的第二配線層132。 35, an electronic component package 100N according to another example may include a frame 110 having a through-hole 110X, an electronic component 120 disposed in the through-hole 110X of the frame 110, a redistribution portion disposed under the frame 110 and the electronic component 120 140 and 150, and an encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A And a through hole 113 penetrating through the second insulating layer 111B. The second insulating layer 111B may be disposed on the first insulating layer 111A. The frame 110 may include a third wiring layer 131 disposed on the upper surface 110A of the second insulating layer 111B, and a second wiring layer 132 disposed on the lower surface 110B of the frame 110.

貫穿孔110X可依序穿透過第三配線層131、第二絕緣層111B、第一配線層112、第一絕緣層111A及第二配線層132。第一配線層112及第一絕緣層111A中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖35中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第 三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the second insulating layer 111B, the first wiring layer 112, the first insulating layer 111A, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the first insulating layer 111A may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 35, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150 or above the upper surface 110A of the frame 110 but at the first The upper surface of the third wiring layer 131, or at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131, as long as the third wiring layer 131 and the electronic component 120 are both encapsulated The sealant 160 can be covered.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100N中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100N according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

除第二絕緣層111B安置於第一絕緣層111A之上以外，根據另一實例的電子元件封裝100N相似於上述電子元件封裝100A至100M。舉例而言，若需要，則亦可應用金屬層135、保護層170、覆蓋層180、第二開口部161、第一開口部171及第三開口部181、第一外部連接端子175及第二外部連接端子185、外配線層162、外通孔163等。 The electronic component package 100N according to another example is similar to the electronic component packages 100A to 100M described above except that the second insulating layer 111B is disposed above the first insulating layer 111A. For example, if necessary, the metal layer 135, the protective layer 170, the cover layer 180, the second opening 161, the first opening 171 and the third opening 181, the first external connection terminal 175 and the second The external connection terminal 185, the external wiring layer 162, the external through hole 163, and the like.

由於除將第二絕緣層111B安置於第一絕緣層111A之上以外，根據另一實例的製造電子元件封裝100N的方法與製造電子元件封裝100A至100F的方法相同，因此將不再對其予以闡述。 Since the method of manufacturing the electronic component package 100N according to another example is the same as the method of manufacturing the electronic component packages 100A to 100F except that the second insulating layer 111B is disposed over the first insulating layer 111A, it will not be provided Elaborate.

圖36是示意性地說明電子元件封裝的另一實例的剖視圖。 36 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖36，根據另一實例的電子元件封裝100O可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、第三絕緣層111C、 分別安置於第一絕緣層111A與第二絕緣層111B之間及第一絕緣層111A與第三絕緣層111C之間的多個第一配線層112A及112B、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的第一通孔113A、以及穿透過第三絕緣層111C的第二通孔113B。框架110可包括安置於第三絕緣層111C的上表面110A上的第三配線層131、及安置於第二絕緣層111B的下表面110B上的第二配線層132。 36, an electronic component package 100O according to another example may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a redistribution portion disposed under the frame 110 and the electronic component 120 140 and 150, and an encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a third insulating layer 111C, A plurality of first wiring layers 112A and 112B disposed between the first insulating layer 111A and the second insulating layer 111B and between the first insulating layer 111A and the third insulating layer 111C, respectively, penetrates through the inside of the first insulating layer 111A The through hole 115, the first through hole 113A penetrating through the second insulating layer 111B, and the second through hole 113B penetrating through the third insulating layer 111C. The frame 110 may include a third wiring layer 131 disposed on the upper surface 110A of the third insulating layer 111C, and a second wiring layer 132 disposed on the lower surface 110B of the second insulating layer 111B.

貫穿孔110X可依序穿透過第三配線層131、第三絕緣層111C、第一配線層112B、第一絕緣層111A、第一配線層112A、第二絕緣層111B、及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖36中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may sequentially pass through the third wiring layer 131, the third insulating layer 111C, the first wiring layer 112B, the first insulating layer 111A, the first wiring layer 112A, the second insulating layer 111B, and the second wiring layer 132 . At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 36, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 with respect to the redistribution portions 140 and 150, or It is located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131 as long as both the third wiring layer 131 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100O中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100O according to another example will be explained in more detail, and content that is duplicated with the above content will not be described again, and content that is different from the above content will be mainly explained.

第一絕緣層111A、第二絕緣層111B、及第三絕緣層111C可以第二絕緣層111B、第一絕緣層111A及第三絕緣層111C的順序自下向上堆疊於一起。第二絕緣層111B及第三絕緣層111C可由相同的材料形成，且可具有彼此對應的厚度。第二絕緣層111B及第三絕緣層111C具有彼此對應的厚度的含義為第二絕緣層111B的厚度與第三絕緣層111C的厚度實質上彼此相同。亦即，此是一包含其中在第二絕緣層111B與第三絕緣層111C之間存在就翹曲方面而言可忽略的厚度差的情形、以及其中第二絕緣層111B的厚度與第三絕緣層111C的厚度彼此完全相同的情形的概念。 The first insulating layer 111A, the second insulating layer 111B, and the third insulating layer 111C may be stacked together in the order of the second insulating layer 111B, the first insulating layer 111A, and the third insulating layer 111C. The second insulating layer 111B and the third insulating layer 111C may be formed of the same material, and may have thicknesses corresponding to each other. The meaning that the second insulating layer 111B and the third insulating layer 111C have thicknesses corresponding to each other is that the thickness of the second insulating layer 111B and the thickness of the third insulating layer 111C are substantially the same as each other. That is, this is a case where there is a thickness difference between the second insulating layer 111B and the third insulating layer 111C that is negligible in terms of warpage, and where the thickness of the second insulating layer 111B and the third insulating The concept of the case where the thicknesses of the layers 111C are completely the same as each other.

依對應層的設計而定，第一配線層112A及112B可執行各種功能。舉例而言，第一配線層112A及112B可充當接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等而作為重新分配圖案。此外，第一配線層112A及112B可充當通孔焊墊等而作為焊墊圖案。如上所述，由於第一配線層112A及112B可執行重新分配功能，因此第一配線層112A及112B可分擔重新分配部140及150的重新分配功能。若需要，則亦可應用金屬層135、保護層170、覆蓋層180、第二開口部161、第一開口部171及第三開口部181、第一外部連接端子175及第二外部連接端子185、外配線層162、外通孔163等。 Depending on the design of the corresponding layer, the first wiring layers 112A and 112B can perform various functions. For example, the first wiring layers 112A and 112B may serve as ground (GND) patterns, power (PWR) patterns, signal (S) patterns, etc. as redistribution patterns. In addition, the first wiring layers 112A and 112B may serve as via pads or the like as pad patterns. As described above, since the first wiring layers 112A and 112B can perform the redistribution function, the first wiring layers 112A and 112B can share the redistribution function of the redistribution sections 140 and 150. If necessary, the metal layer 135, the protective layer 170, the cover layer 180, the second opening 161, the first opening 171 and the third opening 181, the first external connection terminal 175 and the second external connection terminal 185 can also be applied , Outer wiring layer 162, outer through hole 163, etc.

由於除將第三絕緣層111C形成於第一絕緣層111A之上且將第一配線層112B等形成於第一絕緣層111A與第三絕緣層 111C之間以外，根據另一實例的製造電子元件封裝100O的方法與製造電子元件封裝100A至100F的方法相同，因此將不再對其予以闡述。 Since the third insulating layer 111C is formed on the first insulating layer 111A and the first wiring layer 112B and the like are formed on the first insulating layer 111A and the third insulating layer Except between 111C, the method of manufacturing the electronic component package 100O according to another example is the same as the method of manufacturing the electronic component packages 100A to 100F, and therefore will not be described again.

圖37是示意性地說明電子元件封裝的另一實例的剖視圖。 37 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖37，根據另一實例的電子元件封裝100P可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、多個第二絕緣層111B1及111B2、分別安置於第一絕緣層111A與第二絕緣層111B2之間或所述多個第二絕緣層111B1及111B2之間的多個第一配線層112A1及112A2、穿透過第一絕緣層111A的內部通孔115、以及分別穿透過第二絕緣層111B1及111B2的多個通孔113A1及113A2。框架110可包括安置於第一絕緣層111A的上表面110A上的第三配線層131、及安置於第二絕緣層111B2的下表面110B上的第二配線層132。 37, an electronic component package 100P according to another example may include a frame 110 having a through-hole 110X, an electronic component 120 disposed in the through-hole 110X of the frame 110, a redistribution portion disposed under the frame 110 and the electronic component 120 140 and 150, and an encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a plurality of second insulating layers 111B1 and 111B2, respectively disposed between the first insulating layer 111A and the second insulating layer 111B2 or between the plurality of second insulating layers 111B1 and 111B2 A plurality of first wiring layers 112A1 and 112A2, an internal through hole 115 penetrating through the first insulating layer 111A, and a plurality of through holes 113A1 and 113A2 penetrating through the second insulating layers 111B1 and 111B2, respectively. The frame 110 may include a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer 132 disposed on the lower surface 110B of the second insulating layer 111B2.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112A1、第二絕緣層111B1、第一配線層112A2、第二絕緣層111B2及第二配線層132。所述多個第一配線層112A1及112A2以及所述多個第二絕緣層111B1及111B2中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖37中所示，電子元件120的上表面相對於重新分配部140及150位於 框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112A1, the second insulating layer 111B1, the first wiring layer 112A2, the second insulating layer 111B2, and the second wiring layer 132 in order. At least one of the plurality of first wiring layers 112A1 and 112A2 and the plurality of second insulating layers 111B1 and 111B2 may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 37, the upper surface of the electronic component 120 is located relative to the redistribution portions 140 and 150 At the level below the upper surface 110A of the frame 110; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 with respect to the redistribution portions 140 and 150, or It is located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131 as long as both the third wiring layer 131 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100P中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding elements included in the electronic component package 100P according to another example will be explained in more detail, and the contents that are duplicated with the above will not be explained, and the contents that are different from the above will be mainly explained.

在其中第二絕緣層111B1及111B2的數目為複數個的情形中，亦可在所述多個第二絕緣層111B1及111B2之間安置第一配線層112A2。如此一來，第一配線層可進一步代替重新分配部140及150的重新分配功能。第二絕緣層111B1及111B2的數目及第一配線層112A1及112A2的數目並無特別限制，且依設計特定細節而定可為複數個。若需要，則亦可應用金屬層135、保護層170、覆蓋層180、第二開口部161、第一開口部171及第三開口部181、第一外部連接端子175及第二外部連接端子185、外配線層162、外通孔163等。 In the case where the number of the second insulating layers 111B1 and 111B2 is plural, the first wiring layer 112A2 may also be disposed between the plurality of second insulating layers 111B1 and 111B2. In this way, the first wiring layer can further replace the redistribution function of the redistribution units 140 and 150. The number of the second insulating layers 111B1 and 111B2 and the number of the first wiring layers 112A1 and 112A2 are not particularly limited, and may be plural according to design specific details. If necessary, the metal layer 135, the protective layer 170, the cover layer 180, the second opening 161, the first opening 171 and the third opening 181, the first external connection terminal 175 and the second external connection terminal 185 can also be applied , Outer wiring layer 162, outer through hole 163, etc.

由於除第二絕緣層111B1及111B2的數目為複數個以外，根據另一實例的製造電子元件封裝100P的方法與製造電子元件封裝100A至100F的方法相同，因此將不再對其予以闡述。 Since the method of manufacturing the electronic component package 100P according to another example is the same as the method of manufacturing the electronic component packages 100A to 100F except that the number of the second insulating layers 111B1 and 111B2 is plural, they will not be described again.

圖38是示意性地說明電子元件封裝的另一實例的剖視圖。 38 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖38，根據另一實例的電子元件封裝100Q可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、第三絕緣層111C、分別安置於第一絕緣層111A與第二絕緣層111B之間及第一絕緣層111A與第三絕緣層111C之間的多個第一配線層112A及112B、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的第一通孔113A、以及安置於第二絕緣層111B的下表面110B上的第二配線層132。此處，囊封劑160及第三絕緣層111C可具有第四開口部165，且安置於第一絕緣層111A與第三絕緣層111C之間的第一配線層112B的部分可經由第四開口部165而暴露於外部。 38, an electronic component package 100Q according to another example may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a redistribution portion disposed under the frame 110 and the electronic component 120 140 and 150, and an encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a third insulating layer 111C, respectively disposed between the first insulating layer 111A and the second insulating layer 111B and the first insulating layer 111A and the third insulating layer 111C A plurality of first wiring layers 112A and 112B, an internal through hole 115 penetrating through the first insulating layer 111A, a first through hole 113A penetrating through the second insulating layer 111B, and disposed under the second insulating layer 111B The second wiring layer 132 on the surface 110B. Here, the encapsulant 160 and the third insulating layer 111C may have a fourth opening 165, and the portion of the first wiring layer 112B disposed between the first insulating layer 111A and the third insulating layer 111C may pass through the fourth opening The portion 165 is exposed to the outside.

貫穿孔110X可依序穿透過第三絕緣層111C、第一配線層112B、第一絕緣層111A、第一配線層112A、第二絕緣層111B、及第二配線層132。所述多個第一配線層112A及112B以及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖38中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分 配部140及150可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上，只要第三絕緣層111C及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may sequentially penetrate the third insulating layer 111C, the first wiring layer 112B, the first insulating layer 111A, the first wiring layer 112A, the second insulating layer 111B, and the second wiring layer 132. At least one of the plurality of first wiring layers 112A and 112B and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 38, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 with respect to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 is divided The matching parts 140 and 150 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 as long as the third insulating layer 111C and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述包含於根據另一實例的電子元件封裝100Q中的相應元件，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the corresponding components included in the electronic component package 100Q according to another example will be explained in more detail, and the contents that are duplicated with the above will not be explained, and the contents that are different from the above will be mainly explained.

第一配線層112B可安置於第一絕緣層111A與第三絕緣層111C之間。舉例而言，第一配線層112B可安置於第一絕緣層111A的除經由第四開口部165而暴露於外部的某些圖案以外的上表面上，且可嵌置於第三絕緣層111C中。亦即，第一配線層112B可安置於框架110中。此處，第一配線層112B安置於框架110中的含義為第一配線層112B安置於框架110的上表面110A與下表面110B之間。依對應層的設計而定，第一配線層112B可執行各種功能。舉例而言，第一配線層112B可充當接地(GND)圖案、功率(PWR)圖案、訊號(S)圖案等而作為重新分配圖案。此處，訊號(S)圖案可包括除接地(GND)圖案、功率(PWR)圖案等以外的各種訊號，例如資料訊號等。此外，第一配線層112B可充當通孔焊墊、內部通孔焊墊等而作為焊墊圖案。如上所述，由於第一配線層112B可執行重新分配功能，因此第一配線層112B可分擔重新分配部140及150的重新分配功能。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、或其合金等傳導性材料可用作第一配線層112B的材料。第一配線層 112B的厚度亦無特別限制，但可為例如約10微米至50微米左右。第一配線層112B的經由第四開口部165而暴露於外部的圖案可為用於連接至安置於電子元件封裝100Q上的另一電子元件、另一電子元件封裝等的配線結合焊墊。第二絕緣層111B與第三絕緣層111C可由相同的材料形成，且可具有彼此對應的厚度。第二絕緣層111B與第三絕緣層111C具有彼此對應的厚度的含義為第二絕緣層111B的厚度與第三絕緣層111C的厚度彼此相同。亦即，此是一包含其中在第二絕緣層111B與第三絕緣層111C之間存在就翹曲方面而言可忽略的厚度差的情形、以及其中第二絕緣層111B的厚度與第三絕緣層111C的厚度彼此完全相同的情形的概念。若需要，則亦可應用金屬層135、保護層170、第一開口部171、第一外部連接端子175等。 The first wiring layer 112B may be disposed between the first insulating layer 111A and the third insulating layer 111C. For example, the first wiring layer 112B may be disposed on the upper surface of the first insulating layer 111A except for certain patterns exposed to the outside through the fourth opening 165, and may be embedded in the third insulating layer 111C . That is, the first wiring layer 112B may be disposed in the frame 110. Here, the meaning that the first wiring layer 112B is disposed in the frame 110 means that the first wiring layer 112B is disposed between the upper surface 110A and the lower surface 110B of the frame 110. The first wiring layer 112B can perform various functions depending on the design of the corresponding layer. For example, the first wiring layer 112B may serve as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. as a redistribution pattern. Here, the signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, etc., such as a data signal. In addition, the first wiring layer 112B may serve as a via pad, an internal via pad, or the like as a pad pattern. As described above, since the first wiring layer 112B can perform the redistribution function, the first wiring layer 112B can share the redistribution function of the redistribution sections 140 and 150. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), or their alloys can be used as the first wiring layer 112B material. First wiring layer The thickness of 112B is also not particularly limited, but may be about 10 to 50 microns, for example. The pattern of the first wiring layer 112B exposed to the outside through the fourth opening 165 may be a wire bonding pad for connecting to another electronic component disposed on the electronic component package 100Q, another electronic component package, or the like. The second insulating layer 111B and the third insulating layer 111C may be formed of the same material, and may have thicknesses corresponding to each other. The meaning that the second insulating layer 111B and the third insulating layer 111C have thicknesses corresponding to each other is that the thickness of the second insulating layer 111B and the thickness of the third insulating layer 111C are the same as each other. That is, this is a case where there is a thickness difference between the second insulating layer 111B and the third insulating layer 111C that is negligible in terms of warpage, and where the thickness of the second insulating layer 111B and the third insulating The concept of the case where the thicknesses of the layers 111C are completely the same as each other. If necessary, the metal layer 135, the protective layer 170, the first opening 171, the first external connection terminal 175, etc. may also be applied.

由於除將第三絕緣層111C形成於第一絕緣層111A之上並形成第四開口部165以外，根據另一實例的製造電子元件封裝100Q的方法與製造電子元件封裝100B及100E的方法相同，因此將不再對其予以闡述。 Since the method of manufacturing the electronic component package 100Q according to another example is the same as the method of manufacturing the electronic component packages 100B and 100E, except that the third insulating layer 111C is formed on the first insulating layer 111A and the fourth opening 165 is formed Therefore, it will not be elaborated.

圖39是示意性地說明電子元件封裝的信號傳遞的實例的圖。 39 is a diagram schematically illustrating an example of signal transmission of an electronic component package.

將闡述其中使用上述電子元件封裝100B作為電子元件封裝的情形，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 The case where the above-mentioned electronic component package 100B is used as the electronic component package will be explained, and the content that is the same as the above content will not be explained again, and the content different from the above content will be mainly explained.

在實例中，第二配線層132(M1)的絕大部分可由例如 接地平面等接地(GND)圖案形成。由於可在安置電子元件120之前形成的第二配線層132(M1)的絕大部分是由接地(GND)圖案形成，因此配線層142及152(M2及M3)的接地(GND)圖案可顯著地減少。因而，可使用僅兩個配線層M2及M3而充分地設計另一所需重新分配圖案R及/或焊墊圖案P。如此一來，在安置電子元件120之後形成所述重新分配部的製程的數目可顯著地減少。此處，第二配線層的絕大部分是由接地(GND)圖案形成的含義為接地(GND)圖案的面積是所述第二配線層的平面面積的一半或更多。 In an example, most of the second wiring layer 132 (M1) can be A ground plane etc. ground (GND) pattern is formed. Since most of the second wiring layer 132 (M1) that can be formed before placing the electronic component 120 is formed by a ground (GND) pattern, the ground (GND) pattern of the wiring layers 142 and 152 (M2 and M3) can be significant To reduce. Thus, only two wiring layers M2 and M3 can be used to sufficiently design another required redistribution pattern R and/or pad pattern P. In this way, the number of processes for forming the redistribution portion after the electronic component 120 is placed can be significantly reduced. Here, the vast majority of the second wiring layer is formed of a ground (GND) pattern, meaning that the area of the ground (GND) pattern is half or more of the planar area of the second wiring layer.

用於形成第二配線層132(M1)的接地(GND)圖案可充當在第一配線層112(C2)、配線層142(M2)等中所設計的各種訊號(S)圖案等的返回路徑(RP)。由於第二配線層132(M1)的接地(GND)圖案充分地充當在上述上層及下層上形成的各種訊號(S)圖案的返回路徑RP，因此在電子元件封裝100B被電性連接於外部之後，電子元件封裝100B可平穩地運作。 The ground (GND) pattern used to form the second wiring layer 132 (M1) can serve as a return path for various signal (S) patterns etc. designed in the first wiring layer 112 (C2), the wiring layer 142 (M2), etc. (RP). Since the ground (GND) pattern of the second wiring layer 132 (M1) sufficiently serves as the return path RP of the various signal (S) patterns formed on the upper and lower layers, after the electronic component package 100B is electrically connected to the outside The electronic component package 100B can operate smoothly.

第二配線層132(M1)與第一配線層112(C2)之間的距離可小於第二配線層132(M1)與配線層142(M2)之間的距離。所述距離可根據橫截面的厚度方向來決定。如上所述，在其中第二配線層132(M1)與第一配線層112(C2)之間的距離小於第二配線層132(M1)與配線層142(M2)之間的距離的情形中，第二配線層132(M1)的重新分配圖案R中的接地(GND)圖案可更有效地充當返回路徑RP。 The distance between the second wiring layer 132 (M1) and the first wiring layer 112 (C2) may be smaller than the distance between the second wiring layer 132 (M1) and the wiring layer 142 (M2). The distance can be determined according to the thickness direction of the cross section. As described above, in the case where the distance between the second wiring layer 132 (M1) and the first wiring layer 112 (C2) is smaller than the distance between the second wiring layer 132 (M1) and the wiring layer 142 (M2) The ground (GND) pattern in the redistribution pattern R of the second wiring layer 132 (M1) can more effectively serve as the return path RP.

圖40是示意性地說明電子元件封裝的另一實例的剖視圖。 40 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖40，根據另一實例的電子元件封裝可具有其中堆疊有多個電子元件封裝的形式。根據上述各種實例的電子元件封裝100A至100Q可以各種形式應用於根據本實例的電子元件封裝。舉例而言，根據本實例的電子元件封裝可具有其中在上述電子元件封裝100B上安置有另一電子元件封裝200A的形式。 Referring to FIG. 40, an electronic component package according to another example may have a form in which a plurality of electronic component packages are stacked. The electronic component packages 100A to 100Q according to the various examples described above can be applied to the electronic component package according to the present example in various forms. For example, the electronic component package according to the present example may have a form in which another electronic component package 200A is disposed on the above electronic component package 100B.

如上所述，電子元件封裝100B可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、及安置於第二絕緣層111B的下表面110B上的第二配線層132。由於相應元件相同於上述元件，因此將不再對其予以闡述。 As described above, the electronic component package 100B may include the frame 110 having the through-hole 110X, the electronic component 120 disposed in the through-hole 110X of the frame 110, the redistribution portions 140 and 150 disposed under the frame 110 and the electronic component 120, and An encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132. Since the corresponding elements are the same as the above elements, they will not be explained again.

電子元件封裝200A可包括配線基板210、以覆晶形式安裝於配線基板210上的第一電子元件222、以及堆疊於第一電子元件222上的第二電子元件224。此外，電子元件封裝200A可包括設置於第一電子元件222與配線基板210之間的間隙中的底部填充樹脂240、以及用於囊封第一電子元件222及第二電子元件224 等的囊封樹脂230。 The electronic component package 200A may include a wiring substrate 210, a first electronic component 222 mounted on the wiring substrate 210 in a flip-chip form, and a second electronic component 224 stacked on the first electronic component 222. In addition, the electronic component package 200A may include an underfill resin 240 disposed in the gap between the first electronic component 222 and the wiring substrate 210, and for encapsulating the first electronic component 222 and the second electronic component 224 Wait for the encapsulating resin 230.

第一電子元件222及第二電子元件224可為積體電路晶片，例如為揮發性記憶體(例如，動態隨機存取記憶體)、非揮發性記憶體(例如，唯讀記憶體)、快閃記憶體等記憶體晶片。第一電子元件222的平面形狀可較第二電子元件224的平面形狀大。 The first electronic component 222 and the second electronic component 224 may be integrated circuit chips, such as volatile memory (eg, dynamic random access memory), non-volatile memory (eg, read-only memory), fast Memory chips such as flash memory. The planar shape of the first electronic component 222 may be larger than the planar shape of the second electronic component 224.

結合焊墊212A及覆晶焊墊212B可安置於配線基板210的上表面上。配線基板210可包括多個絕緣層(圖中未示出)、通孔圖案(圖中未示出)、及形成於所述多個絕緣層上的配線圖案(圖中未示出)等。配線基板210的通孔圖案(圖中未示出)及配線圖案(圖中未示出)可電性連接至結合焊墊212A、覆晶焊墊212B等。 The bonding pad 212A and the flip chip pad 212B may be placed on the upper surface of the wiring substrate 210. The wiring substrate 210 may include a plurality of insulating layers (not shown in the figure), via patterns (not shown in the figure), wiring patterns (not shown in the figure) formed on the plurality of insulating layers, and the like. The through hole pattern (not shown in the figure) and the wiring pattern (not shown in the figure) of the wiring substrate 210 can be electrically connected to the bonding pad 212A, the flip chip pad 212B, and the like.

結合焊墊212A可經由結合配線252而電性連接至形成於第二電子元件224的上表面上的電極焊墊(圖中未示出)。第一電子元件222的凸塊251可以覆晶形式結合至覆晶焊墊212B。可使用以上所述的傳導性材料作為結合焊墊212A及覆晶焊墊212B的材料。可使用Au、Ni/Au、Ni/Pb/Au等對結合焊墊212A的及覆晶焊墊212B的表面執行金屬層處理。 The bonding pad 212A may be electrically connected to the electrode pad (not shown in the figure) formed on the upper surface of the second electronic element 224 via the bonding wire 252. The bump 251 of the first electronic element 222 may be bonded to the flip-chip bonding pad 212B in a flip-chip form. The conductive material described above can be used as the material of the bonding pad 212A and the flip-chip pad 212B. The metal layer treatment may be performed on the surfaces of the bonding pad 212A and the flip-chip pad 212B using Au, Ni/Au, Ni/Pb/Au, and the like.

使用囊封樹脂230的目的為保護第一電子元件222及第二電子元件224、可囊封第一電子元件222及第二電子元件224。可使用例如環氧系絕緣樹脂等習知的絕緣材料作為囊封樹脂230的材料。 The purpose of using the encapsulating resin 230 is to protect the first electronic component 222 and the second electronic component 224 and to encapsulate the first electronic component 222 and the second electronic component 224. As a material of the encapsulating resin 230, a conventional insulating material such as epoxy-based insulating resin can be used.

使用底部填充樹脂240的目的可為提高第一電子元件 222的凸塊251與覆晶焊墊212B之間的連接部分的連接強度。底部填充樹脂240可設置於配線基板210與第一電子元件222之間的間隙中。亦可使用例如環氧系絕緣樹脂等習知的絕緣材料作為底部填充樹脂240的材料。 The purpose of using the underfill resin 240 can be to improve the first electronic component The connection strength of the connection portion between the bump 251 of 222 and the flip chip pad 212B. The underfill resin 240 may be provided in the gap between the wiring substrate 210 and the first electronic component 222. A conventional insulating material such as epoxy-based insulating resin may also be used as the material of the underfill resin 240.

連接端子191可用於將電子元件封裝200A連接至電子元件封裝100B。電子元件封裝200A及電子元件封裝100B可堆疊於一起並經由連接端子191而結合至彼此。連接端子191可為形成於電子元件封裝100B上的第二外部連接端子185。作為另一選擇，連接端子191可為形成於電子元件封裝200A之下的外部連接端子(圖中未示出)。作為另一選擇，連接端子191可為藉由將形成於電子元件封裝100B上的第二外部連接端子185與形成於電子元件封裝200A之下的外部連接端子(圖中未示出)彼此整合於一起而形成的端子。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、焊料等傳導性材料可用作連接端子191的材料。連接端子191可為焊盤、球、引腳等。連接端子191可由多個層或單個層形成。在其中連接端子191由多個層形成的情形中，連接端子191可含有銅柱及焊料，且在其中連接端子191由單個層形成的情形中，連接端子191可含有錫銀焊料或銅。然而，此僅為實例，且連接端子191並非僅限於此。 The connection terminal 191 may be used to connect the electronic component package 200A to the electronic component package 100B. The electronic component package 200A and the electronic component package 100B may be stacked together and coupled to each other via the connection terminal 191. The connection terminal 191 may be the second external connection terminal 185 formed on the electronic component package 100B. Alternatively, the connection terminal 191 may be an external connection terminal (not shown in the figure) formed under the electronic component package 200A. Alternatively, the connection terminal 191 may be formed by integrating the second external connection terminal 185 formed on the electronic component package 100B and the external connection terminal (not shown) formed under the electronic component package 200A Together to form the terminal. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, etc. can be used as the material of the connection terminal 191. The connection terminal 191 may be a pad, a ball, a pin, or the like. The connection terminal 191 may be formed of multiple layers or a single layer. In the case where the connection terminal 191 is formed of multiple layers, the connection terminal 191 may contain copper pillars and solder, and in the case where the connection terminal 191 is formed of a single layer, the connection terminal 191 may contain tin-silver solder or copper. However, this is only an example, and the connection terminal 191 is not limited to this.

圖41是示意性地說明電子元件封裝的另一實例的剖視圖。 41 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖41，根據另一實例的電子元件封裝可具有其中上 述電子元件封裝100A堆疊於上述電子元件封裝100C上的形式。 Referring to FIG. 41, an electronic component package according to another example may have The electronic component package 100A is stacked on the electronic component package 100C.

如上所述，電子元件封裝100C可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、用於囊封電子元件120的囊封劑160、安置於囊封劑160上的外配線層162、以及穿透過囊封劑160的外通孔163。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、以及安置於第二絕緣層111B的下表面110B上的第二配線層132。由於相應元件相同於上述元件，因此將不再對其予以闡述。 As described above, the electronic component package 100C may include the frame 110 having the through hole 110X, the electronic component 120 disposed in the through hole 110X of the frame 110, the redistribution portions 140 and 150 disposed under the frame 110 and the electronic component 120, and The encapsulant 160 for encapsulating the electronic component 120, the outer wiring layer 162 disposed on the encapsulant 160, and the outer through hole 163 penetrating through the encapsulant 160. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132. Since the corresponding elements are the same as the above elements, they will not be explained again.

如上所述，電子元件封裝100A可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140及150、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、安置於第一絕緣層111A的上表面上的金屬層135、安置於第二絕緣層111B的下表面上的第二配線層132、以及穿透過第二絕緣層111B的通孔113。由於相應元件相同於上述元件，因此將不再對其予以闡述。 As described above, the electronic component package 100A may include the frame 110 having the through-hole 110X, the electronic component 120 disposed in the through-hole 110X of the frame 110, the redistribution portions 140 and 150 disposed under the frame 110 and the electronic component 120, and An encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and a first insulating layer 111A disposed on the upper surface of the first insulating layer 111A The metal layer 135, the second wiring layer 132 disposed on the lower surface of the second insulating layer 111B, and the through hole 113 penetrating through the second insulating layer 111B. Since the corresponding elements are the same as the above elements, they will not be explained again.

電子元件封裝100C與電子元件封裝100A可堆疊於一起 並經由連接端子191而結合至彼此。連接端子191可為形成於電子元件封裝100C上的第二外部連接端子185。作為另一選擇，連接端子191可為形成於電子元件封裝100A之下的第一外部連接端子175。作為另一選擇，連接端子191可為藉由將形成於電子元件封裝100C上的第二外部連接端子185與形成於電子元件封裝100A之下的第一外部連接端子175彼此整合於一起而形成的端子。例如銅(Cu)、鋁(Al)、銀(Ag)、錫(Sn)、金(Au)、鎳(Ni)、鉛(Pb)、焊料等傳導性材料可用作連接端子191的材料。連接端子191可為焊盤、球、引腳等。連接端子191可由多個層或單個層形成。在其中連接端子191由多個層形成的情形中，連接端子191可含有銅柱及焊料，且在其中連接端子191由單個層形成的情形中，連接端子191可含有錫銀焊料或銅。然而，此僅為實例，且連接端子191並非僅限於此。 The electronic component package 100C and the electronic component package 100A can be stacked together And are coupled to each other via the connection terminal 191. The connection terminal 191 may be the second external connection terminal 185 formed on the electronic component package 100C. As another option, the connection terminal 191 may be the first external connection terminal 175 formed under the electronic component package 100A. Alternatively, the connection terminal 191 may be formed by integrating the second external connection terminal 185 formed on the electronic component package 100C and the first external connection terminal 175 formed under the electronic component package 100A Terminal. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, etc. can be used as the material of the connection terminal 191. The connection terminal 191 may be a pad, a ball, a pin, or the like. The connection terminal 191 may be formed of multiple layers or a single layer. In the case where the connection terminal 191 is formed of multiple layers, the connection terminal 191 may contain copper pillars and solder, and in the case where the connection terminal 191 is formed of a single layer, the connection terminal 191 may contain tin-silver solder or copper. However, this is only an example, and the connection terminal 191 is not limited to this.

圖42是示意性地說明電子元件封裝的另一實例的剖視圖。 42 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖42，根據另一實例的電子元件封裝100R可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140、150及155、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔 113、安置於第一絕緣層111A的上表面110A上的第三配線層131、以及安置於第二絕緣層111B的下表面上的第二配線層132。 Referring to FIG. 42, an electronic component package 100R according to another example may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a redistribution portion disposed under the frame 110 and the electronic component 120 140, 150, and 155, and an encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , Through holes through the second insulating layer 111B 113. A third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer 132 disposed on the lower surface of the second insulating layer 111B.

重新分配部155可包括重新分配部絕緣層156、安置於重新分配部絕緣層156上的重新分配部配線層157、以及穿透過重新分配部絕緣層156以藉此電性連接至重新分配部配線層157的重新分配部通孔158。囊封劑160可具有第二開口部161，第二開口部161暴露出安置於框架110的上表面110A上的第三配線層131的至少部分。此外，暴露於外部的第二外部連接端子185可安置於囊封劑160的第二開口部161中。第二外部連接端子185可連接至經由第二開口部161而暴露出的第三配線層131。具有第一開口部171的保護層170可安置於重新分配部155下、凸塊下金屬層(under-bump metal layer)172可安置於第一開口部171中、且第一外部連接端子175可安置於凸塊下金屬層172上。 The redistribution portion 155 may include a redistribution portion insulation layer 156, a redistribution portion wiring layer 157 disposed on the redistribution portion insulation layer 156, and a through redistribution portion insulation layer 156 to thereby be electrically connected to the redistribution portion wiring The redistribution portion of the layer 157 is through hole 158. The encapsulant 160 may have a second opening portion 161 that exposes at least a portion of the third wiring layer 131 disposed on the upper surface 110A of the frame 110. In addition, the second external connection terminal 185 exposed to the outside may be disposed in the second opening portion 161 of the encapsulant 160. The second external connection terminal 185 may be connected to the third wiring layer 131 exposed through the second opening portion 161. The protective layer 170 having the first opening portion 171 may be disposed under the redistribution portion 155, the under-bump metal layer 172 may be disposed in the first opening portion 171, and the first external connection terminal 175 may be Placed on the under bump metal layer 172.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖42中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140、150及155可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上 表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 42, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 relative to the redistribution portions 140, 150 and 155. Or on the third wiring layer 131 At the same level of the surface or on the upper surface of the third wiring layer 131, as long as the third wiring layer 131 and the electronic component 120 are covered by the encapsulant 160.

在下文中，將更詳細地闡述根據另一實例的電子元件封裝100R中的訊號移動路徑及依所述訊號移動路徑而定的接地的佈局，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the layout of the signal movement path and the grounding according to the signal movement path in the electronic component package 100R according to another example will be explained in more detail, and the contents overlapping with the above will not be explained again, and The content different from the above will be mainly explained.

電子元件120可具有用於訊號的電極焊墊(電極焊墊120P中沿路徑S’的至少一者)，所述用於訊號的電極焊墊(電極焊墊120P中沿路徑S’的至少一者)可經由重新分配部140的用於訊號的第一通孔(通孔143中沿路徑S’的至少一者)而電性連接至重新分配部140的配線層142的訊號圖案(配線層142中沿路徑S’的至少一個訊號圖案)，重新分配部140的配線層142的訊號圖案(配線層142中沿路徑S’的至少一個訊號圖案)可經由重新分配部140的用於訊號的第二通孔(通孔143中沿路徑S’的至少另一者)而電性連接至框架110的第二配線層132的訊號圖案(第二配線層132中沿路徑S’的至少一個訊號圖案)，框架110的第二配線層132的訊號圖案(第二配線層132中沿路徑S’的至少一個訊號圖案)可經由框架110的用於訊號的通孔(通孔113中沿路徑S’的至少一者)而電性連接至框架110的第一配線層112的訊號圖案(第一配線層112中沿路徑S’的至少一個訊號圖案)，框架110的第一配線層112的訊號圖案(第一配線層112中沿路徑S’的至少一個訊號圖案)可經由框架110的用於訊號的內部通孔(內 部通孔115中沿路徑S’的至少一者)而電性連接至框架110的第三配線層131的訊號圖案(第三配線層131中沿路徑S’的至少一個訊號圖案)，框架110的第三配線層131的訊號圖案(第三配線層131中沿路徑S’的至少一個訊號圖案)可電性連接至安置於框架110之上的扇出區中的用於訊號的外部連接端子(外部連接端子185中沿路徑S’的至少一者)，且框架110的第二配線層132及第三配線層131可具有用於提供訊號的返回路徑的接地圖案(第三配線層131中沿路徑G’的至少一個接地圖案及第二配線層132中沿路徑G’的至少一個接地圖案)。 The electronic component 120 may have an electrode pad for signals (at least one of the electrode pads 120P along the path S′), and the electrode pad for signals (at least one of the electrode pads 120P along the path S′) The signal pattern of the wiring layer 142 of the redistribution unit 140 (wiring layer) can be electrically connected to the first through hole of the redistribution unit 140 for signals (at least one of the through holes 143 along the path S′). At least one signal pattern along the path S'in 142), the signal pattern of the wiring layer 142 of the redistribution section 140 (at least one signal pattern along the path S'in the wiring layer 142) can be used by the redistribution section 140 for the signal The second through hole (at least another one of the through holes 143 along the path S′) is electrically connected to the signal pattern of the second wiring layer 132 of the frame 110 (at least one signal along the path S′ in the second wiring layer 132 Pattern), the signal pattern of the second wiring layer 132 of the frame 110 (at least one signal pattern along the path S′ in the second wiring layer 132) can pass through the through hole of the frame 110 for signal (via the path S in the through hole 113 At least one) and the signal pattern of the first wiring layer 112 of the frame 110 (at least one signal pattern along the path S′ in the first wiring layer 112), the signal of the first wiring layer 112 of the frame 110 The pattern (at least one signal pattern along the path S′ in the first wiring layer 112) may pass through the internal via hole (internal At least one of the through holes 115 along the path S′) and electrically connected to the signal pattern of the third wiring layer 131 of the frame 110 (at least one signal pattern along the path S′ of the third wiring layer 131), the frame 110 The signal pattern of the third wiring layer 131 (at least one signal pattern along the path S′ in the third wiring layer 131) can be electrically connected to the external connection terminal for signal in the fan-out area disposed above the frame 110 (At least one of the external connection terminals 185 along the path S′), and the second wiring layer 132 and the third wiring layer 131 of the frame 110 may have a ground pattern for providing a return path of the signal (in the third wiring layer 131 At least one ground pattern along the path G'and at least one ground pattern along the path G'in the second wiring layer 132).

舉例而言，使用電子元件120的電極焊墊120P中的某些電極焊墊120P的目的可為用於訊號連接，且使用電極焊墊120P中的其他電極焊墊120P的目的可為用於接地連接。所述訊號中的某些訊號可自用於訊號連接的電極焊墊(電極焊墊120P中沿路徑S’的至少一者)開始經由重新分配部的用於訊號的通孔(通孔143中沿路徑S’的至少一者)而移動至重新分配部的配線層142的訊號圖案(配線層142中沿路徑S’的至少一個訊號圖案)、經由重新分配部的用於訊號的通孔143而移動至框架110的第二配線層132的訊號圖案(第二配線層132中沿路徑S’的至少一個訊號圖案)、經由框架110的用於訊號的通孔(通孔113中沿路徑S’的至少一者)而移動至框架110的第一配線層112的訊號圖案(第一配線層112中沿路徑S’的至少一個訊號圖案)、經由框架110的用於訊號的內部通孔(內部通孔115中沿路徑S’的至少一者)而移動至 框架110的第三配線層131的訊號圖案(第三配線層131中沿路徑S’的至少一個訊號圖案)、並接著經由用於訊號的第二外部連接端子(第二外部連接端子185中沿路徑S’的至少一者)而移動至外部。 For example, some of the electrode pads 120P of the electronic device 120 may be used for signal connection, and other electrode pads 120P of the electrode pad 120P may be used for grounding. connection. Some of the signals may start from the electrode pad for signal connection (at least one of the electrode pads 120P along the path S′) through the through hole for the signal of the redistribution section (the middle edge of the through hole 143 At least one of the paths S′) and the signal pattern of the wiring layer 142 of the redistribution section (at least one signal pattern along the path S′ in the wiring layer 142), and through the through-hole 143 for signals of the redistribution section The signal pattern moving to the second wiring layer 132 of the frame 110 (at least one signal pattern along the path S'in the second wiring layer 132), the through hole for signal passing through the frame 110 (along the path S'in the through hole 113) At least one) and the signal pattern moving to the first wiring layer 112 of the frame 110 (at least one signal pattern along the path S′ in the first wiring layer 112), the internal via hole for the signal (internal At least one of the through holes 115 along the path S') to The signal pattern of the third wiring layer 131 of the frame 110 (at least one signal pattern along the path S′ in the third wiring layer 131), and then via the second external connection terminal for the signal (the second external connection terminal 185 At least one of the paths S') to the outside.

為提供沿上述移動路徑的訊號的返回路徑，可在上述移動路徑之上或之下形成接地圖案。所述接地圖案可形成於框架110的第二配線層132及第三配線層131上以及重新分配部配線層142及152上。在其中框架110的第一配線層112的絕大部分上形成有訊號圖案的情形中，與第一配線層112的下部部分及/或上部部分對應的第二配線層132的及第三配線層131的絕大部分上可形成有接地圖案。此外，重新分配部配線層142的絕大部分上可形成有訊號圖案，且重新分配部配線層152的絕大部分上可形成有接地圖案。如上所述，框架110可用作訊號圖案、接地圖案等的重新分配區，且由於框架110可在安置電子元件120之前形成，因此可提高製程良率等。接地圖案可具有板形形狀等，但並非僅限於此。 In order to provide a signal return path along the moving path, a ground pattern may be formed above or below the moving path. The ground pattern may be formed on the second wiring layer 132 and the third wiring layer 131 of the frame 110 and on the redistribution portion wiring layers 142 and 152. In the case where a signal pattern is formed on most of the first wiring layer 112 of the frame 110, the second wiring layer 132 and the third wiring layer corresponding to the lower portion and/or the upper portion of the first wiring layer 112 The ground pattern may be formed on most of the 131. In addition, a signal pattern may be formed on most of the redistribution portion wiring layer 142, and a ground pattern may be formed on most of the redistribution portion wiring layer 152. As described above, the frame 110 can be used as a redistribution area of signal patterns, ground patterns, and the like, and since the frame 110 can be formed before the electronic device 120 is placed, the process yield and the like can be improved. The ground pattern may have a plate shape or the like, but it is not limited to this.

圖43是示意性地說明電子元件封裝的另一實例的剖視圖。 43 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖43，根據另一實例的電子元件封裝100S可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140、150及155、以及用於囊封電子元件120的囊封劑160。框架 110可包括第一絕緣層111A、第二絕緣層111B、第三絕緣層111C、分別安置於第一絕緣層111A與第二絕緣層111B之間及第一絕緣層111A與第三絕緣層111C之間的多個第一配線層112A及112B、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的第一通孔113A、以及穿透過第三絕緣層111C的第二通孔113B。框架110可更包括安置於第三絕緣層111C的上表面110A上的第三配線層131及安置於第二絕緣層111B的下表面上的第二配線層132。 Referring to FIG. 43, an electronic component package 100S according to another example may include a frame 110 having a through hole 110X, an electronic component 120 disposed in the through hole 110X of the frame 110, a redistribution portion disposed under the frame 110 and the electronic component 120 140, 150, and 155, and an encapsulant 160 for encapsulating the electronic component 120. frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a third insulating layer 111C, respectively disposed between the first insulating layer 111A and the second insulating layer 111B and between the first insulating layer 111A and the third insulating layer 111C A plurality of first wiring layers 112A and 112B, an internal via 115 passing through the first insulating layer 111A, a first via 113A passing through the second insulating layer 111B, and a second through the third insulating layer 111C Through hole 113B. The frame 110 may further include a third wiring layer 131 disposed on the upper surface 110A of the third insulating layer 111C and a second wiring layer 132 disposed on the lower surface of the second insulating layer 111B.

重新分配部155可包括重新分配部絕緣層156、安置於重新分配部絕緣層156上的重新分配部配線層157、及穿透過重新分配部絕緣層156以藉此電性連接至重新分配部配線層157的重新分配部通孔158。囊封劑160可具有第二開口部161，第二開口部161暴露出安置於框架110的上表面110A上的第三配線層131的至少部分。此外，暴露於外部的第二外部連接端子185可安置於囊封劑160的第二開口部161中。第二外部連接端子185可連接至經由第二開口部161而暴露出的第三配線層131。具有第一開口部171的保護層170可安置於重新分配部155下，凸塊下金屬層172可安置於第一開口部171中，且第一外部連接端子175可安置於凸塊下金屬層172上。 The redistribution portion 155 may include a redistribution portion insulation layer 156, a redistribution portion wiring layer 157 disposed on the redistribution portion insulation layer 156, and a through redistribution portion insulation layer 156 to thereby be electrically connected to the redistribution portion wiring The redistribution portion of the layer 157 is through hole 158. The encapsulant 160 may have a second opening portion 161 that exposes at least a portion of the third wiring layer 131 disposed on the upper surface 110A of the frame 110. In addition, the second external connection terminal 185 exposed to the outside may be disposed in the second opening portion 161 of the encapsulant 160. The second external connection terminal 185 may be connected to the third wiring layer 131 exposed through the second opening portion 161. The protective layer 170 having the first opening portion 171 may be disposed under the redistribution portion 155, the under-bump metal layer 172 may be disposed in the first opening portion 171, and the first external connection terminal 175 may be placed in the under-bump metal layer 172.

貫穿孔110X可依序穿透過第三配線層131、第三絕緣層111C、第一配線層112B、第一絕緣層111A、第一配線層112A、第二絕緣層111B及第二配線層132。第一配線層112及第二絕緣 層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖43中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140、150及155可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the third insulating layer 111C, the first wiring layer 112B, the first insulating layer 111A, the first wiring layer 112A, the second insulating layer 111B, and the second wiring layer 132 in order. The first wiring layer 112 and the second insulation At least one of the layers 111B may be located at the level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 43, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 relative to the redistribution portions 140, 150 and 155. Or, it may be located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131, as long as both the third wiring layer 131 and the electronic component 120 are covered with the encapsulant 160.

在下文中，將更詳細地闡述根據另一實例的電子元件封裝100S的訊號移動路徑及依所述訊號移動路徑而定的接地的佈局，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the layout of the signal movement path of the electronic component package 100S according to another example and the grounding according to the signal movement path will be explained in more detail. Mainly elaborate the content different from the above.

電子元件120可具有用於訊號的電極焊墊(電極焊墊120P中沿路徑S”的至少一者)，所述用於訊號的電極焊墊(電極焊墊120P中沿路徑S”的至少一者)可經由重新分配部140的用於訊號的第一通孔(通孔143中沿路徑S”的至少一者)而電性連接至重新分配部140的配線層142的訊號圖案(配線層142中沿路徑S”的至少一個訊號圖案)，重新分配部140的配線層142的訊號圖案(配線層142中沿路徑S”的至少一個訊號圖案)可經由重新分配部140的用於訊號的第二通孔(通孔143中沿路徑S”的至少另一者)而電性連接至框架110的第二配線層132的訊號圖 案(第二配線層132中沿路徑S”的至少一個訊號圖案)，框架110的第二配線層132的訊號圖案(第二配線層132中沿路徑S”的至少一個訊號圖案)可經由框架110的用於下級訊號的通孔(通孔113A中沿路徑S”的至少一者)而電性連接至框架110的第一配線層112A的訊號圖案(第一配線層112A中沿路徑S”的至少一個訊號圖案)，框架110的第一配線層112A的訊號圖案(第一配線層112A中沿路徑S”的至少一個訊號圖案)可經由框架110的用於訊號的內部通孔(內部通孔115中沿路徑S”的至少一者)而電性連接至框架110的第一配線層112B的訊號圖案(第一配線層112B中沿路徑S”的至少一個訊號圖案)，框架110的第一配線層112B的訊號圖案(第一配線層112B中沿路徑S”的至少一個訊號圖案)可經由框架110的用於上級訊號的通孔而電性連接至框架110的第三配線層131的訊號圖案(第三配線層131中沿路徑S”的至少一個訊號圖案)，框架110的第三配線層131的訊號圖案(第三配線層131中沿路徑S”的至少一個訊號圖案)可電性連接至安置於框架110之上的扇出區中的用於訊號的外部連接端子(外部連接端子185中沿路徑S”的至少一者)，且框架110的第二配線層132及第一配線層112B可具有用於提供訊號的返回路徑的接地圖案(第二配線層132中沿路徑G”的至少一個接地圖案及第一配線層112B中沿路徑G”的至少一個接地圖案)。 The electronic component 120 may have an electrode pad for signals (at least one of the electrode pads 120P along the path S"), and the electrode pad for signals (at least one of the electrode pads 120P along the path S" The signal pattern of the wiring layer 142 of the redistribution section 140 (wiring layer) can be electrically connected to the first through hole of the redistribution section 140 for signals (at least one of the through holes 143 along the path S"). At least one signal pattern along the path S" in 142), the signal pattern of the wiring layer 142 of the redistribution section 140 (at least one signal pattern along the path S" in the wiring layer 142) can be used by the redistribution section 140 for the signal Signal diagram of the second through hole (at least another one of the through holes 143 along the path S") electrically connected to the second wiring layer 132 of the frame 110 (At least one signal pattern along the path S" in the second wiring layer 132), the signal pattern of the second wiring layer 132 in the frame 110 (at least one signal pattern along the path S" in the second wiring layer 132) can pass through the frame The through holes for the lower-level signals of 110 (at least one along the path S" in the through hole 113A) are electrically connected to the signal pattern of the first wiring layer 112A of the frame 110 (along the path S" in the first wiring layer 112A At least one signal pattern), the signal pattern of the first wiring layer 112A of the frame 110 (at least one signal pattern along the path S" in the first wiring layer 112A) can pass through the internal via hole of the frame 110 for signals (internal communication At least one of the holes 115 along the path S") and the signal pattern electrically connected to the first wiring layer 112B of the frame 110 (at least one signal pattern along the path S" in the first wiring layer 112B), the first The signal pattern of a wiring layer 112B (at least one signal pattern along the path S" in the first wiring layer 112B) can be electrically connected to the third wiring layer 131 of the frame 110 through the through hole of the frame 110 for the superior signal The signal pattern (at least one signal pattern along the path S" in the third wiring layer 131), the signal pattern of the third wiring layer 131 in the frame 110 (at least one signal pattern along the path S" in the third wiring layer 131) can be electrically Is connected to an external connection terminal for signals (at least one of the external connection terminals 185 along the path S″) disposed in the fan-out area above the frame 110, and the second wiring layer 132 and the first of the frame 110 The wiring layer 112B may have a ground pattern for providing a return path of the signal (at least one ground pattern along the path G" in the second wiring layer 132 and at least one ground pattern along the path G" in the first wiring layer 112B).

舉例而言，使用電子元件120的電極焊墊120P中的某些電極焊墊120P的目的可為用於訊號連接，且使用電極焊墊120P 中的其他電極焊墊120P的目的可為用於接地連接。所述訊號中的某些訊號可自用於訊號連接的電極焊墊(電極焊墊120P中沿路徑S”的至少一者)開始經由重新分配部的用於訊號的第一通孔(通孔143中沿路徑S”的至少一者)而移動至重新分配部配線層142的訊號圖案(重新分配部配線層142中沿路徑S”的至少一個訊號圖案)、經由重新分配部的用於訊號的第二通孔(通孔143中沿路徑S”的至少一者)而移動至框架110的第二配線層132的訊號圖案(第二配線層132中沿路徑S”的至少一個訊號圖案)、經由框架110的用於下級訊號的通孔(通孔113A中沿路徑S”的至少一者)而移動至框架110的第一配線層112A的訊號圖案(第一配線層112A中沿路徑S”的至少一個訊號圖案)、經由框架110的用於訊號的內部通孔(內部通孔115中沿路徑S”的至少一者)而移動至框架110的第一配線層112B的訊號圖案(第一配線層112B中沿路徑S”的至少一個訊號圖案)、經由框架110的用於上級訊號的通孔(通孔113B中沿路徑S”的至少一者)而移動至框架110的第三配線層131的訊號圖案(第三配線層131中沿路徑S”的至少一個訊號圖案)、並接著經由用於訊號的第二外部連接端子(第二外部連接端子185中沿路徑S”的至少一者)而移動至外部。 For example, some electrode pads 120P of the electrode pads 120P of the electronic device 120 may be used for signal connection, and use the electrode pads 120P The purpose of the other electrode pads 120P may be for ground connection. Some of the signals may start from the electrode pad for signal connection (at least one of the electrode pads 120P along the path S") through the first through hole (through hole 143) for the signal of the redistribution section At least one of the middle along the path S") and the signal pattern moved to the redistribution section wiring layer 142 (at least one signal pattern along the path S" in the redistribution section wiring layer 142), A second through hole (at least one of the through holes 143 along the path S") and a signal pattern moving to the second wiring layer 132 of the frame 110 (at least one signal pattern along the path S" in the second wiring layer 132), The signal pattern that moves to the first wiring layer 112A of the frame 110 (via the path S" in the first wiring layer 112A) through the through-hole for the lower-level signal of the frame 110 (at least one along the path S" in the through hole 113A) At least one signal pattern), the signal pattern that moves to the first wiring layer 112B of the frame 110 (the first through the internal via hole of the frame 110 for the signal (at least one of the internal through holes 115 along the path S")) At least one signal pattern along the path S" in the wiring layer 112B), and moves to the third wiring layer of the frame 110 through the through hole of the frame 110 for the superior signal (at least one of the through holes 113B along the path S") The signal pattern of 131 (at least one signal pattern along the path S" in the third wiring layer 131), and then via the second external connection terminal for the signal (at least one of the second external connection terminals 185 along the path S" ) While moving outside.

為提供沿上述移動路徑的訊號的返回路徑，可在上述移動路徑之上或之下形成接地圖案。所述接地圖案可形成於框架110的第二配線層132及第一配線層112B上以及重新分配部配線層142及152上。在其中框架110的第一配線層112A的絕大部分上 形成有訊號圖案的情形中，與第一配線層112A的下部部分及/或上部部分對應的第二配線層132的及第一配線層112B的絕大部分上可形成有接地圖案。此外，重新分配部配線層142的絕大部分上可形成有訊號圖案，且重新分配部配線層152的絕大部分上可形成有接地圖案。如上所述，框架110可用作訊號圖案、接地圖案等的重新分配區，且由於框架110可如上所述在安置電子元件120之前形成，因此可提高製程良率等。接地圖案可具有板形形狀等，但並非僅限於此。 In order to provide a signal return path along the moving path, a ground pattern may be formed above or below the moving path. The ground pattern may be formed on the second wiring layer 132 and the first wiring layer 112B of the frame 110 and on the redistribution portion wiring layers 142 and 152. On most of the first wiring layer 112A of the frame 110 In the case where the signal pattern is formed, a ground pattern may be formed on most of the second wiring layer 132 and the first wiring layer 112B corresponding to the lower portion and/or the upper portion of the first wiring layer 112A. In addition, a signal pattern may be formed on most of the redistribution portion wiring layer 142, and a ground pattern may be formed on most of the redistribution portion wiring layer 152. As described above, the frame 110 can be used as a redistribution area of signal patterns, ground patterns, and the like, and since the frame 110 can be formed before the electronic device 120 is placed as described above, the process yield and the like can be improved. The ground pattern may have a plate shape or the like, but it is not limited to this.

圖44是示意性地說明電子元件封裝的另一實例的剖視圖。 44 is a cross-sectional view schematically illustrating another example of electronic component packaging.

參照圖44，根據另一實例的電子元件封裝100T可包括具有貫穿孔110X的框架110、安置於框架110的貫穿孔110X中的電子元件120、安置於框架110及電子元件120下的重新分配部140、150及155、以及用於囊封電子元件120的囊封劑160。框架110可包括第一絕緣層111A、第二絕緣層111B、安置於第一絕緣層111A與第二絕緣層111B之間的第一配線層112、穿透過第一絕緣層111A的內部通孔115、穿透過第二絕緣層111B的通孔113、安置於第一絕緣層111A的上表面110A上的第三配線層131、及安置於第二絕緣層111B的下表面110B上的第二配線層132。 Referring to FIG. 44, an electronic component package 100T according to another example may include a frame 110 having a through-hole 110X, an electronic component 120 disposed in the through-hole 110X of the frame 110, a redistribution portion disposed under the frame 110 and the electronic component 120 140, 150, and 155, and an encapsulant 160 for encapsulating the electronic component 120. The frame 110 may include a first insulating layer 111A, a second insulating layer 111B, a first wiring layer 112 disposed between the first insulating layer 111A and the second insulating layer 111B, and an internal through hole 115 penetrating through the first insulating layer 111A , A through hole 113 penetrating through the second insulating layer 111B, a third wiring layer 131 disposed on the upper surface 110A of the first insulating layer 111A, and a second wiring layer disposed on the lower surface 110B of the second insulating layer 111B 132.

重新分配部155可包括重新分配部絕緣層156、安置於重新分配部絕緣層156上的重新分配部配線層157、以及穿透過重新 分配部絕緣層156以藉此電性連接至重新分配部配線層157的重新分配部通孔158。囊封劑160可具有第二開口部161，第二開口部161暴露出安置於框架110的上表面110A上的第三配線層131的至少部分。此外，暴露於外部的第二外部連接端子185可安置於囊封劑160的第二開口部161中。第二外部連接端子185可連接至經由第二開口部161而暴露出的第三配線層131。具有第一開口部171的保護層170可安置於重新分配部155下，凸塊下金屬層172可安置於第一開口部171中，且第一外部連接端子175可安置於凸塊下金屬層172上。 The redistribution portion 155 may include a redistribution portion insulation layer 156, a redistribution portion wiring layer 157 disposed on the redistribution portion insulation layer 156, and a through redistribution The distribution portion insulating layer 156 is thereby electrically connected to the redistribution portion through hole 158 of the redistribution portion wiring layer 157. The encapsulant 160 may have a second opening portion 161 that exposes at least a portion of the third wiring layer 131 disposed on the upper surface 110A of the frame 110. In addition, the second external connection terminal 185 exposed to the outside may be disposed in the second opening portion 161 of the encapsulant 160. The second external connection terminal 185 may be connected to the third wiring layer 131 exposed through the second opening portion 161. The protective layer 170 having the first opening portion 171 may be disposed under the redistribution portion 155, the under-bump metal layer 172 may be disposed in the first opening portion 171, and the first external connection terminal 175 may be placed in the under-bump metal layer 172.

貫穿孔110X可依序穿透過第三配線層131、第一絕緣層111A、第一配線層112、第二絕緣層111B、及第二配線層132。第一配線層112及第二絕緣層111B中的至少一者可位於電子元件120的上表面與下表面之間的位階處。如圖44中所示，電子元件120的上表面相對於重新分配部140及150位於框架110的上表面110A下的位階處；然而，本發明並非僅限於此。電子元件120的上表面相對於重新分配部140、150及155可位於與框架110的上表面110A相同的位階處或位於框架110的上表面110A之上但位於第三配線層131的上表面下、或者位於與第三配線層131的上表面相同的位階處或位於第三配線層131的上表面之上，只要第三配線層131及電子元件120均被囊封劑160覆蓋即可。 The through hole 110X may penetrate the third wiring layer 131, the first insulating layer 111A, the first wiring layer 112, the second insulating layer 111B, and the second wiring layer 132 in order. At least one of the first wiring layer 112 and the second insulating layer 111B may be located at a level between the upper surface and the lower surface of the electronic device 120. As shown in FIG. 44, the upper surface of the electronic component 120 is located at a level below the upper surface 110A of the frame 110 relative to the redistribution portions 140 and 150; however, the present invention is not limited to this. The upper surface of the electronic component 120 may be located at the same level as the upper surface 110A of the frame 110 or above the upper surface 110A of the frame 110 but below the upper surface of the third wiring layer 131 relative to the redistribution portions 140, 150 and 155. Or, it may be located at the same level as the upper surface of the third wiring layer 131 or above the upper surface of the third wiring layer 131, as long as both the third wiring layer 131 and the electronic component 120 are covered with the encapsulant 160.

在下文中，將更詳細地闡述根據另一實例的電子元件封裝100T中的訊號移動路徑及依所述訊號移動路徑而定的接地的 佈局，將不再對與上述內容重複的內容予以闡述，且將主要闡述與上述內容不同的內容。 In the following, the signal movement path and the grounding according to the signal movement path in the electronic component package 100T according to another example will be explained in more detail The layout will no longer explain the content that is duplicated with the above content, and will mainly explain the content that is different from the above content.

電子元件120可具有用於訊號的電極焊墊(電極焊墊120P中沿路徑S'''的至少一者)，所述用於訊號的電極焊墊(電極焊墊120P中沿路徑S'''的至少一者)可經由重新分配部140的用於訊號的第一通孔(通孔143中沿路徑S'''的至少一者)而電性連接至重新分配部140的配線層142的第一訊號圖案(配線層142中沿路徑S'''的至少一個訊號圖案)，重新分配部140的配線層142的第一訊號圖案(配線層142中沿路徑S'''的至少一個訊號圖案)可經由重新分配部140的用於訊號的第二通孔(通孔143的沿路徑S'''的至少另一者)而電性連接至框架110的第二配線層132的第一訊號圖案(第二配線層132中沿路徑S'''的至少一個訊號圖案)，框架110的第二配線層132的第一訊號圖案(第二配線層132中沿路徑S'''的至少一個訊號圖案)可經由框架110的用於訊號的第一通孔(通孔113中沿路徑S'''的至少一者)而電性連接至框架110的第一配線層112的訊號圖案(第一配線層112中沿路徑S'''的至少一個訊號圖案)，框架110的第一配線層112的訊號圖案(第一配線層112中沿路徑S'''的至少一個訊號圖案)可經由框架110的用於訊號的第二通孔(通孔113中沿路徑S'''的至少一者)而電性連接至框架110的第二配線層132的第二訊號圖案(第二配線層132中沿路徑S'''的至少一個訊號圖案)，框架110的第二配線層132的第二訊號圖案(第二配線層132中沿路徑S'''的至少另一 訊號圖案)可經由重新分配部140的用於第三訊號的通孔(通孔113中沿路徑S'''的至少又一者)而電性連接至重新分配部140的配線層142的第二訊號圖案(配線層142中沿路徑S'''的至少另一訊號圖案)，重新分配部140的配線層142的第二訊號圖案(配線層142中沿路徑S'''的至少另一訊號圖案)可經由重新分配部150及155的用於訊號的通孔(通孔153中沿路徑S'''的至少一者及通孔158中沿路徑S'''的至少一者)、配線層152及157的訊號圖案(配線層152中沿路徑S'''的至少一個訊號圖案及配線層157中沿路徑S'''的至少一個訊號圖案)等而電性連接至安置於重新分配部140、150及155的一側的扇出區中的用於訊號的外部連接端子(外部連接端子175中沿路徑S'''的至少一者)，且框架110的第二配線層132及第三配線層131可具有用於提供訊號的返回路徑的接地圖案(第三配線層131中沿路徑G'''的至少一個接地圖案及第二配線層132中的沿路徑G'''的至少一個接地圖案)。 The electronic component 120 may have an electrode pad for signals (at least one of the electrode pads 120P along the path S'''), and the electrode pad for signals (the electrode pad 120P along the path S'' 'At least one of them) can be electrically connected to the wiring layer 142 of the redistribution part 140 through the first through hole of the redistribution part 140 for the signal (at least one of the through holes 143 along the path S'') The first signal pattern (at least one signal pattern along the path S''' in the wiring layer 142), the first signal pattern (at least one along the path S''' in the wiring layer 142 of the redistribution section 140 (Signal pattern) may be electrically connected to the second wiring layer 132 of the frame 110 through the second through-hole for signal of the redistribution part 140 (at least another one of the through-hole 143 along the path S′′). A signal pattern (at least one signal pattern along the path S''' in the second wiring layer 132), a first signal pattern (the path along the path S''' in the second wiring layer 132 of the second wiring layer 132 of the frame 110 (At least one signal pattern) may be electrically connected to the signal pattern of the first wiring layer 112 of the frame 110 through the first through hole of the frame 110 for signals (at least one of the through holes 113 along the path S′′) (At least one signal pattern along the path S'' in the first wiring layer 112), the signal pattern of the first wiring layer 112 in the frame 110 (at least one signal pattern along the path S''' in the first wiring layer 112) The second signal pattern (second) of the second wiring layer 132 of the frame 110 may be electrically connected to the second through hole of the frame 110 for signal (at least one of the through holes 113 along the path S′′). At least one signal pattern along the path S"' in the wiring layer 132), the second signal pattern of the second wiring layer 132 of the frame 110 (at least another one along the path S'" in the second wiring layer 132 Signal pattern) can be electrically connected to the first layer of the wiring layer 142 of the redistribution section 140 through the through-hole for the third signal of the redistribution section 140 (at least one of the through holes 113 along the path S′′). Two signal patterns (at least another signal pattern along the path S'' in the wiring layer 142), a second signal pattern (at least another along the path S''' in the wiring layer 142 of the redistribution section 140 (Signal pattern) can pass through the through holes for signals of the redistribution sections 150 and 155 (at least one of the through holes 153 along the path S'' and at least one of the through holes 158 along the path S''', The signal patterns of the wiring layers 152 and 157 (at least one signal pattern along the path S''' in the wiring layer 152 and at least one signal pattern along the path S''' in the wiring layer 157, etc. are electrically connected to the The external connection terminals for signals (at least one of the external connection terminals 175 along the path S′″) in the fan-out area on one side of the distribution portions 140, 150, and 155, and the second wiring layer 132 of the frame 110 And the third wiring layer 131 may have a ground pattern for providing a return path of the signal (at least one ground pattern along the path G'' in the third wiring layer 131 and along the path G''' in the second wiring layer 132 At least one ground pattern).

舉例而言，使用電子元件120中的電極焊墊120P中的某些電極焊墊120P的目的可為用於訊號連接，且使用電極焊墊120P中的其他電極焊墊120P的目的可為用於接地連接。所述訊號中的某些訊號可自用於訊號連接的電極焊墊120P開始經由重新分配部140的用於訊號的第一通孔(通孔143中沿路徑S'''的至少一者)而移動至重新分配部配線層142的訊號圖案(重新分配部配線層142中沿路徑S'''的至少一個訊號圖案)、經由重新分配部140的用於訊號的第二通孔(通孔143中沿路徑S'''的至少一者)而移動 至框架110的第二配線層132的第一訊號圖案(第二配線層132中沿路徑S'''的至少一個訊號圖案)，經由框架110的用於訊號的第一通孔(通孔113中沿路徑S'''的至少一者)而移動至框架110的第一配線層112的訊號圖案(第一配線層112中沿路徑S'''的至少一個訊號圖案)，經由框架110的用於訊號的第二通孔(通孔113中沿路徑S'''的至少另一者)而移動至框架110的第二配線層132的訊號圖案(第二配線層132中沿路徑S'''的至少另一訊號圖案)，經由重新分配部140的用於第三訊號的通孔(通孔143中沿路徑S'''的至少又一者)而移動至重新分配部140的配線層142的第二訊號圖案(配線層142中沿路徑S'''的至少另一訊號圖案)，經由重新分配部150的用於訊號的通孔(通孔153中沿路徑S'''的至少一者)而移動至重新分配部150的配線層152的訊號圖案(配線層152中沿路徑S'''的至少一個訊號圖案)，經由重新分配部155的用於訊號的通孔(通孔158中沿路徑S'''的至少一者)而移動至重新分配部155的配線層157的訊號圖案(配線層157中沿路徑S'''的至少一個訊號圖案)，穿過凸塊下金屬層(凸塊下金屬層172中沿路徑S'''的至少一者)並接著經由安置於扇出區中的用於訊號的第一外部連接端子(第一外部連接端子175中沿路徑S'''的至少一者)而移動至外部。 For example, some of the electrode pads 120P in the electronic component 120 may be used for signal connection, and other electrode pads 120P in the electrode pad 120P may be used for Ground connection. Some of the signals may start from the electrode pad 120P for signal connection through the first through hole of the redistribution portion 140 for the signal (at least one of the through holes 143 along the path S′'') The signal pattern moved to the redistribution section wiring layer 142 (at least one signal pattern along the path S'' in the redistribution section wiring layer 142), and the second through hole for the signal (through hole 143) via the redistribution section 140 At least one along the path S''') and move The first signal pattern to the second wiring layer 132 of the frame 110 (at least one signal pattern along the path S′′ in the second wiring layer 132) passes through the first through hole of the frame 110 for the signal (through hole 113 At least one along the path S''') and the signal pattern moving to the first wiring layer 112 of the frame 110 (at least one signal pattern along the path S''' in the first wiring layer 112), through the frame 110 The second through hole for the signal (at least another one of the through holes 113 along the path S′′) moves to the signal pattern of the second wiring layer 132 of the frame 110 (along the path S′ in the second wiring layer 132 ”At least another signal pattern) through the redistribution section 140 for the third signal through-hole (at least one of the through holes 143 along the path S″′) to move to the wiring of the redistribution section 140 The second signal pattern of the layer 142 (at least another signal pattern along the path S'' in the wiring layer 142) passes through the through hole for the signal of the redistribution section 150 (the path along the path S''' in the through hole 153 At least one) and the signal pattern of the wiring layer 152 of the redistribution section 150 (at least one signal pattern along the path S′′ in the wiring layer 152), through the through hole for the signal of the redistribution section 155 (through At least one of the holes 158 along the path S''') and the signal pattern of the wiring layer 157 (at least one signal pattern along the path S''' in the wiring layer 157) moving to the redistribution section 155, passing through the bump The lower metal layer (at least one of the lower bump metal layer 172 along the path S′″) and then via the first external connection terminal for signal (the middle edge of the first external connection terminal 175 disposed in the fan-out area At least one of the paths S''') to the outside.

為提供沿上述移動路徑的訊號的返回路徑，可在上述移動路徑之上或之下形成接地圖案。所述接地圖案可形成於框架110的第二配線層132及第三配線層131上以及重新分配部配線層142 及152上。在其中框架110的第一配線層112的絕大部分上形成有訊號圖案的情形中，與第一配線層112的下部部分及/或上部部分對應的第二配線層132及第三配線層131的絕大部分上可形成有接地圖案。此外，重新分配部配線層142的絕大部分上可形成有訊號圖案，且重新分配部配線層152的絕大部分上可形成有接地圖案。如上所述，框架110可用作訊號圖案、接地圖案等的重新分配區，且由於框架110可如上所述在安置電子元件120之前形成，因此可提高製程良率等。接地圖案可具有板形形狀等，但並非僅限於此。 In order to provide a signal return path along the moving path, a ground pattern may be formed above or below the moving path. The ground pattern may be formed on the second wiring layer 132 and the third wiring layer 131 of the frame 110 and the redistribution portion wiring layer 142 And 152. In the case where a signal pattern is formed on most of the first wiring layer 112 of the frame 110, the second wiring layer 132 and the third wiring layer 131 corresponding to the lower portion and/or the upper portion of the first wiring layer 112 The ground pattern can be formed on most of the. In addition, a signal pattern may be formed on most of the redistribution portion wiring layer 142, and a ground pattern may be formed on most of the redistribution portion wiring layer 152. As described above, the frame 110 can be used as a redistribution area of signal patterns, ground patterns, and the like, and since the frame 110 can be formed before the electronic device 120 is placed as described above, the process yield and the like can be improved. The ground pattern may have a plate shape or the like, but it is not limited to this.

其中多個電子元件封裝堆疊於一起的形式並非僅限於根據上述實例的形式，且可為其中根據上述各種實例的電子元件封裝100A至100T彼此組合的形式、其中另一類型的電子元件封裝安置於根據上述各種實例的電子元件封裝100A至100T上的形式、其中根據上述各種實例的電子元件封裝100A至100T安置於另一類型的電子元件封裝上的形式等。 The form in which a plurality of electronic component packages are stacked together is not limited to the form according to the above examples, and may be a form in which the electronic component packages 100A to 100T according to the various examples described above are combined with each other, in which another type of electronic component packages are placed in The form on the electronic component packages 100A to 100T according to the various examples described above, the form in which the electronic component packages 100A to 100T according to the various examples described above are disposed on another type of electronic component package, and the like.

根據本發明的電子元件封裝100A至100T及其經修改實例可以除上述形式以外的各種形式應用於電子產品。舉例而言，所述電子元件封裝的經修改實例中的具有內部通孔、覆蓋層、外配線層、及外通孔的電子元件封裝的經修改實例可被安置成下部封裝，且各種單獨表面安裝技術(separate surface-mounting technology，SMT)被動元件(圖中未示出)可安置於電子元件封裝的經修改實例的表面上。此外，若干類型的電子元件封裝或若 干其他類型的電子元件封裝(圖中未示出)可與被動元件一起被安置成上部封裝。所述被動元件亦可安置於開口部中，且可物理地連接至及/或電性連接至各種經由所述開口部而暴露出的配線層。 The electronic component packages 100A to 100T according to the present invention and modified examples thereof can be applied to electronic products in various forms other than the above-mentioned forms. For example, among the modified examples of the electronic component package, the modified examples of the electronic component package having an inner through hole, a cover layer, an outer wiring layer, and an outer through hole may be arranged as a lower package, and various individual surfaces Separate surface-mounting technology (SMT) passive components (not shown in the figure) may be placed on the surface of the modified example of the electronic component package. In addition, several types of electronic component packaging or Other types of electronic component packages (not shown in the figure) can be placed together with passive components as an upper package. The passive element may also be disposed in the opening, and may be physically and/or electrically connected to various wiring layers exposed through the opening.

如上所述，根據本發明中的示例性實施例，可提供一種其中電子元件的良率降低得到顯著抑制的電子元件封裝及其製造方法。 As described above, according to the exemplary embodiments in the present invention, it is possible to provide an electronic component package and a method of manufacturing the same in which the decrease in yield of electronic components is significantly suppressed.

同時，為方便起見，使用用語「下部部分」來指示相對於圖式所示橫截面朝向電子元件封裝的經安裝表面的方向，使用用語「上部部分」來指示與用語「下部部分」所指示的方向相對的方向，且使用用語「側部部分」來指示與用語「上部部分及下部部分」所指示的方向垂直的方向。此外，使用片語「位於下部部分、上部部分、或側部部分處」作為一包含其中目標元件位於對應方向上但不直接接觸參考元件的情形、及其中目標元件在對應方向上直接接觸參考元件的情形的概念。然而，定義該些方向是為了便於說明，且本發明的範圍並非特別地限定於如上所述進行定義的方向。 Meanwhile, for convenience, the term "lower part" is used to indicate the direction toward the mounted surface of the electronic component package with respect to the cross section shown in the drawings, and the term "upper part" is used to indicate the direction indicated by the term "lower part" The direction is opposite to the direction, and the term "side part" is used to indicate a direction perpendicular to the direction indicated by the term "upper part and lower part". In addition, the phrase "at the lower part, the upper part, or the side part" is used as a case where the target element is located in the corresponding direction but does not directly contact the reference element, and the target element directly contacts the reference element in the corresponding direction Concept of the situation. However, these directions are defined for convenience of explanation, and the scope of the present invention is not particularly limited to the directions defined as described above.

同時，詞語「連接」是一包含其中任意元件藉由黏合劑等而間接地連接至另一元件的情形、及其中任意元件直接連接至另一元件的情形的概念。此外，詞語「電性連接」是一包含其中任意元件物理地連接至另一元件的情形及其中任意元件不物理地連接至另一元件的情形二者的概念。此外，用語「第一」、「第二」 等用於區分各個元件，而並非限制對應元件的順序、重要性等。在某些情形中，在不背離本發明的範圍的條件下，第一元件可被稱為第二元件，且第二元件亦可類似地被稱為第一元件。 Meanwhile, the word "connected" is a concept including a case in which any element is indirectly connected to another element by an adhesive or the like, and a case in which any element is directly connected to another element. In addition, the word "electrically connected" is a concept that includes both the case where any element is physically connected to another element and the case where any element is not physically connected to another element. In addition, the terms "first" and "second" Etc. are used to distinguish each element without limiting the order, importance, etc. of the corresponding elements. In some cases, without departing from the scope of the present invention, the first element may be referred to as the second element, and the second element may similarly be referred to as the first element.

同時，用語「實例」並非意指同一示例性實施例，而是被提供以強調及闡述不同的獨有特徵。然而，以上所提出的實例亦可實作為與另一實例的特徵進行組合。舉例而言，即使在一具體實例中闡述的特定細節未在另一實例中進行闡述，但除另有說明外，其亦可被理解為與另一實例相關的闡述。 Meanwhile, the term "example" does not mean the same exemplary embodiment, but is provided to emphasize and explain different unique features. However, the example presented above can also be implemented in combination with the features of another example. For example, even if specific details set forth in a specific example are not set forth in another example, unless otherwise stated, they may also be understood as set forth in relation to another example.

同時，在本發明中所用的用語僅用於闡述實例而非用於限制本發明的範圍。此處，除非上下文中另有解釋，否則單數形式亦包含複數形式。 Meanwhile, the terms used in the present invention are only used to illustrate examples and not to limit the scope of the present invention. Here, unless otherwise explained in the context, singular forms also include plural forms.

儘管以上已示出並闡述了示例性實施例，然而對於熟習此項技術者將顯而易見，在不背離由隨附申請專利範圍界定的本發明的範圍的條件下，可作出潤飾及變型。 Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that retouching and modifications can be made without departing from the scope of the invention defined by the scope of the accompanying patent application.

100A‧‧‧電子元件封裝 100A‧‧‧Electronic component packaging

110‧‧‧框架 110‧‧‧Frame

110A‧‧‧上表面 110A‧‧‧Top surface

110B‧‧‧下表面 110B‧‧‧Lower surface

110X‧‧‧貫穿孔 110X‧‧‧Through hole

111A‧‧‧第一絕緣層 111A‧‧‧First insulation layer

111B‧‧‧第二絕緣層 111B‧‧‧Second insulation layer

112‧‧‧第一配線層 112‧‧‧First wiring layer

113‧‧‧通孔 113‧‧‧Through hole

120‧‧‧電子元件 120‧‧‧Electronic components

120P‧‧‧電極焊墊 120P‧‧‧electrode pad

132‧‧‧第二配線層 132‧‧‧Second wiring layer

135‧‧‧金屬層 135‧‧‧Metal layer

140‧‧‧重新分配部 140‧‧‧ Redistribution Department

141‧‧‧絕緣層 141‧‧‧Insulation

142‧‧‧配線層 142‧‧‧ wiring layer

143‧‧‧通孔 143‧‧‧Through hole

150‧‧‧重新分配部 150‧‧‧ Redistribution Department

151‧‧‧絕緣層 151‧‧‧Insulation

152‧‧‧配線層 152‧‧‧ wiring layer

153‧‧‧通孔 153‧‧‧Through hole

160‧‧‧囊封劑 160‧‧‧Encapsulating agent

170‧‧‧保護層 170‧‧‧Protective layer

171‧‧‧第一開口部 171‧‧‧First opening

175‧‧‧第一外部連接端子 175‧‧‧First external connection terminal

I-I’‧‧‧線 I-I’‧‧‧ line

Claims (32)

一種扇出半導體封裝，包括：第一連接構件，具有貫穿孔；半導體晶片，安置於所述貫穿孔中且具有主動表面以及非主動表面，連接焊墊安置於所述主動表面上且所述非主動表面相對於所述主動表面；囊封劑，囊封所述第一連接構件及所述半導體晶片的所述非主動表面的至少一部分；以及第二連接構件，安置於所述第一連接構件及所述半導體晶片的所述主動表面的下方且包括藉由連接通孔電性連接至所述連接焊墊的重新分配層，其中所述第一連接構件包括第一絕緣層、安置於所述第一絕緣層的表面上的第一重新分配層、安置於所述第一絕緣層上且覆蓋所述第一重新分配層的第二絕緣層以及安置於所述第二絕緣層上的第二重新分配層，以及所述第一連接構件的所述第一重新分配層及所述第二重新分配層藉由所述第二連接構件的所述重新分配層以及所述連接通孔電性連接至所述連接焊墊。 A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and a non-active surface; a connection pad is disposed on the active surface and the non- An active surface relative to the active surface; an encapsulant that encapsulates the first connection member and at least a portion of the inactive surface of the semiconductor wafer; and a second connection member disposed on the first connection member And below the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads through connection vias, wherein the first connection member includes a first insulating layer, disposed on the A first redistribution layer on the surface of the first insulation layer, a second insulation layer disposed on the first insulation layer and covering the first redistribution layer, and a second insulation layer disposed on the second insulation layer A redistribution layer, and the first redistribution layer and the second redistribution layer of the first connection member are electrically connected by the redistribution layer of the second connection member and the connection via To the connection pad. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述第一絕緣層的厚度大於所述第二絕緣層的厚度。 The fan-out semiconductor package as described in item 1 of the patent application range, wherein the thickness of the first insulating layer is greater than the thickness of the second insulating layer. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述第二重新分配層的厚度大於所述第二連接構件的所述重新分配層的厚度。 The fan-out semiconductor package as described in item 1 of the patent application range, wherein the thickness of the second redistribution layer is greater than the thickness of the redistribution layer of the second connection member. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述第二重新分配層位於與所述連接焊墊實質上相同位階上。 The fan-out semiconductor package as described in item 1 of the patent application scope, wherein the second redistribution layer is located at substantially the same level as the connection pads. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述第一重新分配層位於所述半導體晶片的所述主動表面及所述非主動表面之間。 The fan-out semiconductor package as recited in item 1 of the patent scope, wherein the first redistribution layer is located between the active surface and the inactive surface of the semiconductor wafer. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述第一連接構件更包括第三重新分配層，所述第三重新分配層安置於所述第一絕緣層的另一表面上，以及所述第三重新分配層電性連接至所述連接焊墊。 The fan-out semiconductor package as described in item 1 of the patent application range, wherein the first connection member further includes a third redistribution layer disposed on the other surface of the first insulating layer And the third redistribution layer is electrically connected to the connection pad. 如申請專利範圍第6項所述的扇出半導體封裝，其中所述第一連接構件更包括第三絕緣層及第四重新分配層，所述第三絕緣層安置於所述第一絕緣層上且覆蓋所述第三重新分配層，所述第四重新分配層安置於所述第三絕緣層上，以及所述第四重新分配層電性連接至所述連接焊墊。 The fan-out semiconductor package as described in item 6 of the patent application range, wherein the first connection member further includes a third insulating layer and a fourth redistribution layer, and the third insulating layer is disposed on the first insulating layer And cover the third redistribution layer, the fourth redistribution layer is disposed on the third insulating layer, and the fourth redistribution layer is electrically connected to the connection pad. 如申請專利範圍第6項所述的扇出半導體封裝，其中所述半導體晶片包括訊號連接焊墊，所述訊號連接焊墊電性連接至安置於所述第一連接構件上的扇出區中的訊號連接端子，所述訊號連接焊墊電性連接至所述訊號連接端子的電性路徑為通過所述第二連接構件的所述重新分配 層的訊號圖案以及所述第一連接構件的所述第一重新分配層的訊號圖案的次序或反向次序，以及所述第一連接構件的所述第二重新分配層及所述第三重新分配層具有接地圖案。 The fan-out semiconductor package as described in item 6 of the patent application range, wherein the semiconductor chip includes a signal connection pad, and the signal connection pad is electrically connected to a fan-out region disposed on the first connection member Signal connection terminal, the signal connection pad is electrically connected to the signal connection terminal and the electrical path is the redistribution through the second connection member The order of the signal pattern of the layer and the signal pattern of the first redistribution layer of the first connection member or the reverse order, and the second redistribution layer and the third redistribution of the first connection member The distribution layer has a ground pattern. 如申請專利範圍第7項所述的扇出半導體封裝，其中所述半導體晶片包括訊號連接焊墊，所述訊號連接焊墊電性連接至安置於所述第一連接構件上的扇出區中的訊號連接端子，所述訊號連接焊墊電性連接至所述訊號連接端子的電性路徑為通過所述第二連接構件的所述重新分配層的訊號圖案、所述第一連接構件的所述第一重新分配層的訊號圖案以及所述第一連接構件的所述第四重新分配層的訊號圖案的次序或反向次序，且所述第一連接構件的所述第二重新分配層及所述第三重新分配層具有接地圖案。 The fan-out semiconductor package as described in item 7 of the patent application range, wherein the semiconductor chip includes a signal connection pad, and the signal connection pad is electrically connected to a fan-out area disposed on the first connection member Signal connection terminal, the electrical path of the signal connection pad electrically connected to the signal connection terminal is the signal pattern passing through the redistribution layer of the second connection member and the position of the first connection member An order or a reverse order of the signal pattern of the first redistribution layer and the signal pattern of the fourth redistribution layer of the first connection member, and the second redistribution layer of the first connection member and The third redistribution layer has a ground pattern. 如申請專利範圍第6項所述的扇出半導體封裝，其中所述半導體晶片包括訊號連接焊墊，所述訊號連接焊墊電性連接至安置於所述第二連接構件上的扇出區中的訊號連接端子，所述訊號連接焊墊電性連接至所述訊號連接端子的電性路徑為通過所述第二連接構件的所述重新分配層的訊號圖案以及所述第一連接構件的所述第一重新分配層的訊號圖案的次序或反向次序，且所述第一連接構件的所述第二重新分配層及所述第三重新分 配層具有接地圖案。 The fan-out semiconductor package as described in item 6 of the patent application range, wherein the semiconductor chip includes a signal connection pad, and the signal connection pad is electrically connected to a fan-out area disposed on the second connection member Signal connection terminal, the electrical path of the signal connection pad electrically connected to the signal connection terminal is the signal pattern through the redistribution layer of the second connection member and the position of the first connection member The order or reverse order of the signal patterns of the first redistribution layer, and the second redistribution layer and the third redistribution of the first connection member The matching layer has a ground pattern. 如申請專利範圍第6項所述的扇出半導體封裝，其中所述第三重新分配層包括配線結合焊墊，且所述配線結合焊墊暴露於外部。 The fan-out semiconductor package as described in item 6 of the patent application range, wherein the third redistribution layer includes a wire bonding pad, and the wire bonding pad is exposed to the outside. 如申請專利範圍第6項所述的扇出半導體封裝，其中所述第一連接構件更包括：第一通孔，穿透過所述第一絕緣層，以將所述第一重新分配層及所述第三重新分配層彼此連接；以及第二通孔，穿透過所述第二絕緣層，以將所述第一重新分配層及所述第二重新分配層彼此連接，且所述第一通孔的直徑大於所述第二通孔的直徑。 The fan-out semiconductor package as described in item 6 of the patent application scope, wherein the first connection member further includes: a first through hole that penetrates through the first insulating layer to separate the first redistribution layer and the The third redistribution layer is connected to each other; and a second through hole penetrates through the second insulating layer to connect the first redistribution layer and the second redistribution layer to each other, and the first through The diameter of the hole is larger than the diameter of the second through hole. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述第一絕緣層的彈性模量大於所述第二絕緣層的彈性模量。 The fan-out semiconductor package as described in item 1 of the patent application range, wherein the elastic modulus of the first insulating layer is greater than the elastic modulus of the second insulating layer. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述第一連接構件更包括安置於所述貫穿孔的牆表面上的金屬層。 The fan-out semiconductor package as described in item 1 of the patent application range, wherein the first connection member further includes a metal layer disposed on the wall surface of the through hole. 如申請專利範圍第14項所述的扇出半導體封裝，其中所述金屬層電性連接至所述第一重新分配層及所述第二重新分配層中的至少一者。 The fan-out semiconductor package as described in item 14 of the patent application range, wherein the metal layer is electrically connected to at least one of the first redistribution layer and the second redistribution layer. 如申請專利範圍第1項所述的扇出半導體封裝，更包括安置於所述貫穿孔中的被動元件。 The fan-out semiconductor package as described in item 1 of the patent application scope further includes a passive element disposed in the through hole. 如申請專利範圍第1項所述的扇出半導體封裝，其中在所述囊封劑覆蓋所述第一連接構件及所述半導體晶片的所述非主動表面的同時，所述囊封劑填充至所述貫穿孔的牆表面與所述半導體晶片的一側之間的間隙。 The fan-out semiconductor package according to item 1 of the patent application range, wherein the encapsulant is filled to the same time as the encapsulant covers the first connection member and the inactive surface of the semiconductor wafer The gap between the wall surface of the through hole and one side of the semiconductor wafer. 如申請專利範圍第1項所述的扇出半導體封裝，其中所述囊封劑包括玻璃纖維、無機填料及絕緣樹脂。 The fan-out semiconductor package as described in item 1 of the patent application scope, wherein the encapsulant includes glass fiber, inorganic filler and insulating resin. 如申請專利範圍第1項所述的扇出半導體封裝，更包括：保護層，安置於所述第二連接構件上且具有開口部，所述開口部允許所述第二連接構件的所述重新分配層的至少部分被暴露；以及第一連接端子，安置於所述開口部上，其中所述第一連接端子中的至少一者位於扇出區中。 The fan-out semiconductor package as described in item 1 of the patent application scope further includes: a protective layer disposed on the second connection member and having an opening portion, the opening portion allowing the re-connection of the second connection member At least part of the distribution layer is exposed; and a first connection terminal is disposed on the opening portion, wherein at least one of the first connection terminals is located in the fan-out area. 如申請專利範圍第19項所述的扇出半導體封裝，更包括：第二連接端子，安置於穿透過所述囊封劑的所述開口部上且電性連接至所述第一連接構件。 The fan-out semiconductor package as described in item 19 of the patent application scope further includes: a second connection terminal disposed on the opening portion penetrating the encapsulant and electrically connected to the first connection member. 如申請專利範圍第19項所述的扇出半導體封裝，更包括：覆蓋層，安置於所述囊封劑上；以及第二連接端子，安置於穿透過所述覆蓋層的所述開口部上且電性連接至所述第一連接構件。 The fan-out semiconductor package as described in item 19 of the patent application scope further includes: a cover layer disposed on the encapsulant; and a second connection terminal disposed on the opening portion penetrating through the cover layer And it is electrically connected to the first connecting member. 如申請專利範圍第1項所述的扇出半導體封裝，更包括記憶體封裝，其堆疊於所述囊封劑上及電性連接至所述第一連接構件，其中所述半導體晶片包括應用處理器晶片，且所述記憶體封裝包括記憶體晶片。 The fan-out semiconductor package as described in item 1 of the patent application scope further includes a memory package stacked on the encapsulant and electrically connected to the first connection member, wherein the semiconductor chip includes application processing Chip, and the memory package includes a memory chip. 如申請專利範圍第1項所述的扇出半導體封裝，更包括安置於所述囊封劑上的背側重新分配層，其中所述背側重新分配層電性連接至所述連接焊墊。 The fan-out semiconductor package according to item 1 of the scope of the patent application further includes a backside redistribution layer disposed on the encapsulant, wherein the backside redistribution layer is electrically connected to the connection pad. 如申請專利範圍第23項所述的扇出半導體封裝，更包括安置於所述囊封劑上的覆蓋層，其中所述覆蓋層具有開口部，所述開口部使所述背側重新分配層的至少部分被暴露出。 The fan-out semiconductor package as described in item 23 of the patent application scope, further includes a cover layer disposed on the encapsulant, wherein the cover layer has an opening portion, the opening portion allows the backside redistribution layer At least part of it was exposed. 一種製造扇出半導體封裝的方法，所述製造扇出半導體封裝的方法包括：形成第一連接構件，藉由製備第一絕緣層、在所述第一絕緣層的表面上形成第一重新分配層、在所述第一絕緣層上形成第二絕緣層以覆蓋所述第一重新分配層、在所述第二絕緣層上形成第二重新分配層以及形成穿透過所述第一絕緣層及所述第二絕緣層的貫穿孔；安置半導體晶片於所述貫穿孔中，所述半導體晶片具有主動表面以及非主動表面，連接焊墊安置於所述主動表面上且所述非主動表面相對於所述主動表面；形成囊封劑，所述囊封劑囊封所述第一連接構件及所述半導 體晶片的所述非主動表面的至少一部分；以及形成包括重新分配層的第二連接構件，所述重新分配層電性連接至所述第一連接構件及所述半導體晶片的所述主動表面上的所述連接焊墊，其中所述第一重新分配層及所述第二重新分配層電性連接至所述連接焊墊，且是在提供所述半導體晶片之前形成。 A method of manufacturing a fan-out semiconductor package, the method of manufacturing a fan-out semiconductor package includes: forming a first connection member, by preparing a first insulating layer, forming a first redistribution layer on the surface of the first insulating layer Forming a second insulating layer on the first insulating layer to cover the first redistribution layer, forming a second redistribution layer on the second insulating layer, and forming the first insulating layer and the through The through hole of the second insulating layer; placing a semiconductor wafer in the through hole, the semiconductor wafer has an active surface and a non-active surface, a connection pad is disposed on the active surface and the non-active surface is opposite to the The active surface; forming an encapsulant that encapsulates the first connecting member and the semiconducting At least a portion of the non-active surface of the bulk wafer; and forming a second connection member including a redistribution layer electrically connected to the first connection member and the active surface of the semiconductor wafer The connection pad, wherein the first redistribution layer and the second redistribution layer are electrically connected to the connection pad, and are formed before the semiconductor wafer is provided. 如申請專利範圍第25項所述的製造扇出半導體封裝的方法，其中形成所述第一連接構件更包括在所述第一絕緣層的另一表面上形成第三重新分配層，所述第三重新分配層電性連接至所述連接焊墊，且是在提供所述半導體晶片之前形成。 The method for manufacturing a fan-out semiconductor package as described in item 25 of the patent application range, wherein forming the first connection member further includes forming a third redistribution layer on the other surface of the first insulating layer, the first The three redistribution layers are electrically connected to the connection pads, and are formed before the semiconductor wafer is provided. 如申請專利範圍第26項所述的製造扇出半導體封裝的方法，其中形成所述第一連接構件更包括在所述第一絕緣層上形成第三絕緣層以覆蓋所述第三重新分配層，以及在所述第三絕緣層上形成第四重新分配層，所述第四重新分配層電性連接至所述連接焊墊，且是在提供所述半導體晶片之前形成。 The method for manufacturing a fan-out semiconductor package as described in item 26 of the patent application range, wherein forming the first connection member further includes forming a third insulating layer on the first insulating layer to cover the third redistribution layer And forming a fourth redistribution layer on the third insulating layer, the fourth redistribution layer is electrically connected to the connection pad, and is formed before the semiconductor wafer is provided. 如申請專利範圍第25項所述的製造扇出半導體封裝的方法，其中在安置所述半導體晶片中，將黏合膜貼附至所述第一連接構件，且將所述半導體晶片的所述主動表面貼附至經由所述貫穿孔而暴露出的所述黏合膜。 The method for manufacturing a fan-out semiconductor package as described in item 25 of the patent application range, wherein in mounting the semiconductor wafer, an adhesive film is attached to the first connection member, and the active The surface is attached to the adhesive film exposed through the through hole. 一種扇出半導體封裝，包括： 第一連接構件，包括第一絕緣層、安置於所述第一絕緣層下的二個或更多個重新分配層、以及安置於所述二個或更多個重新分配層之間的第二絕緣層；半導體晶片，安置於穿透過所述第一連接構件的貫穿孔中；以及第二連接構件，電性連接至所述二個或更多個重新分配層及所述半導體晶片，且安置於所述第一連接構件及所述半導體晶片上，其中所述二個或更多個重新分配層及所述第二絕緣層安置於所述第二連接構件與所述第一絕緣層之間。 A fan-out semiconductor package, including: The first connection member includes a first insulating layer, two or more redistribution layers disposed under the first insulating layer, and a second disposed between the two or more redistribution layers An insulating layer; a semiconductor wafer, disposed in a through hole penetrating through the first connection member; and a second connection member, electrically connected to the two or more redistribution layers and the semiconductor wafer, and disposed On the first connection member and the semiconductor wafer, wherein the two or more redistribution layers and the second insulating layer are disposed between the second connection member and the first insulating layer . 如申請專利範圍第29項所述的扇出半導體封裝，其中所述二個或更多個重新分配層中的至少一者安置於所述半導體晶片的上表面與下表面之間。 The fan-out semiconductor package as described in item 29 of the patent application range, wherein at least one of the two or more redistribution layers is disposed between the upper surface and the lower surface of the semiconductor wafer. 一種製造扇出半導體封裝的方法，所述製造扇出半導體封裝的方法包括：製備包括多個絕緣層及多個重新分配層的第一連接構件；形成穿透過整個所述第一連接構件的貫穿孔；將所述第一連接構件及安置於所述貫穿孔內的半導體晶片貼附至臨時基板上；藉由至少使用囊封劑填充所述貫穿孔，以囊封所述半導體晶片；將所述臨時基板自所述第一連接構件、所述囊封劑及所述半 導體晶片分離；以及形成第二連接構件於所述第一連接構件、所述囊封劑及所述半導體晶片上，所述第二連接構件將所述半導體晶片彼此電性連接至所述多個重新分配層。 A method for manufacturing a fan-out semiconductor package, which includes: preparing a first connection member including a plurality of insulating layers and a plurality of redistribution layers; forming a penetration through the entire first connection member A hole; attach the first connection member and the semiconductor wafer disposed in the through hole to a temporary substrate; fill the through hole with at least an encapsulant to encapsulate the semiconductor chip; The temporary substrate from the first connecting member, the encapsulant and the semi- Conductor wafer separation; and forming a second connection member on the first connection member, the encapsulant and the semiconductor wafer, the second connection member electrically connects the semiconductor wafers to the plurality of Redistribute layers. 如申請專利範圍第31項所述的製造扇出半導體封裝的方法，其中所述第一連接構件的所述多個重新分配層中的至少一者安置於所述半導體晶片的上表面與下表面之間。 The method for manufacturing a fan-out semiconductor package as described in item 31 of the patent application range, wherein at least one of the plurality of redistribution layers of the first connection member is disposed on the upper and lower surfaces of the semiconductor wafer between.
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