TW201715664A - Electronic component package and method of manufacturing the same - Google Patents

Abstract

An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Description

Electronic component package and method of manufacturing same

The present invention relates to an electronic component package and a method of fabricating the same.

The electronic component packaging technology is a packaging technology for electrically connecting electronic components to a printed circuit board (PCB) such as a motherboard of an electronic device, and protecting the electronic components from external impact, and embedding the electronic components. Techniques in printed circuit boards such as interposer boards differ. Meanwhile, recently, a major trend in development techniques associated with electronic components has been to reduce component size. Thus, in the field of packaging, with the rapid increase in demand for small-sized electronic components and the like, a package having a plurality of pins and having a small size at the same time has been required.

To meet the technical requirements described above, one proposed packaging technique is a wafer level wrap (WLP) technique that utilizes the redistribution of electrode pads of electronic components formed on a wafer. As wafer-level packages (WLPs), there are fan-in WLPs and fan-out WLPs. In particular, fan-out wafer level packages can be used to implement multiple pins with small dimensions, and as a result, fan-out wafer level packages have recently been actively developed.

Meanwhile, in the case of the wafer level package in which the electronic component is encapsulated using only the general encapsulation material as described above, it is difficult to appropriately control excessive heat generation corresponding to high functionality of the package or the like, and it is difficult to appropriately Control electromagnetic waves.

Aspects of the present invention can provide an electronic component package that effectively reduces heat generated in an electronic component and reduces electromagnetic waves, and provides a manufacturing method thereof to efficiently manufacture an electronic component package.

In accordance with aspects of the present invention, an electronic component package can include a frame having a metal layer introduced into an encapsulation region of an electronic component in the package.

Hereinafter, embodiments of the invention will be explained as follows with reference to the accompanying drawings.

However, the invention may be embodied in many different forms and should not be construed as limited to the specific embodiments described herein. Rather, the embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed by those skilled in the art.

Throughout the specification, it will be understood that when a component (eg, layer, region, or wafer (substrate)) is referred to as being "on," "connected to," or "coupled" to another component. The components may be located directly on the other component, directly "connected to", or directly "coupled" to the other component, or other intermediate components may be present. In contrast, when a component is referred to as being "directly on" another component, "directly connected to" or "directly coupled" to another component, there may be no intermediate components or layers. The same reference numbers refer to the same components throughout. The term "and/or" used herein includes any and all combinations of one or more of the associated listed.

It will be apparent that, although the terms "first", "second", "third", and the like may be used herein to describe various components, components, regions, layers, and/or sections, the components, components, regions, Layers, and/or sections should not be limited by these terms. The terms are only used to distinguish between various components, elements, regions, layers, or sections. Thus, a first component, component, region, layer, or section discussed below could be termed a second component, component, region, layer, or section without departing from the teachings of the exemplary embodiments. .

In this paper, for the sake of explanation, spatial relativity such as "above", "upper", "below", "lower", etc. may be used. Terms are used to describe the relationship of one component shown in the figures to another (other) component. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated. For example, if the device in the figures is turned over, the components that are described as "above" or "above" other components will now be "below" or "below" other components or features. Therefore, depending on the specific direction of the figure, the term "above" can encompass both orientations above and below. The device may also have other orientations (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and the invention The singular forms "a", "an" and "the" It should be understood that the phrase "comprises and/or "comprising", when used in this specification, indicates the existence of the stated features, integers, steps, operations, components, components, and/or groups thereof, but not Exclusions or additions of one or more other features, integers, steps, operations, components, components, and/or groups thereof are excluded.

In the following, embodiments of the invention will be explained with reference to the schematic drawings illustrating embodiments of the invention. In the drawings, modifications to the shapes shown may be made as a result of, for example, manufacturing techniques and/or tolerances. Thus, the embodiments of the invention should not be construed as limited to the specific shapes of the regions illustrated herein. The following embodiments may also be composed of one or a combination thereof.

The content of the invention set forth below may have a variety of configurations and only the desired configuration may be presented herein, but the content is not limited thereto.

Electronic component

FIG. 1 is a block diagram schematically showing an example of an electronic device system.

Referring to FIG. 1 , a motherboard 1010 can be housed in the electronic device 1000 . Wafer related component 1020, network related component 1030, other components 1040, etc. can be physically and/or electrically coupled to motherboard 1010. These components can be coupled to other components as will be described below, thereby forming various signal lines 1090.

The wafer related component 1020 may include: a memory chip such as a volatile memory (eg, dynamic random access memory (DRAM)), non-volatile memory (eg, read only memory (read only) Memory, ROM), flash memory, etc.; application processor chips, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphics processing unit (graphic processing unit) , GPU)), digital signal processor, cryptographic processor, microprocessor, microcontroller, etc.; and logic chips, such as analog-to-digital converters, application-specific integrated Application-specific integrated circuit (ASIC), etc. However, wafer related component 1020 is not limited thereto, but may include other types of wafer related components. Moreover, these elements 1020 can be combined with each other.

The network-related component 1030 may include the following protocols: for example, Wi-Fi (Institute of Electrical and Electronics Engineers, IEEE 802.11 family, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access + (HSPA+), High speed downlink packet access + (HSDPA+), high speed uplink packet access + (HSUPA+), enhanced data GSM environment (EDGE), global action Global system for mobile communication (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), Time division multiple access Utili access, TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, 5G, and any other wireless and wireline agreements specified after the agreement. However, network related component 1030 is not limited thereto and may include any of a number of other wireless standards or protocols or wired standards or protocols. Moreover, these elements 1030 can be combined with each other and with the wafer related elements 1020 described above.

The other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, a ferrite bead, a low temperature co-firing ceramic (LTCC), and an electromagnetic interference (electro- Magnetic interference, EMI) filters, multilayer ceramic capacitors (MLCC), etc., but are not limited thereto. In addition to the above elements, other passive components and the like for various purposes may be included. Moreover, these elements 1040 can be combined with the wafer related components 1020 described above and/or the network related components 1030 described above.

Depending on the type of electronic device 1000, electronic device 1000 can include other components that can be physically and/or electrically connected to motherboard 1010 or that may not be physically and/or electrically connected to motherboard 1010. Examples of these other components may include a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown) Out), compass (not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (eg, hard drive) A drive machine (not shown), a compact disk (CD) (not shown), a digital versatile disk (DVD) (not shown), and the like. However, these other elements are not limited thereto, but may include other elements and the like for various purposes depending on the type of the electronic device 1000.

The electronic device 1000 can be a smart phone, a personal digital assistant, a digital camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a portable internet machine ( Netbook), TV, video game console, smart watches, etc. However, the electronic device 1000 is not limited thereto, but may be any other electronic device for processing data and the above-described electronic device.

FIG. 2 schematically illustrates an example of an electronic component package applied to an electronic device.

The electronic component package can be used in various electronic devices 1000 as described above for various purposes. For example, the main board 1110 can be housed in the main body 1101 of the smart phone 1100, and the various electronic components 1120 can be physically and/or electrically connected to the main board 1110. Moreover, another component (eg, camera 1130) that may be physically and/or electrically coupled to motherboard 1210 or that may not be physically and/or electrically connected to motherboard 1210 may be housed in body 1101. In this case, some of the electronic components 1120 may be wafer related components as described above, and the electronic component package 100 may be, for example, an application processor in a wafer related component, but the electronic component 1120 and electronic components The package 100 is not limited to this.

Electronic component packaging

FIG. 3 is a cross-sectional view schematically showing an example of an electronic component package.

Fig. 4 is a schematic cross-sectional plan view of the electronic component package taken along line I-I' shown in Fig. 3.

Referring to FIGS. 3 and 4 , the electronic component package 100A according to an example may include a frame 110 having a cavity 110X, an electronic component 120 disposed in the cavity 110X of the frame 110, and a first metal layer 111 disposed on the frame 110. The inner wall of the cavity 110X; the second metal layer 112B is disposed on the lower surface 110B of the frame 110; the third metal layer 112A is disposed on the upper surface 110A of the frame 110; the encapsulant 150 encapsulates the electronic component 120 And a redistribution layer 130 disposed under the frame 110 and the electronic component 120. Here, the phrase "placed under" may include a case in which a target element is disposed in a corresponding direction but does not contact an element as a base, and a case in which the target element directly contacts the element as a base.

In general, an electronic component package has a structure in which the periphery of the electronic component is molded and surrounded only by an encapsulant such as an epoxy molding compound (EMC). In this case, most of the heat generated in the electronic component is radiated downward along the redistribution layer, and only a very small amount of heat is transferred toward the encapsulant having a low thermal conductivity, so that the heat radiation characteristics are deteriorated. In contrast, in the case where the frame 110 having the metal layers 111, 112A, and 112B is introduced in the encapsulation region of the electronic component 120, the frame 110 can effectively control the warpage of the package, and by the metal layers 111, 112A, and 112B, heat can be It is easily diffused through various routes, so heat radiation characteristics can be improved.

Further, in the case of employing a structure in which the periphery of the electronic component is molded and surrounded by only an encapsulant such as an epoxy resin molding compound (EMC), the operational characteristics and the like of the electronic device in which the electronic component is mounted may be caused by Electromagnetic interference (EMI) caused by electromagnetic waves generated in an electronic component or introduced from the outside is deteriorated. In contrast, in the case where the frame 110 having the metal layers 111, 112A, and 112B is introduced in the encapsulation region of the electronic component 120, in general, since the metal layers 111, 112A, and 112B can also shield electromagnetic waves, they are caused by electromagnetic interference. The problem can also be solved.

Hereinafter, each configuration of the electronic component package 100A according to the example will be explained in more detail.

The frame 110 can be a configuration for supporting the package 100A, and because of the presence of the frame 110, can maintain rigidity and ensure thickness uniformity. The frame 110 may have an upper surface 110A and a lower surface 110B opposite to the upper surface 110A, and the cavity 110X may be formed to penetrate the upper surface 110A and the lower surface 110B. The electronic component 120 can be disposed in the cavity 110X spaced apart from the frame 110, and thus the frame 110 can surround a side surface of the electronic component 120.

The material of the frame 110 is not particularly limited as long as it can support the package. For example, an insulating material can be used. Here, as the insulating material, a thermosetting resin (for example, an epoxy resin), a thermoplastic resin (for example, polyimide), or a reinforcing material (for example, glass fiber or inorganic filler) may be immersed in the thermosetting resin and thermoplastic. Resin in resin (for example, pre-preg, Ajinomoto build-up film (ABF), FR-4, bismaleimide triazine (BT) resin Wait). Alternatively, a metal having excellent rigidity and thermal conductivity can be used. In this case, an Fe-Ni-based alloy can be used as the metal. Here, in order to secure adhesion to the molding material, an interlayer insulating material or the like (for example, a Cu plating layer) may be formed on the surface of the Fe-Ni-based alloy. In addition, glass, ceramics, plastics, and the like can be used.

The cross-sectional thickness of the frame 110 is not particularly limited and may be designed in accordance with the cross-sectional thickness of the electronic component 120. For example, depending on the type of electronic component 120, the cross-sectional thickness of the frame 110 can be, for example, from about 100 microns to about 500 microns.

Electronic component 120 can be various active components (eg, diodes, vacuum tubes, transistors, etc.) or passive components (eg, inductors, capacitors, resistors, etc.). Alternatively, electronic component 120 can be an integrated circuit (IC) wafer in which hundreds to millions or more of components are integrated with one another. If desired, the electronic component 120 can be an electronic component in which the integrated circuit is packaged in a flip chip form. The crystal circuit can be, for example, an application processor chip, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, Microprocessors, microcontrollers, etc., but not limited to this.

The electronic component 120 can include an electrode pad 120P that is electrically connected to the redistribution layer 130. The electrode pad 120P may be a configuration for electrically connecting the electronic component 120 externally, and any conductive material may be used as a material for forming the electrode pad 120P without particular limitation. Copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), alloys thereof, or the like can be used as the conductive material, but used to form an electrode The material of the pad 120P is not limited thereto. The electrode pads 120P may be redistributed by the redistribution layer 130. The electrode pad 120P can be embedded or can be protruded.

In the case where the electronic component 120 is an integrated circuit, the electrode component 120 may have a body (not indicated by a reference number), a passivation layer (not indicated by a reference number), and an electrode pad 120P. The body can be formed, for example, based on a active wafer. In this case, bismuth (Si), germanium (Ge), gallium arsenide (GaAs), or the like can be used as the base material of the body. The passivation layer can be used to protect the body from external factors and can be formed, for example, by an oxide film, a nitride film, or the like. Alternatively, the passivation layer may be formed of a double layer composed of an oxide film and a nitride film. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and alloys thereof can be used as the electrode for electrode formation The material of the pad 120P. The surface on which the electrode pad 120P is formed may become an active layer.

The cross-sectional thickness of the electronic component 120 is not particularly limited and may vary depending on the kind of the electronic component 120. For example, in the case where the electronic component is an integrated circuit, the electronic component 120 may have a cross-sectional thickness of about 100 micrometers to 480 micrometers, but is not limited thereto.

The first metal layer 111 can substantially allow the heat generated in the electronic component 120 to diffuse and disperse toward the frame 110 and shield the electromagnetic waves. The first metal layer 111 may be disposed on an inner wall of the cavity 110X, thereby surrounding a side surface of the electronic component 120. The first metal layer 111 may be a layer that completely covers the inner wall of the cavity 110X. In this case, heat generation problems and electromagnetic interference problems can be more effectively controlled. The first metal layer 111 may contain a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), alloys thereof, and the like. .

The second metal layer 112B can diffuse heat transferred through the first metal layer 111 or the like from the package 100A. In addition, the second metal layer 112B can further improve the electromagnetic wave shielding effect. The second metal layer 112B may be disposed on the lower surface 110B of the frame 110, and according to an example, the second metal layer 112B may be a layer that completely covers the lower surface 110B, and thus heat generation problems and electromagnetic interference problems may be more effectively controlled. The second metal layer 112B may also contain a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and alloys thereof. Wait.

If desired, the second metal layer 112B can be connected to a redistribution pattern of a ground (GND) pattern in the conductive pattern 132 that serves as the redistribution layer 130. Alternatively, the second metal layer 112B can be connected to a dummy pattern in the conductive pattern 132 of the redistribution layer 130. In this case, heat can be more easily dispersed downward from the package 100A. However, the second metal layer 112B is not limited thereto, and heat may be transferred by diffusion in a state in which the second metal layer 112B is not connected to the conductive pattern 132.

The third metal layer 112A can diffuse heat transferred through the first metal layer 111 or the like from the package 100A. Further, the third metal layer 112A can further improve the electromagnetic wave shielding effect. The third metal layer 112A may be disposed on the upper surface 110A of the frame 110, and according to an example, the third metal layer 112A may be a layer that completely covers the upper surface 110A, and thus heat generation problems and electromagnetic interference problems may be more effectively controlled. The third metal layer 112A may also contain a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and alloys thereof. Wait.

The redistribution layer 130 can be a configuration for the electrode pads 120P for redistributing the electronic components 120. The tens to hundreds of electrode pads 120P having various functions may be redistributed by the redistribution layer 130 and externally physically and/or electrically connected via external connection terminals 165 which will be explained below depending on their functions. .

The redistribution layer 130 may include: an insulating layer 131; a conductive pattern 132 disposed on the insulating layer 131; and a conductive via 133 penetrating through the insulating layer 131. In the electrode element package 100A according to the example, the redistribution layer 130 may be composed of a single layer. However, the redistribution layer 130 is not limited thereto and may be composed of a plurality of layers as described below.

An insulating material can be used as the material of the insulating layer 131. In this case, as the insulating material, a thermosetting resin (for example, an epoxy resin), a thermoplastic resin (for example, polyimide), or a reinforcing material (for example, glass fiber or inorganic filler) may be immersed in thermosetting property. Resins in resins and thermoplastic resins (for example, prepregs, ajinomoto-constituting films (ABF), FR-4, bismaleimide triazine (BT) resins, etc.). In the case of using a photosensitive insulating material such as a photo imageable dielectric (PID) resin, the insulating layer 131 can be formed to be thin, and fine pitch can be easily performed. The insulating layer 131 may be formed of the same material as each other, or may be formed of materials different from each other as needed. The thickness of the insulating layer 131 is also not particularly limited. For example, the thickness of the insulating layer 131 other than the conductive pattern 132 may be about 5 micrometers to 20 micrometers, and the insulating layer 131 may have a thickness of about 15 micrometers to 70 micrometers, depending on the thickness of the conductive pattern 132.

The conductive pattern 132 may function as a redistribution pattern, and may use, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and A conductive material such as an alloy is used as a material for forming the conductive pattern 132. The conductive patterns 132 and 142 can perform various functions depending on the design of the corresponding layer. For example, the conductive pattern 132 can function as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, or the like. Here, the signal (S) pattern may include various signal patterns such as a data signal pattern or the like in addition to the GND pattern, the PWR pattern, and the like. Further, the conductive pattern 132 can function as a via pad, an external connection terminal pad, or the like. The thickness of the conductive pattern 132 is also not particularly limited. For example, each of the conductive patterns 132 may have a thickness of about 10 micrometers to 50 micrometers.

If desired, a surface treatment layer may be formed on the exposed conductive pattern 132 in the conductive pattern 132. The surface treatment layer is not particularly limited as long as it is known in the art. For example, by electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) surface treatment or electroless tin plating, electroless silver plating, electroless nickel plating / displacement gold plating, direct immersion gold (direct immersion Gold, DIG) plating, hot air solder leveling (HASL) or the like to form the surface treatment layer.

The conductive via 133 may electrically connect the conductive patterns 132, the electrode pads 120, and the like formed on the different layers to each other, thereby forming an electrical path in the package 100A. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and alloys thereof can be used as the conductive path for forming 133 materials. The conductive path 133 may also be completely filled with a conductive material, or a conductive material may be formed on the wall of the via. Further, all shapes known in the art can be applied to the conductive path 133, such as a tapered shape whose diameter decreases downward, a reverse tapered shape whose diameter increases downward, a cylindrical shape, and the like.

Encapsulant 150 can be a configuration for protecting electronic component 120. To this end, the encapsulant 150 can encapsulate the electronic component 120. The shape of the encapsulant 150 is not particularly limited as long as the encapsulant 150 at least partially surrounds the electronic component 120. According to an example, the encapsulant 150 can cover the upper portion of the frame 110 and the upper portion of the electronic component 120. Thus, the encapsulant can fill the remaining space in the cavity 110X of the frame 110. Here, the term "covering the upper portion" may include a case in which the target element is disposed in the corresponding direction but does not contact the element as the base, and a case in which the target element directly contacts the element as the base. At the same time, encapsulant 150 fills cavity 110X, and thus encapsulant 150 can be used to reduce buckling of electronic component 120 while acting as an adhesive depending on the particular material of encapsulant 150.

The encapsulant 150 can be composed of a plurality of layers formed of a variety of materials. For example, the first encapsulant can fill the space in the cavity 110X, and then the second encapsulant can cover the upper portion of the frame 110 and the upper portion of the electronic component 120. Alternatively, after the first encapsulant is used to fill the space in the cavity 110X while covering the upper portion of the frame 110 and the upper portion of the electronic component 120 with a predetermined thickness, the second encapsulant may be used again to cover the predetermined thickness. An encapsulating agent. Further, the encapsulant 150 can be applied in various forms.

The specific material of the encapsulant 150 is not particularly limited. For example, an insulating material can be used as the material of the encapsulant 150. Here, as the insulating material, a thermosetting resin (for example, an epoxy resin), a thermoplastic resin (for example, polyimide), or a reinforcing material (for example, glass fiber or inorganic filler) may be similarly immersed in the thermosetting resin. And a resin in a thermoplastic resin (for example, a prepreg, ABF, FR-4, BT resin, photo-sensitive dielectric (PID) resin, etc.). Further, a molding material known in the art, such as an epoxy resin molding compound (EMC) or the like, can also be used.

The encapsulant 150 can have a lower modulus of elasticity than the material of the frame 110. For example, the encapsulant 150 can have an elastic modulus of about 15 GPa or less, for example from about 50 MPa to about 15 GPa. As the modulus of elasticity of the encapsulant 150 is relatively reduced, the warpage of the package 100A can be further reduced by the buckling effect and the stress dispersion effect on the electronic component 120. In detail, since the encapsulant 150 fills the space of the cavity 110X, the encapsulant 150 can exert a buckling effect on the electronic component 120, and since the encapsulant 150 covers the electronic component 120, the encapsulant 150 can be dispersed and reduced. The stress generated in the electronic component 120 is small. However, in the case where the elastic modulus is too small, the encapsulant 150 may not exert its essential effect due to excessive deformation.

If desired, the encapsulant 150 may contain conductive particles to shield the electromagnetic waves. Any conductive particles may be used as the conductive particles as long as they can shield electromagnetic waves. For example, the conductive particles may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are merely examples, and the conductive particles are not particularly limited thereto.

The interval in which the space of the encapsulant 150 is filled in the cavity 110X is not particularly limited and can be optimized by those having ordinary knowledge in the art. For example, the spacing may be from about 10 microns to about 150 microns, but is not limited thereto.

The electronic component package 100A according to an example may further include an outer layer 160 disposed under the redistribution layer 130. The outer layer 160 may be in a configuration for protecting the redistribution layer 130 from external physical or chemical damage or the like. The outer layer 160 can have an opening 161 that exposes at least a portion of the conductive pattern 132 of the redistribution layer 130. The opening 161 may expose one surface of a portion of the conductive pattern 132, but in some cases, the opening 161 may expose a side surface thereof.

The material of the outer layer 160 is not particularly limited. For example, a solder resist can be used. Further, the same material as the insulating layer 131 of the redistribution layer 130, such as the same PID resin, may also be used. The outer layer 160 can generally be a single layer, but can be constructed as multiple layers as desired.

The electronic component package 100A according to the example may further include an external connection terminal 165 exposed to the outside via the lower surface of the outer layer 160. The external connection terminal 165 may be a configuration for physically and/or electrically connecting the electronic component package 100A to the outside. For example, the electronic component package 100A can be mounted on the main board of the electronic device via the external connection terminal 165. The external connection terminal 165 may be disposed in the opening 161 and connected to the conductive pattern 132 exposed to the opening 161. Therefore, the external connection terminal 165 can also be electrically connected to the electronic component 120.

The external connection terminal 165 may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are merely examples, and the material of the external connection terminal 165 is not particularly limited thereto. The external connection terminal 165 may be a land, a ball, a pin, or the like. The external connection terminal 165 may be formed of a plurality of layers or a single layer. In the case where the external connection terminal 165 is formed of a plurality of layers, the external connection terminal 165 may contain a copper post and solder, and in the case where the external connection terminal 165 is formed of a single layer, the external connection terminal 165 may contain tin-silver Solder or copper. However, these cases are merely examples, and the external connection terminal 165 is not limited thereto.

Some of the external connection terminals 165 may be disposed in the fan-out area. The fan-out area may be defined as a region deviated from a region in which the electronic component 120 is disposed. That is, the electronic component package 100A according to the example may be a fan-out package. In the case of a fan-out package, reliability is superior to that of a fan-in package, and multiple input/output (I/O) terminals can be implemented, and three-dimensional (3D) interconnection can be easily performed. In addition, since the fan-out package can be mounted on an electronic device without a separate board as compared to a ball grid array (BGA) package, a land grid array (LGA) package, etc., fan-out The package can be manufactured to have a reduced thickness, and the price competitiveness can be excellent.

The number, the interval, the arrangement shape, and the like of the external connection terminals 165 are not particularly limited, and can be sufficiently changed by those skilled in the art according to design. For example, depending on the number of electrode pads 120P of the electronic component 120, the number of external connection terminals 165 may be tens to thousands, but is not limited thereto. The number of external connection terminals 165 may be larger or smaller than the above range.

5A to 5E illustrate an example of a schematic manufacturing process of the electronic component package shown in FIG.

In the description of the example of the manufacturing process of the electronic component package 100A, the description of the above-described electronic component package 100A will not be repeated, and the differences between the two will be mainly described below.

Referring to Figure 5A, a frame 110 can be prepared. Here, A denotes a plan view of the frame 110, and B illustrates a cross section of A which can be used as a certain area of the unit package. The frame 110 can be manufactured to have various sizes so as to be easily mass-produced. That is, after the large-size frame 110 is prepared, the plurality of electronic component packages 100A can be manufactured by a process which will be described later. The plurality of electronic component packages 100 can then be individually divided into individual packages 100 by sawing. A fiducial mark for achieving excellent pick-and-place (P&P) can be provided on the frame 110, and thus the position at which the electronic component 120 is mounted can be more accurately confirmed by the fiducial mark , thereby improving manufacturing integrity.

Referring to FIG. 5B, a cavity 110X penetrating through the frame 110 can be formed. Here, A denotes a plan view of the frame 110 in which the cavity 110X is formed, and B illustrates a cross section of A in A which can be used as a unit package. The method for forming the cavity 110X is not particularly limited. For example, the cavity 110X may be formed by a mechanical drilling method and/or a laser drilling method, a sandblasting method using abrasive particles, a dry etching method using a plasma, or the like. In the case where mechanical drilling and/or laser drilling is used to form the cavity 110X, a decontamination treatment (for example, a permanganate method or the like) may be performed to remove the resin stain in the cavity 110X. The size, shape, and the like of the cavity 110X can be designed to be suitable for the size, shape, number, and the like of the electronic component 120 to be mounted.

Referring to FIG. 5C, metal layers 111, 112A, and 112B may be formed on the upper surface 110A and the lower surface 110B of the frame 110 and the inner wall of the cavity 110X. Here, A denotes a plan view of the frame 110 in which the metal layers 111, 112A, and 112B are formed, and B illustrates a cross section of A in A which can be used as a unit package. Metal layers 111, 112A, and 112B can be formed by methods known in the art. For example, the metal layers 111, 112A, and 112B may be formed by electrolytic copper plating, electroless copper plating, or the like. More specifically, it can be, for example, a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, a sputtering method, a subtractive method, an additive method, and a semi-additive method. The metal layers 111, 112A, and 112B are formed by a method such as a semi-additive process (SAP) or a modified semi-additive process (MSAP), but are not limited thereto.

Referring to Figure 5D, electronic component 120 can be placed in cavity 110X. The electronic component 120 can be placed face down so that the electrode pad 120P faces downward. However, the electronic component 120 is not limited thereto, and if desired, the electronic component 120 can also be placed face up. Thereafter, the electronic component 120 can be encapsulated using an encapsulant 150. The encapsulant 150 may fill the space in the cavity 110X while covering the upper portion of the frame 110 and the upper portion of the electronic component 120. Encapsulant 150 can be formed by methods known in the art. For example, encapsulant 150 can be formed by laminating the precursor of encapsulant 150 and curing the laminated precursor. Alternatively, the encapsulant 150 may be applied in a state in which the lower portion of the cavity 110 is closed using a tape (not shown) or the like to encapsulate the electronic component 120, and then the applied encapsulant may be applied. 150 curing. The electronic component 120 can be fixed by curing. As a method of laminating the precursor, for example, it is possible to perform the process of pressing the object at a high temperature for a predetermined time, cooling the object to room temperature by depressurization, and then separating the processing tool by cooling in a cold press. Hot pressing method and the like. As the application method, for example, a screen printing method in which ink is applied by a squeegee, a spray printing method in which an ink is sprayed to apply ink, or the like can be used.

Referring to FIG. 5E, a redistribution layer 130 can be formed under the frame 110 and the electronic component 120. In detail, the insulating layer 131 may be formed under the frame 110 and the electronic component 120, and then the conductive pattern 132 and the conductive via 133 may be formed, and thus the redistribution layer 130 may be formed.

The insulating layer 131 can be formed by a method known in the art. For example, the insulating layer 131 may be formed by laminating a precursor of the insulating layer 131 and curing the laminated precursor, a method of applying a material of the insulating layer 131, and curing the applied material, or the like. Not limited to this. As a method of laminating the precursor, for example, it is possible to perform the process of pressing the object at a high temperature for a predetermined time, cooling the object to room temperature by depressurization, and then separating the processing tool by cooling in a cold press. Hot pressing method and the like. As the application method, for example, a screen printing method in which ink is applied by a squeegee, a spray printing method in which ink is sprayed to apply ink, and the like can be used. As a post-process curing process, it may be a process of drying the encapsulating material to make it incompletely cured, using a photolithography process, or the like.

The conductive pattern 132 and the conductive via 133 may also be formed by methods known in the art. First, a via hole (not shown) may be formed using mechanical drilling and/or laser drilling as described above, and in the case where the insulating layer 131 contains a PID resin or the like, photolithography may also be used. To form the via hole. The conductive pattern 132 and the conductive via 133 can be formed by electrolytic copper plating, electroless copper plating, or the like using a dry film pattern.

After the redistribution layer 130 is formed, the outer layer 160 may be formed under the redistribution layer 130. Similarly, the outer layer 160 may be formed by a method of laminating a precursor of the outer layer 160 and curing the laminated precursor, a method of applying a material for forming the outer layer 160, and curing the applied material. . Opening 161 may then be formed in outer layer 160 such that conductive pattern 132 is at least partially exposed. The opening 161 can be formed using mechanical drilling and/or laser drilling. Alternatively, the opening 161 can be formed by photolithography.

After the opening 161 is formed in the outer layer 160, the external connection terminal 165 disposed in the opening 161 may be formed. The method for forming the external connection terminal 165 is not particularly limited, and depending on the structure or shape thereof, the external connection terminal 165 can be formed by a method known in the art. The external connection terminal 165 may be fixed by reflow, and a part of the external connection terminal 165 may be embedded in the outer layer 160, and another portion of the external connection terminal 165 may be exposed to the outside, in order to increase the fixing force. This improves reliability. In some cases, only the opening 161 may be formed, and the external connection terminal 165 may be formed by a separate process of the purchase customer of the package 100A as needed.

FIG. 6 is a cross-sectional view schematically showing another example of an electronic component package.

Fig. 7 is a schematic cross-sectional plan view of the electronic component package taken along line II-II' shown in Fig. 6.

Referring to FIGS. 6 and 7, in the electronic component package 100B according to another example, the encapsulant 150 may also surround the outer side surface of the frame 110. When the frame 110 is surrounded by the encapsulant 150 as described above, the frame 110 is not exposed to the outside, and thus reliability can be improved by preventing oxidation or the like. Since the description of each configuration included in the electronic component package 100B according to another example is repeated with the above description, it will not be described again. Further, since the manufacturing method of the electronic component package 100B according to another example is the same as the manufacturing method of the above-described electronic component package 100A except that the frame 110 is formed such that the encapsulant 150 surrounds the outer surface of the frame 110 or the like, I will repeat them.

FIG. 8 is a cross-sectional view schematically showing another example of the electronic component package.

Figure 9 is a schematic cross-sectional plan view of the electronic component package taken along line III-III' shown in Figure 8.

Referring to FIGS. 8 and 9, the electronic component package 100C according to another example may further include a penetration wiring 113 penetrating through the frame 110, and disposed on the lower surface 110B of the frame 110 and the second metal layer 112B on the upper surface 110A and The third metal layer 112A can be patterned. Hereinafter, each configuration included in the electronic component package 100C according to another example will be explained in more detail, but the description overlapping with the above description will not be repeated, and the difference between the two will be mainly explained.

The penetration wiring 113 penetrating through the upper surface 110A and the lower surface 110B of the frame 110 may be used to electrically connect the conductive patterns disposed on the different layers to each other, and may use, for example, copper (Cu), aluminum (Al), silver (Ag) A conductive material such as tin (Sn), gold (Au), nickel (Ni), lead (Pb), or an alloy thereof is used as a material for forming the penetration wiring 113. The upper and lower portions of the electronic component package 100C can be electrically connected to each other via the left and right side surfaces of the electronic component 120 by the penetration wiring 113, and thus the space utilization can be remarkably improved. Therefore, the electronic component package 100C can be applied to a package on package (PoP) or the like by connection in a three-dimensional structure, and thus the electronic component package 100C can be widely applied to various current modules or package application products. The number, the interval, the arrangement shape, and the like of the penetration wiring 113 are not particularly limited, and can be sufficiently changed by those skilled in the art according to design. The penetration wiring 113 may be connected to a pad pattern serving as a pad of the penetration wiring in the second metal layer 112B and the third metal layer 112A. For example, depending on the shape of another package mounted on the electronic component package 100C, the penetration wiring 113 may be disposed only in a specific region of the frame 110 as shown in FIG. Unlike this, the penetration wiring 113 can be disposed on the entire surface of the frame 110. In the case where a metal (for example, an Fe-Ni-based alloy or the like) is used as the material of the frame 110, the insulating material may be disposed between the metal and the penetration wiring 113 and/or the metal layers 112A and 112B to penetrate the wiring 113. Or the metal layers 112A and 112B are electrically insulated.

The second metal layer 112B and the third metal layer 112A may also function as a redistribution pattern, and for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni) may be used. A conductive material such as lead (Pb) or an alloy thereof is used as a material for forming the second metal layer 112B and the third metal layer 112A. The second metal layer 112B and the third metal layer 112A can perform various functions depending on the design of the corresponding layer. For example, the second metal layer 112B and the third metal layer 112A can function as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, a bond finger (BF) pattern, or the like. Here, the signal (S) pattern may include various signal patterns such as a data signal pattern, etc., in addition to the GND pattern, the PWR pattern, the wire bonding (BF) pattern, and the like. Further, the second metal layer 112B and the third metal layer 112A can function as via pads, penetration wiring pads, external connection terminal pads, and the like. The thickness of the second metal layer 112B and the third metal layer 112A is also not particularly limited. For example, each of the second metal layer 112B and the third metal layer 112A may have a thickness of about 10 micrometers to 50 micrometers. In some cases, the second metal layer 112B and the third metal layer 112A may be dummy patterns without redistribution function. According to another example, the second metal layer 112B and the third metal layer 112A may not be connected to the first metal layer 111. However, in the case where the second metal layer 112B and the third metal layer 112A are ground (GND) patterns or dummy patterns, the second metal layer 112B and the third metal layer 112A may be connected to the first metal layer 111, but not Limited to this.

In the electronic component package 100C according to another example, the encapsulant 150 may have an opening 151 that at least partially exposes the third metal layer 112A disposed on the upper surface 110A of the frame 110. Further, the electronic component package 100C may further include an external connection terminal 175 exposed to the outside via an outer edge surface of the encapsulant 150. The external connection terminal 175 may be a configuration for physically and/or electrically connecting another electronic component on the electronic component package 100C, another package, or the like to the electronic component package 100C. For example, another electronic component package may be mounted on the electronic component package 100C via the external connection terminal 175, thereby forming a stacked package structure. The external connection terminal may be disposed in the opening 151 of the encapsulant 150 and connected to the third metal layer 112A exposed through the opening 151. Therefore, the external connection terminal can be electrically connected to the electronic component 120.

The external connection terminal 175 may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are merely examples, and the material of the external connection terminal 175 is not particularly limited thereto. The external connection terminal 175 can be a pad, a ball, a pin, or the like. The external connection terminal 175 may be formed of a plurality of layers or a single layer. In the case where the external connection terminal 175 is formed of a plurality of layers, the external connection terminal 175 may contain a copper post and solder, and in the case where the external connection terminal 175 is formed of a single layer, the external connection terminal 175 may contain tin-silver Solder or copper. However, these cases are merely examples, and the external connection terminal 175 is not limited thereto.

Meanwhile, unlike the one shown in FIGS. 8 and 9, the electronic component package 100C according to another example may be modified into a shape in which the characteristic shape of the above-described electronic component package 100B is applied. In addition, the manufacturing method of the electronic component package 100C according to another example and the above-described electronic component package 100A are performed, except that the penetration wiring 130 is formed in advance in the frame 110 and the second metal layer 112B and the third metal layer 112A are patterned. The manufacturing method is the same, so it will not be described again.

FIG. 10 is a cross-sectional view schematically showing another example of an electronic component package.

Figure 11 is a schematic cross-sectional plan view of the electronic component package taken along line IV-IV' shown in Figure 10 .

Referring to FIGS. 10 and 11, the electronic component package 100D according to another example may further include a penetration wiring 113 penetrating through the frame 110, and disposed on the lower surface 110B of the frame 110 and the second metal layer 112B on the upper surface 110A and The third metal layer 112A can be patterned. In addition, the electronic component package 100D can include an outer edge conductive pattern 152 disposed on the encapsulant 150, and an outer edge conductive via 153 that partially penetrates the encapsulant 150. Hereinafter, each configuration included in the electronic component package 100D according to another example will be explained in more detail, but the description overlapping with the above description will not be repeated, and the difference between the two will be mainly explained.

Similarly, the number, spacing, placement shape, and the like of the penetration wiring 113 penetrating the upper surface 110A and the lower surface 110B of the frame 110 are not particularly limited, and can be sufficiently changed by those skilled in the art according to design. For example, depending on the shape of another package mounted on the electronic component package 100D, the penetration wiring 113 may be disposed on the entire surface of the frame 110 as shown in FIG. Unlike this, the penetration wiring 113 may be disposed only in a specific region of the frame 110.

The outer edge conductive pattern 152 disposed on the encapsulant 150 may function as a redistribution pattern, and may use, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel ( A conductive material such as Ni), lead (Pb), or an alloy thereof is used as a material for forming the outer edge conductive pattern 152. Specific examples are as described above. The outer edge conductive pattern 152 can perform various functions depending on the design of the corresponding layer. For example, the outer edge conductive pattern 152 can function as a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, or the like. Here, the signal (S) pattern may include various signal patterns such as a data signal pattern, etc., in addition to a ground (GND) pattern, a power (PWR) pattern, and the like. In addition, the outer edge conductive pattern 152 can function as a via pad, an external connection terminal pad, or the like. The outer edge conductive pattern 152 may be disposed on the entire surface of the encapsulant 150, and the external connection terminal 175 may also be disposed on the entire surface of the cover layer 170 to be described below according to the outer edge conductive pattern 152, and thus the electronic component package It can be designed in a variety of different ways. The thickness of the outer edge conductive pattern 152 is also not particularly limited. For example, each outer edge conductive pattern 152 can have a thickness of from about 10 microns to about 50 microns. If desired, the outer edge conductive pattern 152 can be positioned to substantially substantially cover the upper region of the electronic component 120 based on the area of the plane occupied by the electronic component 120. In this case, since all surfaces of the electronic component 120 are surrounded by the conductive component, electromagnetic waves can be effectively shielded.

The outer edge conductive vias 153 that partially penetrate the encapsulant 150 can be electrically connected to the conductive patterns 112A and 152 formed on different layers from each other, thereby forming an electrical path in the package 100D. Conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and alloys thereof may also be used as the outer layer for forming The material of the edge conductive path 153. The outer edge conductive via 153 can be completely filled with a conductive material, or a conductive material can be formed on the wall of the via. Further, all shapes known in the art can be applied to the outer edge conductive path 153, such as a tapered shape whose diameter decreases downward, a reverse tapered shape whose diameter increases downward, a cylindrical shape, and the like.

The electronic component package 100D according to another example may further include a cover layer 170 disposed on the encapsulant 150. The cover layer 170 may be in a configuration for protecting the encapsulant 150, the outer edge conductive pattern 152, and the like from external physical or chemical damage or the like. The cover layer 170 can have an opening 171 that at least partially exposes the outer edge conductive pattern 152 disposed on the encapsulant 150. The opening 171 may expose one surface of a portion of the outer edge conductive pattern 152, but in some cases, the opening 171 may expose its side surface. There is no particular limitation on the material of the cover layer 170. For example, a solder resist can be used. In addition, various PID resins can be used. If desired, the cover layer 170 can be constructed of multiple layers.

The electronic component package 100D according to another example may further include an external connection terminal 175 disposed in the opening 171 of the cover layer 170. The external connection terminal 175 may be disposed in the opening 171 and connected to the outer edge conductive pattern 152 exposed to the opening 171. The external connection terminal 175 may be formed of a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), solder, or the like. However, these materials are merely examples, and the material of the external connection terminal 175 is not particularly limited thereto. The external connection terminal 175 can be a pad, a ball, a pin, or the like. The external connection terminal 175 may be formed of a plurality of layers or a single layer. In the case where the external connection terminal 175 is formed of a plurality of layers, the external connection terminal 175 may contain a copper post and solder, and in the case where the external connection terminal 175 is formed of a single layer, the external connection terminal 175 may contain tin-silver Solder or copper. However, these cases are merely examples, and the external connection terminal 175 is not limited thereto. If desired, various individual passive components (not shown) may also be placed in the opening 171.

Meanwhile, unlike the one shown in FIGS. 10 and 11, the electronic component package 100D according to another example may be modified into a shape in which the characteristic shape of the above-described electronic component package 100B is applied. In addition, since the manufacturing method of the electronic component package 100D according to another example is the same as the manufacturing method of the above-described electronic component package 100A except for forming the outer edge conductive pattern 152, the outer edge conductive via 153, and the like, the detailed description thereof will not be repeated.

Fig. 12 is a cross-sectional view schematically showing another example of the electronic component package.

Figure 13 is a schematic cross-sectional plan view of the electronic component package taken along line V-V' shown in Figure 12 .

Referring to FIGS. 12 and 13, in an electronic component package 100E according to another example, at least one of the electronic components 120 and 124 may be an integrated circuit 120, and at least another may be a passive component 124. Hereinafter, each configuration included in the electronic component package 100E according to another example will be explained in more detail, but the description overlapping with the above description will not be described again, and the difference between the two will be mainly explained.

The integrated circuit 120 can be a wafer in which at least hundreds to millions or more of various components are integrated with each other. For example, the integrated circuit 120 can be an application processor chip, such as a central processing unit (eg, a central processing unit (CPU)), a graphics processor (eg, a graphics processing unit (GPU)), a digital signal processor, Cryptographic processors, microprocessors, microcontrollers, etc., but not limited to this. Passive component 124 can be, for example, an inductor, a capacitor, a resistor, etc., but is not limited thereto. The integrated circuit 120 can be electrically connected to the redistribution layer 130 via the electrode pads 120P. The passive component 124 can be electrically connected to the redistribution layer via an electrode pad (not shown) (eg, an external electrode).

The number, spacing, arrangement shape, and the like of the integrated circuit 120 and the passive element 124 are not particularly limited, and can be sufficiently changed by those skilled in the art according to design. For example, the integrated circuit 120 can be disposed near the center of the cavity 110X, and the passive component 124 can be disposed adjacent the inner wall of the cavity 110X, but the integrated circuit 120 and the passive component 124 are not limited thereto. Further, only a single integrated circuit 120 may be disposed, and a plurality of passive elements 124 may be disposed. However, the integrated circuit 120 and the passive component 124 are not limited thereto. That is, a plurality of integrated circuits 120 and a single passive component 124 can be disposed. Alternatively, only a single integrated circuit 120 and a single passive component 124 may be disposed, or a plurality of integrated circuits 120 and a plurality of passive components may be disposed.

Meanwhile, unlike the one shown in FIGS. 12 and 13, the electronic component package 100E according to another example may be modified into a shape in which the specific shape of the above-described electronic component packages 100B to 100D is applied. In addition, since the integrated circuit 120 and the passive element 124 are disposed together as the electronic components 120 and 124 and the like, the manufacturing method of the electronic component package 100E according to another example is the same as that of the above-described electronic component package 100A, and thus It will not be repeated.

FIG. 14 is a cross-sectional view schematically showing another example of an electronic component package.

Figure 15 is a schematic cross-sectional plan view of the electronic component package taken along line VI-VI' shown in Figure 14.

Referring to FIGS. 14 and 15 , an electronic component package 100F according to another example may include a plurality of electronic components 120 and 122 . Hereinafter, each configuration included in the electronic component package 100F according to another example will be explained in more detail, but the description overlapping with the above description will not be described again, and the difference between the two will be mainly explained.

The plurality of electronic components 120 and 122 may be the same or different from each other. The plurality of electronic components 120 and 122 may include electrode pads 120P and 122P electrically connected to the redistribution layer 130, respectively. The electrode pads 120P and 122P may be redistributed by the redistribution layer 130, respectively. The number, spacing, placement shape, and the like of the plurality of electronic components 120 and 122 are not particularly limited, and can be sufficiently changed by those skilled in the art according to design. For example, the number of the plurality of electronic components 120 and 122 may be two as shown in FIG. 14 and FIG. 15, but is not limited thereto. That is, three, four, or more electronic components can be placed.

Meanwhile, unlike the one shown in FIGS. 14 and 15, the electronic component package 100F according to another example may be modified into a shape in which the above-described electronic component packages 100B to 100E are applied in a unique shape. In addition, since the manufacturing method of the electronic component package 100F according to another example is the same as the manufacturing method of the above-described electronic component package 100A except for arranging the plurality of electronic components 120 and 122, etc., the detailed description thereof will not be repeated.

Fig. 16 is a cross-sectional view schematically showing another example of the electronic component package.

Figure 17 is a schematic cross-sectional plan view of the electronic component package taken along line VII-VII' shown in Figure 16 .

Referring to FIGS. 16 and 17, an electronic component package 100G according to another example may include a plurality of cavities 110X1 and 110X2, and electronic components 120 and 122 may be disposed in the cavities 110X1 and 110X2, respectively. Hereinafter, each configuration included in the electronic component package 100G according to another example will be explained in more detail, but the description overlapping with the above description will not be described again, and the difference between the two will be mainly explained.

The areas, shapes, and the like of the plurality of cavities 110X1 and 110X2 may be the same or different from each other, and the electronic components 120 and 122 respectively disposed in the cavities 110X1 and 110X2 may be the same or different from each other. The number, spacing, arrangement shape, and the like of the plurality of cavities 110X1 and 110X2 and the electronic components 120 and 122 respectively disposed therein are not particularly limited, and can be sufficiently changed by those skilled in the art according to design. For example, the number of the plurality of cavities 110X1 and 110X2 may be two as shown in FIGS. 16 and 17, but is not limited thereto. That is, the number of the plurality of cavities 110X1 and 110X2 may be three, four or more. In addition, the number of the electronic components 120 and 122 respectively disposed in the cavities 110X1 and 110X2 may be one as shown in FIGS. 16 and 17, but is not limited thereto. That is, the number of electronic components 120 and 122 may be two, three or more.

Meanwhile, unlike the one shown in FIGS. 16 and 17, the electronic component package 100G according to another example may be modified into a shape in which the characteristic shapes of the above-described electronic component packages 100B to 100F are applied. In addition, the manufacturing method of the electronic component package 100G according to another example and the manufacturing method of the above-described electronic component package 100A are performed, except that the plurality of cavities 110X1 and 110X2 are formed and then the electronic components 120 and 122 are respectively disposed therein, and the like. The same, so they will not be described again.

18 is a cross-sectional view schematically showing another example of an electronic component package.

Referring to FIG. 18, in the electronic component package 100H according to another example, the metal layers 111 and 112B may be disposed only on the inner wall of the cavity 110X and the lower surface 110B of the frame 110. Hereinafter, each configuration included in the electronic component package 100H according to another example will be explained in more detail, but the description overlapping with the above description will not be described again, and the difference between the two will be mainly explained.

In some cases, as in the electronic component package 100H according to another example, the metal layer 112A may not be disposed on the upper surface 110A of the frame 110. However, the heat radiation effect and the electromagnetic wave shielding effect can be sufficiently obtained only when the metal layers 111 and 112B are disposed on the inner wall of the cavity 110X and the lower surface 110B of the frame 110.

Meanwhile, unlike the one shown in FIG. 18, the electronic component package 100H according to another example may be modified into a shape in which the characteristic shapes of the above-described electronic component packages 100B to 100G are applied. In addition, since the metal element package 112A is not formed on the upper surface 110A of the frame 110 or the like, the manufacturing method of the electronic component package 100H according to another example is the same as the above-described manufacturing method of the electronic component package 100A, and thus the description thereof will not be repeated. .

19 is a cross-sectional view schematically showing another example of an electronic component package.

Referring to FIG. 19, an electronic component package 100I according to another example may further include a metal layer 158 disposed on the encapsulant 150. Hereinafter, each configuration included in the electronic component package 100I according to another example will be explained in more detail, but the description overlapping with the above description will not be described again, and the difference between the two will be mainly explained.

In the case where the electronic component package 100I has the metal layer 158, the heat radiation characteristics and the electromagnetic wave shielding characteristics can be further improved. Any conductive material may be used as the material for forming the metal layer 158, and there is no particular limitation thereto. Similarly, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), alloys thereof, or the like can be used as the conductive material, but conductive The material is not limited to this.

Meanwhile, unlike the one shown in FIG. 19, the electronic component package 100I according to another example may be modified into a shape in which the above-described electronic component packages 100B to 100H are applied in a unique shape. In addition, since the manufacturing method of the electronic component package 100I according to another example is the same as the manufacturing method of the above-described electronic component package 100A except that the metal layer 158 or the like is formed on the encapsulant 150, the description thereof will not be repeated.

20 is a cross-sectional view schematically showing another example of an electronic component package.

Referring to FIG. 20, in an electronic component package 100J according to another example, the redistribution layers 130 and 140 may be composed of a plurality of layers. Hereinafter, each configuration included in the electronic component package 100J according to another example will be explained in more detail, but the description overlapping with the above description will not be repeated, and the differences between the two will be mainly explained.

Depending on the type of electronic component, the redistribution layers 130 and 140 may be composed of a plurality of layers, and unlike the one shown in FIG. 20, the redistribution layers 130 and 140 may be composed of two or more layers. The redistribution layers 130 and 140 may include insulating layers 131 and 141, conductive patterns 132 and 142, and conductive vias 133, respectively. Since the description of the redistribution layers 130 and 140 is the same as described above, it will not be described again.

Meanwhile, unlike the one shown in FIG. 20, the electronic component package 100J according to another example may be modified into a shape in which the above-described electronic component packages 100B to 100I are applied in a unique shape. In addition, since the redistribution layers 130 and 140 are constituted by the plurality of layers or the like, the manufacturing method of the electronic component package 100J according to another example is the same as the manufacturing method of the above-described electronic component package 100A, and therefore is not Narration.

21 is a cross-sectional view schematically showing another example of an electronic component package.

Referring to FIG. 21, in an electronic component package 100K according to another example, certain conductive patterns 132 and 142 included in the redistribution layers 130 and 140 may be disposed to be substantially based on the area of a plane occupied by the electronic component 120. The lower area of the electronic component 120 is primarily covered.

Hereinafter, each configuration included in the electronic component package 100K according to another example will be explained in more detail, but the description overlapping with the above description will not be described again, and the difference between the two will be mainly explained.

Certain conductive patterns 132 and 142 disposed to substantially cover the lower region of electronic component 120 based on the area of the plane occupied by electronic component 120 may be a ground (GND) pattern or a dummy pattern. However, in any case, since all surfaces of the electronic component 120 are surrounded by the conductive component, electromagnetic waves can be effectively shielded.

Meanwhile, unlike the one shown in FIG. 21, the electronic component package 100K according to another example may be modified into a shape in which the above-described electronic component packages 100B to 100J are applied in a unique shape. In addition, since some of the conductive patterns 132 and 142 included in the redistribution layers 130 and 140 are disposed to substantially cover the entire lower region of the electronic component 120 based on the area of the plane occupied by the electronic component 120, The manufacturing method of the electronic component package 100K of an example is the same as the manufacturing method of the above-described electronic component package 100A, and therefore will not be described again.

Figure 22 shows the results of thermal radiation simulation of various electronic component packages.

23 is a diagram showing the temperature-cross-sectional distribution of the electronic component package shown in FIG.

The basic model is a case in which the electronic component is only encapsulated with an encapsulant, and Case 1 is a case in which the frame is introduced, but the metal layer is placed on the upper surface and the lower surface of the frame, and Case 2 is where the metal layer is also placed in the cavity. The case on the inner wall, and case 3 is the case where the thickness of the metal layer disposed on the upper and lower surfaces of the frame is increased from 10 micrometers to 30 micrometers. As shown in FIG. 22, it can be understood that the heat radiation effect can be further enhanced in the direction from the basic model toward the case 3. That is, it can be understood that heat can be more easily diffused. Further, it is understood that the heat radiation effect can be excellent particularly in the case where the thickness of the metal layer is 30 μm or more.

As described above, according to an exemplary embodiment of the present invention, an electronic component package capable of solving various problems caused by heat generation and electromagnetic interference, and a method of manufacturing the same can be provided to efficiently manufacture an electronic component package.

Also, in the present invention, the term "connected to" includes one element that is not only directly connected to another element, but also indirectly connected to another element by an adhesive or the like. Also, the term "electrical connection" includes both the case where one element is physically connected to another element and the case where none of the elements are physically connected to the other element. Meanwhile, in the present invention, the terms "first", "second", and the like are used to distinguish the respective elements, and do not limit the order, importance, and the like of the corresponding elements. In some cases, a first element may be referred to as a second element, and a second element may be similarly referred to as a first element, without departing from the scope of the invention.

Also, the term "example" as used in the present invention is not intended to mean the same example, but is provided to emphasize and clarify different unit features. However, the examples presented above may also be combined with features of another example. For example, even if the specific details set forth in one particular example are not set forth in another example, it may be understood as being related to another example, unless otherwise stated.

Also, the terms used in the present invention are used for illustration only and are not intended to limit the invention. Here, the singular forms also include the plural unless the context clearly dictates otherwise.

While the exemplary embodiments have been shown and described, it will be understood by those skilled in the art that various modifications and variations can be made without departing from the scope of the invention as defined by the appended claims.

100‧‧‧Electronic component packaging/packaging
100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K‧‧‧ Electronic component packaging/packaging
110‧‧‧Frame
110A‧‧‧Upper surface
110B‧‧‧ lower surface
110X‧‧‧cavity
110X1‧‧‧ cavity
110X2‧‧‧ cavity
111‧‧‧First metal layer/metal layer
112A‧‧‧ Third metal layer/metal layer/conductive pattern
112B‧‧‧Second metal/metal layer
113‧‧‧ penetration wiring
120‧‧‧Electronic components/integrated circuits
120P‧‧‧electrode pad
122‧‧‧Electronic components
122P‧‧‧electrode pad
124‧‧‧Electronic components/passive components
130‧‧‧ redistribution layer
131‧‧‧Insulation
132‧‧‧ conductive pattern
133‧‧‧Electrical path
140‧‧‧ redistribution layer
141‧‧‧Insulation
142‧‧‧ conductive pattern
150‧‧‧encapsulating agent
151‧‧‧ openings
152‧‧‧Outer edge conductive pattern / conductive pattern
153‧‧‧Outer edge conductive path
158‧‧‧metal layer
160‧‧‧External layer
161‧‧‧ openings
165‧‧‧External connection terminal
170‧‧‧ Coverage
171‧‧‧ openings
175‧‧‧External connection terminal
1000‧‧‧Electronic devices
1010‧‧‧ motherboard
1020‧‧‧ wafer related components
1030‧‧‧Network related components
1040‧‧‧Other components
1050‧‧‧ camera
1060‧‧‧Antenna
1070‧‧‧ display
1080‧‧‧Battery
1090‧‧‧Signal line
1100‧‧‧Smart Phone
1101‧‧‧ Subject
1110‧‧‧ motherboard
1120‧‧‧Electronic components
1130‧‧‧ camera
I-I'‧‧‧ line
II-II'‧‧‧ line
Line III-III'‧‧‧
IV-IV'‧‧‧ line
V-V'‧‧‧ line
VI-VI'‧‧‧ line
VII-VII'‧‧‧ line

The above and other aspects, features, and advantages of the present invention will become more apparent from the written description of the appended claims. FIG. 2 schematically illustrates an example of an electronic component package applied to an electronic device. FIG. 3 is a cross-sectional view schematically showing an example of an electronic component package. Fig. 4 is a schematic cross-sectional plan view of the electronic component package taken along line I-I' shown in Fig. 3. 5A to 5E illustrate an example of a schematic manufacturing process of the electronic component package shown in FIG. FIG. 6 is a cross-sectional view schematically showing another example of an electronic component package. Fig. 7 is a schematic cross-sectional plan view of the electronic component package taken along line II-II' shown in Fig. 6. FIG. 8 is a cross-sectional view schematically showing another example of the electronic component package. Figure 9 is a schematic cross-sectional plan view of the electronic component package taken along line III-III' shown in Figure 8. FIG. 10 is a cross-sectional view schematically showing another example of an electronic component package. Figure 11 is a schematic cross-sectional plan view of the electronic component package taken along line IV-IV' shown in Figure 10 . Fig. 12 is a cross-sectional view schematically showing another example of the electronic component package. Figure 13 is a schematic cross-sectional plan view of the electronic component package taken along line V-V' shown in Figure 12 . FIG. 14 is a cross-sectional view schematically showing another example of an electronic component package. Figure 15 is a schematic cross-sectional plan view of the electronic component package taken along line VI-VI' shown in Figure 14. Fig. 16 is a cross-sectional view schematically showing another example of the electronic component package. Figure 17 is a schematic cross-sectional plan view of the electronic component package taken along line VII-VII' shown in Figure 16 . 18 is a cross-sectional view schematically showing another example of an electronic component package. 19 is a cross-sectional view schematically showing another example of an electronic component package. 20 is a cross-sectional view schematically showing another example of an electronic component package. 21 is a cross-sectional view schematically showing another example of an electronic component package. Figure 22 shows the results of thermal radiation simulation of various electronic component packages. 23 is a diagram showing the temperature-cross-sectional distribution of the electronic component package shown in FIG.

100A‧‧‧Electronic component packaging/packaging

110‧‧‧Frame

110A‧‧‧Upper surface

110B‧‧‧ lower surface

110X‧‧‧cavity

111‧‧‧First metal layer/metal layer

112A‧‧‧ Third metal layer/metal layer/conductive pattern

112B‧‧‧Second metal/metal layer

120‧‧‧Electronic components/integrated circuits

120P‧‧‧electrode pad

130‧‧‧ redistribution layer

131‧‧‧Insulation

132‧‧‧ conductive pattern

133‧‧‧Electrical path

150‧‧‧encapsulating agent

160‧‧‧External layer

161‧‧‧ openings

165‧‧‧External connection terminal

I-I’‧‧‧ line

Claims (16)

An electronic component package comprising: a frame having a cavity; an electronic component disposed in the cavity of the frame; a first metal layer disposed on an inner wall of the cavity of the frame; And encapsulating at least a portion of the electronic component; and a redistribution layer disposed under the frame and the electronic component. The electronic component package of claim 1, wherein the first metal layer surrounds a side surface of the electronic component. The electronic component package of claim 2, wherein the first metal layer completely covers the inner wall of the cavity of the frame. The electronic component package of claim 1, further comprising a second metal layer disposed on a lower surface of the frame. The electronic component package of claim 4, wherein the second metal layer is connected to the first metal layer. The electronic component package of claim 4, wherein the second metal layer completely covers the lower surface of the frame. The electronic component package of claim 4, further comprising a third metal layer disposed on the upper surface of the frame. The electronic component package of claim 7, wherein the third metal layer is connected to the first metal layer. The electronic component package of claim 7, wherein the third metal layer completely covers the upper surface of the frame. The electronic component package of claim 7, wherein the second metal layer and the third metal layer are redistribution patterns or dummy patterns. The electronic component package of claim 10, further comprising a penetration wiring penetrating the frame. The electronic component package of claim 1, further comprising: an outer layer disposed under the redistribution layer and having an opening; and an external connection terminal disposed in the opening, wherein at least one external connection The terminals are placed in the fan-out area. The electronic component package of claim 1, wherein the encapsulant fills a space in the cavity of the frame while covering an upper portion of the frame and an upper portion of the electronic component. The electronic component package of claim 13, wherein the encapsulant surrounds an outer side surface of the frame, and the frame is not exposed to the outside. A method of manufacturing an electronic component package, the method comprising: preparing a frame having a cavity; forming a first metal layer on an inner wall of the cavity of the frame; and placing the electronic component on the frame Forming an encapsulating agent that encapsulates at least a portion of the electronic component; and forming a redistribution layer beneath the frame and the electronic component. The method of claim 15, further comprising: forming a second metal layer on a lower surface of the frame; and forming a third metal layer on an upper surface of the frame, wherein the first to The third metal layer is formed simultaneously.