TWI655726B - Fan-out semiconductor package - Google Patents

Fan-out semiconductor package Download PDF

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Publication number
TWI655726B
TWI655726B TW107116224A TW107116224A TWI655726B TW I655726 B TWI655726 B TW I655726B TW 107116224 A TW107116224 A TW 107116224A TW 107116224 A TW107116224 A TW 107116224A TW I655726 B TWI655726 B TW I655726B
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TW
Taiwan
Prior art keywords
fan
layer
semiconductor package
hole
semiconductor wafer
Prior art date
Application number
TW107116224A
Other languages
Chinese (zh)
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TW201830617A (en
Inventor
李文熙
鄭注奐
鄭栗敎
Original Assignee
南韓商三星電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to ??10-2016-0049830 priority Critical
Priority to KR20160049830 priority
Priority to ??10-2016-0117321 priority
Priority to KR1020160117321A priority patent/KR20170121666A/en
Priority to ??10-2016-0166951 priority
Priority to KR1020160166951A priority patent/KR102016492B1/en
Application filed by 南韓商三星電機股份有限公司 filed Critical 南韓商三星電機股份有限公司
Publication of TW201830617A publication Critical patent/TW201830617A/en
Application granted granted Critical
Publication of TWI655726B publication Critical patent/TWI655726B/en

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

A fan-out type semiconductor package includes: a first connection member having a through hole; a semiconductor chip disposed in the through hole of the first connection member and having an active surface on which a connection pad is placed and a non-active opposite to the active surface A surface; an encapsulation body that encapsulates at least a portion of the first connection member and the inactive surface of the semiconductor wafer; a pattern layer that is disposed on the encapsulation body and covers at least at least the encapsulation body adjacent to the inactive surface of the semiconductor wafer Part; a through hole, which penetrates the encapsulation body and connects the pattern layer and the non-active surface of the semiconductor wafer to each other; and a second connection member, which is disposed on the first connection member and the active surface of the semiconductor wafer and includes an electrical connection to The redistribution layer of the connection pad of the semiconductor wafer.

Description

Fan-out semiconductor package

[Cross reference to related applications]

This application claims Korean Patent Application No. 10-2016-0049830 filed with the Korea Intellectual Property Office on April 25, 2016, 10-2016-0117321 filed on September 12, 2016, and December 8, 2016 The priority rights and interests of No. 10-2016-0166951 filed in Japan, the entire disclosure content of the above application is hereby incorporated by reference.

The present invention relates to a semiconductor package, and more specifically, to a fan-out type semiconductor package in which connection terminals may extend outside the area where the semiconductor wafer is placed.

Recently, an important trend in technology development related to semiconductor wafers is to reduce the size of semiconductor wafers. Therefore, in the field of packaging technology, in accordance with the rapid increase in demand for small-sized semiconductor chips or the like, there has been a need for implementation of semiconductor packages having a compact size while containing multiple pins.

One type of packaging technology proposed to meet the technical requirements as described above is a fan-out packaging. Such a fan-out package has a compact size and can allow multiple pins to be implemented by redistributing the connection terminals out of the area where the semiconductor chip is placed.

The aspect of the present invention can provide a fan-out semiconductor package in which the heat generated by the semiconductor chip can be efficiently dissipated by a simple procedure.

According to an aspect of the present invention, a fan-out semiconductor package can be provided in which a pattern layer is formed on an encapsulation body encapsulating a semiconductor chip and connected to a non-active surface of the semiconductor chip through a through hole penetrating the encapsulation body.

According to an aspect of the present invention, the fan-out semiconductor package may include: a first connection member having a through hole; a semiconductor chip disposed in the through hole of the first connection member and having an active surface on which a connection pad is disposed and a The active surface is opposed to the inactive surface; the encapsulation body encapsulates the first connection member and at least part of the inactive surface of the semiconductor wafer; the pattern layer is disposed on the encapsulation body and covers the inactive surface adjacent to the semiconductor wafer At least part of the surface encapsulation body; a through hole that penetrates the encapsulation body and connects the pattern layer and the non-active surface of the semiconductor wafer to each other; and a second connection member that is disposed on the first connection member and the active part of the semiconductor wafer A redistribution layer on the surface and containing connection pads electrically connected to the semiconductor wafer.

Hereinafter, exemplary embodiments in the present invention will be described in detail with reference to the drawings. In the drawings, the shape, size, and the like of components may be enlarged or reduced for clarity.

Herein, the lower side surface, the lower portion, the lower surface, and the like are used to refer to the direction of the cross-section of the drawing toward the mounting surface of the fan-out semiconductor package, and the upper side surface, the upper portion, the upper surface, and the like Used to refer to the opposite direction of the direction. However, for convenience of explanation, these directions are defined, and the scope of patent application is not specifically limited by the directions defined in the above description.

The meaning of "connection" from a component to another component in the description includes indirect connection through an adhesive layer and direct connection between two components. In addition, "electrical connection" is meant to include the concepts of physical connection and physical disconnection. Understandably, when the elements are referred to by "first" and "second", the elements are not limited thereto. The "first" and "second" can only be used for the purpose of distinguishing the element from other elements, and the order or importance of the elements may not be limited. In some cases, the first element may be referred to as the second element without departing from the scope of the patent application scope set forth herein. Similarly, the second element may also be referred to as the first element.

The term "exemplary embodiment" as used herein does not refer to the same exemplary embodiment, and the exemplary embodiment is provided to emphasize specific features or characteristics that are different from those of another exemplary embodiment. However, it is believed that the exemplary embodiments provided herein can be implemented by combining in whole or in part with another exemplary embodiment. For example, an element described in a specific exemplary embodiment can be understood as a description related to another exemplary embodiment even if it is not described in another exemplary embodiment, unless the contrary or contradiction is provided therein description of.

The terminology used herein is used only to describe exemplary embodiments and not to limit the present invention. In this case, unless otherwise interpreted in context, the singular form includes the plural form. Electronic device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, the electronic device 1000 may accommodate a motherboard 1010 therein. The motherboard 1010 may include chip-related components 1020, network-related components 1030, other components 1040, and the like that are physically or electrically connected thereto. These components may be connected to other components to be described below to form various signal lines 1090.

The chip-related components 1020 may include memory chips, such as volatile memory (such as dynamic random access memory (DRAM)) and non-volatile memory (such as read only memory; ROM) )), flash memory or the like; application processor chips, such as a central processing unit (such as a central processing unit (CPU)), a graphics processor (such as a graphics processing unit (GPU) )), digital signal processors, cryptographic processors, microprocessors, microcontrollers or the like; and logic chips, such as analog-to-digital (ADC) converters, integrated circuits for special applications (Application-specific integrated circuit; ASIC) or similar. However, the wafer-related components 1020 are not limited thereto, but may also include other types of wafer-related components. In addition, the wafer-related components 1020 may be combined with each other.

The network-related components 1030 may include agreements such as: wireless fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series or the like), global interoperability Worldwide Interoperability for microwave access (WiMAX) (IEEE 802.16 series or similar), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high-speed packets Access + (high speed packet access +; HSPA+), high speed downlink packet access + (high speed downlink packet access +; HSDPA+), high speed uplink packet access + (high speed uplink packet access +; HSUPA+) , Enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general package radio service (general package radio service; GPRS), code division multiplex access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G agreement , 4G agreement, 5G agreement and any other wireless and wired agreements specified after the above agreement. However, the network-related components 1030 are not limited thereto, but may also include various other wireless or wired standards or protocols. In addition, the network related components 1030 may be combined with each other together with the chip related components 1020 described above.

Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC), electromagnetic interference (EMI) filtering Device, multilayer ceramic capacitor (MLCC) or the like. However, other components 1040 are not limited thereto, but may also include passive components used for various other purposes or the like. In addition, together with the chip-related components 1020 or the network-related components 1030 described above, other components 1040 may be combined with each other.

Depending on the type of electronic device 1000, electronic device 1000 may include other components that may or may not be physically or electrically connected to motherboard 1010. These other components may include, for example, camera module 1050, antenna 1060, display device 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (Not shown in the figure), compass (not shown in the figure), accelerometer (not shown in the figure), gyroscope (not shown in the figure), speaker (not shown in the figure), mass storage unit (For example, a hard disk drive) (not shown in the figure), a compact disk (CD) machine (not shown in the figure), a digital versatile disk (DVD) machine (not shown in the figure) ) Or similar. However, these other components are not limited thereto, but may also include other components used for various purposes or the like depending on the type of the electronic device 1000.

The electronic device 1000 may be a smart phone, personal digital assistant (PDA), digital video camera, digital still camera, network system, computer, monitor, tablet PC, laptop PC, mini-notebook PC, TVs, video game consoles, smart watches, car components or the like. However, the electronic device 1000 is not limited thereto, and may be any other electronic device that processes data.

2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, semiconductor packages may be used in various electronic devices 1000 as described above for various purposes. For example, the motherboard 1110 can be accommodated in the body 1101 of the smartphone 1100, and various electronic components 1120 can be physically or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically or electrically connected to the main board 1110 (such as the camera module 1130) may be accommodated in the body 1101. Some of the electronic components 1120 may be chip related components, and the semiconductor package 100 may be, for example, an application processor between chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above. Semiconductor packaging

Generally, a large number of fine circuits are integrated in semiconductor chips. However, the semiconductor wafer itself may not serve as a completed semiconductor product, and may be damaged due to external physical or chemical influence. Therefore, the semiconductor wafer cannot be used alone, but can be packaged and used in an electronic device or the like in a packaged state.

Here, a semiconductor package is required due to a difference in circuit width in terms of electrical connection between the semiconductor wafer and the main board of the electronic device. In detail, the size of the connection pads of the semiconductor chip and the spacing between the connection pads of the semiconductor chip are extremely fine, but the size of the component mounting pads of the motherboard and the spacing between the component mounting pads of the motherboard used in the electronic device are significantly larger than that of the semiconductor The size of the connection pads of the wafer and the spacing between the connection pads of the semiconductor wafer. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and a packaging technology for buffering the difference in circuit width between the semiconductor chip and the main board is required.

Semiconductor packages manufactured by packaging technology may be classified as fan-in semiconductor packages or fan-out semiconductor packages depending on the structure and purpose.

The fan-in type semiconductor package and the fan-out type semiconductor package will be described in more detail below with reference to the drawings. Fan-in semiconductor package

3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged.

4 is a schematic cross-sectional view illustrating a packaging procedure of a fan-in semiconductor package.

Referring to the drawings, the semiconductor wafer 2220 may be, for example, an integrated circuit (IC) in a bare state, including: a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs) or The like; the connection pad 2222, which is formed on one surface of the body 2221 and contains a conductive material, such as aluminum (Al) or the like; and the passivation layer 2223, such as an oxide film, a nitride film, or the like, It is formed on one surface of the body 2221 and covers at least part of the connection pad 2222. In this case, since the connection pad 2222 is extremely small, it is difficult to mount an integrated circuit (IC) on an intermediate-level printed circuit board (PCB) and a motherboard of an electronic device or the like.

Therefore, the connection member 2240 may be formed depending on the size of the semiconductor wafer 2220 on the semiconductor wafer 2220 so as to redistribute the connection pad 2222. An insulating layer 2241 can be formed on the semiconductor wafer 2220 by using an insulating material such as photoimagable dielectric (PID) resin, a via hole 2243h opening the connection pad 2222, and then forming a wiring pattern 2242 and a via hole 2243 To form the connecting member 2240. Next, a passivation layer 2250 protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an under bump metal layer 2260 or the like may be formed. That is, the fan-in semiconductor package 2200 including, for example, the semiconductor wafer 2220, the connection member 2240, the passivation layer 2250, and the under-bump metal layer 2260 can be manufactured through a series of procedures.

As described above, the fan-in semiconductor package may have a package form in which all connection pads of the semiconductor wafer (such as input/output (I/O) terminals) are arranged inside the semiconductor wafer, and may have excellent Electrical characteristics, and can be produced at low cost. Therefore, many components mounted in smart phones have been manufactured in the form of fan-in semiconductor packages. In detail, many components installed in smart phones have been developed to implement fast signal transmission while having a compact size.

However, since all I/O terminals need to be placed inside the semiconductor wafer in the fan-in type semiconductor package, the fan-in type semiconductor package has a large space limitation. Therefore, it is difficult to apply this structure to a semiconductor wafer having a large number of I/O terminals or a semiconductor wafer having a compact size. In addition, due to the disadvantages described above, it is not possible to directly install and use a fan-in semiconductor package on the motherboard of an electronic device. The reason is that even in the case of increasing the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip through the redistribution procedure, the size of the I/O terminals of the semiconductor chip and the I of the semiconductor chip The spacing between the /O terminals cannot be sufficient to directly mount the fan-in semiconductor package on the motherboard of the electronic device.

FIG. 5 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device.

6 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device.

Referring to the drawings, in the fan-in semiconductor package 2200, the connection pads 2222 (that is, I/O terminals) of the semiconductor chip 2220 can be redistributed via the interposer substrate 2301, and the fan-in semiconductor package 2200 can be mounted on The plug-in board 2301 is finally mounted on the main board 2500 of the electronic device. In this case, the solder balls 2270 and the like can be fixed by the underfill resin 2280 or the like, and the outside of the semiconductor wafer 2220 can be covered by the molding material 2290 or the like. Alternatively, the fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, and the connection pad 2222 (that is, the I/O terminal) of the semiconductor chip 2220 may be embedded in the interposer substrate 2302 in the fan-in semiconductor package 2200 In the state of being redistributed by the interposer substrate 2302, and the fan-in semiconductor package 2200 can be finally installed on the motherboard 2500 of the electronic device.

As described above, it may be difficult to directly install and use a fan-in semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package can be mounted on a separate plug-in substrate through the packaging procedure and then mounted on the main board of the electronic device; or it can be on the main board of the electronic device with the fan-in semiconductor embedded in the plug-in substrate It is installed and used. Fan-out semiconductor package

7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 2100, for example, the outer side of the semiconductor chip 2120 can be protected by the encapsulant 2130, and the connection pads 2122 of the semiconductor chip 2120 can be redistributed outside the semiconductor chip 2120 by the connection member 2140. In this case, the passivation layer 2150 may be further formed on the connection member 2140, and the under bump metal layer 2160 may be further formed in the opening of the passivation layer 2150. Solder balls 2170 may be further formed on the under bump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC), including a body 2121, a connection pad 2122, a passivation layer (not shown in the figure), and the like. The connection member 2140 may include: an insulating layer 2141; a redistribution layer 2142 formed on the insulating layer 2141; and a through hole 2143 that electrically connects the connection pad 2122 and the redistribution layer 2142 to each other.

As described above, the fan-out type semiconductor package may have a form in which the I/O terminals of the semiconductor wafer are redistributed and arranged outside the semiconductor wafer via the connection member formed on the semiconductor wafer. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor wafer need to be placed inside the semiconductor wafer. Therefore, when the size of the semiconductor wafer is reduced, the size and pitch of the balls need to be reduced, so that the standardized ball layout may not be used in a fan-in type semiconductor package. On the other hand, the fan-out type semiconductor package may have a form in which the I/O terminals of the semiconductor wafer are redistributed and arranged outside the semiconductor wafer via the connection member formed on the semiconductor wafer, as described above. Therefore, even in the case where the size of the semiconductor wafer is reduced, the standardized ball layout can be used as it is in the fan-out semiconductor package, so that the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate insert Type substrate, as described below.

8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device.

Referring to the drawings, the fan-out semiconductor package 2100 may be mounted on the motherboard 2500 of the electronic device via solder balls 2170 or the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor wafer 2120 and capable of redistributing the connection pad 2122 to a fan-out area that exceeds the size range of the semiconductor wafer 2120 to The standardized ball layout can be used as it is in the fan-out semiconductor package 2100. Therefore, the fan-out semiconductor package 2100 can be mounted on the main board 2500 of the electronic device without using a separate plug-in substrate or the like.

As described above, since the fan-out semiconductor package can be mounted on the main board of the electronic device without using a separate plug-in substrate, the fan-out semiconductor package can be implemented with a thickness smaller than that of the fan-in semiconductor package using the plug-in substrate Out-type semiconductor package. Therefore, the fan-out semiconductor package can be miniaturized and thinned. In addition, fan-out semiconductor packages have excellent thermal and electrical characteristics, making them particularly suitable for mobile products. Therefore, the printed circuit board (PCB) can be used to implement the fan-out semiconductor package in a more compact form than the general package-on-package (POP) type, and the fan-out semiconductor package can solve the attribution Due to the problem of bending phenomenon.

Meanwhile, the fan-out type semiconductor package refers to a packaging technology used to mount a semiconductor chip on a motherboard of an electronic device or the like as described above and protect the semiconductor chip from external influences, and is a device such as an interposer substrate or the like The concept of a similar printed circuit board (PCB) is different. The PCB has a different scale, purpose, and the like from a fan-out type semiconductor package, and a fan-in type semiconductor package is embedded.

A fan-out type semiconductor package that can effectively dissipate heat generated by a semiconductor wafer will be described below with reference to the drawings.

9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package.

FIG. 10 is a schematic plan view taken along line II′ of the fan-out semiconductor package of FIG. 9.

Referring to the drawings, the fan-out type semiconductor package 100A according to an exemplary embodiment in the present invention may include: a first connection member 110 having a through hole 110H; a semiconductor chip 120 disposed in the through hole 110H of the first connection member 110 And has an active surface on which the connection pad 122 is disposed and an inactive surface opposite to the active surface; an encapsulation body 130 that encapsulates at least part of the inactive surface of the first connection member 110 and the semiconductor chip 120; the second The connection member 140, which is disposed on the active surface of the first connection member 110 and the semiconductor wafer 120; the passivation layer 150, which is disposed on the second connection member 140; and the under bump metal layer 160, which is formed in the opening of the passivation layer 150 151; and the connection terminal 170, which is formed on the under bump metal layer 160. The pattern layer 132 covering at least part of the encapsulation body 130 adjacent to the inactive surface of the semiconductor chip 120 may be disposed on the encapsulation body 130 and may be connected to the semiconductor chip 120 through the through hole 133 penetrating the encapsulation body 130 Non-active surface. The heat generated by the semiconductor wafer 120 (indicated by the arrow) can be easily dissipated outward through the via hole 133 and the pattern layer 132.

A general fan-out type semiconductor package has a simple molding of a semiconductor chip using an encapsulation body such as an epoxy molding compound (EMC) or the like, and a method such as the above-mentioned epoxy molding compound (EMC) or The encapsulation of its analogous surrounds the structure of the semiconductor wafer. In this case, most of the heat generated by the semiconductor wafer is released downward along the redistribution layer, and only a very small amount of heat is conducted to the encapsulation body with low thermal conductivity to deteriorate the heat dissipation characteristics.

On the other hand, the pattern layer 132 in the fan-out semiconductor package 100A as in the exemplary embodiment is connected to the inactive surface of the semiconductor wafer 120 and the through hole 133 is disposed at a position adjacent to the inactive surface of the semiconductor wafer 120 In the case of, the heat generated by the semiconductor wafer 120 (indicated by the arrow) can be easily dissipated, so that the heat dissipation characteristics can be improved. In addition, the pattern layer 132 may solve electromagnetic interference (EMI).

Meanwhile, since the inactive surface of the semiconductor package 120 is connected to the pattern layer 132 via the via 133, in the case where the fan-out semiconductor package 100A includes a plurality of semiconductor chips 120, the via 133 can only be selectively connected to generate a large amount of heat Some of the semiconductor wafers 120 may only be concentratedly formed in the semiconductor wafers 120 that generate a large amount of heat therebetween. In addition, the through hole 133 and the pattern layer 132 can be simultaneously formed using the same material and integrated with each other, and there is no boundary therebetween. Therefore, the procedure for forming the via 133 and the pattern layer 132 can be simple, and the reliability of the connection between the via 133 and the pattern layer 132 can be excellent.

The respective components included in the fan-out semiconductor package 100A according to the exemplary embodiment will be described in more detail below.

The first connection member 110 may depend on certain materials to maintain the rigidity of the fan-out semiconductor package 100A and to ensure the uniformity of the thickness of the encapsulation body 130. The first connection member 110 may have a through hole 110H. The through hole 110H may allow the semiconductor wafer 120 disposed therein to be spaced apart from the first connection member 110 by a predetermined distance. The side surface of the semiconductor wafer 120 may be surrounded by the first connection member 110. However, this form is only an example, and may have other forms through various modifications, and the fan-out semiconductor package 100A may perform another function depending on this form.

The first connection member 110 may include an insulating layer 111. The material of the insulating layer 111 is not particularly limited. For example, an insulating material can be used as the material of the insulating layer 111. In this case, the insulating material may be a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide resin), a thermosetting resin or a thermoplastic resin and an inorganic filler impregnated into a glass cloth (or glass fabric, for example) ) In the core material, such as prepreg, Ajinomoto Build up Film (ABF), FR-4, bismaleimide triazine (BT) or similar.

The semiconductor chip 120 may be an integrated circuit (IC) provided in an amount of hundreds to millions of elements or more integrated in a single chip. The IC may be, for example, an application processor chip such as a central processing unit (eg, CPU), graphics processor (eg, GPU), digital signal processor, cryptographic processor, microprocessor, microcontroller, or Similar, but not limited to this.

The semiconductor wafer 120 may be formed based on the active wafer. In this case, the base material of the body 121 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits can be formed on the body 121. The connection pad 122 can electrically connect the semiconductor chip 120 to other components. The material of the connection pad 122 may be a conductive material, such as aluminum (Al) or the like. A passivation layer 123 exposing the connection pad 122 may be formed on the body 121, and the passivation layer 123 may be an oxide film, a nitride film, or the like; or may be a double layer of an oxide layer and a nitride layer. The lower surface of the connection pad 122 may have a step through the passivation layer 123 relative to the lower surface of the encapsulation body 130. Therefore, the migration of the encapsulation body 130 can be improved. The insulating layer (not shown in the figure) and the like can be further arranged in other desired positions.

The encapsulation body 130 can protect the first connection member 110 and/or the semiconductor chip 120. The encapsulation form of the encapsulation body 130 is not particularly limited, but may be a form in which the encapsulation body 130 surrounds at least part of the first connection member 110 and/or the semiconductor wafer 120. For example, the encapsulation body 130 may cover the inactive surface of the first connection member 110 and the semiconductor wafer 120 and fill the space between the wall of the through hole 110H and the side surface of the semiconductor wafer 120. In addition, the encapsulation body 130 may also fill at least part of the space between the passivation layer 123 of the semiconductor wafer 120 and the second connection member 140. At the same time, the encapsulation body 130 may fill the through holes 110H, thus acting as an adhesive and reducing the buckling of the semiconductor wafer 120 depending on certain materials.

Certain materials of the encapsulation body 130 are not particularly limited. For example, an insulating material can be used as the material of the encapsulation body 130. In this case, the insulating material may be a material containing an inorganic filler and an insulating resin, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide resin, a resin such as being impregnated in the thermosetting resin and the thermoplastic resin The resin of the reinforcing material of the inorganic filler, such as ABF, FR-4, BT, EMC or the like. As an option, a material in which a thermosetting resin or a thermoplastic resin is impregnated together with an inorganic filler in a core material such as glass fabric can also be used as an insulating material. As an option, photo-imageable dielectric (PID) resin can also be used as the insulating material.

The pattern layer 132 may be formed on the surface of the encapsulation body 130. The pattern layer 132 may be a metal layer containing known conductive materials. For example, the pattern layer 132 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or the like alloy. The pattern layer 132 can be formed together with the through hole 133 by a known plating method. The pattern layer 132 may be a pattern electrically insulated from the connection pad 122 of the semiconductor chip 120, which means a heat dissipation pattern, but is not limited thereto. That is, when the pattern layer 132 is a heat dissipation pattern in the case of performing a ground (GND) function, it may be electrically connected to the connection pad 122 of the semiconductor chip 120 as needed.

The through hole 133 may be formed in a via hole formed in the encapsulation body 130. The via hole may penetrate from one surface of the encapsulation body 130 to the inactive surface of the semiconductor wafer 120. Therefore, the through hole 133 may contact the inactive surface of the semiconductor wafer 120. Depending on the material of the encapsulation 130, the via hole may be a laser drilled via hole or a photo-etched via hole. For example, the via hole may be a laser drilled via hole formed using a known laser drilling method in the case where the encapsulation body 130 is an ABF including an inorganic filler and an insulating resin, and may be an encapsulated When the body 130 includes a photosensitive insulating material, a photoetched via hole is formed by a known photolithography method. The through hole 133 may include conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or Alloy, and can be formed together with the pattern layer 132 by electroplating.

In the case where the pattern layer 132 and the through hole 133 are formed together by an electroplating method, the pattern layer 132 and the through hole 133 may be integrated with each other, and there may be no boundary therebetween. In addition, the pattern layer 132 and the through hole 133 may contain the same conductive material, such as copper (Cu). That is, a separate adhesive material may not be required between the pattern layer 132 and the through hole 133. Therefore, the procedure can be simple, and the heat dissipation member can be implemented to have a lower thickness. In the case where the pattern layer 132 and the through hole 133 are integrated with each other and there is no boundary therebetween to directly contact each other, the heat dissipated through the inactive surface of the semiconductor wafer 120 can be dissipated outward more effectively.

The second connection member 140 may be configured to redistribute the connection pads 122 of the semiconductor chip 120. Dozens to hundreds of connection pads 122 having various functions may be redistributed by the second connection member 140, and may be physically or electrically connected to an external source via connection terminals 170 to be described below depending on the function. The second connection member 140 may include: an insulating layer 141; a redistribution layer 142, which is disposed on the insulating layer 141; and a through hole 143, which penetrates the insulating layer 141 and connects the redistribution layer 142 to each other. In the fan-out semiconductor package 100A according to the exemplary embodiment, the second connection member 140 may include a single layer, but may also include multiple layers.

An insulating material can be used as the material of the insulating layer 141. In this case, a photosensitive insulating material such as photo-imageable dielectric (PID) resin may also be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. In the case where the insulating layer 141 has photosensitive characteristics, the insulating layer 141 may be formed to have a smaller thickness, and the fine pitch of the through holes 143 may be more easily achieved. The insulating layer 141 may be a photosensitive insulating layer containing an insulating resin and an inorganic filler. When the insulating layer 141 is a plurality of layers, the materials of the insulating layer 141 may be the same as each other, and may also be different from each other. When the insulating layer 141 is a plurality of layers, the insulating layers 141 may be integrated with each other depending on procedures, so that the boundary therebetween may not be obvious.

The redistribution layer 142 can be used to redistribute the connection pad 122 substantially. The material of each of the redistribution layers 142 may be a conductive material, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead ( Pb), titanium (Ti) or its alloys. The redistribution layer 142 may perform various functions depending on the design of its corresponding layer. For example, the redistribution layer 142 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, power (PWR) pattern, and the like, such as the data signal pattern and the like. In addition, the redistribution layer 142 may include via pads, connection terminal pads, and the like.

If necessary, a surface treatment layer (not shown in the figure) may be formed on the surface of the exposed redistribution layer 142. For example, the surface treatment layer can be formed by: electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/replacement Gold electroplating, direct immersion gold (DIG) electroplating, hot air solder leveling (HASL) or the like, but not limited thereto.

The through hole 143 may electrically connect the redistribution layer 142, the connection pad 122 or the like formed on different layers to each other, thereby generating an electrical path in the fan-out semiconductor package 100A. The material of each of the through holes 143 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb) , Titanium (Ti) or its alloys. The through hole 143 may also be completely filled with conductive material; or the conductive material may be formed along the wall of the through hole. In addition, the through hole 143 may have all shapes known in the prior art, such as a tapered shape, a cylindrical shape, and the like.

The passivation layer 150 may be additionally configured to protect the second connection member 140 from external physical or chemical damage. The passivation layer 150 may have an opening 151 that exposes at least a portion of the redistribution layer 142 of the second connection member 140. As the material of the passivation layer 150, a material having an elastic modulus greater than that of the insulating layer 141 of the second connection member 140 may be used. For example, ABF, which does not contain glass fiber but contains inorganic filler and insulating resin, can be used as the material of the passivation layer 150. When ABF is used as the material of the passivation layer 150, the weight percentage of the inorganic filler contained in the passivation layer 150 may be greater than the weight percentage of the inorganic filler contained in the insulating layer 141 of the second connection member 140 to improve reliability .

The under bump metal layer 160 may be additionally configured to improve the connection reliability of the connection terminal 170 and improve the board-level reliability of the fan-out semiconductor package 100A. The under-bump metal layer 160 may be connected to the redistribution layer 142 of the second connection member 140 exposed through the opening 151 of the passivation layer 150. The under bump metal layer 160 may be formed in the opening 151 of the passivation layer 150 by a known metallization method using a known conductive metal such as a metal, but is not limited thereto.

The connection terminal 170 may additionally be configured to physically or electrically connect the fan-out semiconductor package 100A. For example, the fan-out semiconductor package 100A can be mounted on the motherboard of the electronic device via the connection terminal 170. Each of the connection terminals 170 may be formed of a conductive material (such as solder or the like). However, this is only an example, and the material of each of the connection terminals 170 is not particularly limited thereto. Each of the connection terminals 170 may be a pad, a ball, a pin, or the like. The connection terminal 170 may be formed in a multi-layer structure or a single-layer structure. When the connection terminal 170 is formed in a multilayer structure, the connection terminal 170 may include copper (Cu) pillars and solder. When the connection terminal 170 is formed in a single-layer structure, the connection terminal 170 may include tin-silver solder or copper (Cu). However, this is only an example, and the connection terminal 170 is not limited to this.

The number, spacing, placement, or the like of the connection terminals 170 are not particularly limited, and can be sufficiently modified by those skilled in the art depending on design details. For example, the connection terminals 170 may be provided in an amount of tens to thousands according to the number of connection pads 122 of the semiconductor chip 120, but is not limited thereto, and may also be tens to thousands or more or tens to thousands The connection terminal 170 is provided in a smaller amount. When the connection terminal 170 is a solder ball, the connection terminal 170 may cover the side surface of the under bump metal layer 160 extending to one surface of the passivation layer 150, and the connection reliability may be better.

At least one of the connection terminals 170 may be disposed in the fan-out area. The fan-out area is an area other than the area where the semiconductor wafer 120 is placed. Compared with fan-in packages, fan-out packages can have excellent reliability, can implement multiple input/output (I/O) terminals, and can facilitate 3D interconnection. In addition, compared to ball grid array (BGA) packages, land grid array (LGA) packages, or the like, fan-out packages can be manufactured with a small thickness and can Price competitive.

11 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

12 is a schematic plan view taken along line II-II' of the fan-out semiconductor package of FIG.

Referring to the drawings, in the fan-out semiconductor package 100B according to another exemplary embodiment, the pattern layer 132 may extend to an area of the encapsulation body 130 covering the first connection member 110. For example, the pattern layer 132 may cover the entire surface of the encapsulation body 130. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

14 is a schematic plan view taken along line III-III' of the fan-out semiconductor package of FIG. 13.

Referring to the drawings, in a fan-out semiconductor package 100C according to another exemplary embodiment of the present invention, the first connection member 110 may further include a metal layer 115 disposed on the wall of the through hole 110H. The metal layer 115 may extend to the upper portion and the lower portion of the insulating layer 111, but is not limited thereto. The heat generated by the semiconductor wafer 120 (indicated by the arrow) may move toward the first connection member 110 and then dissipate above or below the first connection member 110 via the metal layer 115. In addition, electromagnetic waves can be blocked more effectively. The metal layer 115 may also be formed by a known plating method, and may include a known conductive material. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

15 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

16 is a schematic plan view taken along line IV-IV' of the fan-out semiconductor package of FIG.

Referring to the drawings, in the fan-out semiconductor package 100D according to another exemplary embodiment, the metal layer 128 may be disposed on the inactive surface of the semiconductor wafer 120, and the through hole 133 may be connected to the metal layer 128. In addition, the pattern layer 132a and the pattern layer 132b may include a heat dissipation pattern 132a covering at least a portion of the encapsulation body 130 adjacent to the inactive surface of the semiconductor wafer 120, and may include the connection pad 122 of the semiconductor wafer 120 redistributed or the like的wiring pattern 132b. In this case, the heat dissipation pattern 132a and the wiring pattern 132b may be disconnected from each other on the encapsulation body 130. In addition, the first connection member 110 may include a redistribution layer 112a and a redistribution layer 112b disposed on the upper and lower surfaces of the insulating layer 111 to be disconnected from the metal layer 115, and the redistribution layer 112a and the redistribution The layers 112b may be electrically connected to each other by through holes 113 penetrating the insulating layer 111. In addition, the passivation layer 180 covering at least part of the pattern layer 132a and the pattern layer 132b may be disposed on the encapsulation body 130, and the heat dissipation member 190 may be attached to the passivation layer 180. Meanwhile, the heat dissipation member 190 may be directly attached to the passivation layer 180 or may be attached to the passivation layer 180 via the connection member 195 to improve reliability.

The metal layer 128 can be used to more effectively dissipate heat generated by the semiconductor wafer 120 or block electromagnetic waves more effectively, and can be formed on the inactive surface of the semiconductor wafer 120. The metal layer 128 may have a plate shape and may cover the entire inactive surface of the semiconductor wafer 120, but is not limited thereto. The metal layer 128 may also be formed by a known plating method and may include a conductive material such as copper (Cu) or the like. The via 133 may be connected to the metal layer 128 to thereby be connected to the inactive surface of the semiconductor wafer 120.

The heat dissipation pattern 132 a may cover the area where the wiring pattern 132 b is not disposed on the encapsulation body 130. The heat dissipation pattern 132a may have a plate shape, but is not limited thereto. The heat dissipation pattern 132 a may be connected to the metal layer 115 formed in the first connection member 110 via the through hole 133. The heat dissipation pattern 132a and the metal layer 115 may perform a ground (GND) function as needed. In this case, the heat dissipation pattern 132a and the metal layer 115 may be electrically connected to the connection pad of the semiconductor chip 120 via the pattern or via hole for grounding of the redistribution layer formed in the first connection member 110 and the second connection member 140 Connection pad for grounding in 122. That is, the pattern layer 132a and the pattern layer 132b may include ground patterns.

The wiring pattern 132b may be various redistribution patterns for redistribution of the connection pads 122 of the semiconductor wafer 120. When the heat dissipation pattern 132a performs a grounding function, the wiring pattern 132b may include a power pattern and a signal pattern other than the ground pattern. That is, the pattern layer 132a and the pattern layer 132b may include power patterns and signal patterns. The wiring pattern 132 b may be electrically connected to the redistribution layer 112 a and the redistribution layer 112 b of the first connection member 110 and the through hole 113 through the via hole 133. In addition, the wiring pattern 132b may also be electrically connected to the redistribution layer 142 and the through hole 143 of the second connection member 140 via the first connection member 110. The wiring pattern 132b may also be electrically connected to the connection pad 122 of the semiconductor wafer 120 via the path described above. The wiring pattern 132b may also include various pad patterns.

The redistribution layer 112a and the redistribution layer 112b can be used to redistribute the connection pad 122. In the case where the first connection member 110 includes the redistribution layer 112a and the redistribution layer 112b as described above, the number of layers of the second connection member 140 can be reduced, so that design freedom can be improved and it is possible to thin the first Second connection member 140. The redistribution layer 112a and the redistribution layer 112b may perform various functions depending on the design of the corresponding layer. For example, the redistribution layer 112a and the redistribution layer 112b may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, power (PWR) pattern, and the like, such as the data signal pattern and the like. In addition, the redistribution layer 112a and the redistribution layer 112b may include via pads, connection terminal pads, and the like.

The through hole 113 may electrically connect the redistribution layer 112 a and the redistribution layer 112 b formed on different layers to each other. The through hole 113 may be completely filled with conductive material; or the conductive material may be formed along the wall of the through hole 113. In addition, the through hole 113 may have all shapes known in the prior art, such as a cylindrical shape, an hourglass shape, and the like.

The passivation layer 180 may include the same or similar materials as the passivation layer 150 described above. In this case, the bending of the fan-out semiconductor package 100D can be suppressed through the symmetry effect of the passivation layer 150 and the passivation layer 180 disposed on both sides of the fan-out semiconductor package 100D. However, the material of the passivation layer 180 is not limited thereto and may be another material. For example, a prepreg including a core material (such as glass fabric) or the like may be used as the material of the passivation layer 180. Meanwhile, the weight percentage of the inorganic filler contained in the passivation layer 180 may be greater than the weight percentage of the inorganic filler contained in the encapsulation body 130 to suppress bending. The passivation layer 180 may also be attached to the encapsulation body 130 before it is hardened. In this case, pits toward the through holes 110H may be formed due to the movement of the inorganic filler due to hardening.

The heat dissipation member 190 may be a known heat sink. The heat dissipation member 190 can easily dissipate heat dissipated outside the fan-out semiconductor package 100A through the heat dissipation patterns 132a of the pattern layer 132a and the pattern layer 132b. The heat dissipation member 190 may have a plurality of grooves formed in the upper surface thereof to easily dissipate heat. In this case, the surface area can be increased to facilitate heat dissipation. As long as the material of the heat dissipation member 190 has excellent thermal conductivity, it is not particularly limited. For example, the heat dissipation member 190 may include metal. The connection member 195 can easily attach the heat dissipation member 190 to the passivation layer 180, and can prevent an electrical short circuit and efficiently transfer heat as necessary. The material of the connection member 195 may be appropriately selected depending on the material of the heat dissipation member 190.

Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

18 is a schematic plan view taken along line VV' of the fan-out semiconductor package of FIG. 17.

Referring to the drawings, a fan-out semiconductor package 100E according to another exemplary embodiment may include a plurality of through-holes 110Ha, 110Hb, and 110Hc, and may include multiple holes disposed in the plurality of through-holes 110Ha, 110Hb, and 110Hc, respectively. Semiconductor wafer 120, semiconductor wafer 125a, and semiconductor wafer 125b. The semiconductor wafer 125a and the semiconductor wafer 125b that are additionally disposed may be integrated circuits that include the body 123a and the body 123b and the connection pad 124a and the connection pad 124b, which are the same or different from each other. The connection pad 124a of the semiconductor wafer 125a and the connection pad (not shown) of the semiconductor wafer 125b may also be electrically connected to the second connection member 140. If necessary, the through hole 133 may be selectively connected only to certain semiconductor wafers that generate a large amount of heat or may be formed intensively in the semiconductor wafer 120 that generates a large amount of heat therebetween. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

20 is a schematic plan view taken along line VI-VI' of the fan-out semiconductor package of FIG.

Referring to the drawings, a fan-out semiconductor package 100F according to another exemplary embodiment may include a plurality of through-holes 110Ha, 110Hb, and 110Hc, and may include semiconductors disposed in the plurality of through-holes 110Ha, 110Hb, and 110Hc, respectively The chip 120 and the passive device 191 and the passive device 192. The passive component 191 and the passive component 192 may be, for example, capacitors, inductors, or the like that are the same as or different from each other, but are not limited thereto. Meanwhile, the through hole 133 may be selectively formed to be connected only to the semiconductor wafer 120. The surface-mounted passive component 193 may be further disposed on the passivation layer 150 as needed. The surface-mounted passive component 193 may also be, for example, a capacitor, an inductor, or the like, but it is not limited thereto. In some cases, all passive components 191, 192, and 193 may be capacitors and may be connected to the same power wiring line. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

22 is a schematic plan view taken along line VII-VII' of the fan-out semiconductor package of FIG. 21.

Referring to the drawings, a fan-out semiconductor package 100G according to another exemplary embodiment may include a plurality of through-holes 110Ha, 110Hb, and 110Hc, and may include semiconductors disposed in the plurality of through-holes 110Ha, 110Hb, and 110Hc, respectively Wafer 120, semiconductor wafer 125a, and semiconductor wafer 125b. The semiconductor wafer 120, the semiconductor wafer 125a, and the semiconductor wafer 125b may respectively have a metal layer 128, a metal layer 128a, and a metal layer (not shown) disposed on their inactive surfaces, and the via 133 may be connected to the metal layer 128 , A metal layer 128a and a metal layer (not shown in the figure). In addition, the pattern layer 132a and the pattern layer 132b may include a heat dissipation pattern 132a covering at least a portion of the encapsulation 130 adjacent to the inactive surface of each of the semiconductor wafer 120, the semiconductor wafer 125a, and the semiconductor wafer 125b, and may include The wiring patterns 132b of the connection pad 122, the connection pad 124a, and the connection pad (not shown) of the semiconductor wafer 120, the semiconductor wafer 125a, and the semiconductor wafer 125b are redistributed. In addition, the first connection member 110 may include a redistribution layer 112a and a redistribution layer 112b disposed on the upper and lower surfaces of the insulating layer 111 to be disconnected from the metal layer 115, and the redistribution layer 112a and the redistribution The layers 112b may be electrically connected to each other by through holes 113 penetrating the insulating layer 111. In addition, the passivation layer 180 covering at least part of the pattern layer 132a and the pattern layer 132b may be disposed on the encapsulation body 130, and the heat dissipation member 190 may be attached to the passivation layer 180. Meanwhile, the heat dissipation member 190 may be directly attached to the passivation layer 180 or may be attached to the passivation layer 180 via the connection member 195 to improve reliability. Other content overlaps with the content described above, and thus a detailed description thereof is omitted.

23 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out semiconductor package 100H according to another exemplary embodiment of the present invention, the first connection member 110 may include: a first insulating layer 111a that contacts the second connection member 140; the first weight The cloth layer 112a, which contacts the second connection member 140 and is embedded in the first insulating layer 111a; the second redistribution layer 112b, which is disposed to face one surface of the first insulating layer 111a in which the first redistribution layer 112a is embedded On the other surface of the first insulating layer 111a; the second insulating layer 111b, which is disposed on the first insulating layer 111a and covers the second redistribution layer 112b; and the third redistribution layer 112c, which is disposed on the second On the insulating layer 111b. The first redistribution layer 112a, the second redistribution layer 112b, and the third redistribution layer 112c may be electrically connected to the connection pad 122. Meanwhile, the first redistribution layer 112a and the second redistribution layer 112b may be electrically connected to each other through the first through hole 113a penetrating the first insulating layer 111a, and the second redistribution layer 112b and the third redistribution layer 112c may be passed through The second through holes 113b penetrating the second insulating layer 111b are electrically connected to each other.

Since the first redistribution layer 112a is embedded, the insulation distance of the insulation layer 141 of the second connection member 140 may be substantially constant, as described above. Since the first connection member 110 may include a large number of redistribution layers 112a, 112b, and redistribution layers 112c, the second connection member 140 may be simplified. Therefore, the yield reduction situation can be improved depending on defects occurring in the forming process of the second connection member 140. The first redistribution layer 112a may be recessed into the first insulating layer 111a so that there is a step between the lower surface of the first insulating layer 111a and the lower surface of the first redistribution layer 112a. Therefore, when the encapsulation body 130 is formed, the material of the encapsulation body 130 can be prevented from migrating and contaminating the first redistribution layer 112a.

The lower surface of the first redistribution layer 112 a of the first connection member 110 may be disposed at a higher level than the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the first redistribution layer 112a of the first connection member 110 may be greater than the distance between the redistribution layer 142 of the second connection member 140 and the connection pad 122 of the semiconductor chip 120 The distance between. The reason is that the first redistribution layer 112a may be recessed into the insulating layer 111. The second redistribution layer 112b of the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120. The thickness of the first connection member 110 may be formed to correspond to the thickness of the semiconductor wafer 120. Therefore, the second redistribution layer 112b formed in the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120.

The thickness of the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may have a thickness equal to or greater than that of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, and the redistribution layer 112c may be formed to have a larger value depending on the ratio of the first connection member 110 the size of. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed into a relatively small size due to its thinness.

Other content overlaps with the content described above, and thus a detailed description thereof is omitted. Meanwhile, the description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100H.

24 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100I according to another exemplary embodiment, the pattern layer 132 may extend to at least a portion of the area of the encapsulation body 130 covering the first connection member 110. In addition, the pattern layer 132 may be connected to the first connection member 110 through the through hole 133 penetrating the encapsulation body 130 and connected to the first connection member 110. For example, the pattern layer 132 may be connected to the third redistribution layer 112c of the first connection member 110. The redistribution layer of the first connection member 110 electrically connected to the pattern layer 132 may be a ground pattern. That is, the pattern layer 132 may be connected to the ground pattern of the first connection member 110. In this case, the heat can also be dissipated downward through the first connecting member 110, so that the heat dissipation effect can be better. In the drawings, only the first redistribution layer 112a and the third redistribution layer 112c of the first connection member 110 have a ground pattern electrically connected to the pattern layer 132, but in some cases, the first connection member 110 The second redistribution layer 112b may also have a ground pattern electrically connected to the pattern layer 132 through the first through hole 113a. In addition, in some cases, only the third redistribution layer 112c may also have a ground pattern electrically connected to the pattern layer 132.

Other content overlaps with the content described above, and thus a detailed description thereof is omitted. The description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100I.

25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package.

Referring to the drawings, in a fan-out semiconductor package 100J according to another exemplary embodiment of the present invention, the first connection member 110 may include: a first insulating layer 111a; a first redistribution layer 112a and a second redistribution A layer 112b, which is disposed on both surfaces of the first insulating layer 111a; a second insulating layer 111b, which is disposed on the first insulating layer 111a and covers the first redistribution layer 112a; a third redistribution layer 112c, which Disposed on the second insulating layer 111b; the third insulating layer 111c, which is disposed on the first insulating layer 111a and covers the second redistribution layer 112b; and the fourth redistribution layer 112d, which is disposed on the third insulating layer 111c . The first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c, and the fourth redistribution layer 112d may be electrically connected to the connection pad 122. Since the first connection member 110 may include a larger number of redistribution layers 112a, 112b, redistribution layers 112c, and redistribution layers 112d, the second connection member 140 may be further simplified. Therefore, the yield reduction situation can be improved depending on defects occurring in the forming process of the second connection member 140. Meanwhile, the first redistribution layer 112a, the second redistribution layer 112b, the third redistribution layer 112c and the fourth redistribution layer 112d can penetrate the first insulating layer 111a, the second insulating layer 111b and the third insulating layer respectively The first through hole 113a, the second through hole 113b, and the third through hole 113c of 111c are electrically connected to each other.

The thickness of the first insulating layer 111a may be greater than the thickness of the second insulating layer 111b and the thickness of the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to form a larger number of redistribution layers 112c and 112d. The insulating material included in the first insulating layer 111a may be different from the insulating materials of the second insulating layer 111b and the third insulating layer 111c. For example, the first insulating layer 111a may be, for example, a prepreg including a core material, an inorganic filler, and an insulating resin, and the second insulating layer 111b and the third insulating layer 111c may be ABF or include an inorganic filler and Photosensitive insulating film of insulating resin. However, the materials of the first insulating layer 111a and the materials of the second insulating layer 111b and the third insulating layer 111c are not limited thereto.

The lower surface of the third redistribution layer 112c of the first connection member 110 may be disposed at a level below the lower surface of the connection pad 122 of the semiconductor wafer 120. In addition, the distance between the redistribution layer 142 of the second connection member 140 and the third redistribution layer 112c of the first connection member 110 may be smaller than the distance between the redistribution layer 142 of the second connection member 140 and the connection pad 122 of the semiconductor chip 120 The distance between. The reason for this is that the third redistribution layer 112c may be disposed on the second insulating layer 111b in a convex form so as to contact the second connection member 140. The first redistribution layer 112a and the second redistribution layer 112b of the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120. The thickness of the first connection member 110 may be formed to correspond to the thickness of the semiconductor wafer 120. Therefore, the first redistribution layer 112a and the second redistribution layer 112b formed in the first connection member 110 may be disposed at a level between the active surface and the non-active surface of the semiconductor wafer 120.

The thickness of the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d of the first connection member 110 may be greater than the thickness of the redistribution layer 142 of the second connection member 140. Since the thickness of the first connection member 110 may be equal to or greater than the thickness of the semiconductor wafer 120, the redistribution layer 112a, the redistribution layer 112b, the redistribution layer 112c, and the redistribution layer 112d may also be formed to have larger sizes. On the other hand, the redistribution layer 142 of the second connection member 140 may be formed into a relatively small size due to its thinness.

Other content overlaps with the content described above, and thus a detailed description thereof is omitted. Meanwhile, the description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100J.

26 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Referring to the drawings, in the fan-out semiconductor package 100K according to another exemplary embodiment, the pattern layer 132 may extend to at least a portion of the area of the encapsulation body 130 covering the first connection member 110. In addition, the pattern layer 132 may be connected to the first connection member 110 through the through hole 133 penetrating the encapsulation body 130 and connected to the first connection member 110. For example, the pattern layer 132 may be connected to the fourth redistribution layer 112d of the first connection member 110. The redistribution layer of the first connection member 110 electrically connected to the pattern layer 132 may be a ground pattern. That is, the pattern layer 132 may be connected to the ground pattern of the first connection member 110. In this case, the heat can also be dissipated downward through the first connecting member 110, so that the heat dissipation effect can be better. In the drawings, only the second redistribution layer 112b and the fourth redistribution layer 112d of the first connection member 110 have a ground pattern electrically connected to the pattern layer 132, but in some cases, the first connection member 110 The first redistribution layer 112a and/or the third redistribution layer 112c may also have a ground pattern electrically connected to the pattern layer 132 through the first through hole 113a and/or the second through hole 113b. In addition, in some cases, only the fourth redistribution layer 112d may also have a ground pattern electrically connected to the pattern layer 132.

Other content overlaps with the content described above, and thus a detailed description thereof is omitted. The description of the fan-out semiconductor packages 100B to 100G described above can also be applied to the fan-out semiconductor package 100K.

As explained above, according to the exemplary embodiments in the present invention, a fan-out type semiconductor package can be provided in which the heat generated by the semiconductor chip can be efficiently dissipated by a simple procedure.

Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the present invention as defined by the scope of the appended patent application.

100‧‧‧Semiconductor packaging

100A, 100B, 100C, 100D, 100E, 100F, 100G, 100H, 100I, 100J, 100K

110‧‧‧First connecting member

110H, 110Ha, 110Hb, 110Hc

111‧‧‧Insulation

111a‧‧‧First insulation layer

111b‧‧‧Second insulation layer

111c‧‧‧The third insulating layer

112a‧‧‧The first layer of cloth

112b‧‧‧The second layer

112c‧‧‧The third layer of cloth

112d‧‧‧The fourth layer

113‧‧‧Through hole

113a‧‧‧First through hole

113b‧‧‧Second through hole

113c‧‧‧th through hole

115, 128, 128a ‧‧‧ metal layer

120, 125a, 125b ‧‧‧ semiconductor chip

121, 123a, 123b

122, 124a, 124b ‧‧‧ connection pad

123‧‧‧passivation layer

130‧‧‧Encapsulated body

131, 133‧‧‧through hole

132‧‧‧pattern layer

132a‧‧‧pattern layer/heat dissipation pattern

132b‧‧‧pattern layer/wiring pattern

140‧‧‧Second connecting member

141‧‧‧Insulation

142‧‧‧ heavy cloth layer

143‧‧‧Through hole

150, 180‧‧‧ Passivation layer

151‧‧‧ opening

160‧‧‧ under bump metal layer

170‧‧‧Connecting terminal

190‧‧‧radiating component

191,192‧‧‧Passive components

193‧‧‧Surface-mounted passive components

195‧‧‧Connecting member

1000‧‧‧Electronic device

1010‧‧‧Motherboard

1020‧‧‧chip related components

1030‧‧‧Network-related components

1040‧‧‧Other components

1050、1130‧‧‧Camera module

1060‧‧‧ Antenna

1070‧‧‧Display device

1080‧‧‧Battery

1090‧‧‧Signal cable

1100‧‧‧Smartphone

1101‧‧‧Body

1110‧‧‧ Motherboard

1120‧‧‧Electronic components

2100‧‧‧Fan-out semiconductor package

2120‧‧‧Semiconductor chip

2121‧‧‧Body

2122‧‧‧ connection pad

2130‧‧‧Encapsulated body

2140‧‧‧Connecting member

2141‧‧‧Insulation

2142‧‧‧ heavy cloth layer

2143‧‧‧Through hole

2150‧‧‧passivation layer

2160‧‧‧ under bump metal layer

2170‧‧‧solder ball

2200‧‧‧Fan-in semiconductor package

2220‧‧‧Semiconductor chip

2221‧‧‧Body

2222‧‧‧ connection pad

2223‧‧‧passivation layer

2240‧‧‧Connecting member

2241‧‧‧Insulation

2242‧‧‧Wiring pattern

2243‧‧‧Through hole

2243h‧‧‧via hole

2250‧‧‧passivation layer

2251‧‧‧ opening

2260‧‧‧ under bump metal layer

2270‧‧‧solder ball

2280‧‧‧Bottom filling resin

2290‧‧‧Molding material

2301‧‧‧Plug-in board

2302‧‧‧Separate plug-in board

2500‧‧‧ Motherboard

I-I’, II-II’, III-III’, IV-IV’, V-V’, VI-VI’, VII-VII’‧‧‧ line

The above and other aspects, features, and advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the drawings, wherein: FIG. 1 is a schematic block diagram illustrating an example of an electronic device system. 2 is a schematic perspective view illustrating an example of an electronic device. 3A and 3B are schematic cross-sectional views illustrating the state of the fan-in semiconductor package before and after being packaged. 4 is a schematic cross-sectional view illustrating a packaging procedure of a fan-in semiconductor package. FIG. 5 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is mounted on an interposer substrate and finally mounted on a main board of an electronic device. 6 is a schematic cross-sectional view illustrating a case where a fan-in type semiconductor package is embedded in an interposer substrate and finally mounted on a main board of an electronic device. 7 is a schematic cross-sectional view illustrating a fan-out type semiconductor package. 8 is a schematic cross-sectional view illustrating a case where a fan-out type semiconductor package is mounted on a main board of an electronic device. 9 is a schematic cross-sectional view illustrating an example of a fan-out type semiconductor package. FIG. 10 is a schematic plan view taken along line II′ of the fan-out semiconductor package of FIG. 9. 11 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 12 is a schematic plan view taken along line II-II' of the fan-out semiconductor package of FIG. 13 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 14 is a schematic plan view taken along line III-III' of the fan-out semiconductor package of FIG. 13. 15 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 16 is a schematic plan view taken along line IV-IV' of the fan-out semiconductor package of FIG. 17 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 18 is a schematic plan view taken along line VV' of the fan-out semiconductor package of FIG. 17. 19 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 20 is a schematic plan view taken along line VI-VI' of the fan-out semiconductor package of FIG. 21 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 22 is a schematic plan view taken along line VII-VII' of the fan-out semiconductor package of FIG. 21. 23 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 24 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 25 is a schematic cross-sectional view illustrating another example of a fan-out type semiconductor package. 26 is a schematic cross-sectional view illustrating another example of the fan-out type semiconductor package.

Claims (11)

  1. A fan-out semiconductor package includes: a semiconductor chip having an active surface and a non-active surface, a connection pad is disposed on the active surface and the non-active surface is opposed to the active surface; the encapsulation body has a through hole And encapsulating at least part of the inactive surface of the semiconductor wafer, wherein the through hole penetrates the encapsulation body; a pattern layer, which is disposed on the encapsulation body and covers adjacent to the semiconductor wafer At least part of the encapsulated body of the non-active surface, wherein the pattern layer and the non-active surface of the semiconductor wafer are connected to each other through the through hole; and a connecting member, which is disposed on the A redistribution layer electrically connected to the connection pad of the semiconductor wafer on the active surface of the semiconductor wafer, wherein the pattern layer protrudes from an upper layer of the encapsulation body, wherein the pattern layer is The through hole is a metal layer and includes the same material.
  2. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the pattern layer and the via are integrated with each other and there is no boundary between the pattern layer and the via.
  3. The fan-out semiconductor package according to item 1 of the patent application scope, which further includes another metal layer directly disposed on the non-active surface of the semiconductor wafer, wherein the through hole Contact with the other metal layer.
  4. The fan-out semiconductor package as described in item 1 of the patent scope, further comprising: a passivation layer that covers at least part of the pattern layer; and a heat dissipation member that is attached to the passivation layer.
  5. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the pattern layer includes a pattern electrically insulated from the connection pad of the semiconductor wafer.
  6. The fan-out semiconductor package as described in item 1 of the patent application range, wherein the pattern layer includes a ground pattern.
  7. The fan-out semiconductor package as described in item 6 of the patent application range, wherein the pattern layer further includes a signal pattern.
  8. The fan-out semiconductor package according to item 1 of the patent application scope, further comprising a core member having a through hole, wherein the semiconductor wafer is disposed in the through hole of the core member, and the encapsulation body is encapsulated At least part of the core member and fills at least part of the perforation.
  9. The fan-out semiconductor package as recited in item 8 of the patent application range, wherein the core member includes at least one redistribution layer electrically connected to the connection pad.
  10. The fan-out semiconductor package as described in item 8 of the patent application scope further includes another metal layer disposed on the wall of the perforation.
  11. The fan-out semiconductor package as recited in item 8 of the patent application range, wherein the core member includes a first through hole and a second through hole as the through hole, the semiconductor chip is disposed in the first through hole, and the passive component It is disposed in the second through hole, and the through hole is selectively connected to the inactive surface of the semiconductor wafer.
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KR1020160117321A KR20170121666A (en) 2016-04-25 2016-09-12 Fan-out semiconductor package
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KR101973445B1 (en) 2017-11-07 2019-04-29 삼성전기주식회사 Fan-out sensor package and camera module
US10643919B2 (en) 2017-11-08 2020-05-05 Samsung Electronics Co., Ltd. Fan-out semiconductor package
KR102063470B1 (en) 2018-05-03 2020-01-09 삼성전자주식회사 Semiconductor package
KR102070563B1 (en) * 2018-06-01 2020-01-29 삼성전자주식회사 Electromagnetic interference shielding structure and semiconductor package comprising the same
KR102099748B1 (en) 2018-06-04 2020-04-13 삼성전자주식회사 Electronic component package

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JP2004214258A (en) * 2002-12-27 2004-07-29 Renesas Technology Corp Semiconductor module
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US9214434B1 (en) * 2011-11-22 2015-12-15 Amkor Technology, Inc. Fan-out semiconductor package
US20160113127A1 (en) * 2014-10-16 2016-04-21 Infineon Technologies Ag Electronic module having an electrically insulating structure with material having a low modulus of elasticity

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JP5326269B2 (en) * 2006-12-18 2013-10-30 大日本印刷株式会社 Electronic component built-in wiring board, and heat dissipation method for electronic component built-in wiring board

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JP2004214258A (en) * 2002-12-27 2004-07-29 Renesas Technology Corp Semiconductor module
US9214434B1 (en) * 2011-11-22 2015-12-15 Amkor Technology, Inc. Fan-out semiconductor package
US20140202741A1 (en) * 2012-03-01 2014-07-24 Fujikura Ltd. Component built-in board and method of manufacturing the same
US20160113127A1 (en) * 2014-10-16 2016-04-21 Infineon Technologies Ag Electronic module having an electrically insulating structure with material having a low modulus of elasticity

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TW201830617A (en) 2018-08-16

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