JP2012204662A - Wiring board and method for manufacturing the same, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board which has high impedance matching and design flexibility due to flatness, and enables high density mounting, and to provide a method for manufacturing the same, and a semiconductor device.SOLUTION: In a multilayer wiring board 10 which has an insulating layer 12 provided in the upper part of a substrate 11 and has an insulating layer 13 provided in the lower part of the substrate 11 symmetrically with the insulating layer 12, these insulating layers are formed from a polyimide resin, and are formed by building up with respect to the substrate 11 through casting, and either or both of the built-up insulating layers 12 and 13 are set so that the strength in an MD direction which is a flow direction of the substrate and in a TD direction which is a vertical direction of the substrate becomes the same.

Description

  The present invention relates to a wiring board, a manufacturing method thereof, and a semiconductor device, and more particularly to a technique specialized in the structure of the wiring board.

  With the recent increase in the density of electronic devices, high-density semiconductor devices (semiconductor packages) in which a plurality of semiconductor chips are stacked to realize a three-dimensional mounting structure have been developed. In such a semiconductor device, for example, a large number of electronic components such as an integrated circuit, a resistor, and a capacitor are fixed on the surface of a plate-like or film-like substrate, and the electronic circuit is connected by wiring between the components. It constitutes.

  As a multilayer wiring board for forming such a semiconductor device, a build-up board manufactured by a method of repeating lamination, drilling, circuit formation, and the like for each layer is widely used. In a circuit formation process in a build-up substrate, there is one in which an insulating layer is formed by laminating with a film-like resin (see Patent Document 1).

JP 2010-34247 A

  By the way, in multilayer wiring boards that are becoming increasingly thinner in recent years, it has become a problem to maintain the rigidity of the board in handling when mounting electronic components. It aims to be easy to handle. However, in the above prior art, orientation occurs when laminating a film-like resin on the insulating layer of the substrate, causing the wiring substrate to warp.

  The present invention has been proposed in order to solve the above-described problems of the prior art, and its purpose is to provide a multilayer wiring board capable of high-density mounting with high impedance matching and high design freedom due to flatness. An object of the present invention is to provide a manufacturing method and a semiconductor device.

  In order to solve the above-mentioned problems, the invention of claim 1 is based on a resin substrate as a base, a wiring pattern formed on the substrate, and a symmetrical build on both surfaces of the substrate while covering the wiring pattern. And the insulating layer is characterized in that the insulating layer has the same strength in the MD direction and the TD direction.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a multilayer wiring board according to the first aspect, wherein the first through hole is formed at a predetermined position of the resin substrate, and the first and lower surfaces of the substrate are formed on the first and lower surfaces. Forming a metal base layer; forming a first metal layer mainly composed of copper at a predetermined position of the first metal base layer; and forming a first metal layer mainly composed of copper in the first through-hole. A part of the wiring pattern constituted by the first and second metal layers by removing the first metal base layer exposed from the first metal layer, and a step of filling the second metal layer; Forming an insulating layer made of polyimide resin on the partial wiring pattern on the upper surface side and the lower surface side of the substrate, and covering the first metal layer; Until a part of the wiring pattern is exposed at a predetermined position of the insulating layer Forming a second metal through layer, forming a second metal base layer in the second through hole, forming a third metal base layer in the insulating layer, and forming a second metal base layer under the second metal Filling the second through-hole in which the base layer is formed with a third metal layer mainly composed of copper, and forming a fourth metal layer on the third metal base layer; A step of removing the third metal base layer exposed from the metal layer, and a step of forming a remaining portion of the wiring pattern composed of the second and third metal layers. To do.

  In the above aspect, in the insulating layer, the MD direction (Machine Direction) which is the flow direction of the substrate and the TD direction (Transverse Direction) which is the vertical direction of the substrate are set to the same strength. Accordingly, it is possible to provide a flat multilayer wiring board with less warping even when an insulating layer is built up on the board. In addition, since the upper and lower surfaces of the substrate have a vertically symmetrical structure, there is no warpage of the substrate, and at the same time, low thermal expansion can be realized. Even if the substrate is a large size, mounting displacement does not occur.

  According to a second aspect of the present invention, in the first aspect of the present invention, the insulating layer is formed by casting.

  In the above embodiment, the build-up of the insulating layer is performed by casting (solution casting), so that no physical pressure is applied to the film, so that the orientation of the polymer does not occur, and the strength and optical properties are increased. There is no directionality in characteristics. In addition, although the insulating layer marketed as a film is a standard product and has a predetermined thickness, it can be formed to an arbitrary thickness by casting the insulating layer as described above, and for example, an inclined structure is also produced. Is possible. Therefore, it is possible to prevent the product from being enlarged due to unnecessary insulating layer thickness. In addition, a thickness in consideration of signal delay can be set arbitrarily, and a CTE (linear expansion coefficient) material suitable for the circuit density and purpose can be used for the insulating layer, thereby increasing the degree of freedom in design.

  A third aspect of the invention is characterized in that in the invention of the first or second aspect, any or all of the substrate and the insulating layer are made of a polyimide resin.

  By forming any or all of the insulating layers including the substrate with a polyimide resin, it is possible to provide a multilayer wiring board having good heat resistance, a low dielectric constant, and a low linear expansion coefficient. Also, by using polyimide resin and not using epoxy insulating material and solder resist, it becomes possible to achieve good heat resistance, low dielectric constant and low linear expansion coefficient, and there is no mounting deviation even on a large board . A multilayer wiring board made of such a polyimide resin has high rigidity, can be handled in the same manner as a conventional glass epoxy board, and becomes a flexible board that does not require a carrier. Therefore, it is possible to cope with conventional transfer equipment, and it is also possible to cope with a reflow method. Furthermore, an inexpensive multilayer wiring board can be manufactured as compared with an epoxy-based insulating material.

  Invention of Claim 5 is a semiconductor device provided with the multilayer wiring board of any one of Claims 1-3, Comprising: A semiconductor chip laminated body, and any one of Claims 1-3 The multilayer wiring board, and the multilayer wiring board and the semiconductor chip laminated body.

  ADVANTAGE OF THE INVENTION According to this invention, the impedance matching by flatness and the freedom degree of design are high, and the multilayer wiring board in which high-density mounting is possible, its manufacturing method, and a semiconductor device can be provided.

1 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment. It is sectional drawing which shows the structure of the multilayer wiring board which concerns on 1st Embodiment. It is drawing which shows the manufacturing method of the multilayer wiring board which concerns on 1st Embodiment. FIG. 4 is a view showing a method for manufacturing a multilayer wiring board according to the first embodiment, and is a view showing a subsequent process of FIG. 3. It is sectional drawing which shows the structure of the multilayer wiring board which concerns on 2nd Embodiment. It is drawing which shows the manufacturing method of the multilayer wiring board which concerns on 2nd Embodiment. 7 is a diagram illustrating a method for manufacturing a multilayer wiring board according to a second embodiment, and is a diagram illustrating a subsequent process of FIG. 6. It is sectional drawing which shows the structure of the multilayer wiring board which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing method of the multilayer wiring board which concerns on 3rd Embodiment. FIG. 10 is a diagram illustrating a method for manufacturing a multilayer wiring board according to a third embodiment, and is a diagram illustrating a subsequent process of FIG. 9. FIG. 11 is a diagram illustrating a method for manufacturing a multilayer wiring board according to a third embodiment, and is a diagram illustrating a subsequent process of FIG. 10.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. As described above, the present invention can be regarded as an invention related to a multilayer wiring board, and can also be regarded as a manufacturing method and a semiconductor device for manufacturing the multilayer wiring board. Therefore, in the following embodiments, first, the configuration of the semiconductor device will be described, then the configuration of the multilayer wiring board will be specifically described, and further, the manufacturing method of the multilayer wiring board will be described.

[1. First Embodiment]
[1-1. Configuration of Semiconductor Device]
The semiconductor device 1 of the present embodiment is a semiconductor package having a so-called TSV (Through Silicon Via) structure, and as shown in FIG. 1, a multilayer wiring substrate 10, a semiconductor chip stack S, a multilayer wiring substrate 10, and a semiconductor chip. And a controller C disposed between the stacked bodies S.

  As shown in FIG. 1, the semiconductor chip stacked body S is configured by stacking a plurality of Si semiconductor chips S1. Each semiconductor chip S1 functions as a DRAM (Dynamic Random Access Memory). Each semiconductor chip S1 has a through hole S2 (Via), and a through electrode S3 is formed through the through hole S2. Each semiconductor chip S1 is electrically connected to another semiconductor chip S1 and the controller C through the through electrode S3.

  The controller C is made of a Si semiconductor chip C1. A through hole C2 (Via) is also formed in the semiconductor chip C1, and a through electrode C3 is formed through the through hole C2 (Via). The semiconductor chip C1 is sealed with underfill C4. The controller C is electrically connected to the semiconductor chip stacked body S and the multilayer wiring board 10 through the through electrode C3.

[1-2. Configuration of multilayer wiring board]
The multilayer wiring board 10 is a wiring board for expanding the electrode pitch of the semiconductor chip C1. The multilayer wiring board 10 is a so-called multilayer wiring board with solder bumps in which bumps are formed on a flexible flexible board.

  As shown in FIGS. 1 and 2, the multilayer wiring board 10 has a resin substrate 11 that serves as a base. The substrate 11 can be formed of any resin such as glass, silicone, polyimide resin, phenol resin, epoxy resin, polyester resin, and fluorine resin. In this embodiment, it is preferable to form with glass, silicone, or a polyimide resin.

  The multilayer wiring board 10 includes an insulating layer 12 on the upper side of the substrate 11, and an insulating layer 13 on the lower side of the substrate 11 in contrast thereto. These insulating layers are made of polyimide resin, and are formed by building up the substrate 11 by casting (solution casting).

  As a result, either or both of the built-up insulating layers 12 and 13 have the same strength in the MD direction (Machine Direction) which is the flow direction of the substrate and in the TD direction (Transverse Direction) which is the vertical direction of the substrate. It becomes possible to do.

  Here, in the casting of the insulating layer of the present embodiment, in order to prevent the generation of voids (laminated voids, that is, the area where there should be no resin or adhesive), the viscosity that is a precursor of the polyimide resin. A varnish with a low viscosity is filled between the circuits, dried, and then a varnish with a high viscosity is cast. This varnish casting (coating and curing) is performed a plurality of times in order to obtain flatness. The viscosity of each varnish and the number of castings are appropriately set according to L / S (circuit density), circuit thickness, and CTE inclination. The insulating layer formed by such casting maintains adhesion with the wiring pattern and does not cause voids.

  A wiring pattern 14 having a three-dimensional structure is formed on the substrate 11 from the insulating layer 12 to the insulating layer 13. The wiring pattern 14 is made of a metal whose main component is copper. The “metal having copper as a main component” may be copper alone or an alloy in which nickel, cobalt, iron or the like is added to copper. When a metal containing copper as a main component is used as an alloy, the amount of nickel or the like added to copper is preferably 20% or less.

  The wiring pattern 14 mainly includes a lower wiring portion 14a, a connecting wiring portion 14b, and an upper wiring portion 14c. In order to make the following description easy to understand, the wiring pattern 14 is divided into these parts, but these parts are actually formed integrally.

  The lower wiring portion 14a is covered with the insulating layer 13. The insulating layer 13 is patterned in a predetermined pattern, and a part of the lower wiring portion 14 a is exposed from the opening 13 a of the insulating layer 13. An exposed portion of the lower wiring portion 14a functions as an external connection electrode, solder balls or the like are formed on the exposed portion, and the semiconductor device 1 is mounted on a circuit board such as a mother board.

  The connecting wiring portion 14b is formed so as to penetrate the insulating layer 13 and the substrate 11, and is connected to the lower wiring portion 14a and the upper wiring portion 14c at the upper and lower end portions to connect these wiring portions.

  The upper wiring part 14 c is formed in the insulating layer 12. A post 15 is formed on the upper wiring portion 14c. The post 15 is erected on the wiring pattern 14 in a state of penetrating the insulating layer 12. The tip portion (top portion 15 b) of the post 15 is exposed from the insulating layer 12. The insulating layer 12 covers the side surface of the post 15 in a state where the tip end portion (the top portion 15 b) of the post protrudes, and functions as a protective layer that protects the post 15.

  Solder bumps 15 a are formed on the posts 15. The solder bump 15a is a protruding electrode for electrically flip-chip connection with an electronic device such as a semiconductor chip, and is made of, for example, a tin-silver-copper alloy.

  As shown in the enlarged portion of FIG. 2, the post 15 has a tapered shape (reverse taper shape) from the top portion 15b toward the base portion 15c. The top portion 15b is a portion connected to the semiconductor chip C1 of the controller C via the solder bump 15a. The base portion 15 c is a portion connected to the upper wiring portion 14 c of the wiring pattern 14. For example, the diameter of the top portion 15b is +10 to 20 μm with respect to the diameter of the electrode C5 (FIG. 1) of the semiconductor chip C1, and the diameter of the base portion 15c is ± 10 μm with respect to the diameter of the electrode C5 of the semiconductor chip C1.

  Since the post 15 has such a shape, the top portion 15b of the post 15 has a larger area when viewed in plan than the base portion 15c, and can prevent displacement between electrodes when connected to the semiconductor chip C1. On the other hand, the base portion 15c of the post 15 has a smaller area when viewed in plan than the top portion 15b. When the post 15 is formed, the base 15c is misaligned with the upper wiring portion 14c or the upper portion of the post 15 next to the desired upper wiring portion 14c. It is possible to prevent erroneous connection to the wiring portion 14c.

  Although omitted in FIG. 2, a base metal layer is formed at the interface between the substrate 11, the insulating layer 12, the insulating layer 13 and the wiring pattern 14, and the interface between the insulating layer 12 and the post 15. . Such a base metal layer enhances the adhesion of the wiring pattern 14 and the post 15 to the substrate 11 and the like. This base metal layer is made of, for example, a nickel chromium alloy or copper.

Various dimensions of the semiconductor device 1 having the above configuration are designed, for example, as follows (see FIGS. 1 and 2).
The package size (multilayer wiring board 10) is 11 mm × 15 mm.
The chip size (semiconductor chip C1) is 7 mm × 8 mm.
The diameter a of the through electrode C3 is 20 μm.
The pitch b between the through electrodes C3 is 35 μm.
The diameter c of the through electrode C3 is 20 μm.
The pitch d between the through electrodes C3 is 70 μm.
The diameter e of the post 15 is approximately 20 μm.
The pitch f between the solder bumps 15a is 70 μm.
A pitch g between the external connection electrodes (solder balls) is 800 μm.
The height h of the solder bump 15a is 5 μm.
The height i of the post 15 is 35 μm.
The thickness j of the substrate 11 is 38 μm.
The height k of the connecting wiring portion 14b of the wiring pattern 14 is 38 μm.

  Here, in the semiconductor device 1, the controller C (semiconductor chip C1) is formed with an electrode C5 protruding from the bottom surface toward the multilayer wiring board 10 side. The total H (see FIG. 1) of the height of the electrode C5 of the semiconductor chip C1 and the height of the post 15 of the multilayer wiring board 10 is preferably 35 μm or more, and more preferably 50 μm or more.

  In this case, either the electrode C5 of the semiconductor chip C1 or the post 15 of the multilayer wiring board 10 may be high, but the post 15 is preferably made high to ensure the height of the post 15 of 35 μm or more. This is because (i) it is troublesome to manufacture the electrode C5 for each semiconductor chip C1 (for each sheet) to secure the height on the semiconductor chip C1 side, whereas on the multilayer wiring board 10 side This is because the post 15 can be easily manufactured by the roll-to-roll method if the height is to be secured. (Ii) Considering the yield of the semiconductor chip C1 and the multilayer wiring board 10, the total yield is better if the height is secured on the multilayer wiring board 10 side. Therefore, it is preferable that the electrode C5 of the semiconductor chip C1 is composed only of a pad electrode, and no bump or the like is formed on the electrode C5.

[1-3. Manufacturing method of multilayer wiring board]
Then, the manufacturing method of the multilayer wiring board 10 is demonstrated.
As shown in FIG. 3, a through-hole A1 is formed at a predetermined position of the substrate 11 using a laser, and the smear (scratch) is removed (S1). Thereafter, metal is sputtered onto the substrate 11 to form a metal underlayer B1 (S2).

  Thereafter, a metal having copper as a main component is plated at a predetermined position of the metal base layer B1 to form the metal layer ML1 on the metal base layer, and the through hole A1 is also filled with the metal layer ML2 (S3). Thereafter, the metal base layer B1 exposed from the metal layer ML1 is removed by etching (S4). As a result, the wiring pattern 14 (the lower wiring portion 14a, the connecting wiring portion 14b, and the upper wiring portion 14c) composed of the metal layer ML1 and the metal layer ML2 is formed.

  Thereafter, an insulating layer 12 made of polyimide resin is formed on the wiring pattern 14 (upper wiring portion 14 c) on the upper surface side of the substrate 11, and the upper wiring portion 14 c of the wiring pattern 14 is covered with the insulating layer 12. At the same time, an insulating layer 13 made of polyimide resin is formed on the wiring pattern on the lower surface side of the substrate 11 by casting, and the lower wiring portion 14a of the wiring pattern 14 is covered with the insulating layer 13 (S5).

  Here, in the casting of the insulating layer of the present embodiment, as described above, in order to prevent the generation of voids, a low-viscosity varnish that is a polyimide resin precursor is filled between the circuits and dried, and then the high-viscosity is obtained. Cast the varnish. This casting is performed a plurality of times in order to obtain flatness.

  Thereafter, a dry film D1 made of resin is stuck on the insulating layer 12 and exposed to cure the dry film D1 (S6). Thereafter, a through hole A2 is formed using a laser until the upper wiring portion 14c is exposed at a predetermined position of the dry film D1 and the insulating layer 12. At the same time, a through hole (opening 13a) is formed at a predetermined position of the insulating layer 13 using a laser until the lower wiring portion 14a is exposed, and these smears (shavings) are removed (S7).

  Thereafter, as shown in FIG. 4, metal is sputtered on the dry film D1 and the through hole A2 to form the metal base layer B2, and metal is also sputtered on the insulating layer 13 and the opening 13a to form the metal base layer B3. (S8). Thereafter, a dry film D2 made of resin is applied to the metal base layer B3, a metal mainly composed of copper is plated on the metal base layer B2, a metal layer ML3 is formed on the metal base layer B2, and a through hole is further formed. A2 is also filled with the metal layer ML4 (S9). Thereafter, the metal base layer B2 and the metal layer ML3 on the dry film D1 are removed by etching (S10). As a result, the post 15 composed of the metal layer ML4 is formed.

Thereafter, solder is plated on the post 15 to form a solder bump 15a, a dry film D3 is laminated on the solder bump 15a and the dry film D1, and the dry film D3 is cured by exposure (S11). Thereafter, the dry film D2 formed on the metal base layer B3 is peeled off (S12). Thereafter, the metal base layer B3 is removed by etching, and the dry films D1 and D3 on the insulating layer 12 are simultaneously peeled off (S13).
The multilayer wiring board 10 can be manufactured through the processes of S1 to S13.

[1-4. effect]
(Board warpage reduction effect)
According to the multilayer wiring board 10 and the semiconductor device 1 including the multilayer wiring board 10 described above, by casting, in the insulating layers 12 and 13, the MD direction which is the flow direction of the substrate 11 and the TD direction which is the vertical direction of the substrate 11. And can have the same strength. Therefore, even if the insulating layers 12 and 13 are formed on both surfaces of the substrate 11 by build-up, warpage of the substrate 11 due to this can be reduced. In particular, the warpage of the substrate 11 can be more effectively reduced by configuring all of the insulating layers including the substrate 11 with the same material.

  Further, by making the upper and lower insulating layers 12 and 13 symmetrical, there is no warping of the substrate 11 and low thermal expansion can be realized at the same time. For this reason, mounting displacement does not occur even with a large-sized substrate.

(Effects using polyimide resin)
By forming any or all of the insulating layers 12 and 13 including the substrate 11 in polyimide resin, it is possible to provide the multilayer wiring substrate 10 having good heat resistance, low dielectric constant, and low linear expansion coefficient. In addition, it is possible to achieve good heat resistance, low dielectric constant and low linear expansion coefficient by using polyimide resin and not using epoxy insulating material and solder resist. There is no gap.

  The multilayer wiring board 10 made of such a polyimide resin has high rigidity, can be handled in the same way as a glass epoxy board, and becomes a flexible board that does not require a carrier. Therefore, it is possible to cope with conventional transfer equipment, and it is also possible to cope with a reflow method. Furthermore, it is possible to manufacture a multilayer wiring board 10 that is less expensive than an epoxy insulating material.

(Effect of forming an insulating layer on the wiring pattern by casting)
The build-up of the insulating layers 12 and 13 is performed by casting (solution casting), so that no physical pressure is applied to the film, so that the orientation of the polymer does not occur, and the strength, optical characteristics, etc. There is no directionality.

  In addition, although the insulating layer marketed as a film is a standard product and has a predetermined thickness, by casting the insulating layers 12 and 13 as in this embodiment, an arbitrary thickness can be formed. For example, an inclined structure can be produced. Therefore, it is possible to prevent the product from being enlarged due to unnecessary insulating layer thickness. In addition, a thickness in consideration of signal delay can be set arbitrarily, and a CTE (linear expansion coefficient) material suitable for the circuit density and purpose can be used for the insulating layer, thereby increasing the degree of freedom in design.

  As described above, the semiconductor package mounting structure is laminated in the order of LSI chip / NCP (Non Conductive Paste) / interposer / underfill / motherboard. Among these, the CTE is small (3 to 5 ppm) in the LSI chip and large in the mother board. Therefore, in the present embodiment, for example, in a semiconductor package, a material having a small CTE is selected on the insulating layer 12 side (LSI chip side) and a material having a large CTE on the insulating layer 13 side (motherboard side). Select. As a result, the load on the primary (connection to the LSI chip) and secondary (connection to the motherboard) connection terminals can be reduced. In this way, it is possible to provide the multilayer wiring board 10 having a very high degree of design freedom.

  In addition, in casting, the amount of heat applied to the resin is lower than in the melt extrusion molding method (melting like a film-like resin is unnecessary), and the amount of heat stabilizer added can be reduced. Further, the curl condition can be adjusted by setting the melting temperature during casting.

  Moreover, since the process of filtering the solution can be set up by such casting, a resin lump (fish eye) is not generated and scratches are not easily generated. Therefore, a highly transparent film for use in the insulating layers 12 and 13 is formed. Can be molded.

  Thus, by using casting for forming the insulating layers 12 and 13, there is an advantage that the insulating layers 12 and 13 having high thickness accuracy and excellent smoothness, transparency, and gloss can be formed. In addition, by using casting in this way, it becomes easy to form the insulating layers 12 and 13 with a polyimide film having a high melting point and difficult to be extruded.

[2. Second Embodiment]
The second embodiment is different from the first embodiment in the configuration of the multilayer wiring board, and the other configurations are the same as those in the first embodiment. Therefore, the second embodiment is different from the first embodiment below. Only the point will be described. Further, even in the configuration of the multilayer wiring board, the description in the first embodiment is used for points not particularly mentioned.

[2-1. Configuration of multilayer wiring board]
As shown in FIG. 5, the multilayer wiring board 20 of this embodiment includes an insulating layer 22 on the upper side of the substrate 21, and includes an insulating layer 23 on the lower side of the substrate 21 in contrast thereto. Similar to the first embodiment, these insulating layers are formed of polyimide resin, and are formed by building up the substrate 21 using casting. Either or both of the insulating layers 22 and 23 thus built up can have the same strength in the MD direction which is the flow direction of the substrate and in the TD direction which is the vertical direction of the substrate.

  A wiring pattern 24 having a three-dimensional structure is formed on the substrate 21 from the insulating layer 22 to the insulating layer 23. The wiring pattern 24 mainly includes an uppermost wiring portion 24a, an upper wiring portion 24b, a connection wiring portion 24c, a lower wiring portion 24d, and a lowermost wiring portion 24e. Here, as in the first embodiment, for convenience of explanation, the wiring pattern 24 is partitioned into these portions, but these portions are actually formed integrally.

  The lower wiring portion 24d and the lowermost wiring portion 24e are covered with the insulating layer 23, and a part of the lowermost wiring portion 24e is exposed from the opening 23a of the insulating layer 23. The exposed part of the lowermost wiring part 24e functions as an external connection electrode, solder balls or the like are formed on the exposed part, and the semiconductor device 1 is mounted on a circuit board such as a mother board.

  The connecting wiring portion 24c is formed so as to penetrate the substrate 21, and is connected to the upper wiring portion 24b and the lower wiring portion 24d at the upper and lower end portions to connect these wiring portions.

  The upper wiring portion 24 b is covered with the insulating layer 22, and the uppermost wiring portion 24 a connected to the upper wiring portion 24 b is disposed so as to be exposed above the insulating layer 22. The insulating layer 22 is in a state in which the uppermost wiring portion 24a is protruded.

  Solder bumps 25 are formed on the uppermost wiring part 24a, and the uppermost wiring part 24a is a part connected to the semiconductor chip C1 of the controller C via the solder bumps 25. The solder bump 25 is a protruding electrode for electrically flip-chip connection with an electronic device such as a semiconductor chip, and is made of, for example, a tin-silver-copper alloy.

  As in the first embodiment, a base metal layer is formed at the interface between the substrate 21, the insulating layer 22, the insulating layer 23, and the wiring pattern 24. Such a base metal layer enhances the adhesion of the wiring pattern 24 to the substrate 21 and the like. This base metal layer is made of, for example, a nickel chromium alloy or copper.

Various dimensions of the multilayer wiring board 20 having the above configuration are designed, for example, as follows (see FIG. 5).
(A) The diameter of the via hole formed in the insulating layer 22 is designed in the range of 15 μm to 100.
(B) The width of the via land is designed to be larger than 160 μm.
(C) The space between the uppermost wiring portions 24a is designed to be larger than 15 μm.
(D) The line width is designed to be greater than 15 μm.
(E) The thickness of the uppermost wiring part 24a is designed to be smaller than 18 μm.
(F) The thickness of the solder bump 25 is designed in the range of 2 to 8 μm.
(G) The pitch between the openings 23a in the lowermost wiring part 24e is designed to be smaller than 250 μm.
(H) The space between the lowermost wiring portions 24e is designed to be larger than 50 μm.
(I) The thickness of the lowermost wiring part 24e is designed to be smaller than 18 μm.
(J) The thickness of the substrate 21 is designed to be 12.5, 25, 38, 40, or 50 μm.

[2-2. Manufacturing method of multilayer wiring board]
Then, the manufacturing method of the multilayer wiring board 20 is demonstrated.
As shown in FIG. 6, a through-hole A1 is formed at a predetermined position of the substrate 21 using a laser, and the smear (scratch) is removed (S1). Thereafter, metal is sputtered on the substrate 21 to form the metal underlayer B1 (S2).

  Thereafter, a dry film D1 made of resin is laminated on the metal base layer B1 on the lower surface side of the substrate 21, and the dry film D1 is formed using a mask having a pattern corresponding to the upper wiring portion 24b, the connecting wiring portion 24c, and the lower wiring portion 24d. Formed by exposure and development. Thereby, metal base layer B1 will be coat | covered with the resin layer (dry film D1) of a predetermined pattern (S3).

  Thereafter, a metal having copper as a main component is plated at a predetermined position of the metal base layer B1 exposed from the dry film D1, and metal layers ML1 and ML2 are formed on the metal base layer B1 (S4). Thereafter, the dry film D1 and the metal base layer B1 at the position of the dry film D1 are removed by etching (S5). As a result, a part of the wiring pattern 24 composed of the metal layer ML1 and the metal layer ML2 (upper wiring portion 24b, connecting wiring portion 24c, and lower wiring portion 24d) is formed.

  Thereafter, polyimide resin is cast as insulating layers 22 and 23 on both the upper surface side and the lower surface side of the substrate 21. Further, a through hole A2 is formed at a predetermined position of the insulating layers 22 and 23 using a laser until the wiring pattern 24 is exposed, and the smear (shavings) is removed (S6). Thereafter, metal is sputtered on the insulating layers 22 and 23 to form the metal base layer B2 (S7).

  Thereafter, a dry film D2 made of resin is stuck on the insulating layers 22 and 23, and the dry film D2 is cured by exposure (S8). After that, as shown in FIG. 7, a metal having copper as a main component is plated at predetermined positions of the insulating layers 22 and 23 to form metal layers ML3 and ML4 on the insulating layers 22 and 23 (S9). Thereafter, the dry film D2 and the metal base layer B2 at the position of the dry film D2 are removed by etching (S10). Thereby, the uppermost wiring part 24a is formed from the metal layer ML3, and the lowermost wiring part 24e is formed from the metal layer ML4.

  Thereafter, a dry film D3 made of resin is laminated on the upper and lower surfaces of the substrate 21 and the wiring portion, and a pattern corresponding to the solder bumps 25 is exposed using a mask to cure the dry film D3. Thereafter, a solder bump 25 made of tin-silver-copper alloy is formed on the uppermost wiring portion 24a of the wiring pattern 24 provided on the insulating layer 22 (S11). The solder bump 25 is a protruding electrode for electrically flip-chip connection with an electronic device such as a semiconductor chip. Thereafter, the dry film D3 formed on the substrate 21 is peeled off (S12).

Thereafter, polyimide resin is cast on the lower surface side of the substrate (formation of the remaining portion of the insulating layer 23). Further, a through hole 23a is formed at a predetermined position of the insulating layer 23 using a laser until the lowermost wiring layer 24e is exposed, and the smear (scratch) is removed (S13).
The multilayer wiring board 20 can be manufactured through the processes of S1 to S13.

[2-3. effect]
According to the multilayer wiring substrate 20 in the present embodiment as described above, when the insulating layers 22 and 23 are built up on the substrate 21, the insulating layer is formed on the wiring pattern 24 by casting. Thereby, since the freedom degree of design, such as the thickness of an insulating layer, is high, manufacture of a multilayer substrate can be performed easily. Therefore, the degree of freedom of design in via-on-via or filled via, high-density mounting, interlayer reliability, and layer thickness stability are high, and impedance matching due to flatness can be obtained. In the multilayer wiring board of this embodiment, the connection strength can be improved by using filled vias.

[3. Third Embodiment]
The third embodiment is different from the first and second embodiments in the configuration of the multilayer wiring board, but the other configurations are the same as those in the first and second embodiments. Only differences from the first and second embodiments will be described. In addition, regarding the configuration of the multilayer wiring board, the description in the first and second embodiments is used for points not particularly mentioned.

[3-1. Configuration of multilayer wiring board]
As shown in FIG. 8, in the multilayer wiring board 30 according to the present embodiment, an insulating layer 32 is formed below a resin substrate 31 serving as a base, and an insulating layer 33 is further formed below the insulating layer 32. Is formed. These insulating layers are formed of polyimide resin, and are formed by building up the substrate 31 using casting.

  As described in the first embodiment, when one or both of the insulating layers 32 and 33 are built up in this way, the MD direction (Machine Direction) which is the flow direction of the substrate and the vertical direction of the substrate are set. The strength can be made the same in the TD direction (Transverse Direction).

  On the substrate 31, a wiring pattern 34 having a three-dimensional structure is formed from the insulating layer 32 to the insulating layer 33. The wiring pattern 34 mainly includes an upper wiring portion 34a, a connecting wiring portion 34b, and a lower wiring portion 34c. Here, as in the first and second embodiments, for convenience of explanation, the wiring pattern 34 is partitioned into these portions, but these portions are actually formed integrally.

  The upper wiring part 34 a is formed in the insulating layer 32. A post 35 is formed on the upper wiring portion 34a. The post 35 is erected on the wiring pattern 34 while penetrating the substrate 31. The front end portion (top portion 35 b) of the post 35 is slightly exposed from the substrate 31. The substrate 31 covers the side surface of the post 35 in a state where the tip end portion (top portion 35 b) of the post protrudes, and functions as a protective layer that protects the post 35.

  The connection wiring part 34 b is formed so as to penetrate the substrate 31 and the insulating layer 32. The connecting wiring part 34b is connected to the upper wiring part 34a and the lower wiring part 34c, and connects these wiring parts.

  The lower wiring portion 34 c is covered with the insulating layer 33. The insulating layer 33 is patterned in a predetermined pattern, and a part of the lower wiring portion 34 c is exposed from the opening 33 a of the insulating layer 33. The exposed portion of the lower wiring portion 34c functions as an external connection electrode, solder balls or the like are formed on the exposed portion, and the semiconductor device 1 is mounted on a circuit board such as a mother board.

  On the post 35, a solder bump 35a is formed. The solder bump 35a is a protruding electrode for electrically flip-chip connection with an electronic device such as a semiconductor chip, and is made of, for example, a tin-silver-copper alloy.

  As in the first embodiment, a base metal layer is formed on the interface between the substrate 31, the insulating layer 32, the insulating layer 33 and the wiring pattern 34, and the interface between the substrate 31 and the post 35. Such a base metal layer enhances the adhesion of the wiring pattern 34 and the post 35 to the substrate 31 and the like. This base metal layer is made of, for example, a nickel chromium alloy or copper.

Various dimensions of the multilayer wiring board 30 having the above configuration are designed, for example, as follows (see FIGS. 8 and 9).
The package size (multilayer wiring board 30) is 11 mm × 15 mm.
The diameter e of the post 35 is approximately 20 μm.
The pitch f between the solder bumps 35a is 70 μm.
A pitch g between the external connection electrodes (solder balls) is 800 μm.
The height h of the solder bump 35a is 5 μm.
The height i of the post 35 is 35 μm.
The thickness j of the substrate 31 is 25 μm.
The height k of the connection wiring part 34b of the wiring pattern 34 is 38 μm.

  Here, in the semiconductor device 1, the controller C (semiconductor chip C1) is formed with an electrode C5 that protrudes from the bottom surface toward the multilayer wiring board 30 side. The total H (see FIG. 1) of the height of the electrode C5 of the semiconductor chip C1 and the height of the post 35 of the multilayer wiring board 30 is preferably 35 μm or more, and more preferably 50 μm or more.

[3-2. Manufacturing method of multilayer wiring board]
Then, the manufacturing method of the multilayer wiring board 30 is demonstrated.
The multilayer wiring board 30 is manufactured by a roll-to-roll method in which a long substrate 31 wound around a predetermined roll is conveyed so that it is wound around another roll, and a wiring pattern 34 is formed in the conveyance process. Is done.

  Specifically, first, as shown in FIG. 9, a dry film D1 made of resin is laminated on the substrate 31, and the dry film D1 is cured by exposure (S1). Then, the through-hole A1 is formed in the predetermined position of the board | substrate 31 and the dry film D1 using a laser, and the smear (shavings) is removed (S2).

  Thereafter, metal is sputtered on the substrate 31 and the dry film D1 to form the metal base layer B1 (S3). Thereafter, a dry film D2 made of resin is laminated on the metal base layer B1 on the lower surface side of the substrate 31. Then, the dry film D2 is exposed and developed with a pattern corresponding to the upper wiring part 34a, and the metal base layer B1 is covered with a resin layer (dry film D2) having a predetermined pattern (S4).

  Thereafter, a metal base layer B1 on the dry film D1 and a metal base layer B1 exposed from the dry film D2 are plated with a metal containing copper as a main component to form a metal layer ML1 on the metal base layer B1. At the same time, the metal layer ML2 is filled into the through hole A1 (S5). Thereafter, a resin dry film D3 is applied to the metal layer ML1 and the dry film D2 on the lower surface side of the substrate 31, and the metal base layer B1 and the metal layer ML1 on the upper surface side of the dry film D1 are removed by etching (S6). ). As a result, a post 35 composed of the metal layer ML1 is formed.

  In the process of S2, the laser output is adjusted and gradually lowered from the upper side to the lower side, and the through hole A1 is formed in a tapered shape (reverse tapered shape). As a result, a tapered post 35 can be formed (see the enlarged portion in FIG. 8).

  Thereafter, solder is plated on the post 35 to form a solder bump 35a (S7), and the dry films D1, D2, D3 formed on the substrate 31 are peeled off (S8).

  After that, as shown in FIG. 10, a dry film D4 made of resin is attached to the substrate 31, and the metal base layer B1 covered with the dry film D2 on the lower surface of the substrate 31 is removed by etching (S9). . As a result, an upper wiring portion 34a of the wiring pattern 34 composed of the metal layer ML2 is formed. Thereafter, the insulating layer 32 is built up on the lower surface side of the substrate 31 by casting, and the upper wiring portion 34a of the wiring pattern 34 is covered with the insulating layer 32 (S10).

  Thereafter, the dry film D4 is peeled off (S11). Subsequently, the through-hole A2 is formed using a laser until the upper wiring portion 34a is exposed at a predetermined position of the insulating layer 32, and the smear (scratch) is removed (S12).

  Thereafter, a metal base layer B2 is formed by sputtering metal on the insulating layer 32, the through hole A2, and the upper wiring portion 34a (S13). Thereafter, a dry film D5 made of resin is laminated on the substrate 31. At the same time, a dry film D6 made of resin is laminated on the metal base layer B2. Then, the dry film D6 is exposed and developed using a mask having a pattern corresponding to the lower wiring portion 34c and the connecting wiring portion 34b, and the metal base layer B2 is covered with a resin layer (dry film D6) having a predetermined pattern (S14). .

  After that, as shown in FIG. 11, the metal base layer B2 exposed from the dry film D6 is plated with a metal mainly composed of copper, and the metal layer ML2 is formed on the metal base layer B2, the through hole A2, and the upper wiring portion 34a. Form (S15). Thereafter, the dry film D6 is peeled off (S16). Thereafter, the metal base layer B2 covered with the dry film D6 is removed by etching. As a result, the lower wiring part 34c and the connection wiring part 34b of the wiring pattern 34 composed of the metal layer ML2 are formed.

Thereafter, the dry film D5 is peeled off, and the insulating layer 32, the lower wiring portion 34c and the connecting wiring portion 34b are formed with an insulating layer 33 using a polyimide resin without using a solder resist, and using a laser, By forming the opening 33a in the insulating layer 33, a part of the lower wiring part 34c is exposed from the opening 33a (an external connection electrode is formed) (S17).
The multilayer wiring board 30 can be manufactured through the processes of S1 to S17.

[3-3. effect]
According to the multilayer wiring board 30 of the present embodiment as described above, as in the first embodiment, the insulating layers 32 and 33 are built up on the substrate 31, so that the MD direction that is the flow direction of the substrate 31, The strength can be made the same in the TD direction which is the vertical direction of the substrate 31. Thereby, the curvature of the board | substrate 31 can be reduced. In particular, the warp of the substrate 31 can be more effectively reduced by configuring all of the insulating layers including the substrate 31 with the same material.

  By forming any or all of the insulating layers 32 and 33 including the substrate 31 with a polyimide resin, the substrate 31 having good heat resistance, a low dielectric constant, and a low linear expansion coefficient can be provided. Also, by using polyimide resin and not using an epoxy-based insulating material and a solder resist, it becomes possible to achieve good heat resistance, low dielectric constant and low linear expansion coefficient, and the substrate 31 has a large size. There is no mounting deviation.

  Further, when the insulating layers 32 and 33 are built up by casting, no physical pressure is applied to the film, so that the orientation of the polymer does not occur, and the directionality of the strength, optical characteristics, and the like does not occur.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Multilayer wiring board 11 ... Substrate 12, 13 ... Insulating layer 13a ... Opening part 14 ... Wiring pattern 14a ... Lower wiring part 14b ... Connection wiring part 14c ... Upper wiring part 15 ... Post 15a ... Solder bump 15b ... Top portion 15c ... Base portion 20 ... Multilayer wiring substrate 21 ... Substrate 22, 23 ... Insulating layer 23a ... Opening portion 24 ... Wiring pattern 24a ... Upper wiring portion 24b ... Upper wiring portion 24c ... Connecting wiring portion 24d ... Lower wiring portion 24e ... Lower wiring portion 25 ... solder bump 30 ... multilayer wiring substrate 31 ... substrates 32, 33 ... insulating layer 33a ... opening 34 ... wiring pattern 34a ... upper wiring portion 34b ... connection wiring portion 34c ... lower wiring portion 35 ... post 35a ... solder Bump 35b ... Top A1, A2 ... Through hole B1-B3 ... Metal base layer C ... Controller C1 ... Chip C2 ... Through hole C3 ... Through electrode C4 ... An Firu C5 ... electrodes D1 to D6 ... dry film ML1 to ML4 ... metal layer S ... semiconductor chip stack S1 ... semiconductor chip S2 ... through hole S3 ... through electrode

Claims (5)

A base resin substrate;
A wiring pattern formed on the substrate;
An insulating layer formed by building up a part of the wiring pattern;
The insulating layer has the same strength in the MD direction and the TD direction.   The multilayer wiring board according to claim 1, wherein the insulating layer is formed by casting.   The multilayer wiring board according to claim 1 or 2, wherein any or all of the substrate and the insulating layer are made of polyimide resin. Forming a first through hole at a predetermined position of a resin substrate;
Forming a first metal underlayer on the upper and lower surfaces of the substrate;
Forming a first metal layer mainly composed of copper at a predetermined position of the first metal base layer, and filling the second through hole with a second metal layer mainly composed of copper; ,
Removing the first metal underlayer exposed from the first metal layer and forming a part of a wiring pattern composed of the first and second metal layers;
Forming an insulating layer made of polyimide resin on the upper and lower surfaces of the substrate by casting and covering the first metal layer; and
Forming a second through hole until a part of the wiring pattern is exposed at a predetermined position of the insulating layer;
Forming a second metal base layer in the second through-hole and forming a third metal base layer in the insulating layer;
Filling the second through hole in which the second metal base layer is formed with a third metal layer mainly composed of copper, and forming a fourth metal layer on the third metal base layer; When,
Removing the third metal base layer exposed from the fourth metal layer;
Forming a remaining portion of the wiring pattern composed of the second and third metal layers;
A method of manufacturing a wiring board, comprising:   A semiconductor device comprising a semiconductor chip stack, the multilayer wiring board according to claim 1, and the multilayer wiring board and the semiconductor chip stack.

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