CN114582736A - Semiconductor packaging method - Google Patents

Abstract

The application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps: forming an encapsulation structure, wherein the encapsulation structure comprises an encapsulation layer and at least one chip, at least one concave cavity is arranged on the encapsulation layer, the at least one chip is arranged in the at least one concave cavity, the encapsulation layer is exposed out of the front surface of the chip, and a plurality of welding pads are arranged on the front surface of the chip; forming a rewiring structure on the packaging structure, wherein the rewiring structure leads out a welding pad of the chip; and sleeving the insulating film layer provided with the hollow part on the rewiring structure, wherein the surface of the rewiring structure departing from the chip is exposed out of the insulating film layer through the hollow part.

Description

Semiconductor packaging method

technical field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor packaging method.

Background technique

Common semiconductor packaging technology, such as chip packaging technology, mainly includes the following process: For the process of the front side of the chip, first mount the front side of the chip on the carrier board, perform thermocompression molding, peel off the carrier board, and then A redistribution structure is formed on the front side of the chip, then an insulating layer for protecting the redistribution structure is formed on the redistribution structure, and the surface of the redistribution structure facing away from the chip exposes the insulating layer.

In the existing chip packaging technology, when an insulating layer is formed on the rewiring structure, the initially formed insulating layer completely covers the rewiring structure, and then the insulating layer is ground to reduce the thickness of the insulating layer, and the rewiring structure deviates from it. The surface of the chip is exposed. However, the grinding process is time-consuming and affects the packaging efficiency.

SUMMARY OF THE INVENTION

Embodiments of the present application provide a semiconductor packaging method. The semiconductor packaging method includes:

An encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and at least one chip, the encapsulation layer is provided with at least one concave cavity, and the at least one chip is disposed in the at least one concave cavity In the body, the encapsulation layer is exposed on the front side of the chip, and the front side of the chip is provided with a plurality of bonding pads;

forming a redistribution structure on the encapsulation structure, the redistribution structure leading out the pads of the chip;

The insulating film layer disposed in the at least one concave cavity is sleeved on the redistribution structure, and the surface of the redistribution structure facing away from the chip exposes the insulating film layer through the hollow portion.

In one embodiment, a height difference between the side of the redistribution structure facing away from the encapsulation structure and the side of the insulating film layer facing away from the encapsulation structure ranges from 0 to 40 μm.

In one embodiment, the redistribution structure includes a plurality of conductive structures, the insulating film layer is provided with a plurality of the hollowed-out portions, the hollowed-out portions correspond to the conductive structures one-to-one, and the conductive structures are away from One side of the chip is exposed through the corresponding hollow portion.

In one embodiment, the conductive structure includes a trace structure connected to the bonding pad and a conductive bump located on a side of the trace structure away from the chip;

The inner surface of the hollow portion is provided with a stepped structure, the trace structure is located in the hollow portion and is located on the side of the stepped structure close to the chip, the conductive protrusion is located in the hollow portion and is The step structure surrounds.

In one embodiment, the material of the insulating film layer is a flexible material.

In one embodiment, before the insulating film layer provided with the hollow portion is sleeved on the redistribution structure, the semiconductor packaging method further includes: preparing the insulating film layer;

The preparing the insulating film layer includes:

Provide an insulating material layer and a stamping die, the stamping die is provided with a stamping part, and the stamping part has the same shape as the rewiring structure;

The insulating material layer is punched by the punching portion of the punching die, and the hollow portion is formed on the insulating material layer to obtain the insulating film layer.

In one embodiment, before the insulating film layer provided with the hollow portion is sleeved on the redistribution structure, the semiconductor packaging method further includes:

An optical locator is used to locate the insulating film layer.

In one embodiment, forming the encapsulation structure includes:

Mounting the chip on the carrier board with the front side of the chip facing the surface of the carrier board;

forming an encapsulation layer, the encapsulation layer covers the carrier board and encapsulates the chip;

The carrier plate is peeled off to obtain the encapsulated structure.

In one embodiment, the redistribution structure is in direct contact with the pads of the chip; or,

Before forming the redistribution structure on the encapsulation structure, the semiconductor packaging method further includes:

At least one trace layer is formed on the encapsulation layer, and the redistribution structure is electrically connected to the pads of the chip through the at least one trace layer.

In one embodiment, the size of the insulating film layer is larger than the size of the encapsulation structure, and the semiconductor packaging method further includes:

Cutting the edge of the insulating film layer, so that the orthographic projection of the insulating film layer after cutting on the encapsulation structure all falls on the encapsulation structure.

The main technical effects achieved by the embodiments of the present application are:

In the semiconductor packaging method provided by the embodiments of the present application, after the rewiring structure is formed, the pre-prepared insulating film layer is sleeved on the rewiring structure, and the insulating film layer is exposed on the surface of the rewiring structure facing away from the chip, so it is not necessary to install the insulating film Grinding the insulating film layer can save the time of grinding the insulating film layer, improve the packaging efficiency, and reduce the production cost; at the same time, it can avoid the problem of poor thickness uniformity of the insulating film layer caused by the grinding process, and can avoid grinding to conductive structure, the stress on the conductive structure damages the pads of the chip, which helps to improve the quality of the packaged products.

Description of drawings

FIG. 1 is a flowchart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

FIG. 2 is a flowchart of forming an encapsulation structure provided by an exemplary embodiment of the present application;

3 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

4 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided by an exemplary embodiment of the present application;

5 is a schematic structural diagram of an encapsulation structure provided by an exemplary embodiment of the present application;

6 is a cross-sectional view of a third intermediate structure of a semiconductor package structure provided by another exemplary embodiment of the present application;

7 is a cross-sectional view of a semiconductor package structure provided by an exemplary embodiment of the present application;

8 is a cross-sectional view of an insulating film layer provided by an exemplary embodiment of the present application;

9 is a cross-sectional view of an insulating material layer provided by an exemplary embodiment of the present application;

10 is a cross-sectional view of a stamping die provided by an exemplary embodiment of the present application;

FIG. 11 is a cross-sectional view of a semiconductor package structure provided by another exemplary embodiment of the present application.

specific embodiment

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, the same numerals in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as recited in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information without departing from the scope of the present application. Depending on the context, the word "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determining."

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.

Embodiments of the present application provide a semiconductor packaging method. Referring to FIG. 1 , the semiconductor packaging method includes the following steps 110 to 130 .

In step 110, an encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and at least one chip, the encapsulation layer is provided with at least one concave cavity, and the at least one chip is disposed on the at least one chip. In a concave cavity, the encapsulation layer is exposed on the front side of the chip, and the front side of the chip is provided with a plurality of bonding pads.

In step 120, a redistribution structure is formed on the encapsulation structure, and the redistribution structure leads out the bonding pads of the chip.

In step 130, an insulating film layer provided with a hollow portion is sleeved on the redistribution structure, and the surface of the redistribution structure facing away from the chip is exposed to the insulating film layer through the hollow portion.

In the semiconductor packaging method provided by the embodiment of the present application, the insulating film layer is prepared in advance, the insulating film layer is sleeved on the rewiring structure, and the insulating film layer is exposed on the surface of the rewiring structure away from the chip, so there is no need for the insulating film layer. The grinding process can save the time of grinding the insulating film, improve the packaging efficiency, and reduce the production cost; at the same time, it can avoid the problem of poor thickness uniformity of the insulating film caused by the grinding process, and can avoid grinding to the conductive structure during grinding , the stress on the conductive structure damages the pads of the chip, which helps to improve the quality of the packaged products.

Each step of the semiconductor packaging method provided by the embodiments of the present application will be described in detail below.

In step 110, an encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and at least one chip, the encapsulation layer is provided with at least one concave cavity, and the at least one chip is disposed on the at least one chip. In a concave cavity, the encapsulation layer is exposed on the front side of the chip, and the front side of the chip is provided with a plurality of bonding pads.

In one embodiment, the concave cavity on the encapsulation layer and the chip can be in one-to-one correspondence, and the chip is located in the corresponding concave cavity.

In one embodiment, referring to FIG. 2 , the step 110 of forming the encapsulation structure includes the following steps 111 to 113 .

In step 111, the chip is mounted on the carrier board, and the front side of the chip faces the surface of the carrier board.

Through step 111, the first intermediate structure shown in FIG. 3 can be obtained. In the embodiment shown in FIG. 3 , a plurality of chips 20 are mounted on the carrier board 10 . In other embodiments, the number of chips 20 mounted on the carrier board 10 may be one.

In one embodiment, carrier 10 includes a placement area for mounting chips 20 . The shape of the mounting area is designed according to the layout of the chips 20 on the entire carrier board 10 , and the shape of the mounting area may include a circle, a rectangle or other shapes. The carrier board may include multiple placement areas.

In one embodiment, the chip 20 may be obtained by dicing a silicon wafer. The silicon wafer has an active surface, and the active surface of the silicon wafer is provided with a solder pad. The silicon wafer can be cut by mechanical cutting or laser cutting. Optionally, before cutting the silicon wafer, grinding equipment may be used to grind the backside of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.

The bonding pads of the chip 20 are formed by conductive electrodes drawn from the internal circuit of the chip to the surface of the chip. The front side of the chip 20 may be provided with a plurality of bonding pads. The bonding pads are arranged on the conductive electrodes of the chip 20 and are used to lead out the conductive electrodes of the chip 20 .

In one embodiment, the shape of the carrier plate 10 may be circular, rectangular or other shapes. The material of the carrier plate 10 may be an iron-nickel constant expansion alloy, or the material of the carrier plate 10 may also be stainless steel, polymer, or the like.

In one embodiment, the chip 20 can be mounted on the carrier board 10 through an adhesive layer, and the adhesive layer can be made of an easily peelable material, so that the chip 20 can be peeled off from the carrier board 10 later, for example, the adhesive layer can be A thermal separation material that can lose its viscosity by heating is used.

In one embodiment, before the step 111 of mounting the chip on the carrier board, the semiconductor packaging method further includes: forming a protective layer on the front surface of the chip.

In the subsequent step 112 of forming the encapsulation layer 30 , since the encapsulation layer 30 needs to be formed under high pressure, the encapsulation material forming the encapsulation layer 30 can easily penetrate between the carrier 10 and the chip 20 during this process. By forming a protective layer on the front side of the chip 20 , the protective layer can prevent the encapsulation material from penetrating into the surface of the chip 20 , and even if the encapsulation material penetrates into the protective layer when the encapsulation layer 30 is formed, there is no difference between the carrier 10 and the chip 20 . After peeling off, the surface of the protective layer can be directly processed by chemical method or grinding method without directly contacting the front side of the chip 20 , thereby avoiding damage to the bonding pads on the front side of the chip 20 .

In step 112, an encapsulation layer is formed, and the encapsulation layer covers the carrier board and encapsulates the chip.

Through step 112, the second intermediate structure as shown in FIG. 4 can be obtained.

Referring to FIG. 4 , the encapsulation layer 30 is formed on the chip 20 and the exposed carrier 10 for encapsulating the chip 20 to reconstruct a flat structure, so that after the carrier 10 is peeled off, the reconstruction can be continued. rewiring and packaging on this flat panel structure.

In one embodiment, before the encapsulation layer 30 is formed, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities on the surfaces of the chip 20 and the carrier 10, so that the encapsulation layer 30 and the chip 20 and the carrier board 10 can be connected more closely without delamination or cracking.

In one embodiment, the encapsulation layer 30 may be formed by laminating epoxy resin films, or may be formed by injection molding, compression molding, or transfer molding of epoxy resin compounds.

In one embodiment, the step 120 of forming the encapsulation layer may include the steps of:

First, an encapsulation structure is formed, the encapsulation structure covers the carrier board, and covers the chip. In this step, the thickness of the encapsulation structure is greater than the thickness of the chip 20 , so that the encapsulation structure completely encapsulates the chip 20 .

After that, thinning is performed on the side of the encapsulation structure away from the carrier to obtain the encapsulation layer. In this step, the encapsulation structure may be thinned by a grinding process to reduce the encapsulation structure to a specified thickness.

In step 113, the carrier plate is peeled off to obtain the encapsulation structure.

Through step 113, the encapsulation structure shown in FIG. 5 can be obtained.

In one embodiment, the carrier 10 may be mechanically peeled directly from the encapsulation layer 30 and the chip 20 . In another embodiment, the chip 20 and the carrier 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer can also be heated to make the adhesive layer sticky after being heated. lower, and the carrier plate 10 is further peeled off. After the carrier board 10 is peeled off, the front surfaces of the respective chips 20 are exposed.

In one embodiment, when a protective layer is formed on the front surface of the at least one chip 20 , the protective layer is provided with openings for exposing the bonding pads on the front surface of each chip 20 .

In step 120, a redistribution structure is formed on the encapsulation structure, and the redistribution structure leads out the bonding pads of the chip.

Through step 120, the third intermediate structure shown in FIG. 6 can be obtained.

In one embodiment, referring to FIG. 6 , the redistribution structure 40 includes a plurality of conductive structures 41 , and the conductive structures 41 include a trace structure 411 electrically connected to the pads of the chip 20 and located on the trace structure 411 The conductive bumps 412 on the side facing away from the chip 20 . The trace structure 411 is electrically connected to the pads of the chip 20 to lead out the pads of the chip 20, and the conductive bumps 412 are arranged to facilitate electrical connection with other components.

In one embodiment, when the redistribution structure is formed, the trace structure 411 is first formed on the encapsulation structure, and then the conductive bump 412 is formed on the trace structure 411 . In some embodiments, the trace structures 411 and the conductive bumps 412 may be formed by means of metal sputtering, electrolytic plating, electroless plating, or the like.

In step 130, an insulating film layer provided with a hollow portion is sleeved on the redistribution structure, and the surface of the redistribution structure facing away from the chip is exposed to the insulating film layer through the hollow portion.

Through step 130, the semiconductor package structure shown in FIG. 7 can be obtained. The insulating film layer 50 is used to protect the redistribution structure 40 and prevent the redistribution structure 40 from being damaged to affect the electrical connection between the redistribution structure 40 and other components.

In one embodiment, the insulating film layer 50 may be one or more layers of insulating materials, and the material of the insulating film layer 50 may be plastic film, PI (polyimide), PBO (polybenzoxazole), organic Polymer films, organic polymer composites, or other materials with similar properties. In one embodiment, organic or inorganic fillers may also be added to the insulating film layer material.

In the embodiment of the present application, the surface of the rewiring structure 40 facing away from the chip 20 exposing the insulating film layer 50 means that the surface of the rewiring structure 40 facing away from the chip 20 is flush with the surface of the insulating film layer 50 facing away from the chip 20, or the rewiring structure The distance from the surface of 40 away from the chip 20 to the encapsulation structure is slightly greater than the distance from the surface of the insulating film layer 50 away from the chip 20 to the encapsulation structure. This can facilitate the electrical connection of the redistribution structure 40 with other components.

In one embodiment, the height difference between the side of the redistribution structure 40 away from the encapsulation structure and the side of the insulating film layer 50 away from the encapsulation structure ranges from 0 to 40 μm. This arrangement can avoid that the height difference between the surface of the redistribution structure 40 facing away from the encapsulation structure and the surface of the insulating film layer 50 facing away from the encapsulation structure is too large, which may lead to rewiring when other redistribution structures are subsequently formed on the insulating film layer. The structure is broken, or the resulting semiconductor package structure surface has poor flatness. In some embodiments, the range of the height difference between the side of the redistribution structure 40 away from the encapsulation structure and the side of the insulating film layer 50 away from the encapsulation structure is, for example, 0, 10 μm, 20 μm, 30 μm, 40 μm, etc. .

In one embodiment, referring to FIG. 8 , the insulating film layer 50 is provided with a plurality of the hollow portions 51 , the hollow portions 51 correspond to the conductive structures 41 one-to-one, and the conductive structures 41 face away from the One side of the chip 20 is exposed through the corresponding hollow portion 51 . In this way, each conductive structure 41 can be exposed through the corresponding hollow portion 51 .

In one embodiment, the inner surface of the hollow portion 51 is provided with a stepped structure 511 , and the trace structure 411 is located in the hollow portion 51 and on the side of the stepped structure 511 close to the chip. The conductive protrusions 412 are located in the hollow portion 51 and surrounded by the stepped structure 511 . The sidewall of the trace structure 411 can be attached to the inner surface of the hollow portion 51 , and the sidewall of the conductive bump 412 can be attached to the wall of the stepped structure 511 , so that the insulating film layer 50 is sheathed on the conductive structure 41 and then the insulating film layer is 50 does not move relative to conductive structure 41 .

In some embodiments, in a direction parallel to the extending direction of the insulating film layer, the size of the trace structure 411 is larger than the size of the conductive bump 412 , and the hollow portion 51 is located at the portion of the step structure 511 facing the chip 10 side. The size is larger than the size of the part enclosed by the step structure 511 , and the orthographic projection of the part enclosed by the step structure 511 on the encapsulation structure completely falls on the part located on the side of the step structure 511 facing the chip 10 on the encapsulation structure in the orthographic projection.

In one embodiment, the material of the insulating film layer 50 is a flexible material. The material of the insulating film layer 50 is, for example, an organic insulating material. By setting the insulating film layer 50 to be a flexible material, the insulating film layer 50 has a certain elasticity, and the hollow portion 51 of the insulating film layer 50 is more easily sleeved on the corresponding conductive structure 41 .

In one embodiment, before the step 130 of wrapping the insulating film layer provided with the hollow portion on the redistribution structure, the semiconductor packaging method further includes: preparing the insulating film layer.

In some embodiments, the preparing the insulating film layer includes the following steps:

First, an insulating material layer and a stamping die are provided, the stamping die is provided with a stamping portion, and the stamping portion has the same shape as the rewiring structure.

Referring to FIG. 9 , the insulating material layer 60 is not provided with hollows, that is, the insulating material layer is a complete film layer. In some embodiments, when forming the insulating material layer, a carrier may be provided, and the insulating material layer 60 may be formed on the carrier by lamination, spin coating, printing, molding or other suitable methods, and then the carrier may be peeled off .

Referring to FIG. 10 , the stamping die 70 includes a body 71 and a plurality of stamping parts 72 disposed on one side of the body 71 . The body 71 may have a plate shape. The plurality of stamping parts 72 correspond to the plurality of conductive structures 41 one-to-one. The stamping part 72 includes a first stamping part 721 and a second stamping part 722 located on one side of the first stamping part 721 . The first stamping part 721 can be connected with the trace structure. The shape and size of the 411 are the same, and the shape and size of the second stamping part 722 can be the same as that of the conductive bump 412 . The first stamping part 721 is connected to the body 71 , and the second stamping part 722 is located on the side of the first stamping part 721 away from the body 71 .

Then, the insulating material layer is punched by the punching part of the punching die, and the hollow part is formed on the insulating material layer to obtain the insulating film layer.

Through the above steps, the insulating film layer as shown in FIG. 7 can be obtained.

When the insulating material layer 60 is punched by the punching part 72 of the punching die, part of the material of the insulating material layer will be lost, so the size of the hollow part 51 formed on the insulating material layer 60 is slightly larger than the size of the conductive structure 41 , so that the conductive structure 41 It can be accommodated in the hollow part 51 .

In one embodiment, before the step 130 of wrapping the insulating film layer provided with the hollow portion on the redistribution structure, the semiconductor packaging method further includes: using an optical locator to position the insulating film layer .

By using an optical locator to locate the insulating film layer 50 , the hollow portion 51 of the insulating film layer 50 and the corresponding conductive structure 41 can be aligned more accurately, and the alignment of the hollow portion 51 of the insulating film layer 50 with the corresponding conductive structure 41 can be avoided. The inaccuracy of the bit leads to the problem that the insulating film layer 50 cannot be placed on the redistribution structure 40 .

In the semiconductor package structure shown in FIG. 7 , the redistribution structure 40 is in direct contact with the pads of the chip 20 . In other embodiments, before forming a redistribution structure on the encapsulation structure, the semiconductor packaging method further includes:

At least one trace layer is formed on the encapsulation layer, and the redistribution structure is electrically connected to the pads of the chip through the at least one trace layer.

That is, at least one trace layer is formed between the redistribution structure 40 and the encapsulation structure. An insulating film layer can be sleeved on each trace layer, and a conductive bump is formed on the side of each trace layer away from the encapsulation structure, and the surface of the conductive bump away from the encapsulation structure exposes the corresponding insulating film layer. For the steps of forming the trace layer, the conductive bumps and the insulating film layer on the trace layer, reference may be made to the description of steps 120 and 130, and details are not repeated here.

Referring to FIG. 11 , a trace layer 81 and a conductive bump 82 located on the side of the trace layer 81 away from the encapsulation structure are formed between the redistribution structure 40 and the encapsulation structure. The trace layer 82 and the conductive bump 82 are sleeved on the trace layer 82 . There is an insulating film layer 83 , and the surface of the conductive bump 82 facing away from the encapsulation structure is exposed through the hollow portion 831 on the insulating film layer 83 and is electrically connected to the conductive structure 41 . FIG. 11 only takes as an example that one trace layer is formed between the redistribution structure 40 and the encapsulation structure. In other embodiments, multiple trace layers may be formed between the redistribution structure 40 and the encapsulation structure.

By covering each trace layer with an insulating film layer, and exposing the insulating film layer on the surface of the re-wiring structure away from the chip, it is not necessary to grind the insulating film layer corresponding to each trace layer, which can save the need for the insulating film layer. The grinding time improves the packaging efficiency and reduces the production cost; at the same time, it can avoid the problem of poor thickness uniformity of the insulating film caused by the grinding process, and avoid the conductive structure being ground during grinding and stressing the conductive structure and damaging the soldering of the chip. pads, which help to improve the quality of packaged products.

In one embodiment, the size of the insulating film layer is larger than the size of the encapsulation structure, and the semiconductor packaging method further includes:

Cutting the edge of the insulating film layer, so that the orthographic projection of the insulating film layer after cutting on the encapsulation structure all falls on the encapsulation structure.

By cutting the edge of the insulating film layer, the edge of the insulating film layer can be kept from exceeding the encapsulation structure, so that the appearance of the obtained semiconductor package structure is more regular.

In one embodiment, the encapsulation structure includes two or more chips, and the semiconductor encapsulation method further includes: cutting the semiconductor encapsulation structure obtained in the above steps to obtain a plurality of sub-package structures, each sub-package structure Only one chip is included.

In some embodiments, the process of dicing the semiconductor package structure and the process of dicing the edge of the insulating film layer may be performed simultaneously.

It should be noted that the drawings provided in the embodiments of the present application are only schematic, and there may be some differences with the actual structure. For example, the solder pads on the front of the chip are not shown in the drawings. In practice, the solder pads on the front of the chip are electrically connected to the rewiring structure. connect.

It should be noted that, in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or more than one intervening layer or element may be present. In addition, it will also be understood that when a layer or element is referred to as being 'between' two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer may also be present or components. Like reference numerals indicate like elements throughout.

Other embodiments of the present application will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses or adaptations of this application that follow the general principles of this application and include common knowledge or conventional techniques in the technical field not disclosed in this application . The specification and examples are to be regarded as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise structures described above and illustrated in the accompanying drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. a semiconductor packaging method, is characterized in that, comprises: An encapsulation structure is formed, the encapsulation structure includes an encapsulation layer and at least one chip, the encapsulation layer is provided with at least one concave cavity, and the at least one chip is disposed in the at least one concave cavity In the body, the encapsulation layer is exposed on the front side of the chip, and the front side of the chip is provided with a plurality of bonding pads; forming a redistribution structure on the encapsulation structure, the redistribution structure leading out the pads of the chip; The insulating film layer provided with the hollow part is sleeved on the redistribution structure, and the surface of the redistribution structure facing away from the chip is exposed to the insulating film layer through the hollow part. 2 . The semiconductor packaging method according to claim 1 , wherein a height difference between a side of the redistribution structure facing away from the encapsulation structure and a side of the insulating film layer facing away from the encapsulation structure is equal to 2 . The range is 0 to 40 μm. 3 . The semiconductor packaging method according to claim 1 , wherein the redistribution structure comprises a plurality of conductive structures, the insulating film layer is provided with a plurality of the hollow parts, and the hollow parts are connected to the hollow parts. 4 . The conductive structures are in one-to-one correspondence, and the side of the conductive structures facing away from the chip is exposed through the corresponding hollow portion. 4. The semiconductor packaging method according to claim 3, wherein the conductive structure comprises a trace structure connected to the bonding pad and a conductive bump located on a side of the trace structure away from the chip; The inner surface of the hollow portion is provided with a stepped structure, the trace structure is located in the hollow portion and is located on the side of the stepped structure close to the chip, the conductive protrusion is located in the hollow portion and is The step structure surrounds. 5 . The semiconductor packaging method according to claim 1 , wherein the material of the insulating film layer is a flexible material. 6 . 6 . The semiconductor packaging method according to claim 1 , wherein, before the insulating film layer provided with the hollow portion is sleeved on the redistribution structure, the semiconductor packaging method further comprises: preparing the insulating film. 7 . film layer; The preparing the insulating film layer includes: Provide an insulating material layer and a stamping die, the stamping die is provided with a stamping part, and the stamping part has the same shape as the rewiring structure; The insulating material layer is punched by the punching portion of the punching die, and the hollow portion is formed on the insulating material layer to obtain the insulating film layer. 7 . The semiconductor packaging method according to claim 1 , wherein before the insulating film layer provided with the hollow portion is sleeved on the redistribution structure, the semiconductor packaging method further comprises: 8 . An optical locator is used to locate the insulating film layer. 8. The semiconductor packaging method according to claim 1, wherein the forming the encapsulation structure comprises: Mounting the chip on a carrier board with the front side of the chip facing the surface of the carrier board; forming an encapsulation layer, the encapsulation layer covers the carrier board and encapsulates the chip; The carrier plate is peeled off to obtain the encapsulated structure. 9 . The semiconductor packaging method according to claim 1 , wherein the redistribution structure is in direct contact with the bonding pads of the chip; or, Before forming the redistribution structure on the encapsulation structure, the semiconductor packaging method further includes: At least one trace layer is formed on the encapsulation layer, and the redistribution structure is electrically connected to the pads of the chip through the at least one trace layer. 10 . The semiconductor packaging method according to claim 1 , wherein the size of the insulating film layer is larger than the size of the packaging structure, and the semiconductor packaging method further comprises: 11 . The edge of the insulating film layer is cut, so that the orthographic projection of the insulating film layer after cutting on the encapsulation structure all falls on the encapsulation structure.

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