CN114582736A

CN114582736A - Semiconductor packaging method

Info

Publication number: CN114582736A
Application number: CN202011378925.1A
Authority: CN
Inventors: 涂旭峰; 霍炎
Original assignee: SIPLP Microelectronics Chongqing Ltd
Current assignee: SIPLP Microelectronics Chongqing Ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2022-06-03

Abstract

The application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps: forming an encapsulation structure, wherein the encapsulation structure comprises an encapsulation layer and at least one chip, at least one concave cavity is arranged on the encapsulation layer, the at least one chip is arranged in the at least one concave cavity, the encapsulation layer is exposed out of the front surface of the chip, and a plurality of welding pads are arranged on the front surface of the chip; forming a rewiring structure on the packaging structure, wherein the rewiring structure leads out a welding pad of the chip; and sleeving the insulating film layer provided with the hollow part on the rewiring structure, wherein the surface of the rewiring structure departing from the chip is exposed out of the insulating film layer through the hollow part.

Description

Semiconductor packaging method

Technical Field

The present disclosure relates to semiconductor technologies, and in particular, to a semiconductor packaging method.

Background

The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: for the process of carrying out the process treatment on the front surface of the chip, firstly, the front surface of the chip is attached to a carrier plate, hot-press plastic package is carried out, the carrier plate is peeled off, then a rewiring structure is formed on the front surface of the chip, then, an insulating layer for protecting the rewiring structure is formed on the rewiring structure, and the surface of the rewiring structure, which is deviated from the chip, is exposed out of the insulating layer.

In the conventional chip packaging technology, when an insulating layer is formed on a rewiring structure, the initially formed insulating layer covers the rewiring structure completely, and then the insulating layer is ground to reduce the thickness of the insulating layer, so that the surface of the rewiring structure, which is away from a chip, is exposed. However, the grinding process is time consuming and affects the packaging efficiency.

Disclosure of Invention

The embodiment of the application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps:

forming an encapsulation structure, wherein the encapsulation structure comprises an encapsulation layer and at least one chip, at least one concave cavity is arranged on the encapsulation layer, the at least one chip is arranged in the at least one concave cavity, the encapsulation layer is exposed out of the front surface of the chip, and a plurality of welding pads are arranged on the front surface of the chip;

forming a rewiring structure on the packaging structure, wherein the rewiring structure leads out a welding pad of the chip;

and sleeving an insulating film layer in the at least one concave cavity on the rewiring structure, wherein the rewiring structure deviates from the surface of the chip and is exposed out of the insulating film layer through the hollow part.

In one embodiment, a height difference between a side of the rewiring structure facing away from the encapsulation structure and a side of the insulating film layer facing away from the encapsulation structure ranges from 0 to 40 μm.

In one embodiment, the rewiring structure includes a plurality of conductive structures, a plurality of the hollow portions are arranged on the insulating film layer, the hollow portions correspond to the conductive structures one to one, and one side of each conductive structure, which is away from the chip, is exposed through the corresponding hollow portion.

In one embodiment, the conductive structure comprises a trace structure connected with the welding pad and a conductive convex column positioned at one side of the trace structure, which faces away from the chip;

the inner surface of the hollow part is provided with a step structure, the trace structure is positioned in the hollow part and on one side of the step structure close to the chip, and the conductive convex column is positioned in the hollow part and surrounded by the step structure.

In one embodiment, the material of the insulating film layer is a flexible material.

In one embodiment, before the step of sleeving the insulating film layer provided with the hollowed-out portion on the re-wiring structure, the semiconductor packaging method further includes: preparing the insulating film layer;

the preparing the insulating film layer includes:

providing an insulating material layer and a stamping die, wherein the stamping die is provided with a stamping part, and the stamping part and the rewiring structure have the same shape;

and stamping the insulating material layer by adopting the stamping part of the stamping die, and forming the hollow part on the insulating material layer to obtain the insulating film layer.

In one embodiment, before the step of sleeving the insulating film layer provided with the hollowed-out portion on the re-wiring structure, the semiconductor packaging method further includes:

and positioning the insulating film layer by adopting an optical positioning instrument.

In one embodiment, the forming an encapsulated structure comprises:

the chip is attached to a carrier plate, and the front surface of the chip faces to the surface of the carrier plate;

forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and encapsulates the chip;

and peeling off the carrier plate to obtain the packaging structure.

In one embodiment, the re-routing structure is in direct contact with a pad of the chip; or,

before the forming of the rewiring structure on the encapsulating structure, the semiconductor packaging method further includes:

at least one trace layer is formed on the encapsulation layer, and the rewiring structure is electrically connected with the bonding pad of the chip through the at least one trace layer.

In one embodiment, the size of the insulating film layer is larger than the size of the encapsulation structure, and the semiconductor packaging method further includes:

and cutting the edge of the insulating film layer so that the orthographic projection of the cut insulating film layer on the encapsulating structure is totally fallen on the encapsulating structure.

The embodiment of the application achieves the main technical effects that:

according to the semiconductor packaging method provided by the embodiment of the application, after the rewiring structure is formed, the pre-prepared insulating film layer is sleeved on the rewiring structure, and the insulating film layer is exposed on the surface of the rewiring structure, which is far away from the chip, so that the insulating film layer does not need to be ground, the time for grinding the insulating film layer can be saved, the packaging efficiency is improved, and the production cost is reduced; meanwhile, the problem of poor thickness uniformity of the insulating film layer caused by a grinding process can be avoided, and the phenomenon that the conductive structure is ground during grinding, so that the stress of the conductive structure damages the welding pad of the chip can be avoided, and the quality of a packaged product can be improved.

Drawings

FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;

FIG. 2 is a flow chart of forming an encapsulated structure provided by an exemplary embodiment of the present application;

fig. 3 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

fig. 4 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;

FIG. 5 is a schematic structural diagram of an encapsulation structure provided by an exemplary embodiment of the present application;

fig. 6 is a cross-sectional view of a third intermediate structure of a semiconductor package structure provided in another exemplary embodiment of the present application;

fig. 7 is a cross-sectional view of a semiconductor package structure provided in an exemplary embodiment of the present application;

FIG. 8 is a cross-sectional view of an insulating film layer provided by an exemplary embodiment of the present application;

FIG. 9 is a cross-sectional view of a layer of insulating material provided in accordance with an exemplary embodiment of the present application;

FIG. 10 is a cross-sectional view of a stamping die provided in accordance with an exemplary embodiment of the present application;

fig. 11 is a cross-sectional view of a semiconductor package structure provided in another exemplary embodiment of the present application.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 130.

In step 110, an encapsulation structure is formed, where the encapsulation structure includes an encapsulation layer and at least one chip, the encapsulation layer is provided with at least one concave cavity, the at least one chip is disposed in the at least one concave cavity, the encapsulation layer is exposed from the front surface of the chip, and the front surface of the chip is provided with a plurality of bonding pads.

In step 120, a rewiring structure is formed on the encapsulation structure, and the rewiring structure leads out a bonding pad of the chip.

In step 130, an insulating film layer provided with a hollow portion is sleeved on the rewiring structure, and the surface of the rewiring structure departing from the chip is exposed out of the insulating film layer through the hollow portion.

According to the semiconductor packaging method provided by the embodiment of the application, the insulating film layer is prepared in advance, the insulating film layer is sleeved on the rewiring structure, and the surface of the rewiring structure, which is far away from the chip, is exposed out of the insulating film layer, so that the insulating film layer is not required to be ground, the time for grinding the insulating film layer can be saved, the packaging efficiency is improved, and the production cost is reduced; meanwhile, the problem of poor thickness uniformity of the insulating film layer caused by a grinding process can be avoided, and the phenomenon that the conductive structure is ground during grinding, so that the stress of the conductive structure damages the welding pad of the chip can be avoided, and the quality of a packaged product can be improved.

The steps of the semiconductor packaging method provided by the embodiments of the present application will be described in detail below.

In step 110, an encapsulation structure is formed, where the encapsulation structure includes an encapsulation layer and at least one chip, the encapsulation layer is provided with at least one recessed cavity, the at least one chip is disposed in the at least one recessed cavity, the encapsulation layer is exposed at the front surface of the chip, and the front surface of the chip is provided with a plurality of bonding pads.

In one embodiment, the recessed cavities on the encapsulating layer correspond to the chips one by one, and the chips are located in the corresponding recessed cavities.

In one embodiment, referring to fig. 2, the step 110 of forming the encapsulation structure includes the following steps 111 to 113.

In step 111, the chip is mounted on a carrier, and the front surface of the chip faces the surface of the carrier.

A first intermediate structure as shown in fig. 3 is obtained by step 111. In the embodiment shown in fig. 3, a plurality of chips 20 are mounted on the carrier 10. In other embodiments, the number of the chips 20 mounted on the carrier board 10 may be one.

In one embodiment, the carrier board 10 includes a mounting area for mounting the chip 20. The shape of the mounting area is designed according to the layout of the chips 20 on the whole carrier 10, and may include a circle, a rectangle or other shapes. The carrier plate may include a plurality of mounting regions.

In one embodiment, the chip 20 may be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.

The bonding pads of the chip 20 are formed by conductive electrodes led out from the internal circuit of the chip to the surface of the chip. The front surface of the chip 20 may be provided with a plurality of pads. The bonding pad is disposed on the conductive electrode of the chip 20, and is used for leading out the conductive electrode of the chip 20.

In one embodiment, the shape of the carrier plate 10 may be circular, rectangular or other shape. The material of the carrier plate 10 may be iron-nickel alloy, or the material of the carrier plate 10 may also be stainless steel, polymer, etc.

In one embodiment, the die 20 may be attached to the carrier 10 by an adhesive layer, and the adhesive layer may be a peelable material to peel the die 20 from the carrier 10 later, for example, the adhesive layer may be a thermal release material that can be heated to lose its adhesiveness.

In one embodiment, before the step 111 of mounting the chip on a carrier board, the semiconductor packaging method further includes: and forming a protective layer on the front surface of the chip.

In the subsequent step 112 of forming the encapsulating layer 30, since the encapsulating layer 30 needs to be formed under high pressure during the forming process, the encapsulating material forming the encapsulating layer 30 easily penetrates between the carrier 10 and the chip 20. By forming a protection layer on the front surface of the chip 20, the protection layer can prevent the encapsulating material from penetrating into the surface of the chip 20, and even if the encapsulating material penetrates into the protection layer when the encapsulating layer 30 is formed, after the carrier plate 10 is peeled off from the chip 20, the surface of the protection layer can be directly treated by a chemical method or a grinding method without directly contacting the front surface of the chip 20, so that the bonding pad on the front surface of the chip 20 can be prevented from being damaged.

In step 112, an encapsulation layer is formed, and the encapsulation layer covers the carrier and encapsulates the chip.

A second intermediate structure as shown in fig. 4 may be obtained, via step 112.

Referring to fig. 4, an encapsulation layer 30 is formed on the chip 20 and the exposed carrier 10 for encapsulating the chip 20 to reconstruct a flat plate structure, so that after the carrier 10 is peeled off, re-wiring and packaging can be continued on the reconstructed flat plate structure.

In one embodiment, before the formation of the encapsulating layer 30, some pre-treatment steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the surfaces of the chip 20 and the carrier 10, so that the connection between the encapsulating layer 30 and the chip 20 and the carrier 10 can be more intimate and no delamination or cracking occurs.

In one embodiment, the encapsulating layer 30 may be formed by laminating an epoxy resin film, or by injection molding, compression molding, or transfer molding an epoxy compound.

In one embodiment, the step 120 of forming the encapsulation layer may include the steps of:

firstly, an encapsulation structure is formed, and the encapsulation structure covers the carrier plate and coats the chip. In this step, the thickness of the encapsulation structure is greater than the thickness of the chip 20, so that the encapsulation structure completely encapsulates the chip 20.

And then, thinning one side of the encapsulating structure, which is far away from the carrier plate, to obtain the encapsulating layer. In this step, the encapsulating structure may be thinned to a specified thickness by performing a thinning process on the encapsulating structure through a grinding process.

In step 113, the carrier is peeled off to obtain the encapsulation structure.

An encapsulated structure as shown in fig. 5 may be obtained through step 113.

In one embodiment, the carrier plate 10 can be mechanically peeled off from the encapsulating layer 30 and the chip 20 directly. In another embodiment, the chip 20 and the carrier 10 are bonded by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity, so as to peel off the carrier 10. After the carrier board 10 is peeled off, the front surface of each chip 20 is exposed.

In one embodiment, when the front surface of the at least one chip 20 is formed with the protection layer, the protection layer is provided with an opening for exposing the pad on the front surface of each chip 20.

A third intermediate structure as shown in fig. 6 is obtained by step 120.

In one embodiment, referring to fig. 6, the redistribution structure 40 includes a plurality of conductive structures 41, and each conductive structure 41 includes a trace structure 411 electrically connected to a pad of the chip 20 and a conductive pillar 412 located on a side of the trace structure 411 facing away from the chip 20. The trace structure 411 is electrically connected to a pad of the chip 20, the pad of the chip 20 is led out, and the conductive pillar 412 is disposed to facilitate electrical connection with other components.

In one embodiment, in forming the rewiring structure, the trace structure 411 is first formed on the encapsulation structure, followed by forming the conductive posts 412 on the trace structure 411. In some embodiments, the trace structure 411 and the conductive posts 412 can be formed by metal sputtering, electrolytic plating, electroless plating, and the like.

The semiconductor package structure shown in fig. 7 can be obtained through step 130. The insulating film layer 50 is used to protect the redistribution structure 40 and prevent the redistribution structure 40 from being damaged and affecting the electrical connection between the redistribution structure 40 and other components.

In one embodiment, the insulating film layer 50 may be one or more layers of insulating materials, and the material of the insulating film layer 50 may be a plastic film, PI (polyimide), PBO (polybenzoxazole), an organic polymer film, an organic polymer composite, or other materials with similar properties. In one embodiment, an organic or inorganic filler may also be added to the insulating film layer material.

In the embodiment of the present application, the surface of the re-wiring structure 40 facing away from the chip 20 exposes the insulating film layer 50, which means that the surface of the re-wiring structure 40 facing away from the chip 20 is flush with the surface of the insulating film layer 50 facing away from the chip 20, or the distance from the surface of the re-wiring structure 40 facing away from the chip 20 to the encapsulation structure is slightly greater than the distance from the surface of the insulating film layer 50 facing away from the chip 20 to the encapsulation structure. This may facilitate electrical connection of the rewiring structure 40 to other components.

In one embodiment, the height difference between the side of the rewiring structure 40 facing away from the encapsulation structure and the side of the insulating film layer 50 facing away from the encapsulation structure ranges from 0 to 40 μm. With such an arrangement, it can be avoided that the height difference between the surface of the rewiring structure 40 departing from the encapsulation structure and the surface of the insulating film layer 50 departing from the encapsulation structure is too large, which may result in the breakage of the rewiring structure when other rewiring structures are formed on the insulating film layer in the following process, or result in poor flatness of the surface of the obtained semiconductor package structure. In some embodiments, the height difference between the side of the rewiring structure 40 facing away from the encapsulation structure and the side of the insulating film layer 50 facing away from the encapsulation structure ranges, for example, from 0, 10 μm, 20 μm, 30 μm, 40 μm, and the like.

In an embodiment, referring to fig. 8, a plurality of the hollow portions 51 are disposed on the insulating film layer 50, the hollow portions 51 correspond to the conductive structures 41 one by one, and one side of the conductive structure 41 away from the chip 20 is exposed through the corresponding hollow portions 51. In this way, each conductive structure 41 can be exposed through the corresponding hollow portion 51.

In one embodiment, the inner surface of the hollow portion 51 is provided with a step structure 511, the trace structure 411 is located in the hollow portion 51 and located on one side of the step structure 511 close to the chip, and the conductive pillar 412 is located in the hollow portion 51 and surrounded by the step structure 511. The sidewall of the trace structure 411 may be attached to the inner surface of the hollow portion 51, and the sidewall of the conductive pillar 412 may be attached to the wall of the step structure 511, so that the insulating film 50 does not move relative to the conductive structure 41 after the insulating film 50 is sleeved on the conductive structure 41.

In some embodiments, in a direction parallel to the extending direction of the insulating film, the size of the trace structure 411 is greater than that of the conductive stud 412, the size of the portion of the hollow portion 51 located on the side of the step structure 511 facing the chip 10 is greater than that of the portion enclosed by the step structure 511, and an orthogonal projection of the portion enclosed by the step structure 511 on the encapsulation structure completely falls within an orthogonal projection of the portion located on the side of the step structure 511 facing the chip 10 on the encapsulation structure.

In one embodiment, the material of the insulating film layer 50 is a flexible material. The material of the insulating film layer 50 is, for example, an organic insulating material. Through setting up insulating film 50 for flexible material, insulating film 50 has certain elasticity, and the fretwork portion 51 of insulating film 50 overlaps more easily on corresponding conductive structure 41.

In one embodiment, before the step 130 of sleeving the insulating film layer provided with the hollow portion on the re-wiring structure, the semiconductor packaging method further includes: and preparing the insulating film layer.

In some embodiments, the preparing the insulating film layer includes the steps of:

first, an insulating material layer and a stamping die are provided, wherein the stamping die is provided with a stamping part, and the stamping part and the rewiring structure are the same in shape.

Referring to fig. 9, the insulating material layer 60 is not provided with a hollow-out, that is, the insulating material layer is a complete film layer. In some embodiments, in forming the layer of insulating material, a carrier plate may be provided, on which the layer of insulating material 60 is formed by lamination, spin coating, printing, molding or other suitable means, and then peeled off.

Referring to fig. 10, the press mold 70 includes a body 71 and a plurality of press parts 72 provided at one side of the body 71. The body 71 may have a plate shape. The plurality of stamping parts 72 correspond to the plurality of conductive structures 41 one by one, each stamping part 72 includes a first stamping part 721 and a second stamping part 722 located at one side of the first stamping part 721, the first stamping part 721 may have the same shape and size as the trace structure 411, and the second stamping part 722 may have the same shape and size as the conductive pillar 412. The first stamping 721 is connected to the body 71, and the second stamping 722 is located on the side of the first stamping 721 facing away from the body 71.

And then, stamping the insulating material layer by using a stamping part of the stamping die, and forming the hollow part on the insulating material layer to obtain the insulating film layer.

The insulating film layer shown in fig. 7 can be obtained through the above steps.

When the insulating material layer 60 is punched by the punching part 72 of the punching die, a part of the material of the insulating material layer is lost, so that the size of the hollow part 51 formed on the insulating material layer 60 is slightly larger than that of the conductive structure 41, so that the conductive structure 41 can be accommodated in the hollow part 51.

In one embodiment, before the step 130 of sleeving the insulating film layer provided with the hollow portion on the re-wiring structure, the semiconductor packaging method further includes: and positioning the insulating film layer by adopting an optical positioning instrument.

Through adopting the optical positioning instrument to fix a position insulating film 50, can make insulating film 50's fretwork portion 51 more accurate with the electrically conductive structure 41 counterpoint that corresponds, avoid insulating film 50's fretwork portion 51 not accurate with the electrically conductive structure 41 counterpoint that corresponds and lead to can not overlapping insulating film 50 on rewiring structure 40's problem.

In the semiconductor package structure shown in fig. 7, the re-wiring structure 40 is in direct contact with the pad of the chip 20. In other embodiments, before forming the rewiring structure on the encapsulation structure, the semiconductor packaging method further includes:

That is, at least one trace layer is formed between the rewiring structure 40 and the encapsulating structure. Can all overlap on each trace layer and be equipped with insulating rete, and each trace layer deviates from one side of encapsulating the structure and all is formed with electrically conductive projection, and the surface that electrically conductive projection deviates from encapsulating the structure exposes corresponding insulating rete. The steps of forming the trace layer, forming the conductive stud and sleeving the insulating film layer on the trace layer can be referred to the descriptions of step 120 and step 130, and are not described in detail again.

Referring to fig. 11, a trace layer 81 and a conductive protruding pillar 82 located on a side of the trace layer 81 departing from the encapsulation structure are formed between the rewiring structure 40 and the encapsulation structure, an insulating film layer 83 is sleeved on the trace layer 82 and the conductive protruding pillar 82, and a surface of the conductive protruding pillar 82 departing from the encapsulation structure is exposed through a hollow portion 831 on the insulating film layer 83 and is electrically connected with the conductive structure 41. Fig. 11 illustrates only one trace layer formed between the rewiring structure 40 and the encapsulating structure, and in other embodiments, multiple trace layers may be formed between the rewiring structure 40 and the encapsulating structure.

By sleeving the insulating film layers on the trace layers and exposing the insulating film layers on the surfaces of the rewiring structures, which are far away from the chip, the insulating film layers corresponding to the trace layers do not need to be ground, so that the time for grinding the insulating film layers can be saved, the packaging efficiency is improved, and the production cost is reduced; meanwhile, the problem that the thickness uniformity of the insulating film layer is poor due to a grinding process can be avoided, and the phenomenon that the conductive structure is ground to apply stress to the conductive structure to damage a welding pad of the chip during grinding can be avoided, so that the quality of a packaged product is improved.

The edge of the insulating film layer is cut, so that the edge of the insulating film layer does not exceed the encapsulation structure, and the appearance of the obtained semiconductor packaging structure is more regular.

In one embodiment, the encapsulation structure includes two or more chips, and the semiconductor packaging method further includes: and cutting the semiconductor packaging structure obtained in the step to obtain a plurality of sub-packaging structures, wherein each sub-packaging structure only comprises one chip.

In some embodiments, the process of cutting the semiconductor package structure and the process of cutting the edge of the insulating film layer may be performed simultaneously.

It should be noted that the drawings provided in the embodiments of the present application are only schematic and may have some differences from the actual structure, for example, the bonding pads on the front surface of the chip are not illustrated in the drawings, and the bonding pads on the front surface of the chip are electrically connected to the redistribution structure in practice.

It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A semiconductor packaging method, comprising:

and sleeving the insulating film layer provided with the hollow part on the rewiring structure, wherein the surface of the rewiring structure departing from the chip is exposed out of the insulating film layer through the hollow part.

2. The semiconductor packaging method according to claim 1, wherein a height difference between a side of the rewiring structure facing away from the encapsulating structure and a side of the insulating film layer facing away from the encapsulating structure is in a range of 0 to 40 μm.

3. The semiconductor packaging method according to claim 1, wherein the redistribution structure comprises a plurality of conductive structures, a plurality of the hollowed-out portions are arranged on the insulating film layer, the hollowed-out portions correspond to the conductive structures one to one, and one side of the conductive structure, which is away from the chip, is exposed through the corresponding hollowed-out portions.

4. The semiconductor packaging method according to claim 3, wherein the conductive structure comprises a trace structure connected to the pad and a conductive post on a side of the trace structure facing away from the chip;

5. The semiconductor packaging method according to claim 1, wherein the material of the insulating film layer is a flexible material.

6. The semiconductor packaging method according to claim 1, wherein before the step of fitting the insulating film layer provided with the hollowed-out portion over the rewiring structure, the semiconductor packaging method further comprises: preparing the insulating film layer;

the preparing the insulating film layer includes:

7. The semiconductor packaging method according to claim 1, wherein before the step of fitting the insulating film layer provided with the hollowed-out portion over the rewiring structure, the semiconductor packaging method further comprises:

8. The semiconductor packaging method of claim 1, wherein the forming an encapsulation structure comprises:

and peeling off the carrier plate to obtain the packaging structure.

9. The semiconductor packaging method according to claim 1, wherein the rewiring structure is in direct contact with a pad of the chip; or,

10. The semiconductor packaging method according to claim 1, wherein a size of the insulating film layer is larger than a size of the encapsulation structure, the semiconductor packaging method further comprising: