CN111755340A - Semiconductor packaging method and semiconductor packaging structure - Google Patents

Semiconductor packaging method and semiconductor packaging structure Download PDF

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Publication number
CN111755340A
CN111755340A CN202010621946.5A CN202010621946A CN111755340A CN 111755340 A CN111755340 A CN 111755340A CN 202010621946 A CN202010621946 A CN 202010621946A CN 111755340 A CN111755340 A CN 111755340A
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auxiliary
layer
chip
heat dissipation
carrier plate
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Chinese (zh)
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霍炎
涂旭峰
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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Priority to CN202010621946.5A priority Critical patent/CN111755340A/en
Publication of CN111755340A publication Critical patent/CN111755340A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4882—Assembly of heatsink parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method comprises the following steps: attaching at least one chip to be packaged and an auxiliary part on a carrier plate; the auxiliary piece comprises auxiliary structures which correspond to the chips one by one, each chip comprises a first surface and a second surface opposite to the first surface, the first surface faces the carrier plate, and a plurality of welding pads are arranged on the first surface; the auxiliary piece comprises a third surface and a fourth surface opposite to the third surface, the first surface and the third surface are positioned on the same side, the second surface and the fourth surface are positioned on the same side, and the third surface faces the carrier plate; forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and encapsulates the at least one chip to be encapsulated and the auxiliary piece, and the second surface and the fourth surface are exposed out of the encapsulating layer; forming a heat dissipation layer on one side of the second surface, wherein the heat dissipation layer covers the chip and the auxiliary structure; the material of the heat dissipation layer and the material of the auxiliary structure are both metal.

Description

Semiconductor packaging method and semiconductor packaging structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method and a semiconductor packaging structure.
Background
The conventional semiconductor packaging technology, such as chip packaging technology, mainly includes the following processes: the front surface of the chip is bonded on the carrier plate through the adhesive tape, hot-press plastic package is carried out, the carrier plate is peeled off, then a rewiring structure is formed on the front surface of the chip, and packaging is carried out.
In order to improve the heat dissipation performance of the chip, a metal heat dissipation layer is usually formed on the back surface of the chip during the packaging process. However, the metal heat dissipation layer is different from the chip and the encapsulation layer in material, and the lattice constants of different materials are different, so that the bonding force between the chip and the encapsulation layer and the metal heat dissipation layer is poor, and the metal heat dissipation layer, the chip and the encapsulation layer may be peeled off, thereby affecting the reliability of the product.
Disclosure of Invention
A first aspect of embodiments of the present application provides a semiconductor packaging method. The semiconductor packaging method comprises the following steps:
attaching at least one chip to be packaged and an auxiliary part on a carrier plate; the auxiliary part comprises auxiliary structures which correspond to the chips one by one, each chip comprises a first surface and a second surface opposite to the first surface, the first surface faces the carrier plate, and a plurality of welding pads are arranged on the first surface; the auxiliary part comprises a third surface and a fourth surface opposite to the third surface, the first surface and the third surface are positioned on the same side, the second surface and the fourth surface are positioned on the same side, and the third surface faces the carrier plate;
forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and encapsulates the at least one chip to be encapsulated and the auxiliary piece, and the second surface and the fourth surface are exposed out of the encapsulating layer;
forming a heat dissipation layer on one side of the second surface, wherein the heat dissipation layer covers the chip and the auxiliary structure; the material of the heat dissipation layer and the material of the auxiliary structure are both metal.
In one embodiment, the auxiliary structure is made of the same material as the heat dissipation layer.
In one embodiment, the auxiliary structure comprises an auxiliary portion, the auxiliary portion is arranged around the corresponding chip and is continuous and uninterrupted; the third surface and the fourth surface respectively expose the encapsulating layer.
In one embodiment, the auxiliary portion is spaced apart from the corresponding chip, and the heat dissipation layer covers a portion of the encapsulation layer between the chip and the auxiliary portion.
In one embodiment, the auxiliary structure further includes a plurality of pins arranged at intervals outside the auxiliary portion, and the pins are arranged at intervals with the auxiliary portion.
In one embodiment, the auxiliary structure further includes a connecting portion extending outward from the auxiliary portion, the auxiliary member further includes a frame body, and the connecting portion and the leads of the auxiliary structure are respectively connected to the frame body;
after the forming of the heat dissipation layer on the second face side, the semiconductor packaging method further includes:
and removing the frame body.
In one embodiment, the forming an encapsulation layer comprises:
forming an encapsulation structure, wherein the encapsulation structure covers the carrier plate and completely encapsulates the at least one chip to be encapsulated, the auxiliary part and the pins, and the distance from the surface of the pins departing from the carrier plate to the carrier plate is greater than the distance from the fourth surface to the carrier plate;
and thinning the packaging structure and the pins to enable the packaging structure to form the packaging layer, wherein the second surface, the surfaces of the pins departing from the carrier plate and the fourth surface are flush and exposed out of the packaging layer.
In one embodiment, the semiconductor packaging method further includes:
peeling off the carrier plate to expose the first surface and the third surface;
forming an insulating layer on one side of the first surface, wherein the insulating layer covers the chip, the auxiliary piece and the encapsulating layer;
forming a contact hole on the insulating layer, the contact hole exposing the pad;
and forming a rewiring layer for leading out the welding pad on the insulating layer.
A second aspect of an embodiment of the present application provides a semiconductor package structure, including:
the encapsulating layer is provided with at least one first accommodating groove and at least one second accommodating groove, and the first accommodating groove penetrates through the encapsulating layer;
the chip is embedded in the corresponding first accommodating groove and comprises a first surface and a second surface opposite to the first surface, and the first surface is provided with a plurality of welding pads; the first surface and the second surface respectively expose the encapsulating layer;
the auxiliary structures correspond to the chips one to one, the auxiliary structures correspond to the second accommodating grooves one to one, and the auxiliary structures are embedded in the second accommodating grooves; the auxiliary structure comprises a third surface and a fourth surface opposite to the third surface, the third surface and the first surface are positioned on the same side, the fourth surface and the second surface are positioned on the same side, and the encapsulation layer is exposed from the fourth surface;
the heat dissipation layer is positioned on one side of the second surface and covers the chip and the auxiliary structure; the material of the heat dissipation layer and the material of the auxiliary structure are both metal.
In one embodiment, the auxiliary structure is the same material as the heat sink layer; and/or the presence of a gas in the gas,
the auxiliary structure comprises auxiliary parts which are arranged around the corresponding chips and are continuous and uninterrupted; the second accommodating groove penetrates through the encapsulating layer, and the encapsulating layer is exposed from the third surface and the fourth surface;
the auxiliary parts and the corresponding chips are arranged at intervals, and the heat dissipation layer covers the part, between the chips and the auxiliary parts, of the encapsulating layer; and/or the presence of a gas in the gas,
the auxiliary structure further comprises a plurality of pins arranged at intervals and arranged on the outer side of the auxiliary part, and the pins and the auxiliary part are arranged at intervals.
In one embodiment, the semiconductor package structure further includes an insulating layer disposed on one side of the first surface and a redistribution layer disposed on one side of the insulating layer away from the chip;
the insulating layer covers the chip, the auxiliary piece and the encapsulating layer, a contact hole is formed in the insulating layer, and the contact hole corresponds to the welding pad; the rewiring layer is electrically connected with the welding pad through the contact hole, and the welding pad is led out.
The embodiment of the application achieves the main technical effects that:
according to the semiconductor packaging method and the semiconductor packaging structure provided by the embodiment of the application, the auxiliary structure of the auxiliary piece and the heat dissipation layer are made of metal, the heat dissipation layer covers the auxiliary structure, so that the adhesion between the heat dissipation layer and the auxiliary structure is good, the bonding force is large, the chip and the auxiliary piece form an integrated structure through the encapsulating layer, the bonding force among the chip, the encapsulating layer and the heat dissipation layer can be improved due to the arrangement of the auxiliary structure, and the risk that the heat dissipation layer, the chip and the encapsulating layer are peeled off is reduced.
Drawings
FIG. 1 is a flow chart of a semiconductor packaging method provided by an exemplary embodiment of the present application;
fig. 2 is a schematic structural diagram of a first intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
FIG. 3 is a top view of an auxiliary structure provided by an exemplary embodiment of the present application;
fig. 4 is a schematic perspective view of an auxiliary member and a connecting portion of an auxiliary structure according to an exemplary embodiment of the present disclosure;
FIG. 5 is a schematic structural view of an auxiliary element provided in an exemplary embodiment of the present application;
fig. 6 is a schematic structural diagram of a second intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 7 is a schematic structural diagram of a semiconductor package structure provided in an exemplary embodiment of the present application when no thinning process is performed on the encapsulating layer;
FIG. 8 is a flow chart of a method of packaging a semiconductor provided by another exemplary embodiment of the present application;
fig. 9 is a schematic structural diagram of a third intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 10 is a schematic structural diagram of a fourth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 11 is a schematic structural diagram of a fifth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 12 is a schematic structural diagram of a sixth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 13 is a schematic structural diagram of a seventh intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 14 is a schematic structural diagram of an eighth intermediate structure of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 15 is a schematic structural diagram of a semiconductor package structure provided by an exemplary embodiment of the present application when the dielectric layer is not thinned;
fig. 16 is a schematic structural diagram of a semiconductor package structure provided in an exemplary embodiment of the present application;
fig. 17 is a schematic structural view of a semiconductor package structure provided in an exemplary embodiment of the present application when the semiconductor package structure and the second substrate are not peeled off.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
The embodiment of the application provides a semiconductor packaging method. Referring to fig. 1, the semiconductor packaging method includes the following steps 110 to 130.
In step 110, at least one chip to be packaged and an auxiliary component are attached to a carrier; the auxiliary part comprises auxiliary structures which correspond to the chips one by one, each chip comprises a first surface and a second surface opposite to the first surface, the first surface faces the carrier plate, and a plurality of welding pads are arranged on the first surface; the auxiliary member comprises a third surface and a fourth surface opposite to the third surface, the first surface and the third surface are located on the same side, the second surface and the fourth surface are located on the same side, and the third surface faces the carrier plate.
In step 120, an encapsulation layer is formed, the encapsulation layer covers the carrier plate, encapsulates the at least one chip to be packaged and the auxiliary component, and the encapsulation layer is exposed from the second surface and the fourth surface.
In step 130, forming a heat dissipation layer on the second surface side, wherein the heat dissipation layer covers the chip and the auxiliary structure; the material of the heat dissipation layer and the material of the auxiliary structure are both metal.
According to the semiconductor packaging method provided by the embodiment of the application, the auxiliary structure of the auxiliary piece and the heat dissipation layer are made of metal, the heat dissipation layer covers the auxiliary structure, so that the adhesion between the heat dissipation layer and the auxiliary structure is good, the bonding force is high, and the chip and the auxiliary piece form an integrated structure through the encapsulation layer.
The semiconductor packaging method provided by the embodiment of the present application will be described in detail below.
In step 110, at least one chip to be packaged and an auxiliary component are attached to a carrier; the auxiliary part comprises auxiliary structures which correspond to the chips one by one, each chip comprises a first surface and a second surface opposite to the first surface, the first surface faces the carrier plate, and a plurality of welding pads are arranged on the first surface; the auxiliary member comprises a third surface and a fourth surface opposite to the third surface, the first surface and the third surface are located on the same side, the second surface and the fourth surface are located on the same side, and the third surface faces the carrier plate.
A first intermediate structure as shown in fig. 2 may be obtained via step 110. In the embodiment shown in fig. 2, only one chip 20 to be packaged is attached to the carrier 10. In other embodiments, the number of the chips 20 to be packaged mounted on the carrier 10 may be two or more.
In one embodiment, the shape of the carrier plate 10 may be circular, rectangular or other shape. The carrier 10 may be a small-sized wafer substrate, or may be a larger-sized carrier, such as a stainless steel substrate, a polymer substrate, etc.
In one embodiment, the chip 20 to be packaged may be obtained by dicing a silicon wafer. The silicon chip is provided with an active surface, and the active surface of the silicon chip is provided with a welding pad. The silicon wafer can be cut by adopting a mechanical cutting mode or a laser cutting mode. Optionally, before the silicon wafer is cut, a grinding device may be used to grind the back surface of the silicon wafer opposite to the active surface, so that the thickness of the silicon wafer is a specified thickness.
The bonding pads of the chip 20 to be packaged are formed by conductive electrodes leading out from the internal circuit of the chip to the surface of the chip. The first side of the chip 20 to be packaged may be provided with a plurality of pads. The bonding pad is arranged on the conductive electrode of the chip, and the conductive electrode of the chip 20 is led out.
In one embodiment, before the step 110 of attaching at least one chip to be packaged and an auxiliary device on a carrier, the semiconductor packaging method may further include: a protective layer 21 is formed on a first side of the chip 20 to be packaged.
In the subsequent step of forming the encapsulation layer, since the encapsulation layer needs to be formed under high pressure during the formation process, the encapsulation material forming the encapsulation layer easily penetrates between the carrier 10 and the chip 20 to be packaged. By forming a protective layer 21 on the first surface of the chip 20 to be packaged, the protective layer 21 can prevent the encapsulating material from penetrating into the first surface of the chip 20 to be packaged, and even if the encapsulating material penetrates when the encapsulating layer is formed, after the carrier 10 is peeled off from the chip 20, the surface of the protective layer 21 can be directly processed by a chemical method or a grinding method without directly contacting the first surface of the chip 20 to be packaged, so that the pad of the first surface of the chip 20 to be packaged can be prevented from being damaged.
In one embodiment, the chip 20 and the auxiliary component to be packaged may be attached to the carrier 10 by an adhesive layer, and the adhesive layer may be made of a material that is easy to peel off, so that the chip 20 and the auxiliary component to be packaged can be subsequently peeled off from the carrier 10, for example, the adhesive layer may be made of a thermal release material that can lose its adhesiveness by heating.
Referring to fig. 3 to 5, the auxiliary 50 includes the auxiliary structures 40, and the auxiliary 50 includes the auxiliary structures 40 corresponding to the chips 20 to be packaged one to one. In the embodiment shown in fig. 5, the auxiliary element 50 includes four auxiliary structures 40, and in other embodiments, the auxiliary element 50 may include auxiliary structures 40 different from four.
In one embodiment, the auxiliary structure 40 includes an auxiliary portion 41, and the auxiliary portion 41 is disposed around the corresponding chip 20 and is continuous and uninterrupted. With such an arrangement, the contact area between the auxiliary portion 41 and the metal heat dissipation layer formed later is larger, and the adhesion between the auxiliary portion 41 and the heat dissipation layer is better, which is more helpful for improving the bonding force between the chip 20 and the encapsulating layer and the heat dissipation layer. The shape of the auxiliary portion 41 may be substantially the same as the shape of the chip 20. In the illustrated embodiment, the chip 20 is substantially rectangular, and the auxiliary portion 41 may be substantially rectangular. In other embodiments, the auxiliary portion 41 may also include a plurality of metal structures spaced around the chip 20.
In one embodiment, the auxiliary portion 41 is spaced apart from the corresponding chip 20. With this arrangement, when an encapsulating layer is formed in a subsequent step, a portion of the encapsulating layer enters between the auxiliary portion 41 and the corresponding chip 20, which helps to enhance the bonding force among the encapsulating layer, the auxiliary portion 41 and the chip 20.
In one embodiment, the auxiliary structure 40 further includes a plurality of pins 42 arranged at intervals outside the auxiliary portion 41, and the pins 42 are arranged at intervals with the auxiliary portion 41. The outer side of the auxiliary portion 41 refers to the side facing away from the chip 20. With this arrangement, when an encapsulating layer is formed in a subsequent step, a portion of the encapsulating layer enters between the auxiliary portion 41 and the pin 42, which helps to enhance the bonding force between the encapsulating layer, the auxiliary structure 40 and the chip 20. Each side of the auxiliary portion 41 may be provided with a plurality of pins 42 arranged at intervals to more effectively increase the bonding force between the encapsulation layer, the auxiliary structure 40 and the chip 20.
In one embodiment, the auxiliary structure 40 further includes a connecting portion 43 extending outward from the auxiliary portion 41, the auxiliary element 50 further includes a frame 51, and in the auxiliary structure 40 corresponding to each chip mounted on the carrier 10, the connecting portion 43 and the leads 42 are respectively connected to the frame 51. With such an arrangement, the auxiliary portion 41 of the auxiliary structure 40 and the leads 42 are integrated, so that the auxiliary structure 40 can be attached to the carrier 10 conveniently, thereby simplifying the operation and saving the time.
In one embodiment, the frame body 51 includes a plurality of first connecting rods 511 and a plurality of second connecting rods 512, the plurality of first connecting rods 511 are enclosed to form a frame, the plurality of second connecting rods 512 are disposed in the frame to divide the frame into a plurality of regions, and each region is provided with an auxiliary structure 40.
In one embodiment, each auxiliary structure 40 includes a plurality of connecting portions 43. This makes the auxiliary structure 40 and the frame body 50 more firmly connected. In the illustrated embodiment, each auxiliary structure 40 includes four connecting portions 43 arranged at intervals, and in other embodiments, each auxiliary structure 40 may include a number of connecting portions 44 different from four.
In one embodiment, the connection portion 43 includes a rod portion 431 connected to the auxiliary portion 41 and a branched structure 432 at an end of the rod portion 431, and the branched structure 432 includes two branches, and the two branches of the branched structure are respectively connected to the first link 511 or the second link 512, so that the connection portion 43 and the frame body 51 can be more firmly connected.
In step 120, an encapsulation layer is formed, the encapsulation layer covers the carrier plate, encapsulates the at least one chip to be packaged and the auxiliary component, and the encapsulation layer is exposed from the second surface and the fourth surface.
A second intermediate structure as shown in fig. 6 may be obtained through step 120.
Referring to fig. 6, the encapsulating layer 60 is used for encapsulating the chip 20 to be packaged and the auxiliary structure 40 to reconstruct a flat plate structure, so that after the carrier plate 10 is peeled off, the re-wiring and packaging can be continued on the reconstructed flat plate structure.
In one embodiment, before forming the encapsulating layer 60, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., may be performed to remove impurities from the surfaces of the chip 20, the auxiliary structure 40, and the carrier 10, so that the connection between the encapsulating layer 60 and the chip 20 to be packaged, the auxiliary structure 40, and the carrier 10 is more intimate and no delamination or cracking occurs.
In one embodiment, the encapsulating layer 60 may be formed by plastic molding or laminating an epoxy resin film, or by injection molding, compression molding, transfer molding, or the like of an epoxy resin compound.
In one embodiment, referring to fig. 6, the third surface and the fourth surface of the auxiliary portion 41 respectively expose the encapsulation layer 60. As such, the auxiliary portion 41 penetrates through the encapsulation layer 60, so that the bonding force between the auxiliary portion 41 and the encapsulation layer 60 is better.
In one embodiment, the step 120 of forming the encapsulation layer includes the following processes:
firstly, an encapsulation structure is formed, the encapsulation structure covers the carrier plate and completely encapsulates the at least one chip to be encapsulated, the auxiliary part and the pins, and the distance from the surface of the pins departing from the carrier plate to the carrier plate is greater than the distance from the fourth surface to the carrier plate. By this step the structure as shown in fig. 7 is obtained. Referring to fig. 7, the thickness of the encapsulation structure 61 is greater than the thickness of the auxiliary portion 41, the thickness of the leads 42, and the thickness of the chip 20, so that the encapsulation structure 61 can completely encapsulate the auxiliary portion 41, the leads 42, and the chip 20.
And then, thinning the packaging structure and the pins to enable the packaging structure to form the packaging layer, wherein the first surface of the chip, the surface of the pins departing from the carrier plate and the fourth surface of the auxiliary part are flush and exposed out of the packaging layer.
By setting the distance from the surface of the pin 42 departing from the carrier 10 to be greater than the distance from the fourth surface of the auxiliary portion 41 to the carrier, in the process of thinning the encapsulation structure, after the pin 42 is exposed, the thinning speed can be reduced, so as to prevent the second surface of the chip 20 from being damaged due to the excessively fast thinning speed, and to help protect the chip 20. In one exemplary embodiment, the thinning process may be performed by grinding.
In other embodiments, in the auxiliary structure 40, the distance from the surface of the pin 42 facing away from the carrier board 10 to the carrier board 10 may be equal to the distance from the fourth surface of the auxiliary portion 41 to the carrier board.
In one embodiment, referring to fig. 8, after step 120 and before step 130, the semiconductor packaging method further includes the following steps 140 to 170.
In step 140, the carrier is peeled off to expose the first surface and the third surface.
A third intermediate structure as shown in fig. 9 may be obtained through step 140.
In one embodiment, the encapsulating layer 60, the chip 20 to be packaged and the auxiliary element 50 can be directly and mechanically peeled off from the carrier plate 10. In another embodiment, the chip 20 to be packaged and the auxiliary element 50 are bonded to the carrier 10 by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity, so as to peel off the carrier 10. After the carrier 10 is peeled off, the first surface of the chip 20 to be packaged and the third surface of the auxiliary portion 41 are exposed.
In step 150, an insulating layer is formed on the first surface side, and the insulating layer covers the chip, the auxiliary member, and the encapsulating layer.
A fourth intermediate structure as shown in fig. 10 may be obtained, via step 150.
Prior to step 150, the semiconductor packaging method may further include: providing the first substrate 11, and turning over and fixing the third intermediate structure on the first substrate 11 so that the first surface of the chip 20 is away from the first substrate 11. The first substrate 11 functions to support the third intermediate structure. The first substrate 11 may be a small-sized wafer substrate, or may be a larger-sized substrate, such as a stainless steel substrate or a polymer substrate.
In this step, the insulating layer 70 may be formed to entirely cover a side of the third intermediate structure facing away from the first substrate 11. By forming the insulating layer 70, it is possible to prevent the rewiring layer formed later from being electrically connected to the auxiliary portion 41 or the leads 42, thereby affecting the operation of the chip 20. And the formed rewiring layer is not influenced by the auxiliary structure, the rewiring area of the rewiring layer is larger, and the degree of freedom of product design is higher.
In one embodiment, the insulating layer 70 may be formed by plastic molding.
In step 160, contact holes are formed in the insulating layer, which expose the pads.
A fifth intermediate structure as shown in fig. 11 may be obtained through step 160.
In this step, the insulating layer 70 may be etched by a process of exposure and development or laser etching to form the contact hole 71. When the protective layer 21 is formed on the first surface of the chip 20, the insulating layer is etched and the protective layer 21 is also etched, and the contact hole 71 penetrates the insulating layer 70 and the protective layer 21.
In step 170, a rewiring layer for leading out the pad is formed on the insulating layer.
By this step, a sixth intermediate structure as shown in fig. 12 can be obtained. As shown in fig. 12, the re-wiring layer 72 is formed while forming the conductive structure 75 located in the contact hole, and the re-wiring layer 72 is electrically connected to the pad through the conductive structure 75 located in the contact hole 71, thereby drawing out the pad. The redistribution layer 72 includes a plurality of conductive traces 721, and one conductive trace 721 may be electrically connected to a plurality of conductive structures 75.
In one embodiment, the redistribution layer may be formed by sputtering a metal layer and then patterning the metal layer. Compared with the scheme of adopting the conducting wire to be electrically connected with the welding pad, the contact area between the rewiring layer and the welding pad is larger, the electric connection effect is better, and the heat dissipation effect of the rewiring layer is better.
In one embodiment, the semiconductor manufacturing method may further include: conductive posts 73 are formed on the redistribution layer 72. A plurality of conductive posts 73 may be formed on one conductive trace 721. The redistribution layer 72 is electrically connected to the bonding pad of the chip 20, and the redistribution layer 72 is led out through the conductive pillar 73, so that the bonding pad of the chip 20 is led out by the conductive pillar 73. A seventh intermediate structure as shown in fig. 13 can be obtained by this step.
In one embodiment, the semiconductor packaging method may further include: forming a dielectric layer 74, wherein the dielectric layer 74 covers and covers the conductive pillar 73, the exposed rewiring layer 72 and the exposed insulating layer 70, and the dielectric layer 74 is exposed on the surface of the conductive pillar 73 away from the first substrate 11. The dielectric layer 74 may protect the redistribution layer 72. An eighth intermediate structure as shown in fig. 14 can be obtained by this step.
In one embodiment, as shown in fig. 15, when the dielectric layer 74 is formed, the initially formed dielectric layer may cover the surface and the side portions of the conductive studs 73, that is, the distance from the surface of the initially formed dielectric layer 74 facing away from the first substrate 11 to the first substrate 11 is greater than the distance from the surface of the conductive studs 73 facing away from the first substrate 11 to the first substrate 11. The dielectric layer is then thinned to make the surface of the dielectric layer 74 substantially flush with the surface of the conductive posts 73, thereby exposing the surface of the conductive posts 73 to the dielectric layer 74.
After this step, the semiconductor packaging method may further include: the first substrate 11 is peeled off. In one embodiment, the encapsulating layer 60, the chip 20 to be packaged and the auxiliary member 50 may be directly and mechanically peeled off from the first substrate 11. In another embodiment, the chip 20 and the auxiliary member 50 to be packaged are bonded to the first substrate 11 by an adhesive layer, and when the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity after being heated, so as to peel off the first substrate 11. After the first substrate 11 is peeled off, the second surface of the chip 20 to be packaged and the fourth surface of the auxiliary structure 40 are exposed.
In step 130, forming a heat dissipation layer on the second surface side, wherein the heat dissipation layer covers the chip and the auxiliary structure; the material of the heat dissipation layer and the material of the auxiliary structure are both metal.
The semiconductor package structure shown in fig. 16 can be obtained through step 130.
In one embodiment, prior to step 130, as shown in fig. 17, an eighth intermediate structure may be secured to the second substrate 12 such that the conductive posts 73 are adjacent to the second substrate 12. The second substrate 12 functions to support the seventh intermediate structure. The second substrate 12 may be a small-sized wafer substrate, or may be a larger-sized substrate, such as a stainless steel substrate, a polymer substrate, or the like.
After step 130, the semiconductor packaging method further includes: the semiconductor package is peeled off the second substrate 12. In one embodiment, the semiconductor package structure may be directly mechanically peeled from the second substrate 12. In another embodiment, when the semiconductor package structure is bonded to the second substrate 12 by an adhesive layer, and the material of the adhesive layer is a thermal separation material, the adhesive layer may be heated to reduce its viscosity, so as to peel off the second substrate 12.
In one embodiment, the heat dissipation layer 80 may be formed on the side opposite the second side of the chip 20 by an electroplating process.
In one embodiment, the material of the auxiliary structure 40 is the same as the material of the heat dissipation layer 80. The auxiliary structure 40 and the heat dissipation layer 80 are made of the same material, and the lattice constants of the auxiliary structure 40 and the heat dissipation layer 80 are the same, so that the adhesion between the auxiliary structure 40 and the heat dissipation layer 80 is the largest, which is more helpful for improving the bonding force between the chip 20, the encapsulation layer 60 and the heat dissipation layer 80, and further improving the reliability of the semiconductor package structure. In an exemplary embodiment, the material of the auxiliary portion 41, the pins 42 and the connection portions 43 of the auxiliary structure 40, and the heat dissipation layer 80 may be all copper. The heat dissipation performance of copper is better, and the heat dissipation effect of the semiconductor packaging structure is favorably improved.
In one embodiment, the portion of the encapsulation layer 60 between the chip 20 and the auxiliary portion 41 covered by the heat dissipation layer 80, that is, the portion of the heat dissipation layer 80 covering the second side of the chip, the portion of the heat dissipation layer 80 covering the encapsulation layer 60 between the chip 20 and the auxiliary portion 41, and the portion of the heat dissipation layer 80 covering the auxiliary portion 41 are continuous and are a unitary structure. With such an arrangement, the heat dissipation layer 80 and the auxiliary portion 41 form a structure similar to a "T" shape, and the heat dissipation layer 80 and the auxiliary portion 41 are embedded in the encapsulating layer 60, so as to further improve the bonding force between the encapsulating layer 60 and the heat dissipation layer.
In one embodiment, a portion of the heat dissipation layer 80 is hollowed out. By such an arrangement, the semiconductor package structure can be prevented from warping and deforming due to stress concentration of the heat dissipation layer 80. In the illustrated embodiment, the heat dissipation layer 80 is hollowed out in a portion corresponding to the region between the auxiliary portion 41 and the lead 42. In other embodiments, the heat dissipation layer 80 may be hollowed out at other positions.
In one embodiment, when the auxiliary member includes the frame body 51, after the step 130 of forming the heat dissipation layer on the second face side, the semiconductor packaging method further includes: and removing the frame body. Removing the frame body may avoid the need for additional structural connections to the plurality of chips 20.
In the above embodiments and the drawings, step 130 is performed after step 170, and in other embodiments, step 130 may be performed before step 140, and the obtained semiconductor packages have the same structure, and the processes of providing the packages are substantially the same, and are not described again.
The embodiment of the application also provides a semiconductor packaging structure. Referring to fig. 16, the semiconductor package structure includes:
the encapsulating layer 60 is provided with at least one first accommodating groove and at least one second accommodating groove, and the first accommodating groove penetrates through the encapsulating layer 60;
at least one chip 20 to be packaged, where the chip corresponds to the first receiving groove one to one, the chip 20 is embedded in the corresponding first receiving groove, the chip 20 includes a first surface and a second surface opposite to the first surface, and the first surface and the second surface respectively expose the encapsulating layer 60; the first surface is provided with a plurality of welding pads;
the auxiliary structures 40 are in one-to-one correspondence with the chips 20, the auxiliary structures 40 are in one-to-one correspondence with the second accommodating grooves, and the auxiliary structures 40 are embedded in the second accommodating grooves; the auxiliary structure 40 includes a third surface and a fourth surface opposite to the third surface, the third surface is located on the same side as the first surface, the fourth surface is located on the same side as the second surface, and the fourth surface exposes the encapsulation layer 60;
a heat dissipation layer 80 located on one side of the second surface, wherein the heat dissipation layer 80 covers the chip 20 and the auxiliary structure 40; the material of the heat dissipation layer 80 and the material of the auxiliary structure 40 are both metals.
In one embodiment, the material of the auxiliary structure 40 is the same as the material of the heat dissipation layer 80.
In one embodiment, the auxiliary structure 40 includes an auxiliary portion 41, and the auxiliary portion 41 is disposed around the corresponding chip 20 and is continuous and uninterrupted; the second receiving groove penetrates through the encapsulating layer 60, and the third surface and the fourth surface of the auxiliary portion 41 are exposed out of the encapsulating layer 60.
In one embodiment, the auxiliary portion 41 is spaced apart from the corresponding chip 20, and the heat dissipation layer 80 covers a portion of the encapsulation layer 60 between the chip 20 and the auxiliary portion 41.
In one embodiment, the auxiliary structure 40 further includes a plurality of pins 42 arranged at intervals outside the auxiliary portion 41, and the pins 42 are arranged at intervals with the auxiliary portion 41.
In one embodiment, referring to fig. 3 and 4, the auxiliary structure 40 further includes a connection portion 43 extending outward from the auxiliary portion 41, a thickness of the connection portion 43 may be equal to a thickness of the auxiliary portion 41, and opposite surfaces of the connection portion 43 may be respectively exposed by the encapsulation layer 60.
In one embodiment, the second receiving groove includes a first receiving cavity for receiving the auxiliary portion 41 and the connecting portion 43, and a second receiving cavity for receiving the pin 42, and both the first receiving cavity and the second receiving cavity may penetrate through the encapsulating layer 60.
In one embodiment, the semiconductor package structure further includes an insulating layer 70 disposed on a first side of the chip 20 and a re-wiring layer 72 disposed on a side of the insulating layer 70 facing away from the chip;
the insulating layer 70 covers the chip 20, the auxiliary structure 40 and the encapsulating layer 60, a contact hole is formed in the insulating layer 70, the contact hole corresponds to the pad, and a conductive structure 75 is formed in the contact hole; the redistribution layer 72 is electrically connected to the pad through the conductive structure 75 in the contact hole, leading the pad out.
In one embodiment, a protection layer 21 is disposed between the first surface of the chip 20 and the insulation layer 70, and the contact hole penetrates through the insulation layer 70 and the protection layer 21.
In one embodiment, the semiconductor package structure further includes a conductive pillar 73 and a dielectric layer 74 located on a side of the redistribution layer 72 away from the chip 20, the dielectric layer 74 is exposed on a surface of the conductive pillar 73, and the conductive pillar 73 is electrically connected to the redistribution layer 72.
The embodiments of the semiconductor package structure and the semiconductor package method provided in the embodiments of the present application belong to the same concept, and the description of the relevant details and the description of the beneficial effects can be referred to each other, which is not repeated herein.
The semiconductor packaging structure provided by the embodiment of the application, through setting up the auxiliary member, the material of the auxiliary structure of auxiliary member and the material of heat dissipation layer are the metal, and the heat dissipation layer covers the auxiliary structure, can make the adhesion between heat dissipation layer and the auxiliary structure better, and the cohesion is great, and chip and auxiliary member form a body structure through the encapsulated layer, therefore the cohesion between chip, encapsulated layer and the heat dissipation layer can be promoted in the setting of auxiliary structure, reduces the risk that heat dissipation layer and chip and encapsulated layer take place to peel off.
In the present application, the apparatus embodiments and the method embodiments may complement each other without conflict. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the application. One of ordinary skill in the art can understand and implement it without inventive effort.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

Claims (11)

1. A semiconductor packaging method, characterized in that the semiconductor packaging method comprises:
attaching at least one chip to be packaged and an auxiliary part on a carrier plate; the auxiliary part comprises auxiliary structures which correspond to the chips one by one, each chip comprises a first surface and a second surface opposite to the first surface, the first surface faces the carrier plate, and a plurality of welding pads are arranged on the first surface; the auxiliary part comprises a third surface and a fourth surface opposite to the third surface, the first surface and the third surface are positioned on the same side, the second surface and the fourth surface are positioned on the same side, and the third surface faces the carrier plate;
forming an encapsulating layer, wherein the encapsulating layer covers the carrier plate and encapsulates the at least one chip to be encapsulated and the auxiliary piece, and the second surface and the fourth surface are exposed out of the encapsulating layer;
forming a heat dissipation layer on one side of the second surface, wherein the heat dissipation layer covers the chip and the auxiliary structure; the material of the heat dissipation layer and the material of the auxiliary structure are both metal.
2. The semiconductor packaging method according to claim 1, wherein the auxiliary structure is made of the same material as the heat dissipation layer.
3. The semiconductor packaging method according to claim 1, wherein the auxiliary structure includes an auxiliary portion that is disposed around the corresponding chip and is continuous and uninterrupted; the third surface and the fourth surface respectively expose the encapsulating layer.
4. The semiconductor packaging method according to claim 3, wherein the auxiliary portion is spaced apart from the corresponding chip, and the heat dissipation layer covers a portion of the encapsulation layer between the chip and the auxiliary portion.
5. The semiconductor packaging method according to claim 3, wherein the auxiliary structure further comprises a plurality of pins arranged at intervals outside the auxiliary portion, and the pins are arranged at intervals with the auxiliary portion.
6. The semiconductor packaging method according to claim 5, wherein the auxiliary structure further comprises a connecting portion extending outward from the auxiliary portion, the auxiliary member further comprises a frame body, and the connecting portion and the leads of the auxiliary structure are respectively connected to the frame body;
after the forming of the heat dissipation layer on the second face side, the semiconductor packaging method further includes:
and removing the frame body.
7. The semiconductor packaging method of claim 5, wherein the forming an encapsulation layer comprises:
forming an encapsulation structure, wherein the encapsulation structure covers the carrier plate and completely encapsulates the at least one chip to be encapsulated, the auxiliary part and the pins, and the distance from the surface of the pins departing from the carrier plate to the carrier plate is greater than the distance from the fourth surface to the carrier plate;
and thinning the packaging structure and the pins to enable the packaging structure to form the packaging layer, wherein the second surface, the surfaces of the pins departing from the carrier plate and the fourth surface are flush and exposed out of the packaging layer.
8. The semiconductor packaging method according to claim 1, further comprising:
peeling off the carrier plate to expose the first surface and the third surface;
forming an insulating layer on one side of the first surface, wherein the insulating layer covers the chip, the auxiliary piece and the encapsulating layer;
forming a contact hole on the insulating layer, the contact hole exposing the pad;
and forming a rewiring layer for leading out the welding pad on the insulating layer.
9. A semiconductor package structure, comprising:
the encapsulating layer is provided with at least one first accommodating groove and at least one second accommodating groove, and the first accommodating groove penetrates through the encapsulating layer;
the chip is embedded in the corresponding first accommodating groove and comprises a first surface and a second surface opposite to the first surface, and the first surface is provided with a plurality of welding pads; the first surface and the second surface respectively expose the encapsulating layer;
the auxiliary structures correspond to the chips one to one, the auxiliary structures correspond to the second accommodating grooves one to one, and the auxiliary structures are embedded in the second accommodating grooves; the auxiliary structure comprises a third surface and a fourth surface opposite to the third surface, the third surface and the first surface are positioned on the same side, the fourth surface and the second surface are positioned on the same side, and the encapsulation layer is exposed from the fourth surface;
the heat dissipation layer is positioned on one side of the second surface and covers the chip and the auxiliary structure; the material of the heat dissipation layer and the material of the auxiliary structure are both metal.
10. The semiconductor package structure of claim 9, wherein the auxiliary structure is made of the same material as the heat dissipation layer; and/or the presence of a gas in the gas,
the auxiliary structure comprises auxiliary parts which are arranged around the corresponding chips and are continuous and uninterrupted; the second accommodating groove penetrates through the encapsulating layer, and the encapsulating layer is exposed from the third surface and the fourth surface;
the auxiliary parts and the corresponding chips are arranged at intervals, and the heat dissipation layer covers the part, between the chips and the auxiliary parts, of the encapsulating layer; and/or the presence of a gas in the gas,
the auxiliary structure further comprises a plurality of pins arranged at intervals and arranged on the outer side of the auxiliary part, and the pins and the auxiliary part are arranged at intervals.
11. The semiconductor package structure according to claim 9, further comprising an insulating layer disposed on the first surface side and a redistribution layer disposed on a side of the insulating layer facing away from the chip;
the insulating layer covers the chip, the auxiliary piece and the encapsulating layer, a contact hole is formed in the insulating layer, and the contact hole corresponds to the welding pad; the rewiring layer is electrically connected with the welding pad through the contact hole, and the welding pad is led out.
CN202010621946.5A 2020-06-30 2020-06-30 Semiconductor packaging method and semiconductor packaging structure Pending CN111755340A (en)

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