CN110265306A - A kind of coreless substrate encapsulating structure and its manufacturing method - Google Patents
A kind of coreless substrate encapsulating structure and its manufacturing method Download PDFInfo
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- CN110265306A CN110265306A CN201910419184.8A CN201910419184A CN110265306A CN 110265306 A CN110265306 A CN 110265306A CN 201910419184 A CN201910419184 A CN 201910419184A CN 110265306 A CN110265306 A CN 110265306A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The present invention provides a kind of coreless substrate encapsulating structure and its manufacturing method, and the manufacturing method includes: one package substrate of preparation, wherein the package substrate includes heat conducting base material and the interconnection metal layer for being formed in the heat conducting base material lower surface；The chip putting hole for exposing the interconnection metal layer is formed in the heat conducting base material, and encapsulation chip is placed in the chip putting hole, and the encapsulation chip is electrically connected with the interconnection metal layer；The plastic packaging layer at least coating the encapsulation chip bottom is formed in the chip putting hole, and is formed in the interconnection metal layer far from the surface of the heat conducting base material and draws pad, wherein the extraction pad is electrically connected with the interconnection metal layer.It solves the problems, such as existing coreless substrate encapsulating structure bad mechanical property through the invention, be easy to appear warpage and heat dissipation performance is poor.
Description
Technical field
The present invention relates to semiconductor integrated circuit package fields, more particularly to a kind of coreless substrate encapsulating structure and its system
Make method.
Background technique
As electronic product develops to high density, multi-functional, miniaturization, high performance direction, correspondingly, semiconductor is integrated
The encapsulation of circuit will also develop towards light and short high performance direction.And the main component of semiconductor integrated circuit package is envelope
Substrate is filled, electrical connection and mechanical connection protection is played a part of.
In order to adapt to the frivolous requirement of encapsulating products, there is coreless substrate product.Due to coreless substrate product not compared with
The support of thick package substrate, mechanical strength is poor, is easy to appear warpage in process of production；And it is mechanical strong in order to increase
Degree wraps up chip usually using capsulation material in encapsulation process, but since capsulation material is typically all the bad of heat
Conductor, it is poor so as to cause the heat dissipation performance of chip.In consideration of it, it is necessary to design a kind of new coreless substrate encapsulating structure and its
Manufacturing method is with to solve the above technical problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of coreless substrate encapsulating structure and
Its manufacturing method, for solve existing coreless substrate encapsulating structure bad mechanical property, be easy to appear warpage and heat dissipation performance difference
Problem.
In order to achieve the above objects and other related objects, the present invention provides a kind of manufacturer of coreless substrate encapsulating structure
Method, the manufacturing method include:
A package substrate is prepared, wherein the package substrate includes heat conducting base material and is formed in the heat conducting base material lower surface
Interconnection metal layer；
The chip putting hole for exposing the interconnection metal layer is formed in the heat conducting base material, and encapsulation chip is placed in
In the chip putting hole, and the encapsulation chip is electrically connected with the interconnection metal layer；
The plastic packaging layer at least coating the encapsulation chip bottom is formed in the chip putting hole, and in the wiring gold
Belong to layer and form extraction pad far from the surface of the heat conducting base material, wherein the extraction pad is electrically connected with the interconnection metal layer
It connects.
Optionally, the method for preparing the package substrate includes: the offer heat conducting base material, and under the heat conducting base material
Surface forms the interconnection metal layer.
Optionally, the method for preparing the package substrate includes:
A composite base material is prepared, wherein the composite base material includes: adhesive layer and is respectively formed in table on the adhesive layer
The heat conducting base material in face and lower surface；
The interconnection metal layer is formed far from the surface of the adhesive layer in the heat conducting base material, is later formed with surface
The heat conducting base material of the interconnection metal layer is removed from the adhesive layer, to complete the preparation of the package substrate.
Optionally, the method for preparing the composite base material include: using process for pressing in the adhesive layer upper surface and
Lower surface presses the heat conducting base material, is had described in the heat conducting base material using high temperature and pressure baking process to surface pressing later
Adhesive layer carries out high temperature and pressure baking processing, to complete the preparation of the composite base material.
Optionally, the heat conducting base material includes the metal that thermal coefficient is greater than 10W/mK.
Optionally, after forming the chip putting hole, the manufacturing method further include: Yu Suoshu heat conducting base material surface is formed
The step of protective layer, wherein the protective layer includes inoxidzable coating and/or solder mask.
Optionally, the manufacturing method further include: to the step of forming cooling fin less than the encapsulation chip upper surface.
Optionally, Yu Suoshu heat conducting base material upper surface and the encapsulation chip upper surface form the cooling fin, method packet
Include: Yu Suoshu heat conducting base material upper surface forms high thermal conductivity adhesive layer, and forms thermal interfacial material in the encapsulation chip upper surface
Layer；The cooling fin is formed in high thermal conductivity adhesive layer upper surface and the thermal interface material layer upper surface later.
The present invention also provides a kind of coreless substrate encapsulating structure, the encapsulating structure includes:
Package substrate including heat conducting base material and is formed in the interconnection metal layer of the heat conducting base material lower surface, wherein described
The chip putting hole for exposing the interconnection metal layer is formed in heat conducting base material；
Chip is encapsulated, is placed in the chip putting hole, and be electrically connected with the interconnection metal layer；
Plastic packaging layer is formed in the chip putting hole, and is at least coated on the bottom of the encapsulation chip；
Draw pad, the surface set on the interconnection metal layer far from the heat conducting base material, and with the interconnection metal layer
Electrical connection.
Optionally, the heat conducting base material includes the metal that thermal coefficient is greater than 10W/mK.
Optionally, the encapsulating structure further include: the protective layer on the heat conducting base material surface is formed in, wherein the protection
Layer includes inoxidzable coating and/or solder mask.
Optionally, the encapsulating structure further include: at least formed on the heat dissipating layer of the encapsulation chip upper surface.
Optionally, the heat dissipating layer is formed in the heat conducting base material and the encapsulation chip upper surface, the at this time encapsulation
Structure further include:
High thermal conductivity adhesive layer is formed in the upper surface of the heat conducting base material；
Thermal interface material layer is formed in the upper surface of the encapsulation chip；
Cooling fin is formed in the upper surface of the high thermal conductivity adhesive layer and the thermal interface material layer.
As described above, a kind of coreless substrate encapsulating structure of the invention and its manufacturing method, in the centreless base for realizing chip
When plate encapsulates, using the heat conducting base material with high thermal conductivity coefficient as the radiator structure of encapsulation chip, to improve the encapsulation core
The heat dissipation performance of piece；Mechanical support is provided for entire encapsulating structure simultaneously, to increase its mechanical strength, avoid it that warpage occurs.
Detailed description of the invention
Fig. 1 is shown as the flow chart of coreless substrate encapsulating structure manufacturing method of the present invention.
Fig. 2 to Fig. 7 is shown as the structural schematic diagram of each step in coreless substrate encapsulating structure manufacturing method of the present invention.
Component label instructions
10 package substrates
100 adhesive layers
101 heat conducting base materials
102 interconnection metal layers
103 metal connecting line layers
104 dielectric layers
20 chip putting holes
30 encapsulation chips
40 plastic packaging layers
50 draw pad
60 high thermal conductivity adhesive layers
70 thermal interface material layers
80 cooling fins
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Fig. 7.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout form may also be increasingly complex.
As shown in Figure 1, the present embodiment provides a kind of manufacturing method of coreless substrate encapsulating structure, the manufacturing method packet
It includes:
A package substrate 10 is prepared, wherein the package substrate 10 is including heat conducting base material 101 and is formed in the thermally conductive base
The interconnection metal layer 102 of 101 lower surface of material；
The chip putting hole 20 for exposing the interconnection metal layer 102 is formed in the heat conducting base material 101, and will encapsulation
Chip 30 is placed in the chip putting hole 20, and the encapsulation chip 30 is electrically connected with the interconnection metal layer 102；
The plastic packaging layer 40 at least coating encapsulation 30 bottom of chip is formed in the chip putting hole 20, and in described
Interconnection metal layer 102 far from the heat conducting base material 101 surface formed draw pad 50, wherein the extraction pad 50 with it is described
Interconnection metal layer 102 is electrically connected.
Below incorporated by reference to Fig. 1, refering to Fig. 2 to Fig. 7 coreless substrate encapsulating structure described in the present embodiment manufacturing method into
Row is described in detail.
A package substrate 10 is prepared refering to 2 to Fig. 4 in conjunction with Fig. 1, wherein the package substrate 10 includes heat conducting base material 101
And it is formed in the interconnection metal layer 102 of 101 lower surface of heat conducting base material.
As an example, as shown in Figures 2 to 4, the method for preparing the package substrate 10 includes:
A composite base material is prepared, wherein the composite base material includes: adhesive layer 100 and is respectively formed in the adhesive layer
The heat conducting base material 101 of 100 upper and lower surfaces；
The interconnection metal layer 102 is formed far from the surface of the adhesive layer 100 in the heat conducting base material 101, later will
The heat conducting base material 101 that surface is formed with the interconnection metal layer 102 is removed from the adhesive layer 100, described in completing
The preparation of package substrate 10.
Specifically, as shown in Fig. 2, the method for preparing the composite base material includes: using process for pressing in the adhesive layer
100 upper and lower surfaces press the heat conducting base material 101, are pressed using high temperature and pressure baking process to surface later
The adhesive layer 100 for stating heat conducting base material 101 carries out high temperature and pressure baking processing, to complete the preparation of the composite base material.Its
Described in adhesive layer 100 can be general prepreg in traditional handicraft；The heat conducting base material 101 is greater than including thermal coefficient
The metal of 10W/mK, the present embodiment are preferably the copper that thermal coefficient is about 400W/mK, and thickness is between 0.05mm~5mm.
Heat conducting base material 101 described in the present embodiment is the interconnection metal layer as substrate when being subsequently formed the interconnection metal layer 102
102 provide mechanical support, and provide mechanical support in encapsulation process for entire coreless substrate encapsulating structure, thus described in increasing
The mechanical strength of coreless substrate encapsulating structure avoids it that warpage occurs；The heat conducting base material 101 is also used as the encapsulation core simultaneously
The radiator structure of piece 30, to improve the heat dissipation performance of entire coreless substrate encapsulating structure.It should be noted that described herein thermally conductive
The thickness of substrate 101 numberical range required between 0.05mm~5mm includes endpoint value 0.05mm and 5mm.
Specifically, as shown in figure 3, the interconnection metal layer 102 is including metal connecting line layer 103 and is formed in the metal company
Dielectric layer 104 around line layer 103, the metal connecting line layer include that metal contact wires, metal connection welding and metal draw weldering
Point, wherein the metal, which draws solder joint, is located at surface of the dielectric layer 104 far from the heat conducting base material 101, the metal connects
Connect relatively another surface that solder joint is located at the dielectric layer 104, the metal contact wires be located in the dielectric layer 104 and to
It is electrically connected the metal connection welding and the metal draws solder joint.Wherein use physical vapour deposition (PVD), chemical vapor deposition, electricity
Plating or the methods of chemical plating form the metal connecting line layer 103, and the material of the metal connecting line layer 103 include Al, Cu, Sn,
One of Ni, Au, Ag or a variety of；Using the methods of spin coating, chemical vapor deposition or plasma reinforced chemical vapour deposition shape
At the dielectric layer 104, and the material of the dielectric layer 104 includes polybenzoxazoles, phosphorosilicate glass, spin glass, spins and gather
Close one of object, silica, SiOxCy, Si-C composite material or a variety of.It should be noted that the metal contact wires can be with
For one layer or multilayer, the present embodiment is not limited the number of plies of the metal contact wires.
Specifically, as shown in figure 4, surface is formed with described in the interconnection metal layer 102 using mechanical stripping technique
Heat conducting base material 101 is removed from the adhesive layer 100, to complete the preparation of the package substrate 10；Certainly, other to can be realized
The method of removing is applied equally to the present embodiment.
As another example, as shown in figure 4, the method for preparing the package substrate 10 includes: to provide the heat conducting base material
101, and the interconnection metal layer 102 is formed in 101 lower surface of heat conducting base material.
Specifically, the heat conducting base material 101 includes the metal that thermal coefficient is greater than 10W/mK, the present embodiment is preferably thermally conductive
The copper that coefficient is about 400W/mK, thickness is between 0.05mm~5mm.Heat conducting base material 101 described in the present embodiment is forming institute
When stating interconnection metal layer 102, mechanical support is provided for the interconnection metal layer 102 as substrate, and be whole in encapsulation process
A coreless substrate encapsulating structure provides mechanical support, to increase the mechanical strength of the coreless substrate encapsulating structure, avoid it
Warpage occurs；Radiator structure of the heat conducting base material 101 also as the encapsulation chip 30 simultaneously, to improve entire coreless substrate
The heat dissipation performance of encapsulating structure.It should be noted that the thickness of heat conducting base material 101 described herein is between 0.05mm~5mm
Required numberical range includes endpoint value 0.05mm and 5mm.
Specifically, the interconnection metal layer 102 includes metal connecting line layer 103 and is formed in the metal connecting line layer 103 weeks
The dielectric layer 104 enclosed, the metal connecting line layer include that metal contact wires, metal connection welding and metal draw solder joint, wherein institute
It states metal extraction solder joint and is located at surface of the dielectric layer 104 far from the heat conducting base material 101, the metal connection welding is located at
Relatively another surface of the dielectric layer 104, the metal contact wires are located in the dielectric layer 104 and described to be electrically connected
Metal connection welding and the metal draw solder joint.Wherein use physical vapour deposition (PVD), chemical vapor deposition, plating or chemical plating
The methods of form the metal connecting line layer 103, and the material of the metal connecting line layer 103 includes in Al, Cu, Sn, Ni, Au, Ag
It is one or more；The dielectric is formed using the methods of spin coating, chemical vapor deposition or plasma reinforced chemical vapour deposition
Layer 104, and the material of the dielectric layer 104 includes polybenzoxazoles, phosphorosilicate glass, spin glass, spin polymer, oxidation
One of silicon, SiOxCy, Si-C composite material are a variety of.It should be noted that the metal contact wires can be one layer
It can be multilayer, the present embodiment does not limit the number of plies of the metal contact wires.
In conjunction with Fig. 1, refering to Fig. 5 and Fig. 6, is formed in Yu Suoshu heat conducting base material 101 and expose the interconnection metal layer 102
Chip putting hole 20, and encapsulation chip 30 is placed in the chip putting hole 20, and the encapsulation chip 30 and the wiring
Metal layer 102 is electrically connected.
As an example, as shown in figure 5, using mechanically or chemically the chip is formed in the heat conducting base material 101
Putting hole 20；Wherein the length and width of the chip putting hole 20 is all larger than the length and width of the encapsulation chip 30, with
The encapsulation chip 30 is placed and to the bottom progress plastic packaging of the encapsulation chip 30 convenient for subsequent, it is often more important that described in utilization
The air gap that encapsulation chip 30 is formed when being placed in the chip putting hole 20 radiates to the encapsulation chip 30, to mention
The heat dissipation performance of the high encapsulation chip 30.
As an example, as shown in fig. 6, realizing the method that the encapsulation chip 30 is electrically connected with the interconnection metal layer 102
It include: first the encapsulation chip 30 to be placed in the chip putting hole 20, and make the chip welding spot on the encapsulation chip 30
It is corresponded with the metal connection welding in the interconnection metal layer 102；Heating above structure is so that the chip welding spot later
It is welded with the metal connection welding, realizes being electrically connected between the encapsulation chip 30 and the interconnection metal layer 102.
As an example, after forming the chip putting hole 20, the manufacturing method further include: Yu Suoshu heat conducting base material 101
Surface forms the step of protective layer (not shown), wherein the protective layer includes inoxidzable coating and/or solder mask, to keep away
Exempt to cause and heat conducting base material 101 when the air in environment aoxidizes it or weld the chip welding spot and the metal connection welding
The case where short circuit.Specifically, the inoxidzable coating includes metal coating or organic coating of the thickness less than 1 μm, wherein described
The material of metal coating includes one of Sn, Ni, Au, Ag, is generally formed using electro-plating method；The material of the organic coating
It is selected generally from azole, such as benzotriazole, imidazoles or benzimidazole, generally by former with the metal in the heat conducting base material 101
Son forms coordinate bond and is adsorbed on 101 surface of heat conducting base material to form thicker film.
In conjunction with Fig. 1, refering to Fig. 6 and Fig. 7, is formed in Yu Suoshu chip putting hole 20 and at least coat 30 bottom of encapsulation chip
The plastic packaging layer 40 in portion, and formed in the interconnection metal layer 102 far from the surface of the heat conducting base material 101 and draw pad 50,
Described in extraction pad 50 be electrically connected with the interconnection metal layer 102.It should be noted that plastic packaging layer 40 described herein coats institute
The bottom for stating encapsulation chip 30 refers to that the plastic packaging layer 40 coats the chip welding spot in the encapsulation chip 30 completely, with realization pair
The chip welding spot is sealed protection.
As an example, the plastic packaging layer 40 is formed using hydraulic seal moulding process, wherein the material of the plastic packaging layer 40
Including one of polyimide layer, layer of silica gel or epoxy resin layer；Solder joint is drawn in the metal using ball reflux technique is planted
Place forms the extraction pad 50, wherein it is described draw pad 50 material include one of Al, Cu, Sn, Ni, Au, Ag or
It is a variety of.As an example, after forming the extraction pad 50, if the encapsulating structure is that multi-chip encapsulates simultaneously at this time, the system
The method of making further includes the steps that cutting scribing, to obtain the coreless substrate encapsulating structure of single-chip.
As shown in fig. 7, the manufacturing method further include: form cooling fin 80 to less than encapsulation 30 upper surface of chip
Step；The present embodiment preferably forms the cooling fin in the heat conducting base material 101 and 30 upper surface of encapsulation chip simultaneously
80, so that the coreless substrate encapsulating structure has optimal structural strength and heat dissipation performance.Specific method includes: to lead in described
101 upper surface of hot substrate forms high thermal conductivity adhesive layer 60, and forms thermal interface material layer 70 in 30 upper surface of encapsulation chip；
The cooling fin 80 is formed in 60 upper surface of high thermal conductivity adhesive layer and 70 upper surface of the thermal interface material layer later.It needs
It is noted that as previously mentioned, in order to make the coreless substrate encapsulating structure that there is optimal structural strength, high thermal conductivity described herein
The upper surface of adhesive layer 60 and the upper surface of the thermal interface material layer 70 are in same level；Certainly, described herein same
One horizontal plane can be by adjusting the thickness of the high thermal conductivity adhesive layer 60 and the thickness realization of the thermal interface material layer 70, can also
To be realized in step in front by adjusting the thickness of the heat conducting base material 101.
As an example, the high thermal conductivity adhesive layer 60 is formed in 101 upper surface of heat conducting base material using spin coating proceeding,
Described in the material of high thermal conductivity adhesive layer 60 include silica gel or epoxy resin added with highly heat-conductive material, the highly heat-conductive material
Including silica, aluminium oxide or aluminium nitride etc.；The hot interface is formed in 30 upper surface of encapsulation chip using spin coating proceeding
Material layer 70, wherein the material of the thermal interface material layer 70 includes having sticking silicon lipid materials.Certainly, the high thermal conductivity
The material of adhesive layer 60 and the thermal interface material layer 70 can also be identical, is all silica gel or epoxy added with highly heat-conductive material
One of resin, the sticking silicon lipid materials of tool；The cooling fin 80 includes conventional metals cooling fin.
As shown in fig. 6, the present embodiment additionally provides a kind of coreless substrate encapsulating structure, the encapsulating structure includes:
Package substrate 10 including heat conducting base material 101 and is formed in the interconnection metal layer of 101 lower surface of heat conducting base material
102, wherein being formed with the chip putting hole 20 for exposing the interconnection metal layer 102 in the heat conducting base material 101；
Chip 30 is encapsulated, is placed in the chip putting hole 20, and be electrically connected with the interconnection metal layer 102；
Plastic packaging layer 40 is formed in the chip putting hole 20, and is at least coated on the bottom of the encapsulation chip 30；
Draw pad 50, the surface set on the interconnection metal layer 102 far from the heat conducting base material 101, and with the cloth
Line metal layer 102 is electrically connected.
As an example, as shown in fig. 6, the heat conducting base material 101 includes the metal that thermal coefficient is greater than 10W/mK, this implementation
Example is preferably the copper that thermal coefficient is about 400W/mK, and thickness is between 0.05mm~5mm.Thermally conductive base described in the present embodiment
Material 101 is that the interconnection metal layer 102 provides mechanical support, and is sealing when forming the interconnection metal layer 102, as substrate
Mechanical support is provided for entire coreless substrate encapsulating structure during dress, to increase the machinery of the coreless substrate encapsulating structure
Intensity avoids it that warpage occurs；Radiator structure of the heat conducting base material 101 also as the encapsulation chip 30 simultaneously, to improve
The heat dissipation performance of entire coreless substrate encapsulating structure.It should be noted that heat conducting base material 101 described herein thickness between
Required numberical range includes endpoint value 0.05mm and 5mm between 0.05mm~5mm.
As an example, as shown in fig. 6, the interconnection metal layer 102 is including metal connecting line layer 103 and is formed in the metal
Dielectric layer 104 around connecting line layer 103, the metal connecting line layer include that metal contact wires, metal connection welding and metal are drawn
Solder joint, wherein the metal, which draws solder joint, is located at surface of the dielectric layer 104 far from the heat conducting base material 101, the metal
Connection welding is located at relatively another surface of the dielectric layer 104, and the metal contact wires are located in the dielectric layer 104 and use
Solder joint is drawn to be electrically connected the metal connection welding and the metal.Wherein the material of the metal connecting line layer 103 include Al,
One of Cu, Sn, Ni, Au, Ag or a variety of, the material of the dielectric layer 104 include polybenzoxazoles, phosphorosilicate glass, spin
One of glass, spin polymer, silica, SiOxCy, Si-C composite material are a variety of.It should be noted that the gold
The number of plies of the metal contact wires can not limited for one layer or multilayer, the present embodiment by belonging to connecting line.
As an example, as shown in fig. 6, the length and width of the chip putting hole 20 is all larger than the encapsulation chip 30
Length and width carries out plastic packaging in order to the subsequent placement encapsulation chip 30 and to the bottom of the encapsulation chip 30, heavier
What is wanted is using the air gap formed when chip 30 is placed in the chip putting hole 20 that encapsulates to the encapsulation chip
30 radiate, to improve the heat dissipation performance of the encapsulation chip 30.
As an example, the encapsulating structure further include: be formed in the protective layer on 101 surface of heat conducting base material (in figure not
Show), wherein the protective layer includes inoxidzable coating and/or solder mask, it is aoxidized or is welded to avoid the air in environment
The case where being shorted with heat conducting base material 101 is caused when connecing the chip welding spot and the metal connection welding.Specifically, the oxygen
Change coating include metal coating or organic coating of the thickness less than 1 μm, wherein the material of the metal coating include Sn, Ni, Au,
One of Ag, the material of the organic coating are selected generally from azole, such as benzotriazole, imidazoles or benzimidazole.
As an example, the material of the plastic packaging layer 40 includes one of polyimide layer, layer of silica gel or epoxy resin layer,
The material for drawing pad 50 includes one of Al, Cu, Sn, Ni, Au, Ag or a variety of.It should be noted that the present embodiment
The bottom that the plastic packaging layer 40 coats the encapsulation chip 30 refers to that the plastic packaging layer 40 is coated completely in the encapsulation chip 30
Chip welding spot, with realize protection is sealed to the chip welding spot.
As shown in fig. 7, the encapsulating structure further includes the heat dissipating layer 80 at least formed on encapsulation 30 upper surface of chip.
In the present embodiment, the heat dissipating layer 80 is formed simultaneously in the heat conducting base material 101 and 30 upper surface of encapsulation chip, at this time institute
State encapsulating structure further include: high thermal conductivity adhesive layer 60 is formed in the upper surface of the heat conducting base material 101；Thermal interface material layer 70,
It is formed in the upper surface of the encapsulation chip 30；Cooling fin 80 is formed in the high thermal conductivity adhesive layer 60 and the hot interface material
The upper surface of the bed of material 70.It should be noted that in order to make the coreless substrate encapsulating structure that there is optimal structural strength, herein
The upper surface of the high thermal conductivity adhesive layer 60 and the upper surface of the thermal interface material layer 70 are in same level；Certainly, this
Locate it is described same level can be by adjusting the thickness of the thickness and the thermal interface material layer 70 of the high thermal conductivity adhesive layer 60
Degree is realized, can also be realized in step by adjusting the thickness of the heat conducting base material 101 in front.
As an example, the material of the high thermal conductivity adhesive layer 60 includes silica gel or asphalt mixtures modified by epoxy resin added with highly heat-conductive material
Rouge, the highly heat-conductive material include silica, aluminium oxide or aluminium nitride etc.；The material of the thermal interface material layer 70 includes having
The silicon lipid materials of viscosity.Certainly, the material of the high thermal conductivity adhesive layer 60 and the thermal interface material layer 70 can also be identical,
It is all one of silica gel or epoxy resin, the sticking silicon lipid materials of tool added with highly heat-conductive material；The cooling fin
80 include conventional metals cooling fin.
In conclusion a kind of coreless substrate encapsulating structure of the invention and its manufacturing method, in the centreless base for realizing chip
When plate encapsulates, using the heat conducting base material with high thermal conductivity coefficient as the radiator structure of encapsulation chip, to improve the encapsulation core
The heat dissipation performance of piece；Mechanical support is provided for entire encapsulating structure simultaneously, to increase its mechanical strength, avoid it that warpage occurs.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (13)
1. a kind of manufacturing method of coreless substrate encapsulating structure, which is characterized in that the manufacturing method includes:
A package substrate is prepared, wherein the package substrate includes heat conducting base material and the cloth for being formed in the heat conducting base material lower surface
Line metal layer；
Formed in the heat conducting base material and expose the chip putting hole of the interconnection metal layer, and will encapsulation chip be placed in it is described
In chip putting hole, and the encapsulation chip is electrically connected with the interconnection metal layer；
The plastic packaging layer at least coating the encapsulation chip bottom is formed in the chip putting hole, and in the interconnection metal layer
Surface far from the heat conducting base material, which is formed, draws pad, wherein the extraction pad is electrically connected with the interconnection metal layer.
2. the manufacturing method of coreless substrate encapsulating structure according to claim 1, which is characterized in that prepare the encapsulation base
The method of plate includes: to provide the heat conducting base material, and form the interconnection metal layer in the heat conducting base material lower surface.
3. the manufacturing method of coreless substrate encapsulating structure according to claim 1, which is characterized in that prepare the encapsulation base
The method of plate includes:
Prepare a composite base material, wherein the composite base material include: adhesive layer and be respectively formed in the adhesive layer upper surface and
The heat conducting base material of lower surface；
The interconnection metal layer is formed far from the surface of the adhesive layer in the heat conducting base material, is later formed with surface described
The heat conducting base material of interconnection metal layer is removed from the adhesive layer, to complete the preparation of the package substrate.
4. the manufacturing method of coreless substrate encapsulating structure according to claim 3, which is characterized in that prepare the composite base
The method of material includes: that the upper and lower surfaces using process for pressing in the adhesive layer press the heat conducting base material, is adopted later
High temperature and pressure baking processing is carried out with the adhesive layer that high temperature and pressure baking process has the heat conducting base material to surface pressing, with
Complete the preparation of the composite base material.
5. the manufacturing method of coreless substrate encapsulating structure according to any one of claims 1 to 4, which is characterized in that described
Heat conducting base material includes the metal that thermal coefficient is greater than 10W/mK.
6. the manufacturing method of coreless substrate encapsulating structure according to claim 1, which is characterized in that form the chip and put
After setting hole, the manufacturing method further include: Yu Suoshu heat conducting base material surface forms the step of protective layer, wherein the protective layer packet
Include inoxidzable coating and/or solder mask.
7. the manufacturing method of coreless substrate encapsulating structure according to claim 1, which is characterized in that the manufacturing method is also
It include: to the step of forming cooling fin less than the encapsulation chip upper surface.
8. the manufacturing method of coreless substrate encapsulating structure according to claim 7, which is characterized in that Yu Suoshu heat conducting base material
Upper surface and the encapsulation chip upper surface form the cooling fin, and method includes: to form height in the heat conducting base material upper surface
Thermally conductive adhesive layer, and thermal interface material layer is formed in the encapsulation chip upper surface；Later in table on the high thermal conductivity adhesive layer
Face and the thermal interface material layer upper surface form the cooling fin.
9. a kind of coreless substrate encapsulating structure, which is characterized in that the encapsulating structure includes:
Package substrate including heat conducting base material and is formed in the interconnection metal layer of the heat conducting base material lower surface, wherein described thermally conductive
The chip putting hole for exposing the interconnection metal layer is formed in substrate；
Chip is encapsulated, is placed in the chip putting hole, and be electrically connected with the interconnection metal layer；
Plastic packaging layer is formed in the chip putting hole, and is at least coated on the bottom of the encapsulation chip；
Pad, the surface set on the interconnection metal layer far from the heat conducting base material are drawn, and is electrically connected with the interconnection metal layer
It connects.
10. coreless substrate encapsulating structure according to claim 9, which is characterized in that the heat conducting base material includes thermally conductive system
Number is greater than the metal of 10W/mK.
11. coreless substrate encapsulating structure according to claim 9, which is characterized in that the encapsulating structure further include: formed
Protective layer in the heat conducting base material surface, wherein the protective layer includes inoxidzable coating and/or solder mask.
12. coreless substrate encapsulating structure according to claim 9, which is characterized in that the encapsulating structure further include: at least
It is formed in the heat dissipating layer of the encapsulation chip upper surface.
13. coreless substrate encapsulating structure according to claim 12, which is characterized in that the heat dissipating layer is formed in described lead
Hot substrate and the encapsulation chip upper surface, the at this time encapsulating structure further include:
High thermal conductivity adhesive layer is formed in the upper surface of the heat conducting base material；
Thermal interface material layer is formed in the upper surface of the encapsulation chip；
Cooling fin is formed in the upper surface of the high thermal conductivity adhesive layer and the thermal interface material layer.
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| CN111755340A (en) * | 2020-06-30 | 2020-10-09 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method and semiconductor packaging structure |
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